同步步兵代码，暂时关闭底盘跟随

底盘/.vscode/launch.json

@@ -8,8 +8,8 @@
       "args": [],
       "stopAtEntry": false,
       "externalConsole": true,
-      "cwd": "f:/Mas_Infantry_Control-main/开源代码/V1.0/Hero/底盘/底盘/CarBody",
-      "program": "f:/Mas_Infantry_Control-main/开源代码/V1.0/Hero/底盘/底盘/CarBody/build/Debug/outDebug",
+      "cwd": "f:/Mas_Infantry_Control-main/开源代码/V1.0/new-infantry/底盘/底盘/CarBody",
+      "program": "f:/Mas_Infantry_Control-main/开源代码/V1.0/new-infantry/底盘/底盘/CarBody/build/Debug/outDebug",
       "MIMode": "gdb",
       "miDebuggerPath": "gdb",
       "setupCommands": [

底盘/底盘-old/底盘/.vscode/c_cpp_properties.json

@@ -0,0 +1,195 @@
+{
+    "configurations": [
+        {
+            "name": "windows-cygwin-gcc-x64",
+            "includePath": [
+                "${workspaceFolder}/**",
+                "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Start",
+                "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Library",
+                "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\System",
+                "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Algorithm",
+                "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Hardware",
+                "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Motor",
+                "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Function",
+                "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Control",
+                "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\CarBody",
+                "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\User",
+                "C:\\Keil_v5\\ARM\\ARMCC\\include"
+            ],
+            "defines": [
+                "USE_STDPERIPH_DRIVER",
+                "STM32F40_41xxx",
+                "__CC_ARM",
+                "__arm__",
+                "__align(x)=",
+                "__ALIGNOF__(x)=",
+                "__alignof__(x)=",
+                "__asm(x)=",
+                "__forceinline=",
+                "__restrict=",
+                "__global_reg(n)=",
+                "__inline=",
+                "__int64=long long",
+                "__INTADDR__(expr)=0",
+                "__irq=",
+                "__packed=",
+                "__pure=",
+                "__smc(n)=",
+                "__svc(n)=",
+                "__svc_indirect(n)=",
+                "__svc_indirect_r7(n)=",
+                "__value_in_regs=",
+                "__weak=",
+                "__writeonly=",
+                "__declspec(x)=",
+                "__attribute__(x)=",
+                "__nonnull__(x)=",
+                "__register=",
+                "__breakpoint(x)=",
+                "__cdp(x,y,z)=",
+                "__clrex()=",
+                "__clz(x)=0U",
+                "__current_pc()=0U",
+                "__current_sp()=0U",
+                "__disable_fiq()=",
+                "__disable_irq()=",
+                "__dmb(x)=",
+                "__dsb(x)=",
+                "__enable_fiq()=",
+                "__enable_irq()=",
+                "__fabs(x)=0.0",
+                "__fabsf(x)=0.0f",
+                "__force_loads()=",
+                "__force_stores()=",
+                "__isb(x)=",
+                "__ldrex(x)=0U",
+                "__ldrexd(x)=0U",
+                "__ldrt(x)=0U",
+                "__memory_changed()=",
+                "__nop()=",
+                "__pld(...)=",
+                "__pli(...)=",
+                "__qadd(x,y)=0",
+                "__qdbl(x)=0",
+                "__qsub(x,y)=0",
+                "__rbit(x)=0U",
+                "__rev(x)=0U",
+                "__return_address()=0U",
+                "__ror(x,y)=0U",
+                "__schedule_barrier()=",
+                "__semihost(x,y)=0",
+                "__sev()=",
+                "__sqrt(x)=0.0",
+                "__sqrtf(x)=0.0f",
+                "__ssat(x,y)=0",
+                "__strex(x,y)=0U",
+                "__strexd(x,y)=0",
+                "__strt(x,y)=",
+                "__swp(x,y)=0U",
+                "__usat(x,y)=0U",
+                "__wfe()=",
+                "__wfi()=",
+                "__yield()=",
+                "__vfp_status(x,y)=0"
+            ],
+            "intelliSenseMode": "linux-gcc-x64",
+            "cStandard": "${default}",
+            "cppStandard": "${default}",
+            "compilerPath": "C:/cygwin64/bin/gcc.exe"
+        },
+        {
+            "name": "Target 1",
+            "includePath": [
+                "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\new-infantry\\底盘\\底盘-old\\底盘\\Start",
+                "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\new-infantry\\底盘\\底盘-old\\底盘\\Library",
+                "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\new-infantry\\底盘\\底盘-old\\底盘\\System",
+                "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\new-infantry\\底盘\\底盘-old\\底盘\\Algorithm",
+                "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\new-infantry\\底盘\\底盘-old\\底盘\\Hardware",
+                "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\new-infantry\\底盘\\底盘-old\\底盘\\Motor",
+                "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\new-infantry\\底盘\\底盘-old\\底盘\\Function",
+                "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\new-infantry\\底盘\\底盘-old\\底盘\\Control",
+                "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\new-infantry\\底盘\\底盘-old\\底盘\\CarBody",
+                "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\new-infantry\\底盘\\底盘-old\\底盘\\User",
+                "C:\\Keil_v5\\ARM\\ARMCC\\include"
+            ],
+            "defines": [
+                "USE_STDPERIPH_DRIVER",
+                "STM32F40_41xxx",
+                "__CC_ARM",
+                "__arm__",
+                "__align(x)=",
+                "__ALIGNOF__(x)=",
+                "__alignof__(x)=",
+                "__asm(x)=",
+                "__forceinline=",
+                "__restrict=",
+                "__global_reg(n)=",
+                "__inline=",
+                "__int64=long long",
+                "__INTADDR__(expr)=0",
+                "__irq=",
+                "__packed=",
+                "__pure=",
+                "__smc(n)=",
+                "__svc(n)=",
+                "__svc_indirect(n)=",
+                "__svc_indirect_r7(n)=",
+                "__value_in_regs=",
+                "__weak=",
+                "__writeonly=",
+                "__declspec(x)=",
+                "__attribute__(x)=",
+                "__nonnull__(x)=",
+                "__register=",
+                "__breakpoint(x)=",
+                "__cdp(x,y,z)=",
+                "__clrex()=",
+                "__clz(x)=0U",
+                "__current_pc()=0U",
+                "__current_sp()=0U",
+                "__disable_fiq()=",
+                "__disable_irq()=",
+                "__dmb(x)=",
+                "__dsb(x)=",
+                "__enable_fiq()=",
+                "__enable_irq()=",
+                "__fabs(x)=0.0",
+                "__fabsf(x)=0.0f",
+                "__force_loads()=",
+                "__force_stores()=",
+                "__isb(x)=",
+                "__ldrex(x)=0U",
+                "__ldrexd(x)=0U",
+                "__ldrt(x)=0U",
+                "__memory_changed()=",
+                "__nop()=",
+                "__pld(...)=",
+                "__pli(...)=",
+                "__qadd(x,y)=0",
+                "__qdbl(x)=0",
+                "__qsub(x,y)=0",
+                "__rbit(x)=0U",
+                "__rev(x)=0U",
+                "__return_address()=0U",
+                "__ror(x,y)=0U",
+                "__schedule_barrier()=",
+                "__semihost(x,y)=0",
+                "__sev()=",
+                "__sqrt(x)=0.0",
+                "__sqrtf(x)=0.0f",
+                "__ssat(x,y)=0",
+                "__strex(x,y)=0U",
+                "__strexd(x,y)=0",
+                "__strt(x,y)=",
+                "__swp(x,y)=0U",
+                "__usat(x,y)=0U",
+                "__wfe()=",
+                "__wfi()=",
+                "__yield()=",
+                "__vfp_status(x,y)=0"
+            ],
+            "intelliSenseMode": "${default}"
+        }
+    ],
+    "version": 4
+}

底盘/底盘-old/底盘/.vscode/keil-assistant.log

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+

底盘/底盘-old/底盘/.vscode/launch.json

@@ -0,0 +1,24 @@
+{
+  "version": "0.2.0",
+  "configurations": [
+    {
+      "name": "C/C++ Runner: Debug Session",
+      "type": "cppdbg",
+      "request": "launch",
+      "args": [],
+      "stopAtEntry": false,
+      "externalConsole": true,
+      "cwd": "f:/Mas_Infantry_Control-main/开源代码/V1.0/底盘/底盘/CarBody",
+      "program": "f:/Mas_Infantry_Control-main/开源代码/V1.0/底盘/底盘/CarBody/build/Debug/outDebug",
+      "MIMode": "gdb",
+      "miDebuggerPath": "gdb",
+      "setupCommands": [
+        {
+          "description": "Enable pretty-printing for gdb",
+          "text": "-enable-pretty-printing",
+          "ignoreFailures": true
+        }
+      ]
+    }
+  ]
+}

底盘/底盘-old/底盘/.vscode/settings.json

@@ -0,0 +1,71 @@
+{
+  "C_Cpp_Runner.cCompilerPath": "gcc",
+  "C_Cpp_Runner.cppCompilerPath": "g++",
+  "C_Cpp_Runner.debuggerPath": "gdb",
+  "C_Cpp_Runner.cStandard": "",
+  "C_Cpp_Runner.cppStandard": "",
+  "C_Cpp_Runner.msvcBatchPath": "C:/Program Files/Microsoft Visual Studio/VR_NR/Community/VC/Auxiliary/Build/vcvarsall.bat",
+  "C_Cpp_Runner.useMsvc": false,
+  "C_Cpp_Runner.warnings": [
+    "-Wall",
+    "-Wextra",
+    "-Wpedantic",
+    "-Wshadow",
+    "-Wformat=2",
+    "-Wcast-align",
+    "-Wconversion",
+    "-Wsign-conversion",
+    "-Wnull-dereference"
+  ],
+  "C_Cpp_Runner.msvcWarnings": [
+    "/W4",
+    "/permissive-",
+    "/w14242",
+    "/w14287",
+    "/w14296",
+    "/w14311",
+    "/w14826",
+    "/w44062",
+    "/w44242",
+    "/w14905",
+    "/w14906",
+    "/w14263",
+    "/w44265",
+    "/w14928"
+  ],
+  "C_Cpp_Runner.enableWarnings": true,
+  "C_Cpp_Runner.warningsAsError": false,
+  "C_Cpp_Runner.compilerArgs": [],
+  "C_Cpp_Runner.linkerArgs": [],
+  "C_Cpp_Runner.includePaths": [
+    "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Start",
+    "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Library",
+    "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\System",
+    "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Algorithm",
+    "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Hardware",
+    "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Motor",
+    "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Function",
+    "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Control",
+    "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\CarBody",
+    "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\User",
+    "C:\\Keil_v5\\ARM\\ARMCC\\include"
+  ],
+  "C_Cpp_Runner.includeSearch": [
+    "*",
+    "**/*"
+  ],
+  "C_Cpp_Runner.excludeSearch": [
+    "**/build",
+    "**/build/**",
+    "**/.*",
+    "**/.*/**",
+    "**/.vscode",
+    "**/.vscode/**"
+  ],
+  "C_Cpp_Runner.useAddressSanitizer": false,
+  "C_Cpp_Runner.useUndefinedSanitizer": false,
+  "C_Cpp_Runner.useLeakSanitizer": false,
+  "C_Cpp_Runner.showCompilationTime": false,
+  "C_Cpp_Runner.useLinkTimeOptimization": false,
+  "C_Cpp_Runner.msvcSecureNoWarnings": false
+}

底盘/底盘-old/底盘/.vscode/uv4.log

@@ -0,0 +1,3 @@
+Load "f:\\Mas_Infantry_Control-main\\<5C><>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD>\\V1.0\\new-infantry\\<5C><><EFBFBD><EFBFBD>\\<5C><><EFBFBD><EFBFBD>\\Objects\\Project.axf" 
+Erase Done.Programming Done.Verify OK.Application running ...
+Flash Load finished at 09:20:54

底盘/底盘-old/底盘/.vscode/uv4.log.lock

@@ -0,0 +1 @@
+2025/3/28 9:20:55

底盘/底盘-old/底盘/CarBody/Mecanum.c

@@ -0,0 +1,356 @@
+#include "stm32f4xx.h"                  // Device header
+#include "stm32f4xx_conf.h"
+#include <math.h>
+#include "M3508.h"
+#include "GM6020.h"
+#include "Remote.h"
+#include "PID.h"
+#include "Parameter.h"
+#include "RefereeSystem.h"
+#include "Ultra_CAP.h"
+#include "Mecanum.h"
+#include "Delay.h"
+
+#define Mecanum_PowerControlSpeedNormalizationValue			3.0f//功率控制归一化速度标准值,范围[0,3]
+#define Mecanum_PowerControlGainCoefficientInitialValue		0.5f//功率控制增益系数初始值
+#define Mecanum_PowerControl_T								5.0f//功率控制周期(T=Mecanum_PowerControl_T*2ms)
+#define Mecanum_PowerControl_UseBuffer						30.0f//功率控制消耗的缓冲能量
+#define Mecanum_PowerControl_PowerMax						3.0f//功率控制功率上限与裁判系统功率上限比值上限
+#define Mecanum_PowerControl_UltraCAPPower					1.0f//使用超电增加功率
+
+//float Gear_ratio = 0.56666666666666666666666666666667f;//齿轮比17/30
+
+PID_PositionInitTypedef Mecanum_SpeedPID[4];//底盘四个电机的转速PID
+PID_PositionInitTypedef Mecanum_TrackPID;//底盘跟随PID
+float Mecanum_YawTheta;//底盘云台相对偏航角度
+uint8_t Mecanum_GyroScopeFlag;//底盘小陀螺标志位
+float Mecanum_Power;//底盘功率(软件计算值)
+float Mecanum_Current,Mecanum_PowerLimit,Mecanum_CurrentLimit=16384*4.0f;//底盘电流总和,功率控制功率上限,底盘电流限幅
+extern uint16_t RefereeSystem_Ref;
+
+/*
+ *函数简介:麦轮初始化
+ *参数说明:无
+ *返回类型:无
+ *备注:即四个转速PID的初始化
+ *备注:四个电机的ID参照上方的宏定义,最好使用M3508电机的ID1~4,否则下方电机控制的代码需要修改
+ */
+void Mecanum_Init(void)
+{
+	PID_PositionStructureInit(&Mecanum_SpeedPID[0],0);//左前轮
+	PID_PositionSetParameter(&Mecanum_SpeedPID[0],0.8,0,0);
+	PID_PositionSetEkRange(&Mecanum_SpeedPID[0],-5,5);
+	PID_PositionSetOUTRange(&Mecanum_SpeedPID[0],-15000,15000);
+	
+	PID_PositionStructureInit(&Mecanum_SpeedPID[1],0);//右前轮
+	PID_PositionSetParameter(&Mecanum_SpeedPID[1],0.8,0,0);
+	PID_PositionSetEkRange(&Mecanum_SpeedPID[1],-5,5);
+	PID_PositionSetOUTRange(&Mecanum_SpeedPID[1],-15000,15000);
+	
+	PID_PositionStructureInit(&Mecanum_SpeedPID[2],0);//左后轮
+	PID_PositionSetParameter(&Mecanum_SpeedPID[2],0.8,0,0);
+	PID_PositionSetEkRange(&Mecanum_SpeedPID[2],-5,5);
+	PID_PositionSetOUTRange(&Mecanum_SpeedPID[2],-15000,15000);
+	
+	PID_PositionStructureInit(&Mecanum_SpeedPID[3],0);//右后轮
+	PID_PositionSetParameter(&Mecanum_SpeedPID[3],0.8,0,0);
+	PID_PositionSetEkRange(&Mecanum_SpeedPID[3],-5,5);
+	PID_PositionSetOUTRange(&Mecanum_SpeedPID[3],-15000,15000);
+	
+    PID_PositionStructureInit(&Mecanum_TrackPID,Yaw_GM6020PositionValue);//底盘跟随relative_angle
+	//PID_PositionStructureInit(&Mecanum_TrackPID,Mecanum_YawTheta);
+    //PID_PositionStructureInit(&Mecanum_TrackPID,GM6020_MotorStatus[0].Chassis_positive_direction);
+	PID_PositionSetParameter(&Mecanum_TrackPID,0.001,0,0.01);
+	PID_PositionSetEkRange(&Mecanum_TrackPID,-1,1);
+	PID_PositionSetOUTRange(&Mecanum_TrackPID,-1,1);
+}
+
+/*
+ *函数简介:麦轮PID清理
+ *参数说明:无
+ *返回类型:无
+ *备注:清理四个转速位置式PID
+ */
+void Mecanum_CleanPID(void)
+{
+	PID_PositionClean(&Mecanum_SpeedPID[0]);//左前轮
+	PID_PositionClean(&Mecanum_SpeedPID[1]);//右前轮
+	PID_PositionClean(&Mecanum_SpeedPID[2]);//左后轮
+	PID_PositionClean(&Mecanum_SpeedPID[3]);//右后轮
+	PID_PositionClean(&Mecanum_TrackPID);//底盘跟随
+}
+
+/*
+ *函数简介:麦轮速度控制
+ *参数说明:左前轮速度
+ *参数说明:右前轮速度
+ *参数说明:左后轮速度
+ *参数说明:右后轮速度
+ *返回类型:无
+ *备注:单独控制四个轮子的速度
+ */
+void Mecanum_ControlSpeed(int16_t LeftFrontSpeed,int16_t RightFrontSpeed,int16_t LeftRearSpeed,int16_t RightRearSpeed)
+{
+	//更改期望
+	Mecanum_SpeedPID[0].Need_Value=LeftFrontSpeed;//左前轮
+	Mecanum_SpeedPID[1].Need_Value=RightFrontSpeed;//右前轮;
+	Mecanum_SpeedPID[2].Need_Value=LeftRearSpeed;//左后轮
+	Mecanum_SpeedPID[3].Need_Value=RightRearSpeed;//右后轮
+	
+	//PID计算
+	PID_PositionCalc(&Mecanum_SpeedPID[0],M3508_MotorStatus[Mecanum_LeftFrontWheel-0x201].RotorSpeed);//左前轮
+	PID_PositionCalc(&Mecanum_SpeedPID[1],M3508_MotorStatus[Mecanum_RightFrontWheel-0x201].RotorSpeed);//右前轮
+	PID_PositionCalc(&Mecanum_SpeedPID[2],M3508_MotorStatus[Mecanum_LeftRearWheel-0x201].RotorSpeed);//左后轮
+	PID_PositionCalc(&Mecanum_SpeedPID[3],M3508_MotorStatus[Mecanum_RightRearWheel-0x201].RotorSpeed);//右后轮
+
+	Mecanum_Current=0;
+	for(uint8_t i=0;i<4;i++)
+		Mecanum_Current+=fabs(Mecanum_SpeedPID[i].OUT);
+	if(Mecanum_Current>Mecanum_CurrentLimit)
+	{
+		Mecanum_SpeedPID[0].OUT*=(Mecanum_CurrentLimit/Mecanum_Current);
+		Mecanum_SpeedPID[1].OUT*=(Mecanum_CurrentLimit/Mecanum_Current);
+		Mecanum_SpeedPID[2].OUT*=(Mecanum_CurrentLimit/Mecanum_Current);
+		Mecanum_SpeedPID[3].OUT*=(Mecanum_CurrentLimit/Mecanum_Current);
+	}
+	
+	M3508_CANSetLIDCurrent(Mecanum_SpeedPID[1].OUT,Mecanum_SpeedPID[0].OUT,Mecanum_SpeedPID[2].OUT,Mecanum_SpeedPID[3].OUT);//M3508控制
+}
+
+/*
+ *函数简介:麦轮逆运动解算
+ *参数说明:x轴速度,单位m/s(以前为正)
+ *参数说明:y轴速度,单位m/s(以左为正)
+ *参数说明:z轴转速,单位rad/s(以逆时针为正)
+ *返回类型:无
+ *备注:速度转速转换系数:
+ *	   w'=v/R (rad/s)=v/(2Π×R) (r/s)=60×v/(2Π×R) (r/min)=1/19 w
+ *	   ⇒ w=19×60×v/(2Π×R/100)=19×60×100×v/(2Π×R)=18143.663512×v/R,R单位cm
+ *备注:麦轮半径参数在上方宏定义Mecanum_WheelRadius修改,默认7cm,转换参数2591.95
+ *备注:底盘中心到轮子中心的距离由上方宏定义x轴分量Mecanum_rx和y轴分量Mecanum_ry决定
+ */
+void Mecanum_InverseMotionControl(float v_x,float v_y,float w)
+{
+	//逆运动解算
+	int16_t LeftFrontSpeed=(int16_t)((-v_x-v_y-w*(Mecanum_rx+Mecanum_ry)/100.0f)/Mecanum_WheelRadius*18143.663512f);//左前轮
+	int16_t RightFrontSpeed=(int16_t)((v_x-v_y-w*(Mecanum_rx+Mecanum_ry)/100.0f)/Mecanum_WheelRadius*18143.663512f);//右前轮
+	int16_t LeftRearSpeed=(int16_t)((-v_x+v_y-w*(Mecanum_rx+Mecanum_ry)/100.0f)/Mecanum_WheelRadius*18143.663512f);//左后轮
+	int16_t RightRearSpeed=(int16_t)((v_x+v_y-w*(Mecanum_rx+Mecanum_ry)/100.0f)/Mecanum_WheelRadius*18143.663512f);//右后轮
+	
+	Mecanum_ControlSpeed(LeftFrontSpeed,RightFrontSpeed,LeftRearSpeed,RightRearSpeed);//M3508速度控制
+}
+/*
+
+  * @brief          设置底盘控制设定点，三个运动控制值由"chassis_behaviour_control_set".
+  * @param[out]     chassis_move_update: "chassis_move" valiable point
+  * @retval         
+  
+void chassis_relative_angle(float relative_angle)
+ {
+  if(last_relative_angle!=99&&fabs(relative_angle-last_relative_angle)<5)
+  {
+    fake_relative_angle+=((relative_angle-last_relative_angle)/(30/17));
+  }
+  last_relative_angle=relative_angle;
+  if(fake_relative_angle>3.141592653589793238462643383279f)fake_relative_angle=-3.141592653589793238462643383279f;
+  if(fake_relative_angle<-3.141592653589793238462643383279f)fake_relative_angle=3.141592653589793238462643383279f;
+ }
+*/
+/*
+ *函数简介:麦轮功率控制
+ *参数说明:无
+ *返回类型:无
+ *备注:麦轮是否开启可功率控制模式决定于上方宏定义Mecanum_PowerControl
+ *备注:以Mecanum_PowerControl_T*2ms为控制周期,取底盘平均功率(通过M3508反馈数据计算),通过速度增益系数和速度归一化控制速度大小,速度增益系数在[0,2]范围内
+ *备注:速度归一化的标准值在上方宏定义Mecanum_PowerControlSpeedNormalizationValue修改,范围[0,3]
+ *备注:增益系数的初始值在上方宏定义Mecanum_PowerControlGainCoefficientInitialValue修改
+ *备注:设定功率上限最高为150W限幅
+ *备注:速度转速转换系数:
+ *	   w'=v/R (rad/s)=v/(2Π×R) (r/s)=60×v/(2Π×R) (r/min)=1/19 w
+ *	   ⇒ w=19×60×v/(2Π×R/100)=19×60×100×v/(2Π×R)=18143.663512×v/R,R单位cm
+ *备注:底盘中心到轮子中心的距离由上方宏定义x轴分量Mecanum_rx和y轴分量Mecanum_ry决定
+ */
+void Mecanum_PowerMoveControl(void)
+{
+	static uint8_t Mecanum_GyroScopeCloseFlag=0;//小陀螺待关闭标志位
+	static float GainCoefficient=1.0f;//速度增益系数
+	static uint8_t Count=0;//计数器,以Mecanum_PowerControl_T*2ms为控制周期
+
+	/*==========三轴速度获取==========*/
+
+	float vx=1024-Remote_RxData.Remote_R_UD;
+	float vy=1024-Remote_RxData.Remote_R_RL;
+	float w=1024-Remote_RxData.Remote_L_RL;//获取三个轴的速度参量
+	float sigma=sqrtf(vx*vx+vy*vy);//获取xy轴速度归一化系数
+	if(sigma!=0)//x,y轴速度归一化(正交合成速度不变为标准值)
+	{
+		vx=vx/sigma*Mecanum_PowerControlSpeedNormalizationValue;
+		vy=vy/sigma*Mecanum_PowerControlSpeedNormalizationValue;
+	}
+	
+	int16_t Raw_Theta=Yaw_GM6020PositionValue-GM6020_MotorStatus[0].Angle;//获取底盘云台相对角度原始数据
+	if(Raw_Theta<0)Raw_Theta+=8192;
+	//Mecanum_YawTheta=Raw_Theta/8192.0f*2.0f*3.141592653589793238462643383279f;
+	Mecanum_YawTheta=Raw_Theta*0.000766990393942820614859043794746f;//获取底盘云台相对角度*0.56666666666666666666666666666667f
+	
+	float vx_=vx,vy_=vy;
+	vx=vx_*cosf(Mecanum_YawTheta)-vy_*sinf(Mecanum_YawTheta);
+	vy=vx_*sinf(Mecanum_YawTheta)+vy_*cosf(Mecanum_YawTheta);//根据底盘云台相对角度修正xy轴速度
+	
+	/*==========小陀螺处理==========*/
+	if(Yaw_GM6020PositionValue<4096)//正向小陀螺为逆时针
+	{
+		if((Remote_RxData.Remote_RS==2 ) || (Mecanum_GyroScopeFlag==1 && Mecanum_GyroScopeCloseFlag==1 && GM6020_MotorStatus[0].Position<Yaw_GM6020PositionValue+500))//小陀螺模式
+		{
+			w=Mecanum_LGyroScopeAngularVelocity;
+			Mecanum_GyroScopeFlag=1;//处于小陀螺状态
+			Mecanum_GyroScopeCloseFlag=1;//小陀螺处于待关闭状态
+		}
+		else if(Mecanum_GyroScopeFlag==1 && ((GM6020_MotorStatus[0].Angle>Yaw_GM6020PositionValue+100 || GM6020_MotorStatus[0].Angle<Yaw_GM6020PositionValue-100) || (GM6020_MotorStatus[0].Speed>2||GM6020_MotorStatus[0].Speed<-2)))//小陀螺关闭状态
+		{
+			PID_PositionSetOUTRange(&Mecanum_TrackPID,-2,2);
+			PID_PositionCalc(&Mecanum_TrackPID,GM6020_MotorStatus[0].Position);//底盘跟云台GM6020_MotorStatus[0].Chassis_positive_direction
+			//w = Mecanum_RGyroScopeAngularVelocity;
+			w=-Mecanum_TrackPID.OUT;
+			Mecanum_GyroScopeCloseFlag=0;//小陀螺未处于待关闭状态
+		}
+		else if(Remote_RxData.Remote_RS==1|| Remote_RxData.Remote_KeyPush_Ctrl==1)//反向小陀螺模式(仅检录使用)
+			w=-Mecanum_LGyroScopeAngularVelocity;
+		else
+		{
+			PID_PositionSetOUTRange(&Mecanum_TrackPID,-2,2);
+			Mecanum_GyroScopeFlag=0;
+			PID_PositionCalc(&Mecanum_TrackPID,GM6020_MotorStatus[0].Position);//底盘跟云台
+			//w = Mecanum_RGyroScopeAngularVelocity;
+			w=-Mecanum_TrackPID.OUT;
+		}
+	}
+	else//正向小陀螺为顺时针
+	{
+		if((Remote_RxData.Remote_RS==2 || Remote_RxData.Remote_KeyPush_Ctrl==1) || (Mecanum_GyroScopeFlag==1 && Mecanum_GyroScopeCloseFlag==1 && GM6020_MotorStatus[0].Position>Yaw_GM6020PositionValue-500))//小陀螺模式
+		{
+			w=-Mecanum_LGyroScopeAngularVelocity;
+			Mecanum_GyroScopeFlag=1;//处于小陀螺状态
+			Mecanum_GyroScopeCloseFlag=1;//小陀螺处于待关闭状态
+		}
+		else if(Mecanum_GyroScopeFlag==1 && ((GM6020_MotorStatus[0].Angle>Yaw_GM6020PositionValue+5 || GM6020_MotorStatus[0].Angle<Yaw_GM6020PositionValue-5) || (GM6020_MotorStatus[0].Speed>1||GM6020_MotorStatus[0].Speed<-1)))//小陀螺关闭状态
+		{
+			PID_PositionSetOUTRange(&Mecanum_TrackPID,-2,2);
+			PID_PositionCalc(&Mecanum_TrackPID,GM6020_MotorStatus[0].Position);//底盘跟云台
+			//w = Mecanum_RGyroScopeAngularVelocity;
+			w=-Mecanum_TrackPID.OUT;
+			Mecanum_GyroScopeCloseFlag=0;//小陀螺未处于待关闭状态
+		}
+		else if(Remote_RxData.Remote_RS==1)//反向小陀螺模式(仅检录使用)
+			w=Mecanum_LGyroScopeAngularVelocity;
+		else
+		{
+			PID_PositionSetOUTRange(&Mecanum_TrackPID,-2,2);
+			Mecanum_GyroScopeFlag=0;
+			PID_PositionCalc(&Mecanum_TrackPID,GM6020_MotorStatus[0].Position);//底盘跟云台
+			//w = Mecanum_RGyroScopeAngularVelocity;
+			w=-Mecanum_TrackPID.OUT;
+		}
+	}		
+	
+	/*==========功率上限处理==========*/
+	/*由缓冲能量得到功率控制功率上限*/
+	float Mecanum_PowerRef=1.0f/(60.0f-Mecanum_PowerControl_UseBuffer)*RefereeSystem_Buffer;//功率增益
+	if(Mecanum_PowerRef>Mecanum_PowerControl_PowerMax)Mecanum_PowerRef=Mecanum_PowerControl_PowerMax;
+	Mecanum_PowerLimit=Mecanum_PowerRef*RefereeSystem_Ref;
+	
+	/*由运动状态约束功率控制功率上限*/
+	float Scale=sigma/660.0f;
+	if(Scale<1 && Scale>0)Mecanum_PowerLimit*=Scale;//平移约束
+	if(Mecanum_GyroScopeFlag==1)Mecanum_PowerLimit=Mecanum_PowerRef*RefereeSystem_Ref;//小陀螺约束
+	if(Mecanum_PowerLimit>150.0f)Mecanum_PowerLimit=150.0f;//限幅约束
+
+
+
+
+	/*由超电约束功率控制功率上限*/
+	/*
+	if(Remote_RxData.Remote_KeyPush_Shift==1)//开启超电
+	{
+		if(Mecanum_PowerLimit>0.0f)
+		{
+			if(Mecanum_PowerLimit<RefereeSystem_Ref)Mecanum_PowerLimit+=Mecanum_PowerControl_UltraCAPPower;
+			else Mecanum_PowerLimit=RefereeSystem_Ref+Mecanum_PowerControl_UltraCAPPower;
+		}
+		Ultra_CAP_SetPower(RefereeSystem_Ref);
+	}
+	else
+		Ultra_CAP_SetPower(Mecanum_PowerLimit);
+	*/
+	/*==========功率控制==========*/
+	static float PowerSum=0;//控制周期内的功率积分
+	Mecanum_Power=1.732050807568877f*(M3508_MotorStatus[Mecanum_LeftFrontWheel-0x201].Power \
+				  +M3508_MotorStatus[Mecanum_RightFrontWheel-0x201].Power \
+				  +M3508_MotorStatus[Mecanum_LeftRearWheel-0x201].Power \
+				  +M3508_MotorStatus[Mecanum_RightRearWheel-0x201].Power);//获取底盘功率
+	PowerSum+=Mecanum_Power;
+	
+	/*速度增益*/
+	if(Count==Mecanum_PowerControl_T)//一个控制周期
+	{
+		Count=0;//计数器清零
+		float Power_avg=PowerSum/Mecanum_PowerControl_T;
+		PowerSum=0;
+		
+		if(Power_avg<Mecanum_PowerLimit/2.0f)
+		{
+			GainCoefficient+=0.05f;//增益系数递减
+			if(GainCoefficient>2)GainCoefficient=2;//增益系数限上幅2
+		}
+		else if(Power_avg<Mecanum_PowerLimit-5)
+		{
+			GainCoefficient+=0.02f;//增益系数递减
+			if(GainCoefficient>2)GainCoefficient=2;//增益系数限上幅2
+		}
+		else if(Power_avg>Mecanum_PowerLimit+5)
+		{
+			if(RefereeSystem_Buffer<60.0f-Mecanum_PowerControl_UseBuffer)GainCoefficient-=0.05f;//增益系数递增
+			else GainCoefficient-=0.02f;//增益系数递增
+			if(GainCoefficient<Mecanum_PowerControlGainCoefficientInitialValue/2.0f)GainCoefficient=Mecanum_PowerControlGainCoefficientInitialValue/2.0f;//增益系数限下幅
+		}
+	}
+	else if(vx!=0 || vy!=0 || Mecanum_GyroScopeFlag==1)//正常运动
+		Count++;
+	else//停止运动
+		GainCoefficient=Mecanum_PowerControlGainCoefficientInitialValue;//增益系数回归初始值
+	if(Mecanum_GyroScopeFlag==1 && (vx!=0 || vy!=0)){w*=0.6f;vx*=0.5f;vy*=0.5f;}//小陀螺移动直接降速,保证移动瞬间为缓冲能量增加
+	
+	/*电流限幅*/
+	float Mecanum_BufferCurrent=Mecanum_PowerLimit*512.0f/15.0f;
+	float Mecanum_PowerCurrent=Mecanum_PowerLimit*512.0f/15.0f*5.0f;
+	float B,C=0.9f;
+	if(60.0f-Mecanum_PowerControl_UseBuffer-10.0f>10.0f)B=60.0f-Mecanum_PowerControl_UseBuffer-10.0f;
+	else B=10.0f;
+	if(RefereeSystem_Buffer>B)
+	{
+		float PowerScale=0;
+		if(Mecanum_Power>C*Mecanum_PowerLimit)
+		{
+			if(Mecanum_Power>Mecanum_PowerLimit)PowerScale=0;
+			else PowerScale=(Mecanum_PowerLimit-Mecanum_Power)/(Mecanum_PowerLimit-C*Mecanum_PowerLimit);
+		}
+		else PowerScale=1;
+		Mecanum_CurrentLimit=Mecanum_BufferCurrent+Mecanum_PowerCurrent*PowerScale;
+	}
+	else
+	{
+		if(RefereeSystem_Buffer<5.0f)Mecanum_CurrentLimit=Mecanum_BufferCurrent*0.5f;
+		else Mecanum_CurrentLimit=Mecanum_BufferCurrent*(RefereeSystem_Buffer+B-10.0f)/(2*B-10.0f);
+	}
+	if(Mecanum_CurrentLimit>16384*4)Mecanum_CurrentLimit=16384*4;
+
+	/*==========运动控制==========*/
+	vx*=GainCoefficient;vy*=GainCoefficient;
+	if(Mecanum_GyroScopeFlag==1)w*=GainCoefficient;
+	int16_t LeftFrontSpeed=(int16_t)((-vx-vy-w*(Mecanum_rx+Mecanum_ry)/100.0f)/Mecanum_WheelRadius*18143.663512f);//左前
+	int16_t RightFrontSpeed=(int16_t)((vx-vy-w*(Mecanum_rx+Mecanum_ry)/100.0f)/Mecanum_WheelRadius*18143.663512f);//右前
+	int16_t LeftRearSpeed=(int16_t)((-vx+vy-w*(Mecanum_rx+Mecanum_ry)/100.0f)/Mecanum_WheelRadius*18143.663512f);//左后
+	int16_t RightRearSpeed=(int16_t)((vx+vy-w*(Mecanum_rx+Mecanum_ry)/100.0f)/Mecanum_WheelRadius*18143.663512f);//右后
+	
+	Mecanum_ControlSpeed(LeftFrontSpeed,RightFrontSpeed,LeftRearSpeed,RightRearSpeed);
+}

底盘/底盘-old/底盘/CarBody/Mecanum.h

@@ -0,0 +1,19 @@
+#ifndef __MECANUM_H
+#define __MECANUM_H
+
+#define Mecanum_LeftFrontWheel								M3508_2//左前轮
+#define Mecanum_RightFrontWheel								M3508_1//右前轮
+#define Mecanum_LeftRearWheel								M3508_3//左后轮
+#define Mecanum_RightRearWheel								M3508_4//右后轮
+
+extern float Mecanum_Power;//底盘功率(软件计算值)
+extern float Mecanum_YawTheta;//底盘云台相对偏航角度
+
+
+void Mecanum_Init(void);//麦轮初始化
+void Mecanum_CleanPID(void);//麦轮PID清理
+void Mecanum_ControlSpeed(int16_t LeftFrontSpeed,int16_t RightFrontSpeed,int16_t LeftRearSpeed,int16_t RightRearSpeed);//麦轮速度控制
+void Mecanum_InverseMotionControl(float v_x,float v_y,float w);//麦轮逆运动解算
+void Mecanum_PowerMoveControl(void);//麦轮功率控制
+
+#endif

底盘/底盘-old/底盘/CarBody/RefereeSystem.c

@@ -0,0 +1,213 @@
+#include "stm32f4xx.h"                  // Device header
+#include "stm32f4xx_conf.h"
+#include "RefereeSystem_CRCTable.h"
+#include "UART.h"
+
+/****************************************************************************************************
+
+	此处裁判系统只接收0x0201命令,获取机器人性能体系数据,主要获取发射机构是否上电
+	帧格式:
+		0xA5	0x0D	0x00	包序号	帧头CRC8校验	0x01	0x02	13ByteData	整包CRC16校验
+		 |___________________________________|			 |_______|			 |
+						 帧头							  命令码			数据
+	
+****************************************************************************************************/
+
+/*接收数据缓冲区数组元素数=命令码对应数据段长度+9*/
+uint8_t RefereeSystem_RxHEXPacket1[22]={0xA5,0x0D,0x00,0x00,0x00,0x01,0x02,0};//裁判系统0x0201命令码接收数据缓冲区
+uint8_t RefereeSystem_RxHEXPacket2[25]={0xA5,0x10,0x00,0x00,0x00,0x02,0x02,0};//裁判系统0x0202命令码接收数据缓冲区
+
+uint8_t RefereeSystem_ShooterStatus=1;//发射机构状态,0-发射机构未上电,1-发射机构上电
+uint16_t RefereeSystem_Ref=80,RefereeSystem_Buffer=30.0f;//底盘功率上限,底盘功率缓冲能量(若无裁判系统,默认功率上限80W,缓冲能量30J)
+float RefereeSystem_Power;//底盘实时功率
+uint8_t RefereeSystem_RobotID=0;//机器人ID(无裁判系统时一直为0,4号步兵ID为4/104)
+
+/*
+ *函数简介:裁判系统CRC8查表计算
+ *参数说明:校验数据
+ *参数说明:数据长度
+ *参数说明:CRC初始值(默认给参数0xFF)
+ *返回类型:无
+ *备注:表格位于Referee System_CRCTable.h文件中CRC8_Table数组
+ */
+uint8_t RefereeSystem_GetCRC8CheckSum(uint8_t *Data,uint16_t Length,uint8_t Initial) 
+{ 
+	uint8_t Minuend;
+	while(Length--)
+	{
+		Minuend=Initial^(*Data);
+		Data++;
+		Initial=CRC8_Table[Minuend];
+	}
+	return Initial;
+}
+
+/*
+ *函数简介:裁判系统CRC8校验
+ *参数说明:校验数据(含尾端CRC校验码)
+ *参数说明:数据长度
+ *返回类型:校验正确返回1,否则返回0
+ *备注:无
+ */
+uint8_t RefereeSystem_VerifyCRC8CheckSum(uint8_t *Data,uint16_t Length) 
+{ 
+	uint8_t CRC8CheckSum=0;
+	if((Data==0) || (Length<=2))return 0;//特殊情况处理
+	CRC8CheckSum=RefereeSystem_GetCRC8CheckSum(Data,Length-1,CRC8_Initial);//获取CRC8计算值
+	return CRC8CheckSum==Data[Length-1];//测量值与计算值相比较
+} 
+
+/*
+ *函数简介:裁判系统CRC16查表计算
+ *参数说明:校验数据
+ *参数说明:数据长度
+ *参数说明:CRC初始值(默认给参数0xFFFF)
+ *返回类型:无
+ *备注:表格位于Referee System_CRCTable.h文件中CRC16_Table数组
+ */
+uint16_t RefereeSystem_GetCRC16CheckSum(uint8_t *Data,uint32_t Length,uint16_t Initial)
+{ 
+	uint8_t Minuend;
+	while(Length--)
+	{
+		Minuend=*Data;
+		Data++;
+		Initial=((uint16_t)(Initial)>>8)^CRC16_Table[((uint16_t)(Initial)^(uint16_t)(Minuend))&0x00FF];
+	}
+	return Initial;
+}
+
+/*
+ *函数简介:裁判系统CRC16校验
+ *参数说明:校验数据(含尾端CRC校验码)
+ *参数说明:数据长度
+ *返回类型:校验正确返回1,否则返回0
+ *备注:无
+ */
+uint32_t RefereeSystem_VerifyCRC16CheckSum(uint8_t *Data, uint32_t Length) 
+{ 
+	uint16_t CRC16CheckSum=0; 
+	if((Data==0)||(Length<=2))return 0;//特殊情况处理 
+	CRC16CheckSum=RefereeSystem_GetCRC16CheckSum(Data,Length-2,CRC16_Initial);//获取CRC16计算值
+	return ((CRC16CheckSum&0xFF)==Data[Length-2]&&((CRC16CheckSum>>8)&0xff)==Data[Length-1]);//测量值与计算值相比较
+}
+
+/*
+ *函数简介:裁判系统接收初始化
+ *参数说明:无
+ *返回类型:无
+ *备注:默认使用UART2(USART1)
+ */
+void RefereeSystem_Init(void)
+{
+	//UART2_Init();
+	//while(RefereeSystem_RobotID==0);//等待裁判系统通讯建立
+}
+
+/*
+ *函数简介:UART2串口中断接收裁判系统数据
+ *参数说明:无
+ *返回类型:无
+ *备注:数据帧格式在最上方注释
+ */
+
+// /*
+// void USART1_IRQHandler(void)
+// {
+
+// 	#define DataLength1		15//裁判系统0x0201命令码有效数据位数
+// 	#define DataLength2		18//裁判系统0x0202命令码有效数据位数
+	
+// 	static int RxHEXState=0;//定义静态变量用于接收模式的选择
+// 	static int pRxHEXState=0;//定义静态变量用于充当计数器
+	
+// 	uint8_t RefereeSystem_RxData;//裁判系统接收数据
+// 	int RefereeSystem_PowerRow;//底盘实时功率原始数据
+	
+// 	if(USART_GetITStatus(USART1,USART_IT_RXNE)==SET)//查询接收中断标志位
+// 	{
+// 		USART_ClearITPendingBit(USART1,USART_IT_RXNE);//清除接收中断标志位
+		
+// 		RefereeSystem_RxData=USART_ReceiveData(USART1);//将数据存入缓存区
+		
+// 		/*=====检查帧头=====*/
+// 		if(RxHEXState==0){if(RefereeSystem_RxData==0xA5)RxHEXState=1;}
+		
+// 		/*=====检查数据段长度,区分命令码=====*/
+// 		else if(RxHEXState==1)
+// 		{
+// 			if(RefereeSystem_RxData==0x0D)RxHEXState=2;//0x0201命令码
+// 			else if(RefereeSystem_RxData==0x10)RxHEXState=8;//0x0202命令码
+// 			else RxHEXState=0;//其他命令码直接跳过
+// 		}
+		
+// 		/*=====0x0201命令码=====*/
+// 			/*=====检查帧头其他部分=====*/
+// 			else if(RxHEXState==2){if(RefereeSystem_RxData==0x00)RxHEXState=3;else RxHEXState=0;}
+// 			else if(RxHEXState==3){RefereeSystem_RxHEXPacket1[3]=RefereeSystem_RxData;RxHEXState=4;}
+// 			else if(RxHEXState==4)
+// 			{
+// 				RefereeSystem_RxHEXPacket1[4]=RefereeSystem_RxData;
+				
+// 				if(RefereeSystem_VerifyCRC8CheckSum(RefereeSystem_RxHEXPacket1,5)==1)RxHEXState=5;//检查CRC8
+// 				else RxHEXState=0;
+// 			}	
+			
+// 			/*=====检查命令码=====*/
+// 			else if(RxHEXState==5){if(RefereeSystem_RxData==0x01)RxHEXState=6;else RxHEXState=0;}
+// 			else if(RxHEXState==6){if(RefereeSystem_RxData==0x02){RxHEXState=7;pRxHEXState=0;}else RxHEXState=0;}
+			
+// 			/*=====接收有效数据=====*/
+// 			else if(RxHEXState==7)
+// 			{
+// 				RefereeSystem_RxHEXPacket1[pRxHEXState+7]=RefereeSystem_RxData;//接收数据
+// 				pRxHEXState++;
+				
+// 				if(pRxHEXState>=DataLength1)
+// 				{
+// 					if(RefereeSystem_VerifyCRC16CheckSum(RefereeSystem_RxHEXPacket1,22)==1)//CRC校验
+// 					{
+// 						RefereeSystem_RobotID=RefereeSystem_RxHEXPacket1[7];//获取机器人ID
+// 						RefereeSystem_ShooterStatus=(RefereeSystem_RxHEXPacket1[19]&0x04)>>2;//获取发射机构状态
+// 						RefereeSystem_Ref=RefereeSystem_RxHEXPacket1[17]|((uint16_t)RefereeSystem_RxHEXPacket1[18]<<8);//获取功率上限
+// 					}
+// 					RxHEXState=0;
+// 				}
+// 			}
+		
+		
+// 		/*=====0x0202命令码=====*/
+// 			/*=====检查帧头其他部分=====*/
+// 			else if(RxHEXState==8){if(RefereeSystem_RxData==0x00)RxHEXState=9;else RxHEXState=0;}
+// 			else if(RxHEXState==9){RefereeSystem_RxHEXPacket2[3]=RefereeSystem_RxData;RxHEXState=10;}
+// 			else if(RxHEXState==10)
+// 			{
+// 				RefereeSystem_RxHEXPacket2[4]=RefereeSystem_RxData;
+// 				if(RefereeSystem_VerifyCRC8CheckSum(RefereeSystem_RxHEXPacket2,5)==1)RxHEXState=11;
+// 				else RxHEXState=0;
+// 			}	
+			
+// 			/*=====检查命令码=====*/
+// 			else if(RxHEXState==11){if(RefereeSystem_RxData==0x02)RxHEXState=12;else RxHEXState=0;}
+// 			else if(RxHEXState==12){if(RefereeSystem_RxData==0x02){RxHEXState=13;pRxHEXState=0;}else RxHEXState=0;}
+			
+// 			/*=====接收有效数据=====*/
+// 			else if(RxHEXState==13)
+// 			{
+// 				RefereeSystem_RxHEXPacket2[pRxHEXState+7]=RefereeSystem_RxData;//接收数据
+// 				pRxHEXState++;
+				
+// 				if(pRxHEXState>=DataLength2)
+// 				{
+// 					if(RefereeSystem_VerifyCRC16CheckSum(RefereeSystem_RxHEXPacket2,25)==1)//CRC校验
+// 					{
+// 						RefereeSystem_Buffer=RefereeSystem_RxHEXPacket2[15]|((uint16_t)RefereeSystem_RxHEXPacket2[16]<<8);//获取缓冲能量
+// 						RefereeSystem_PowerRow=(int32_t)((uint32_t)RefereeSystem_RxHEXPacket2[11]|((uint32_t)RefereeSystem_RxHEXPacket2[12]<<8)|((uint32_t)RefereeSystem_RxHEXPacket2[13]<<16)|((uint32_t)RefereeSystem_RxHEXPacket2[14]<<24));
+// 						RefereeSystem_Power=*((float *)(&RefereeSystem_PowerRow));//获取底盘实时功率
+// 					}
+// 					RxHEXState=0;
+// 				}
+// 			}
+// 	}
+// }
+// */

底盘/底盘-old/底盘/CarBody/RefereeSystem.h

@@ -0,0 +1,66 @@
+#ifndef __REFEREESYSTEM_H
+#define __REFEREESYSTEM_H
+
+typedef struct
+{
+  /**
+   * @brief robot id
+   *             0: robot none
+   *             1: red hero
+   *             2: red engineer
+   *         3/4/5: red infantry
+   *             6: red aerial
+   *             7: red sentry
+   *             8: red dart
+   *             9: red radar station
+   *           101: blue hero
+   *           102: blue engineer
+   *   103/104/105: blue infantry
+   *           106: blue aerial
+   *           107: blue sentry
+   *           108: blue dart
+   *           109: blue radar station
+   */
+  uint8_t robot_id;
+  uint8_t robot_level;
+  uint16_t current_HP;
+  uint16_t maximum_HP;
+
+  uint16_t shooter_barrel_cooling_value;
+  uint16_t shooter_barrel_heat_limit;
+  uint16_t chassis_power_limit;
+
+  uint8_t mains_power_gimbal_output : 1;
+  uint8_t mains_power_chassis_output : 1;
+  uint8_t mains_power_shooter_output : 1;
+} robot_status_t;
+
+typedef struct 
+{
+  uint8_t Index;
+  uint16_t DataLength;
+  robot_status_t robot_status;
+
+}Referee_System_Info_TypeDef;
+
+
+typedef struct 
+{
+  uint8_t  SOF;           /*!< Data frame start byte, fixed value is 0xA5 */
+  uint16_t Data_Length;   /*!< the length of data in the data frame */
+  uint8_t  Seq;           /*!< package serial number */
+  uint8_t  CRC8;          /*!< Frame header CRC8 checksum */
+}FrameHeader_TypeDef;
+
+
+extern uint8_t RefereeSystem_ShooterStatus;//发射机构状态,0-发射机构未上电,1-发射机构上电
+extern uint16_t RefereeSystem_Ref,RefereeSystem_Buffer;//底盘功率上限,底盘功率缓冲能量
+extern float RefereeSystem_Power;//底盘实时功率
+extern uint8_t RefereeSystem_RobotID;//机器人ID
+
+uint8_t RefereeSystem_GetCRC8CheckSum(uint8_t *Data,uint16_t Length,uint8_t Initial);//裁判系统CRC8查表计算
+uint16_t RefereeSystem_GetCRC16CheckSum(uint8_t *Data,uint32_t Length,uint16_t Initial);//裁判系统CRC16查表计算
+void RefereeSystem_Init(void);//裁判系统接收初始化
+void HandPowercontrol();
+
+#endif

底盘/底盘-old/底盘/CarBody/RefereeSystem_CRCTable.c

@@ -0,0 +1,46 @@
+#include "stm32f4xx.h"                  // Device header
+#include "stm32f4xx_conf.h"
+
+//crc8 generator polynomial:G(x)=x8+x5+x4+1//CRC8-MAXIM
+uint8_t CRC8_Initial=0xFF;//CRC8初始值
+const uint8_t CRC8_Table[256]=
+{ 
+	0x00,0x5E,0xBC,0xE2,0x61,0x3F,0xDD,0x83,0xC2,0x9C,0x7E,0x20,0xA3,0xFD,0x1F,0x41,
+	0x9D,0xC3,0x21,0x7F,0xFC,0xA2,0x40,0x1E,0x5F,0x01,0xE3,0xBD,0x3E,0x60,0x82,0xDC,
+	0x23,0x7D,0x9F,0xC1,0x42,0x1C,0xFE,0xA0,0xE1,0xBF,0x5D,0x03,0x80,0xDE,0x3C,0x62,
+	0xBE,0xE0,0x02,0x5C,0xDF,0x81,0x63,0x3D,0x7C,0x22,0xC0,0x9E,0x1D,0x43,0xA1,0xFF,
+	0x46,0x18,0xFA,0xA4,0x27,0x79,0x9B,0xC5,0x84,0xDA,0x38,0x66,0xE5,0xBB,0x59,0x07,
+	0xDB,0x85,0x67,0x39,0xBA,0xE4,0x06,0x58,0x19,0x47,0xA5,0xFB,0x78,0x26,0xC4,0x9A,
+	0x65,0x3B,0xD9,0x87,0x04,0x5A,0xB8,0xE6,0xA7,0xF9,0x1B,0x45,0xC6,0x98,0x7A,0x24,
+	0xF8,0xA6,0x44,0x1A,0x99,0xC7,0x25,0x7B,0x3A,0x64,0x86,0xD8,0x5B,0x05,0xE7,0xB9,
+	0x8C,0xD2,0x30,0x6E,0xED,0xB3,0x51,0x0F,0x4E,0x10,0xF2,0xAC,0x2F,0x71,0x93,0xCD,
+	0x11,0x4F,0xAD,0xF3,0x70,0x2E,0xCC,0x92,0xD3,0x8D,0x6F,0x31,0xB2,0xEC,0x0E,0x50,
+	0xAF,0xF1,0x13,0x4D,0xCE,0x90,0x72,0x2C,0x6D,0x33,0xD1,0x8F,0x0C,0x52,0xB0,0xEE,
+	0x32,0x6C,0x8E,0xD0,0x53,0x0D,0xEF,0xB1,0xF0,0xAE,0x4C,0x12,0x91,0xCF,0x2D,0x73,
+	0xCA,0x94,0x76,0x28,0xAB,0xF5,0x17,0x49,0x08,0x56,0xB4,0xEA,0x69,0x37,0xD5,0x8B,
+	0x57,0x09,0xEB,0xB5,0x36,0x68,0x8A,0xD4,0x95,0xCB,0x29,0x77,0xF4,0xAA,0x48,0x16,
+	0xE9,0xB7,0x55,0x0B,0x88,0xD6,0x34,0x6A,0x2B,0x75,0x97,0xC9,0x4A,0x14,0xF6,0xA8,
+	0x74,0x2A,0xC8,0x96,0x15,0x4B,0xA9,0xF7,0xB6,0xE8,0x0A,0x54,0xD7,0x89,0x6B,0x35
+};
+
+//crc16 generator polynomial:G(x)=x16+x12+x5+1//CRC16-CCITT
+uint16_t CRC16_Initial=0xFFFF;//CRC16初始值
+const uint16_t CRC16_Table[256]=
+{ 
+	0x0000,0x1189,0x2312,0x329B,0x4624,0x57AD,0x6536,0x74BF,0x8C48,0x9DC1,0xAF5A,0xBED3,0xCA6C,0xDBE5,0xE97E,0xF8F7,
+	0x1081,0x0108,0x3393,0x221A,0x56A5,0x472C,0x75B7,0x643E,0x9CC9,0x8D40,0xBFDB,0xAE52,0xDAED,0xCB64,0xF9FF,0xE876,
+	0x2102,0x308B,0x0210,0x1399,0x6726,0x76AF,0x4434,0x55BD,0xAD4A,0xBCC3,0x8E58,0x9FD1,0xEB6E,0xFAE7,0xC87C,0xD9F5,
+	0x3183,0x200A,0x1291,0x0318,0x77A7,0x662E,0x54B5,0x453C,0xBDCB,0xAC42,0x9ED9,0x8F50,0xFBEF,0xEA66,0xD8FD,0xC974,
+	0x4204,0x538D,0x6116,0x709F,0x0420,0x15A9,0x2732,0x36BB,0xCE4C,0xDFC5,0xED5E,0xFCD7,0x8868,0x99E1,0xAB7A,0xBAF3,
+	0x5285,0x430C,0x7197,0x601E,0x14A1,0x0528,0x37B3,0x263A,0xDECD,0xCF44,0xFDDF,0xEC56,0x98E9,0x8960,0xBBFB,0xAA72,
+	0x6306,0x728F,0x4014,0x519D,0x2522,0x34AB,0x0630,0x17B9,0xEF4E,0xFEC7,0xCC5C,0xDDD5,0xA96A,0xB8E3,0x8A78,0x9BF1,
+	0x7387,0x620E,0x5095,0x411C,0x35A3,0x242A,0x16B1,0x0738,0xFFCF,0xEE46,0xDCDD,0xCD54,0xB9EB,0xA862,0x9AF9,0x8B70,
+	0x8408,0x9581,0xA71A,0xB693,0xC22C,0xD3A5,0xE13E,0xF0B7,0x0840,0x19C9,0x2B52,0x3ADB,0x4E64,0x5FED,0x6D76,0x7CFF,
+	0x9489,0x8500,0xB79B,0xA612,0xD2AD,0xC324,0xF1BF,0xE036,0x18C1,0x0948,0x3BD3,0x2A5A,0x5EE5,0x4F6C,0x7DF7,0x6C7E,
+	0xA50A,0xB483,0x8618,0x9791,0xE32E,0xF2A7,0xC03C,0xD1B5,0x2942,0x38CB,0x0A50,0x1BD9,0x6F66,0x7EEF,0x4C74,0x5DFD,
+	0xB58B,0xA402,0x9699,0x8710,0xF3AF,0xE226,0xD0BD,0xC134,0x39C3,0x284A,0x1AD1,0x0B58,0x7FE7,0x6E6E,0x5CF5,0x4D7C,
+	0xC60C,0xD785,0xE51E,0xF497,0x8028,0x91A1,0xA33A,0xB2B3,0x4A44,0x5BCD,0x6956,0x78DF,0x0C60,0x1DE9,0x2F72,0x3EFB,
+	0xD68D,0xC704,0xF59F,0xE416,0x90A9,0x8120,0xB3BB,0xA232,0x5AC5,0x4B4C,0x79D7,0x685E,0x1CE1,0x0D68,0x3FF3,0x2E7A,
+	0xE70E,0xF687,0xC41C,0xD595,0xA12A,0xB0A3,0x8238,0x93B1,0x6B46,0x7ACF,0x4854,0x59DD,0x2D62,0x3CEB,0x0E70,0x1FF9,
+	0xF78F,0xE606,0xD49D,0xC514,0xB1AB,0xA022,0x92B9,0x8330,0x7BC7,0x6A4E,0x58D5,0x495C,0x3DE3,0x2C6A,0x1EF1,0x0F78
+};

底盘/底盘-old/底盘/CarBody/RefereeSystem_CRCTable.h

@@ -0,0 +1,12 @@
+#ifndef __REFEREESYSTEM_CRCTABLE_H
+#define __REFEREESYSTEM_CRCTABLE_H
+
+//crc8 generator polynomial:G(x)=x8+x5+x4+1//CRC8-MAXIM
+extern uint8_t CRC8_Initial;//CRC8初始值
+extern const uint8_t CRC8_Table[256];
+
+//crc16 generator polynomial:G(x)=x16+x12+x5+1//CRC16-CCITT
+extern uint16_t CRC16_Initial;//CRC16初始值
+extern const uint16_t CRC16_Table[256];
+
+#endif

底盘/底盘-old/底盘/CarBody/UI.c

@@ -0,0 +1,68 @@
+#include "stm32f4xx.h"                  // Device header
+#include "stm32f4xx_conf.h"
+#include "UI_Library.h"
+#include "Remote.h"
+#include "CloseLoopControl.h"
+#include "Delay.h"
+#include "RefereeSystem.h"
+
+/*
+ *函数简介:UI初始化
+ *参数说明:无
+ *返回类型:无
+ *备注:无
+ */
+void UI_Init(void)
+{
+	_ui_init_default_Ungroup_1();
+	Delay_ms(100);
+	_ui_init_default_Ungroup_0();
+	Delay_ms(100);
+	_ui_init_default_Ungroup_2();
+	Delay_ms(100);
+	_ui_init_default_Ungroup_1();
+	Delay_ms(100);
+}
+
+/*
+ *函数简介:UI更新
+ *参数说明:无
+ *返回类型:无
+ *备注:无
+ */
+void UI_Updata(void)
+{
+	static uint8_t Count=0;
+	Count=(Count+1)%2;//每次更新一个,循环更新提高效率
+	
+	if(CloseLoopControl_ErrorFlag==1)//遥控器未连接,所有指示灯变绿
+	{
+		CloseLoopControl_ErrorFlag=0;
+		_ui_update_default_Ungroup_2_NOCheck();
+	}
+	else
+	{
+		if(Count==0)//更新Shift
+		{
+			if(Remote_RxData.Remote_KeyPush_Shift==1)_ui_update_default_Ungroup_2_Shift_Open();
+			else _ui_update_default_Ungroup_2_Shift_Close();
+		}
+		else//更新Ctrl
+		{
+			if(Remote_RxData.Remote_KeyPush_Ctrl==1)_ui_update_default_Ungroup_2_Ctrl_Open();
+			else _ui_update_default_Ungroup_2_Ctrl_Close();
+		}
+	}
+}
+
+/*
+ *函数简介:UI显示遥控器未连接
+ *参数说明:无
+ *返回类型:无
+ *备注:所有指示灯变绿
+ */
+void UI_RemoteNoCheck(void)
+{
+	if(CloseLoopControl_ErrorFlag==1)CloseLoopControl_ErrorFlag=0;
+	_ui_update_default_Ungroup_2_NOCheck();
+}

底盘/底盘-old/底盘/CarBody/UI.h

@@ -0,0 +1,8 @@
+#ifndef __UI_H
+#define __UI_H
+
+void UI_Init(void);//UI初始化
+void UI_Updata(void);//UI更新
+void UI_RemoteNoCheck(void);//UI显示遥控器未连接
+
+#endif

底盘/底盘-old/底盘/CarBody/UI_Base.c

@@ -0,0 +1,41 @@
+#include "stm32f4xx.h"                  // Device header
+#include "stm32f4xx_conf.h"
+#include "UI_Base.h"
+#include <string.h>
+#include "RefereeSystem.h"
+#include "RefereeSystem_CRCTable.h"
+
+uint8_t UI_seq=0;
+
+#define DEFINE_FRAME_PROC(num,id)														\
+void ui_proc_##num##_frame(ui_##num##_frame_t *msg)										\
+{   																					\
+    msg->header.SOF=0xA5;																\
+    msg->header.data_length=6+15*num;													\
+    msg->header.seq=UI_seq++;															\
+    msg->header.CRC8=RefereeSystem_GetCRC8CheckSum((uint8_t*)msg,4,CRC8_Initial);		\
+    msg->header.cmd_id=0x0301;															\
+    msg->header.dada_cmd_id=id;															\
+    msg->header.sender_id=RefereeSystem_RobotID;													\
+    msg->header.receiver_id=RefereeSystem_RobotID+256;												\
+    msg->CRC16=RefereeSystem_GetCRC16CheckSum((uint8_t*)msg,13+15*num,CRC16_Initial);	\
+}
+
+DEFINE_FRAME_PROC(1,0x0101)
+DEFINE_FRAME_PROC(2,0x0102)
+DEFINE_FRAME_PROC(5,0x0103)
+DEFINE_FRAME_PROC(7,0x0104)
+
+void ui_proc_string_frame(ui_string_frame_t *msg)
+{
+    msg->header.SOF=0xA5;
+    msg->header.data_length=51;
+    msg->header.seq=UI_seq++;
+    msg->header.CRC8=RefereeSystem_GetCRC8CheckSum((uint8_t*)msg,4,CRC8_Initial);
+    msg->header.cmd_id=0x0301;
+    msg->header.dada_cmd_id=0x0110;
+    msg->header.sender_id=RefereeSystem_RobotID;
+    msg->header.receiver_id=RefereeSystem_RobotID+256;
+    msg->option.str_length=strlen(msg->option.string);
+    msg->CRC16=RefereeSystem_GetCRC16CheckSum((uint8_t *)msg,58,CRC16_Initial);
+}

底盘/底盘-old/底盘/CarBody/UI_Base.h

@@ -0,0 +1,103 @@
+#ifndef __UI_BASE_H
+#define __UI_BASE_H
+
+#define PRIMITIVE_CAT(x, y)	x##y
+#define MESSAGE_PACKED __attribute__((packed))
+
+#define DEFINE_MESSAGE(name,p_a,p_b,p_c,p_d,p_e)	\
+typedef struct										\
+{													\
+uint8_t figure_name[3];								\
+uint32_t operate_tpye:3;							\
+uint32_t figure_tpye:3;								\
+uint32_t layer:4;									\
+uint32_t color:4;									\
+uint32_t PRIMITIVE_CAT(details_,p_a):9;				\
+uint32_t PRIMITIVE_CAT(details_,p_b):9;				\
+uint32_t width:10;									\
+uint32_t start_x:11;								\
+uint32_t start_y:11;								\
+uint32_t PRIMITIVE_CAT(details_,p_c):10;				\
+uint32_t PRIMITIVE_CAT(details_,p_d):11;				\
+uint32_t PRIMITIVE_CAT(details_,p_e):11;				\
+}MESSAGE_PACKED ui_interface_##name##_t
+
+DEFINE_MESSAGE(figure,_a,_b,_c,_d,_e);
+DEFINE_MESSAGE(line,_a,_b,_c,end_x,end_y);
+DEFINE_MESSAGE(rect,_a,_b,_c,end_x,end_y);
+DEFINE_MESSAGE(round,_a,_b,r,_d,_e);
+DEFINE_MESSAGE(ellipse,_a,_b,_c,rx,ry);
+DEFINE_MESSAGE(arc,start_angle,end_angle,_c,rx,ry);
+
+typedef struct
+{
+    uint8_t figure_name[3];
+    uint32_t operate_tpye:3;
+    uint32_t figure_tpye:3;
+    uint32_t layer:4;
+    uint32_t color:4;
+    uint32_t font_size:9;
+    uint32_t _b:9;
+    uint32_t width:10;
+    uint32_t start_x:11;
+    uint32_t start_y:11;
+    int32_t number;
+}MESSAGE_PACKED ui_interface_number_t;
+
+typedef struct
+{
+    uint8_t figure_name[3];
+    uint32_t operate_tpye:3;
+    uint32_t figure_tpye:3;
+    uint32_t layer:4;
+    uint32_t color:4;
+    uint32_t font_size:9;
+    uint32_t str_length:9;
+    uint32_t width:10;
+    uint32_t start_x:11;
+    uint32_t start_y:11;
+    uint32_t _c:10;
+    uint32_t _d:11;
+    uint32_t _e:11;
+    char string[30];
+}MESSAGE_PACKED ui_interface_string_t;
+
+typedef struct
+{
+    uint8_t SOF;
+    uint16_t data_length;
+    uint8_t seq;
+	uint8_t CRC8;
+    uint16_t cmd_id;
+	uint16_t dada_cmd_id;
+    uint16_t sender_id;
+	uint16_t receiver_id;
+}MESSAGE_PACKED ui_frame_header_t;
+
+#define DEFINE_FIGURE_MESSAGE(num)		\
+typedef struct							\
+{										\
+	ui_frame_header_t header;			\
+	ui_interface_figure_t data[num];	\
+	uint16_t CRC16;						\
+}MESSAGE_PACKED ui_##num##_frame_t
+
+DEFINE_FIGURE_MESSAGE(1);
+DEFINE_FIGURE_MESSAGE(2);
+DEFINE_FIGURE_MESSAGE(5);
+DEFINE_FIGURE_MESSAGE(7);
+
+typedef struct
+{
+    ui_frame_header_t header;
+    ui_interface_string_t option;
+    uint16_t CRC16;
+}MESSAGE_PACKED ui_string_frame_t;
+
+void ui_proc_1_frame(ui_1_frame_t *msg);
+void ui_proc_2_frame(ui_2_frame_t *msg);
+void ui_proc_5_frame(ui_5_frame_t *msg);
+void ui_proc_7_frame(ui_7_frame_t *msg);
+void ui_proc_string_frame(ui_string_frame_t *msg);
+
+#endif

底盘/底盘-old/底盘/CarBody/UI_Library.c

@@ -0,0 +1,222 @@
+#include "stm32f4xx.h"                  // Device header
+#include "stm32f4xx_conf.h"
+#include "UI_Base.h"
+#include <string.h>
+#include "UART.h"
+
+/*==========Shift文本==========*/
+ui_string_frame_t ui_default_Ungroup_0;
+ui_interface_string_t* ui_default_Ungroup_Text_Shift=&ui_default_Ungroup_0.option;
+
+void _ui_init_default_Ungroup_0(void)
+{
+    ui_default_Ungroup_0.option.figure_name[0]=0;
+    ui_default_Ungroup_0.option.figure_name[1]=0;
+    ui_default_Ungroup_0.option.figure_name[2]=0;
+    ui_default_Ungroup_0.option.operate_tpye=1;
+    ui_default_Ungroup_0.option.figure_tpye=7;
+    ui_default_Ungroup_0.option.layer=0;
+    ui_default_Ungroup_0.option.font_size=30;
+    ui_default_Ungroup_0.option.start_x=75;
+    ui_default_Ungroup_0.option.start_y=850;
+    ui_default_Ungroup_0.option.color=2;
+    ui_default_Ungroup_0.option.str_length=5;
+    ui_default_Ungroup_0.option.width=6;
+    strcpy(ui_default_Ungroup_Text_Shift->string, "Shift");
+
+    ui_proc_string_frame(&ui_default_Ungroup_0);
+	UART1_SendArray((uint8_t *)&ui_default_Ungroup_0,sizeof(ui_default_Ungroup_0));
+}
+
+void _ui_update_default_Ungroup_0(void)
+{
+    ui_default_Ungroup_0.option.operate_tpye=2;
+
+    ui_proc_string_frame(&ui_default_Ungroup_0);
+	UART1_SendArray((uint8_t *)&ui_default_Ungroup_0,sizeof(ui_default_Ungroup_0));
+}
+
+void _ui_remove_default_Ungroup_0(void)
+{
+    ui_default_Ungroup_0.option.operate_tpye=3;
+
+    ui_proc_string_frame(&ui_default_Ungroup_0);
+	UART1_SendArray((uint8_t *)&ui_default_Ungroup_0,sizeof(ui_default_Ungroup_0));
+}
+
+/*==========Ctrl文本==========*/
+ui_string_frame_t ui_default_Ungroup_1;
+ui_interface_string_t* ui_default_Ungroup_Text_Ctrl=&ui_default_Ungroup_1.option;
+
+void _ui_init_default_Ungroup_1(void)
+{
+    ui_default_Ungroup_1.option.figure_name[0]=0;
+    ui_default_Ungroup_1.option.figure_name[1]=0;
+    ui_default_Ungroup_1.option.figure_name[2]=1;
+    ui_default_Ungroup_1.option.operate_tpye=1;
+    ui_default_Ungroup_1.option.figure_tpye=7;
+    ui_default_Ungroup_1.option.layer=0;
+    ui_default_Ungroup_1.option.font_size=30;
+    ui_default_Ungroup_1.option.start_x=75;
+    ui_default_Ungroup_1.option.start_y=750;
+    ui_default_Ungroup_1.option.color=2;
+    ui_default_Ungroup_1.option.str_length=4;
+    ui_default_Ungroup_1.option.width=6;
+    strcpy(ui_default_Ungroup_Text_Ctrl->string,"Ctrl");
+
+    ui_proc_string_frame(&ui_default_Ungroup_1);
+	UART1_SendArray((uint8_t *)&ui_default_Ungroup_1,sizeof(ui_default_Ungroup_1));
+}
+
+void _ui_update_default_Ungroup_1(void)
+{
+    ui_default_Ungroup_1.option.operate_tpye=2;
+
+    ui_proc_string_frame(&ui_default_Ungroup_1);
+	UART2_SendArray((uint8_t *)&ui_default_Ungroup_1,sizeof(ui_default_Ungroup_1));
+}
+
+void _ui_remove_default_Ungroup_1(void)
+{
+    ui_default_Ungroup_1.option.operate_tpye=3;
+
+    ui_proc_string_frame(&ui_default_Ungroup_1);
+	UART1_SendArray((uint8_t *)&ui_default_Ungroup_1,sizeof(ui_default_Ungroup_1));
+}
+
+/*==========指示灯==========*/
+ui_2_frame_t ui_default_Ungroup_2;
+ui_interface_round_t *ui_default_Ungroup_Round_Shift=(ui_interface_round_t *)&(ui_default_Ungroup_2.data[0]);
+ui_interface_round_t *ui_default_Ungroup_Round_Ctrl=(ui_interface_round_t *)&(ui_default_Ungroup_2.data[1]);
+
+void _ui_init_default_Ungroup_2(void)
+{
+    for(int i=0;i<2;i++)
+	{
+        ui_default_Ungroup_2.data[i].figure_name[0]=0;
+        ui_default_Ungroup_2.data[i].figure_name[1]=0;
+        ui_default_Ungroup_2.data[i].figure_name[2]=i+2;
+        ui_default_Ungroup_2.data[i].operate_tpye=1;
+    }
+
+    ui_default_Ungroup_Round_Shift->figure_tpye=2;
+    ui_default_Ungroup_Round_Shift->layer=0;
+    ui_default_Ungroup_Round_Shift->details_r=20;
+    ui_default_Ungroup_Round_Shift->start_x=250;
+    ui_default_Ungroup_Round_Shift->start_y=835;
+    ui_default_Ungroup_Round_Shift->color=2;
+    ui_default_Ungroup_Round_Shift->width=2;
+
+    ui_default_Ungroup_Round_Ctrl->figure_tpye=2;
+    ui_default_Ungroup_Round_Ctrl->layer=0;
+    ui_default_Ungroup_Round_Ctrl->details_r=20;
+    ui_default_Ungroup_Round_Ctrl->start_x=250;
+    ui_default_Ungroup_Round_Ctrl->start_y=735;
+    ui_default_Ungroup_Round_Ctrl->color=2;
+    ui_default_Ungroup_Round_Ctrl->width=2;
+
+    ui_proc_2_frame(&ui_default_Ungroup_2);
+	UART1_SendArray((uint8_t *)&ui_default_Ungroup_2,sizeof(ui_default_Ungroup_2));
+}
+
+void _ui_update_default_Ungroup_2_ERROR(void)
+{
+	ui_default_Ungroup_2.data[0].operate_tpye=2;
+	ui_default_Ungroup_2.data[1].operate_tpye=2;
+	
+	ui_default_Ungroup_Round_Shift->details_r=10;
+	ui_default_Ungroup_Round_Shift->start_x=240;
+	ui_default_Ungroup_Round_Shift->start_y=825;
+	ui_default_Ungroup_Round_Shift->color=0;
+	ui_default_Ungroup_Round_Shift->width=20;
+
+    ui_default_Ungroup_Round_Ctrl->details_r=10;
+    ui_default_Ungroup_Round_Ctrl->start_x=240;
+    ui_default_Ungroup_Round_Ctrl->start_y=725;
+    ui_default_Ungroup_Round_Ctrl->color=0;
+    ui_default_Ungroup_Round_Ctrl->width=20;
+	
+    ui_proc_2_frame(&ui_default_Ungroup_2);
+	UART1_SendArray((uint8_t *)&ui_default_Ungroup_2,sizeof(ui_default_Ungroup_2));
+}
+
+void _ui_update_default_Ungroup_2_NOCheck(void)
+{
+	ui_default_Ungroup_2.data[0].operate_tpye=2;
+	ui_default_Ungroup_2.data[1].operate_tpye=2;
+	
+    ui_default_Ungroup_Round_Shift->details_r=20;
+    ui_default_Ungroup_Round_Shift->start_x=250;
+    ui_default_Ungroup_Round_Shift->start_y=835;
+    ui_default_Ungroup_Round_Shift->color=2;
+    ui_default_Ungroup_Round_Shift->width=2;
+
+    ui_default_Ungroup_Round_Ctrl->details_r=20;
+    ui_default_Ungroup_Round_Ctrl->start_x=250;
+    ui_default_Ungroup_Round_Ctrl->start_y=735;
+    ui_default_Ungroup_Round_Ctrl->color=2;
+    ui_default_Ungroup_Round_Ctrl->width=2;
+	
+    ui_proc_2_frame(&ui_default_Ungroup_2);
+	UART1_SendArray((uint8_t *)&ui_default_Ungroup_2,sizeof(ui_default_Ungroup_2));
+}
+
+void _ui_update_default_Ungroup_2_Shift_Open(void)
+{
+	ui_default_Ungroup_2.data[0].operate_tpye=2;
+	ui_default_Ungroup_2.data[1].operate_tpye=0;
+	
+    ui_default_Ungroup_Round_Shift->details_r=10;
+    ui_default_Ungroup_Round_Shift->start_x=250;
+    ui_default_Ungroup_Round_Shift->start_y=835;
+    ui_default_Ungroup_Round_Shift->color=2;
+    ui_default_Ungroup_Round_Shift->width=20;
+	
+    ui_proc_2_frame(&ui_default_Ungroup_2);
+	UART1_SendArray((uint8_t *)&ui_default_Ungroup_2,sizeof(ui_default_Ungroup_2));
+}
+
+void _ui_update_default_Ungroup_2_Shift_Close(void)
+{
+	ui_default_Ungroup_2.data[0].operate_tpye=2;
+	ui_default_Ungroup_2.data[1].operate_tpye=0;
+	
+    ui_default_Ungroup_Round_Shift->details_r=20;
+    ui_default_Ungroup_Round_Shift->start_x=250;
+    ui_default_Ungroup_Round_Shift->start_y=835;
+    ui_default_Ungroup_Round_Shift->color=2;
+    ui_default_Ungroup_Round_Shift->width=2;
+	
+    ui_proc_2_frame(&ui_default_Ungroup_2);
+	UART1_SendArray((uint8_t *)&ui_default_Ungroup_2,sizeof(ui_default_Ungroup_2));
+}
+
+void _ui_update_default_Ungroup_2_Ctrl_Open(void)
+{
+	ui_default_Ungroup_2.data[0].operate_tpye=0;
+	ui_default_Ungroup_2.data[1].operate_tpye=2;
+	
+    ui_default_Ungroup_Round_Ctrl->details_r=10;
+    ui_default_Ungroup_Round_Ctrl->start_x=250;
+    ui_default_Ungroup_Round_Ctrl->start_y=735;
+    ui_default_Ungroup_Round_Ctrl->color=2;
+    ui_default_Ungroup_Round_Ctrl->width=20;
+	
+    ui_proc_2_frame(&ui_default_Ungroup_2);
+	UART1_SendArray((uint8_t *)&ui_default_Ungroup_2,sizeof(ui_default_Ungroup_2));
+}
+
+void _ui_update_default_Ungroup_2_Ctrl_Close(void)
+{
+	ui_default_Ungroup_2.data[0].operate_tpye=0;
+	ui_default_Ungroup_2.data[1].operate_tpye=2;
+	
+    ui_default_Ungroup_Round_Ctrl->details_r=20;
+    ui_default_Ungroup_Round_Ctrl->start_x=250;
+    ui_default_Ungroup_Round_Ctrl->start_y=735;
+    ui_default_Ungroup_Round_Ctrl->color=2;
+    ui_default_Ungroup_Round_Ctrl->width=2;
+	
+    ui_proc_2_frame(&ui_default_Ungroup_2);
+	UART1_SendArray((uint8_t *)&ui_default_Ungroup_2,sizeof(ui_default_Ungroup_2));
+}

底盘/底盘-old/底盘/CarBody/UI_Library.h

@@ -0,0 +1,23 @@
+#ifndef __UI_LIBRARY_H
+#define __UI_LIBRARY_H
+
+/*==========Shift文本==========*/
+void _ui_init_default_Ungroup_0(void);
+void _ui_update_default_Ungroup_0(void);
+void _ui_remove_default_Ungroup_0(void);
+
+/*==========Ctrl文本==========*/
+void _ui_init_default_Ungroup_1(void);
+void _ui_update_default_Ungroup_1(void);
+void _ui_remove_default_Ungroup_1(void);
+
+/*==========指示灯==========*/
+void _ui_init_default_Ungroup_2(void);
+void _ui_update_default_Ungroup_2_ERROR(void);
+void _ui_update_default_Ungroup_2_NOCheck(void);
+void _ui_update_default_Ungroup_2_Shift_Open(void);
+void _ui_update_default_Ungroup_2_Shift_Close(void);
+void _ui_update_default_Ungroup_2_Ctrl_Open(void);
+void _ui_update_default_Ungroup_2_Ctrl_Close(void);
+
+#endif

底盘/底盘-old/底盘/CarBody/Ultra_CAP.c

@@ -0,0 +1,122 @@
+#include "stm32f4xx.h"                  // Device header
+#include "stm32f4xx_conf.h"
+
+/*
+ *函数简介:超电使能
+ *参数说明:0-停机,1-运行(负载关),2-运行(负载开)
+ *返回类型:1-发送成功,0-发送失败
+ *备注:标识符0x600,数据长度4字节
+ */
+uint8_t Ultra_CAP_Enable(uint8_t EnableFlag)
+{
+	CanTxMsg TxMessage;
+	TxMessage.StdId=0x600;//ID标准标识符0x600
+	TxMessage.RTR=CAN_RTR_Data;//数据帧
+	TxMessage.IDE=CAN_Id_Standard;//标准格式
+	TxMessage.DLC=0x04;//4字节数据段
+	TxMessage.Data[0]=0;
+	TxMessage.Data[1]=EnableFlag;
+	TxMessage.Data[2]=0;
+	TxMessage.Data[3]=0;
+	
+	uint8_t mbox=CAN_Transmit(CAN1,&TxMessage);//发送数据并获取邮箱号
+	uint16_t i=0;
+	while((CAN_TransmitStatus(CAN1,mbox)==CAN_TxStatus_Failed)&&(i<0xFFF))i++;//等待发送结束
+	if(i>=0xFFF)return 0;//发送失败
+	return 1;//发送成功
+}
+
+/*
+ *函数简介:超电设置电压上限
+ *参数说明:电压
+ *返回类型:1-发送成功,0-发送失败
+ *备注:标识符0x602,数据长度4字节,默认存入EEPROM
+ *备注:设定值=电压*100
+ */
+uint8_t Ultra_CAP_SetVoltage(float Voltage)
+{
+	uint16_t SetVoltage=(uint16_t)((int16_t)(Voltage*100.0f));
+	CanTxMsg TxMessage;
+	TxMessage.StdId=0x602;//ID标准标识符0x602
+	TxMessage.RTR=CAN_RTR_Data;//数据帧
+	TxMessage.IDE=CAN_Id_Standard;//标准格式
+	TxMessage.DLC=0x04;//4字节数据段
+	TxMessage.Data[0]=(uint8_t)(SetVoltage>>8);
+	TxMessage.Data[1]=(uint8_t)(SetVoltage & 0x00FF);
+	TxMessage.Data[2]=0;
+	TxMessage.Data[3]=0x01;
+	
+	uint8_t mbox=CAN_Transmit(CAN1,&TxMessage);//发送数据并获取邮箱号
+	uint16_t i=0;
+	while((CAN_TransmitStatus(CAN1,mbox)==CAN_TxStatus_Failed)&&(i<0xFFF))i++;//等待发送结束
+	if(i>=0xFFF)return 0;//发送失败
+	return 1;//发送成功
+}
+
+/*
+ *函数简介:超电设置电流上限
+ *参数说明:无
+ *返回类型:1-发送成功,0-发送失败
+ *备注:标识符0x603,数据长度4字节,默认存入EEPROM
+ *备注:设定值=电流*100
+ */
+uint8_t Ultra_CAP_SetCurrent(float Current)
+{
+	uint16_t SetCurrent=(uint16_t)((int16_t)(Current*100.0f));
+	CanTxMsg TxMessage;
+	TxMessage.StdId=0x603;//低位ID标准标识符0x603
+	TxMessage.RTR=CAN_RTR_Data;//数据帧
+	TxMessage.IDE=CAN_Id_Standard;//标准格式
+	TxMessage.DLC=0x04;//4字节数据段
+	TxMessage.Data[0]=(uint8_t)(SetCurrent>>8);
+	TxMessage.Data[1]=(uint8_t)(SetCurrent & 0x00FF);
+	TxMessage.Data[2]=0;
+	TxMessage.Data[3]=0x01;
+	
+	uint8_t mbox=CAN_Transmit(CAN1,&TxMessage);//发送数据并获取邮箱号
+	uint16_t i=0;
+	while((CAN_TransmitStatus(CAN1,mbox)==CAN_TxStatus_Failed)&&(i<0xFFF))i++;//等待发送结束
+	if(i>=0xFFF)return 0;//发送失败
+	return 1;//发送成功
+}
+
+/*
+ *函数简介:超电设置功率上限
+ *参数说明:无
+ *返回类型:1-发送成功,0-发送失败
+ *备注:标识符0x601,数据长度4字节
+ *备注:设定值=功率*100
+ */
+uint8_t Ultra_CAP_SetPower(float PowerLimit)
+{	
+	uint16_t SetPower=(uint16_t)((int16_t)(PowerLimit*100.0f));
+	CanTxMsg TxMessage;
+	TxMessage.StdId=0x601;//低位ID标准标识符0x601
+	TxMessage.RTR=CAN_RTR_Data;//数据帧
+	TxMessage.IDE=CAN_Id_Standard;//标准格式
+	TxMessage.DLC=0x04;//4字节数据段
+	TxMessage.Data[0]=(uint8_t)(SetPower>>8);
+	TxMessage.Data[1]=(uint8_t)(SetPower & 0x00FF);
+	TxMessage.Data[2]=0;
+	TxMessage.Data[3]=0;
+	
+	uint8_t mbox=CAN_Transmit(CAN1,&TxMessage);//发送数据并获取邮箱号
+	uint16_t i=0;
+	while((CAN_TransmitStatus(CAN1,mbox)==CAN_TxStatus_Failed)&&(i<0xFFF))i++;//等待发送结束
+	if(i>=0xFFF)return 0;//发送失败
+	return 1;//发送成功
+}
+
+/*
+ *函数简介:超电初始化
+ *参数说明:无
+ *返回类型:无
+ *备注:默认设定电压23V,电流8A,功率150W
+ */
+void Ultra_CAP_Init(void)
+{
+	Ultra_CAP_SetVoltage(23.0f);
+	Ultra_CAP_SetCurrent(8.0f);
+	Ultra_CAP_Enable(2);
+	Ultra_CAP_SetPower(150.0f);
+}

底盘/底盘-old/底盘/CarBody/Ultra_CAP.h

@@ -0,0 +1,7 @@
+#ifndef __ULTRA_CAP_H
+#define __ULTRA_CAP_H
+
+void Ultra_CAP_Init(void);//超电初始化
+uint8_t Ultra_CAP_SetPower(float PowerLimit);//超电设置功率上限
+
+#endif

底盘/底盘-old/底盘/CarBody/sys.h

@@ -0,0 +1,598 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : Referee_System.h
+  * @brief          : The header file of Referee_System.c
+  * @author         : GrassFan Wang
+  * @date           : 2025/01/22
+  * @version        : v1.0
+  ******************************************************************************
+  * @attention      : None
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef REFEREE_INFO_H
+#define REFEREE_INFO_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stdint.h"
+#include "stdbool.h"
+
+/* Exported defines ----------------------------------------------------------*/
+
+#define REFEREE_RXFRAME_LENGTH  136
+
+/**
+ * @brief Referee Communication protocol format
+ */
+#define FrameHeader_Length    5U   /*!< the length of frame header */
+#define CMDID_Length          2U   /*!< the length of CMD ID */
+#define CRC16_Length          2U   /*!< the length of CRC ID */
+
+/**
+ * @brief Cmd id
+ */
+#define GAME_STATUS_ID                    0x0001U  /*!< game status data */
+#define GAME_RESULT_ID                    0x0002U  /*!< game result data */
+#define GAME_ROBOTHP_ID                   0x0003U  /*!< robot HP data */
+#define EVENE_DATA_ID                     0x0101U  /*!< site event data */
+#define SUPPLY_ACTION_ID                  0x0102U  /*!< supply station action data */
+#define REFEREE_WARNING_ID                0x0104U  /*!< referee warning data */
+#define DART_INFO_ID                      0x0105U  /*!< dart shoot data */
+#define ROBOT_STATUS_ID                   0x0201U  /*!< robot status data */
+#define POWER_HEAT_ID                     0x0202U  /*!< real power heat data */
+#define ROBOT_POSITION_ID                 0x0203U  /*!< robot position data */
+#define ROBOT_BUFF_ID                     0x0204U  /*!< robot buff data */
+#define AIR_SUPPORT_ID                    0x0205U  /*!< aerial robot energy data */
+#define ROBOT_HURT_ID                     0x0206U  /*!< robot hurt data */
+#define SHOOT_DATA_ID                     0x0207U  /*!< real robo t shoot data */
+#define PROJECTILE_ALLOWANCE_ID           0x0208U  /*!< bullet remain data */
+#define RFID_STATUS_ID                    0x0209U  /*!< RFID status data */
+#define DART_CLIENT_CMD_ID                0x020AU  /*!< DART Client cmd data */
+#define GROUND_ROBOT_POSITION_ID          0x020BU  /*!< ground robot position */
+#define RADAR_MARAKING_DATA_ID            0x020CU  /*!< Radar marking progress*/
+#define SENTRY_INFO_ID                    0X020DU  /*!< SENTRY make autonomous decisions*/
+#define RADAR_INFO_ID                     0X020EU  /*!< RADAR make autonomous decisions*/
+
+#define INTERACTIVE_DATA_ID               0x0301U  /*!< robot interactive data */
+#define CUSTOM_CONTROLLER_ID              0x0302U  /*!< custom controller data */
+#define MINIMAP_INTERACTIVE_ID            0x0303U  /*!< mini map interactive data */
+#define KEYMOUSE_INFO_ID                  0x0304U  /*!< key mouse data according the image transmission */
+#define MINIMAP_RECV_ID                   0x0305U  /*!< mini map receive data */
+#define CUSTOM_CONTROLLER_INTERACTIVE_ID  0x0306U  /*!< mini map receive data */
+#define MAP_SENTRY_DATA_ID                0x0307U  /*!< mini map sentry path */
+#define MAP_ROBOT_DATA_ID                 0x0308U  /*!< mini map robot  path */
+/**
+ * @brief Robot id
+ */
+#define ROBOT_RED_HERO_ID                 0x0001U
+#define ROBOT_RED_ENGINEER_ID             0x0002U
+#define ROBOT_RED_3_INFANTEY_ID           0x0003U
+#define ROBOT_RED_4_INFANTEY_ID           0x0004U
+#define ROBOT_RED_5_INFANTEY_ID           0x0005U
+#define ROBOT_RED_AERIAL_INFANTEY_ID      0x0006U
+#define ROBOT_RED_SENTEY_INFANTEY_ID      0x0007U
+#define ROBOT_RED_DART_INFANTEY_ID        0x0008U
+#define ROBOT_RED_RADAR_INFANTEY_ID       0x0009U
+#define ROBOT_RED_OUTPOST_INFANTEY_ID     0x0010U
+#define ROBOT_RED_BASE_INFANTEY_ID        0x0011U
+
+#define ROBOT_BLUE_HERO_ID                0x0101U
+#define ROBOT_BLUE_ENGINEER_ID            0x0102U
+#define ROBOT_BLUE_3_INFANTEY_ID          0x0103U
+#define ROBOT_BLUE_4_INFANTEY_ID          0x0104U
+#define ROBOT_BLUE_5_INFANTEY_ID          0x0105U
+#define ROBOT_BLUE_AERIAL_INFANTEY_ID     0x0106U
+#define ROBOT_BLUE_SENTEY_INFANTEY_ID     0x0107U
+#define ROBOT_BLUE_DART_INFANTEY_ID       0x0108U
+#define ROBOT_BLUE_RADAR_INFANTEY_ID      0x0109U
+#define ROBOT_BLUE_OUTPOST_INFANTEY_ID    0x0110U
+#define ROBOT_BLUE_BASE_INFANTEY_ID       0x0111U
+
+/**
+ * @brief client id
+ */
+#define CLIENT_RED_HERO_ID                0x0101U
+#define CLIENT_RED_ENGINEER_ID            0x0102U
+#define CLIENT_RED_3_INFANTEY_ID          0x0103U
+#define CLIENT_RED_4_INFANTEY_ID          0x0104U
+#define CLIENT_RED_5_INFANTEY_ID          0x0105U
+#define CLIENT_RED_AERIAL_INFANTEY_ID     0x0106U
+
+#define CLIENT_BLUE_HERO_ID               0x0165U
+#define CLIENT_BLUE_ENGINEER_ID           0x0166U
+#define CLIENT_BLUE_3_INFANTEY_ID         0x0167U
+#define CLIENT_BLUE_4_INFANTEY_ID         0x0168U
+#define CLIENT_BLUE_5_INFANTEY_ID         0x0169U
+#define CLIENT_BLUE_AERIAL_INFANTEY_ID    0x016AU
+
+/* Exported types ------------------------------------------------------------*/
+/* cancel byte alignment */
+#pragma  pack(1)
+
+/**
+ * @brief typedef structure that contains the information of frame header
+ */
+typedef struct 
+{
+  uint8_t  SOF;           /*!< Data frame start byte, fixed value is 0xA5 */
+  uint16_t Data_Length;   /*!< the length of data in the data frame */
+  uint8_t  Seq;           /*!< package serial number */
+  uint8_t  CRC8;          /*!< Frame header CRC8 checksum */
+}FrameHeader_TypeDef;
+
+
+/**
+ * @brief typedef structure that contains the information of game status, id: 0x0001U
+ */
+typedef struct          
+{
+  /**
+   * @brief the type of game,
+            1:RMUC,
+            2:RMUT,
+            3:RMUA,
+            4:RMUL,3v3,
+            5:RMUL,1v1,
+   */
+	 uint8_t game_type : 4;        
+	 uint8_t game_progress : 4;	    /*!< the progress of game */
+	 uint16_t stage_remain_time;	    /*!< remain time of real progress */
+   uint64_t SyncTimeStamp;         /*!< unix time */
+       
+}game_status_t;
+
+/**
+ * @brief typedef structure that contains the information of game result, id: 0x0002U
+ */
+typedef struct
+{
+  /**
+   * @brief the result of game
+            0:draw
+            1:Red wins
+            2:Blue wins
+   */
+ uint8_t winner;
+}game_result_t;
+
+/**
+ * @brief typedef structure that contains the information of robot HP data, id: 0x0003U
+ */
+typedef struct
+{
+  uint16_t red_1_robot_HP;   /*!< Red Hero HP */
+  uint16_t red_2_robot_HP;   /*!< Red Engineer HP */
+  uint16_t red_3_robot_HP;   /*!< Red 3 Infantry HP */
+  uint16_t red_4_robot_HP;   /*!< Red 4 Infantry HP */
+  uint16_t red_reserved;          
+  uint16_t red_7_robot_HP;   /*!< Red Sentry HP */
+  uint16_t red_outpost_HP;   /*!< Red Outpost HP */
+  uint16_t red_base_HP;      /*!< Red Base HP */
+
+  uint16_t blue_1_robot_HP;   /*!< Blue Hero HP */
+  uint16_t blue_2_robot_HP;   /*!< Blue Engineer HP */
+  uint16_t blue_3_robot_HP;   /*!< Blue 3 Infantry HP */
+  uint16_t blue_4_robot_HP;   /*!< Blue 4 Infantry HP */
+  uint16_t blue_reserved;  
+  uint16_t blue_7_robot_HP;   /*!< Blue Sentry HP */
+  uint16_t blue_outpost_HP;   /*!< Blue Outpost HP */
+  uint16_t blue_base_HP;      /*!< Blue Base HP */
+} game_robot_HP_t;
+
+/**
+ * @brief typedef structure that contains the information of site event data, id: 0x0101U
+ */
+typedef union
+{
+    /**
+     * @brief the event of site
+	            bits 0-2:
+              bit 0:  Status of the supply zone that does not overlap with the exchange zone, 1 for occupied
+              bit 1:  Status of the supply zone that overlaps with the exchange zone, 1 for occupied
+              bit 2:  Status of the supply zone, 1 for occupied (applicable only to RMUL)
+	
+	            bits 3-5: Status of the energy mechanism:
+              bit 3:    Status of the small energy mechanism, 1 for activated
+              bit 4:    Status of the large energy mechanism, 1 for activated
+              bit 5-6:  Status of the central highland, 1 for occupied by own side, 2 for occupied by the opponent
+              bit 7-8:  Status of the trapezoidal highland, 1 for occupied
+              bit 9-17: Time of the opponent's last dart hit on the own side's outpost or base (0-420, default is 0 at the start)
+	            bit 18-20:  Specific target of the opponent's last dart hit on the own side's outpost or base, default is 0 at the start, 
+	                        1 for hitting the outpost, 2 for hitting the fixed target on the base, 3 for hitting the random fixed target on the base, 
+	                        4 for hitting the random moving target on the base
+	            bit 21-22: Status of the central gain point, 0 for unoccupied, 1 for occupied by own side, 
+	                       2 for occupied by the opponent, 3 for occupied by both sides (applicable only to RMUL)               
+              bit 23-31: Reserved
+                        
+    */
+    uint32_t  event_data;
+}event_data_t;
+
+/**
+ * @brief typedef structure that contains the warning  of Referee , id: 0x0104U
+ */
+typedef struct 
+{ 
+	/**
+   * @brief the type of game,
+            1: Double Yellow Card,
+            2: Yellow Card,
+            3:RMUA,
+            4:RMUL,3v3,
+            5:RMUL,1v1,
+   */
+  uint8_t level; 
+  uint8_t offending_robot_id; 
+  uint8_t count; 
+}referee_warning_t; 
+
+/**
+ * @brief typedef structure that contains the information of dart, id: 0x0105U
+ */
+typedef  struct
+{
+ 
+ uint8_t dart_remaining_time;/* The remaining time for our side's dart launcher, in seconds.*/
+ 
+ uint16_t dart_info;
+  /**
+   * @brief dart_info
+   *       bit 0-2 The most recent target hit by our side's dart is defaulted to 0 at the start, 
+	                 where 1 indicates hitting the outpost, 2 indicates hitting the base's fixed target, 
+	                 3 indicates hitting the base's random fixed target, and 4 indicates hitting the base's random moving target.
+   *       bit 3-5 The cumulative hit count of the opponent's recently hit target (defaulting to 0 at the start, with a maximum of 4)
+   *       bit 6-7 The currently selected target for the dart (defaulting to 0 at the start or when not selected/selecting the outpost, 
+	                 1 for selecting the base's fixed target, 2 for selecting the base's random fixed target, 3 for selecting the base's random moving target)
+   *       bit 8-15 Reserved
+   */
+}dart_info_t;
+
+
+
+/**
+ * @brief typedef structure that contains the information of robot status, id: 0x0201U
+ */
+typedef struct
+{
+  /**
+   * @brief robot id
+   *             0: robot none
+   *             1: red hero
+   *             2: red engineer
+   *         3/4/5: red infantry
+   *             6: red aerial
+   *             7: red sentry
+   *             8: red dart
+   *             9: red radar station
+   *           101: blue hero
+   *           102: blue engineer
+   *   103/104/105: blue infantry
+   *           106: blue aerial
+   *           107: blue sentry
+   *           108: blue dart
+   *           109: blue radar station
+   */
+  uint8_t robot_id;
+  uint8_t robot_level;
+  uint16_t current_HP;
+  uint16_t maximum_HP;
+
+  uint16_t shooter_barrel_cooling_value;
+  uint16_t shooter_barrel_heat_limit;
+  uint16_t chassis_power_limit;
+
+  uint8_t mains_power_gimbal_output : 1;
+  uint8_t mains_power_chassis_output : 1;
+  uint8_t mains_power_shooter_output : 1;
+} robot_status_t;
+
+/**
+ * @brief typedef structure that contains the information of power heat data, id: 0x0202U
+ */
+typedef struct
+{
+  uint16_t buffer_energy;
+  uint16_t shooter_17mm_1_barrel_heat;
+  uint16_t shooter_17mm_2_barrel_heat;
+  uint16_t shooter_42mm_barrel_heat;
+} power_heat_data_t;
+
+/**
+ * @brief typedef structure that contains the information of robot position data, id: 0x0203U
+ */
+typedef struct
+{
+  float x;    /*!< position x coordinate, unit: m */
+  float y;    /*!< position y coordinate, unit: m */
+  float  angle;  /*!< Position muzzle, unit: degrees */
+} robot_pos_t;
+
+/**
+ * @brief typedef structure that contains the information of robot buff data, id: 0x0204U
+ */
+typedef union
+{
+  uint8_t recovery_buff;
+  uint8_t cooling_buff;
+  uint8_t defence_buff;
+  uint8_t vulnerability_buff;
+  uint16_t attack_buff;
+	uint8_t remaining_energy;
+}buff_t;
+/**
+ * @brief typedef structure that contains the information of robot hurt, id: 0x0206U
+ */
+typedef struct
+{
+ uint8_t armor_id : 4; /*!< hurt armor id */
+  /**
+   * @brief hurt type
+   *        0: armor hurt
+   *        1: module offline
+   *        2: over fire rate
+   *        3: over fire heat
+   *        4: over chassis power
+   *        5: armor bump
+   */
+ uint8_t HP_deduction_reason : 4;
+}hurt_data_t;
+
+/**
+ * @brief typedef structure that contains the information of real shoot data, id: 0x0207U
+ */
+typedef  struct
+{
+  uint8_t bullet_type;  
+  uint8_t shooter_number; 
+  uint8_t launching_frequency;  
+  float initial_speed;  
+}shoot_data_t;
+
+/**
+ * @brief typedef structure that contains the information of bullet remaining number, id: 0x0208U
+ */
+typedef  struct
+{
+  uint16_t projectile_allowance_17mm; 
+  uint16_t projectile_allowance_42mm;  
+  uint16_t remaining_gold_coin; 
+}projectile_allowance_t;;
+
+/**
+ * @brief typedef structure that contains the information of RFID status, id: 0x0209U
+ */
+typedef union
+{
+ uint32_t rfid_status;
+}rfid_status_t;
+
+/**
+ * @brief typedef structure that contains the information of dart client data, id: 0x020AU
+ */
+typedef  struct
+{
+ uint8_t dart_launch_opening_status;
+ uint8_t reserved;
+ uint16_t target_change_time;
+ uint16_t latest_launch_cmd_time;
+}dart_client_cmd_t;
+
+/**
+ * @brief typedef structure that contains the information of robot position in mimi map, id: 0x020BU
+ */
+typedef struct
+{
+  float hero_x;
+  float hero_y;
+  float engineer_x;
+  float engineer_y;
+  float standard_3_x;
+  float standard_3_y;
+  float standard_4_x;
+  float standard_4_y;
+}ground_robot_position_t;
+
+/**
+ * @brief typedef structure that contains the information of robot mark, id: 0x020C
+ */
+typedef struct
+{
+  uint8_t mark_progress; 
+}radar_mark_data_t;
+
+/**
+ * @brief typedef structure that contains the information of robot mark, id: 0x020D
+ */
+typedef  struct
+{
+  uint32_t sentry_info; 
+  uint16_t sentry_info_2; 
+} sentry_info_t;
+
+/**
+ * @brief typedef structure that contains the information of radar, id: 0x020E
+ */
+typedef  struct
+{
+ uint8_t radar_info;
+}radar_info_t;
+/**
+ * @brief typedef structure that contains the information of custom controller interactive, id: 0x0301U
+ */
+typedef struct{ 
+ uint16_t data_cmd_id;
+ uint16_t sender_id;
+ uint16_t receiver_id;
+ uint8_t user_data[113];
+}robot_interaction_data_t;
+/**
+ * @brief typedef structure that contains the information of custom controller interactive, id: 0x0302U
+ */
+typedef struct 
+{
+  uint8_t data[30];
+} custom_robot_data_t;
+
+/**
+ * @brief typedef structure that contains the information of client transmit data, id: 0x0303U
+ */
+typedef struct
+{
+  /**
+   * @brief target position coordinate, is 0 when transmit target robot id
+   */
+  float target_position_x;
+  float target_position_y;
+  float target_position_z;
+
+  uint8_t commd_keyboard;
+  uint16_t target_robot_ID;   /* is 0 when transmit position data */
+} ext_robot_command_t;
+
+/**
+ * @brief typedef structure that contains the information of client receive data, id: 0x0305U
+ */
+typedef struct
+{
+  uint16_t target_robot_ID;
+  float target_position_x;
+  float target_position_y;
+} ext_client_map_command_t;
+
+/**
+ * @brief typedef structure that contains the information of custom controller key mouse, id: 0x0306U
+ */
+typedef struct
+{
+ uint16_t key_value;
+ uint16_t x_position:12;
+ uint16_t mouse_left:4;
+ uint16_t y_position:12;
+ uint16_t mouse_right:4;
+ uint16_t reserved;
+}custom_client_data_t;
+
+/**
+ * @brief typedef structure that contains the information of sentry path, id: 0x0307U
+ */
+typedef struct
+{
+  /**
+   * @brief  sentry status
+   *         1: attack on target point
+   *         2: defend on target point
+   *         3: move to target point
+   */
+  uint8_t intention;
+  uint16_t start_position_x;
+  uint16_t start_position_y;
+  int8_t delta_x[49];
+  int8_t delta_y[49];
+}map_sentry_data_t;
+
+/**
+ * @brief typedef structure that contains the information of Referee
+ */
+typedef struct 
+{
+  uint8_t Index;
+  uint16_t DataLength;
+  
+#ifdef GAME_STATUS_ID
+  game_status_t game_status;
+#endif
+
+#ifdef GAME_RESULT_ID
+  game_result_t game_result;
+#endif
+
+#ifdef  GAME_ROBOTHP_ID
+	game_robot_HP_t game_robot_HP;
+#endif	
+	
+#ifdef EVENE_DATA_ID
+  event_data_t event_data;
+#endif
+
+#ifdef REFEREE_WARNING_ID
+    referee_warning_t referee_warning;
+#endif
+
+#ifdef DART_INFO_ID
+  dart_info_t dart_info;
+#endif
+
+#ifdef ROBOT_STATUS_ID
+  robot_status_t robot_status;
+#endif
+
+#ifdef POWER_HEAT_ID
+  power_heat_data_t power_heat_data;
+#endif
+
+#ifdef ROBOT_POSITION_ID
+  robot_pos_t  robot_pos;
+#endif
+
+#ifdef ROBOT_BUFF_ID
+  buff_t  buff;
+#endif
+
+#ifdef ROBOT_HURT_ID
+  hurt_data_t  hurt_data;
+#endif
+
+#ifdef SHOOT_DATA_ID
+  shoot_data_t  shoot_data;
+#endif
+
+#ifdef PROJECTILE_ALLOWANCE_ID
+  projectile_allowance_t projectile_allowance;
+#endif
+#ifdef  RFID_STATUS_ID
+    rfid_status_t rfid_status;
+#endif
+
+#ifdef DART_CLIENT_CMD_ID
+    dart_client_cmd_t  dart_client_cmd;
+#endif
+
+#ifdef GROUND_ROBOT_POSITION_ID
+    ground_robot_position_t  ground_robot_position;
+#endif 
+
+#ifdef RADAR_MARAKING_DATA_ID
+    radar_mark_data_t  radar_mark_data;
+#endif
+
+#ifdef SENTRY_INFO_ID
+    sentry_info_t  sentry_info;
+#endif
+
+#ifdef RADAR_INFO_ID
+    radar_info_t  radar_info;
+#endif
+}Referee_System_Info_TypeDef;
+
+/* restore byte alignment */
+#pragma  pack()
+
+/* Exported variables ---------------------------------------------------------*/
+/**
+ * @brief Referee_RxDMA MultiBuffer
+ */
+extern uint8_t Referee_System_Info_MultiRx_Buf[2][REFEREE_RXFRAME_LENGTH];
+
+/**
+ * @brief Referee structure variable
+ */
+extern Referee_System_Info_TypeDef Referee_Info;
+
+
+/* Exported functions prototypes ---------------------------------------------*/
+extern void Referee_System_Frame_Update(uint8_t *Buff);
+
+#endif //REFEREE_INFO_H

底盘/底盘-old/底盘/Control/PID.c

@@ -0,0 +1,202 @@
+#include "stm32f4xx.h"                  // Device header
+#include "stm32f4xx_conf.h"
+#include "PID.h"
+
+/*
+ *函数简介:位置式PID初始化结构体
+ *参数说明:位置式PID参数结构体
+ *参数说明:预期值
+ *返回类型:无
+ *备注:无
+ */
+void PID_PositionStructureInit(PID_PositionInitTypedef* PID_InitStructure,float NeedValue)
+{
+	PID_InitStructure->Need_Value=NeedValue;
+	PID_InitStructure->Ek=0;
+	PID_InitStructure->Sum_Ek=0;
+	PID_InitStructure->Ek_low=0;
+	PID_InitStructure->Ek_up=0;
+	PID_InitStructure->Kp=0;
+	PID_InitStructure->Ki=0;
+	PID_InitStructure->Kd=0;
+	PID_InitStructure->OUT_low=-1e10;
+	PID_InitStructure->OUT_up=1e10;
+}
+
+/*
+ *函数简介:位置式PID设置参数
+ *参数说明:位置式PID参数结构体
+ *参数说明:单精度浮点型Kp
+ *参数说明:单精度浮点型Ki
+ *参数说明:单精度浮点型Kd
+ *返回类型:无
+ *备注:无
+ */
+void PID_PositionSetParameter(PID_PositionInitTypedef* PID_InitStructure,float kp,float ki,float kd)
+{
+	PID_InitStructure->Kp=kp;
+	PID_InitStructure->Ki=ki;
+	PID_InitStructure->Kd=kd;
+}
+
+/*
+ *函数简介:位置式PID设置误差为0阈值
+ *参数说明:位置式PID参数结构体
+ *参数说明:误差为0阈值下限
+ *参数说明:误差为0阈值上限
+ *返回类型:无
+ *备注:无
+ */
+void PID_PositionSetEkRange(PID_PositionInitTypedef* PID_InitStructure,float ek_low,float ek_up)
+{
+	PID_InitStructure->Ek_low=ek_low;
+	PID_InitStructure->Ek_up=ek_up;
+}
+
+/*
+ *函数简介:位置式PID设置输出限幅
+ *参数说明:位置式PID参数结构体
+ *参数说明:输出限幅下限
+ *参数说明:输出限幅上限
+ *返回类型:无
+ *备注:无
+ */
+void PID_PositionSetOUTRange(PID_PositionInitTypedef* PID_InitStructure,float out_low,float out_up)
+{
+	PID_InitStructure->OUT_low=out_low;
+	PID_InitStructure->OUT_up=out_up;
+}
+
+/*
+ *函数简介:位置式PID清理
+ *参数说明:位置式PID参数结构体
+ *返回类型:无
+ *备注:使Ek和Sum为0
+ */
+void PID_PositionClean(PID_PositionInitTypedef* PID_InitStructure)
+{
+	PID_InitStructure->Ek=0;
+	PID_InitStructure->Sum_Ek=0;
+}
+
+/*
+ *函数简介:位置式PID计算
+ *参数说明:位置式PID参数结构体
+ *参数说明:当前值
+ *返回类型:无
+ *备注:OUT=POUT+IOUT+DOUT=Kp*Ek+Ki*ΣEk+Kd*(Ek-Ek_1)
+ *备注:计算结果保存在位置式PID参数结构体中
+ */
+void PID_PositionCalc(PID_PositionInitTypedef* PID_InitStructure,float NowValue)
+{
+	PID_InitStructure->Now_Value=NowValue;
+	PID_InitStructure->Ek_1=PID_InitStructure->Ek;
+	PID_InitStructure->Ek=PID_InitStructure->Need_Value-PID_InitStructure->Now_Value;
+	if(PID_InitStructure->Ek_low<PID_InitStructure->Ek&&PID_InitStructure->Ek<PID_InitStructure->Ek_up)//误差为0检测
+		PID_InitStructure->Ek=0;
+	PID_InitStructure->Sum_Ek+=PID_InitStructure->Ek;
+	PID_InitStructure->Del_Ek=PID_InitStructure->Ek-PID_InitStructure->Ek_1;
+
+	PID_InitStructure->P_OUT=PID_InitStructure->Kp*PID_InitStructure->Ek;
+	PID_InitStructure->I_OUT=PID_InitStructure->Ki*PID_InitStructure->Sum_Ek;
+	PID_InitStructure->D_OUT=PID_InitStructure->Kd*PID_InitStructure->Del_Ek;
+	PID_InitStructure->OUT=PID_InitStructure->P_OUT+PID_InitStructure->I_OUT+PID_InitStructure->D_OUT;
+	
+	if(PID_InitStructure->OUT<PID_InitStructure->OUT_low)//输出限幅
+		PID_InitStructure->OUT=PID_InitStructure->OUT_low;
+	if(PID_InitStructure->OUT>PID_InitStructure->OUT_up)
+		PID_InitStructure->OUT=PID_InitStructure->OUT_up;
+}
+
+/*
+ *函数简介:增量式PID初始化结构体
+ *参数说明:增量式PID参数结构体
+ *参数说明:预期值
+ *返回类型:无
+ *备注:无
+ */
+void PID_IncrementalStructureInit(PID_IncrementalInitTypedef* PID_InitStructure,float NeedValue)
+{
+	PID_InitStructure->Need_Value=NeedValue;
+	PID_InitStructure->Ek=0;
+	PID_InitStructure->Ek_1=0;
+	PID_InitStructure->Ek_low=0;
+	PID_InitStructure->Ek_up=0;
+	PID_InitStructure->Kp=0;
+	PID_InitStructure->Ki=0;
+	PID_InitStructure->Kd=0;
+	PID_InitStructure->OUT_low=-1e10;
+	PID_InitStructure->OUT_up=1e10;
+}
+
+/*
+ *函数简介:增量式PID设置参数
+ *参数说明:增量式PID参数结构体
+ *参数说明:单精度浮点型Kp
+ *参数说明:单精度浮点型Ki
+ *参数说明:单精度浮点型Kd
+ *返回类型:无
+ *备注:无
+ */
+void PID_IncrementalSetParameter(PID_IncrementalInitTypedef* PID_InitStructure,float kp,float ki,float kd)
+{
+	PID_InitStructure->Kp=kp;
+	PID_InitStructure->Ki=ki;
+	PID_InitStructure->Kd=kd;
+}
+
+/*
+ *函数简介:增量式PID设置误差为0阈值
+ *参数说明:增量式PID参数结构体
+ *参数说明:误差为0阈值下限
+ *参数说明:误差为0阈值上限
+ *返回类型:无
+ *备注:无
+ */
+void PID_IncrementalSetEkRange(PID_IncrementalInitTypedef* PID_InitStructure,float ek_low,float ek_up)
+{
+	PID_InitStructure->Ek_low=ek_low;
+	PID_InitStructure->Ek_up=ek_up;
+}
+
+/*
+ *函数简介:增量式PID设置输出限幅
+ *参数说明:增量式PID参数结构体
+ *参数说明:输出限幅下限
+ *参数说明:输出限幅上限
+ *返回类型:无
+ *备注:无
+ */
+void PID_IncrementalSetOUTRange(PID_IncrementalInitTypedef* PID_InitStructure,float out_low,float out_up)
+{
+	PID_InitStructure->OUT_low=out_low;
+	PID_InitStructure->OUT_up=out_up;
+}
+
+/*
+ *函数简介:增量式PID计算
+ *参数说明:增量式PID参数结构体
+ *参数说明:当前值
+ *返回类型:无
+ *备注:OUT=POUT+IOUT+DOUT=Kp*ΔEk+Ki*ΣΔEk+Kd*(ΔEk-ΔEk_1)=Kp*(Ek-Ek_1)+Ki*Ek+Kd*(Ek-2*Ek_1+Ek_2)
+ *备注:计算结果保存在增量式PID参数结构体中
+ */
+void PID_IncrementalCalc(PID_IncrementalInitTypedef* PID_InitStructure,float NowValue)
+{
+	PID_InitStructure->Now_Value=NowValue;
+	PID_InitStructure->Ek_2=PID_InitStructure->Ek_1;
+	PID_InitStructure->Ek_1=PID_InitStructure->Ek;
+	PID_InitStructure->Ek=PID_InitStructure->Need_Value-PID_InitStructure->Now_Value;
+	if(PID_InitStructure->Ek_low<PID_InitStructure->Ek&&PID_InitStructure->Ek<PID_InitStructure->Ek_up)//误差为0检测
+		PID_InitStructure->Ek=0;
+
+	PID_InitStructure->P_OUT=PID_InitStructure->Kp*(PID_InitStructure->Ek-PID_InitStructure->Ek_1);
+	PID_InitStructure->I_OUT=PID_InitStructure->Ki*PID_InitStructure->Ek;
+	PID_InitStructure->D_OUT=PID_InitStructure->Kd*(PID_InitStructure->Ek-2*PID_InitStructure->Ek_1+PID_InitStructure->Ek_2);
+	PID_InitStructure->OUT=PID_InitStructure->P_OUT+PID_InitStructure->I_OUT+PID_InitStructure->D_OUT;
+	
+	if(PID_InitStructure->OUT<PID_InitStructure->OUT_low)//输出限幅
+		PID_InitStructure->OUT=PID_InitStructure->OUT_low;
+	if(PID_InitStructure->OUT>PID_InitStructure->OUT_up)
+		PID_InitStructure->OUT=PID_InitStructure->OUT_up;
+}

底盘/底盘-old/底盘/Control/PID.h

@@ -0,0 +1,63 @@
+#ifndef __PID_H__
+#define __PID_H__
+
+typedef struct
+{
+	float Need_Value;//预期值
+	float Now_Value;//当前值
+
+	float Ek;//本次误差
+	float Ek_1;//上一次误差
+	float Sum_Ek;//误差积分
+	float Del_Ek;//误差差分
+	float Ek_low;//误差为0阈值下限
+	float Ek_up;//误差为0阈值上限
+
+	float Kp;//Kp
+	float Ki;//Ki
+	float Kd;//Kd
+
+	float P_OUT;//比例输出
+	float I_OUT;//积分输出
+	float D_OUT;//微分输出
+	float OUT;//总输出
+	float OUT_low;//输出限幅下限
+	float OUT_up;//输出限幅上限
+}PID_PositionInitTypedef;//位置式PID参数结构体
+
+typedef struct
+{
+	float Need_Value;//预期值
+	float Now_Value;//当前值
+
+	float Ek;//本次误差
+	float Ek_1;//上一次误差
+	float Ek_2;//上两次误差
+	float Ek_low;//误差为0阈值下限
+	float Ek_up;//误差为0阈值上限
+
+	float Kp;//Kp
+	float Ki;//Ki
+	float Kd;//Kd
+
+	float P_OUT;//比例输出
+	float I_OUT;//积分输出
+	float D_OUT;//微分输出
+	float OUT;//总输出
+	float OUT_low;//输出限幅下限
+	float OUT_up;//输出限幅上限
+}PID_IncrementalInitTypedef;//增量式PID参数结构体
+
+void PID_PositionStructureInit(PID_PositionInitTypedef* PID_InitStructure,float NeedValue);//位置式PID初始化结构体
+void PID_PositionSetParameter(PID_PositionInitTypedef* PID_InitStructure,float kp,float ki,float kd);//位置式PID设置参数
+void PID_PositionSetEkRange(PID_PositionInitTypedef* PID_InitStructure,float ek_low,float ek_up);//位置式PID设置误差为0阈值
+void PID_PositionSetOUTRange(PID_PositionInitTypedef* PID_InitStructure,float out_low,float out_up);//位置式PID设置输出限幅
+void PID_PositionClean(PID_PositionInitTypedef* PID_InitStructure);//位置式PID清理
+void PID_PositionCalc(PID_PositionInitTypedef* PID_InitStructure,float NowValue);//位置式PID计算
+void PID_IncrementalStructureInit(PID_IncrementalInitTypedef* PID_InitStructure,float NeedValue);//增量式PID初始化结构体
+void PID_IncrementalSetParameter(PID_IncrementalInitTypedef* PID_InitStructure,float kp,float ki,float kd);//增量式PID设置参数
+void PID_IncrementalSetEkRange(PID_IncrementalInitTypedef* PID_InitStructure,float ek_low,float ek_up);//增量式PID设置误差为0阈值
+void PID_IncrementalSetOUTRange(PID_IncrementalInitTypedef* PID_InitStructure,float out_low,float out_up);//增量式PID设置输出限幅
+void PID_IncrementalCalc(PID_IncrementalInitTypedef* PID_InitStructure,float NowValue);//增量式PID计算
+
+#endif

底盘/底盘-old/底盘/DebugConfig/Target_1_STM32F407IGHx.dbgconf

@@ -0,0 +1,48 @@
+// File: STM32F405_415_407_417_427_437_429_439.dbgconf
+// Version: 1.0.0
+// Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
+//       refer to STM32F40x STM32F41x datasheets
+//       refer to STM32F42x STM32F43x datasheets
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Debug MCU configuration register (DBGMCU_CR)
+//   <o.2>  DBG_STANDBY              <i> Debug Standby Mode
+//   <o.1>  DBG_STOP                 <i> Debug Stop Mode
+//   <o.0>  DBG_SLEEP                <i> Debug Sleep Mode
+// </h>
+DbgMCU_CR = 0x00000007;
+
+// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
+//                                   <i> Reserved bits must be kept at reset value
+//   <o.26> DBG_CAN2_STOP            <i> CAN2 stopped when core is halted
+//   <o.25> DBG_CAN1_STOP            <i> CAN2 stopped when core is halted
+//   <o.23> DBG_I2C3_SMBUS_TIMEOUT   <i> I2C3 SMBUS timeout mode stopped when core is halted
+//   <o.22> DBG_I2C2_SMBUS_TIMEOUT   <i> I2C2 SMBUS timeout mode stopped when core is halted
+//   <o.21> DBG_I2C1_SMBUS_TIMEOUT   <i> I2C1 SMBUS timeout mode stopped when core is halted
+//   <o.12> DBG_IWDG_STOP            <i> Independent watchdog stopped when core is halted
+//   <o.11> DBG_WWDG_STOP            <i> Window watchdog stopped when core is halted
+//   <o.10> DBG_RTC_STOP             <i> RTC stopped when core is halted
+//   <o.8>  DBG_TIM14_STOP           <i> TIM14 counter stopped when core is halted
+//   <o.7>  DBG_TIM13_STOP           <i> TIM13 counter stopped when core is halted
+//   <o.6>  DBG_TIM12_STOP           <i> TIM12 counter stopped when core is halted
+//   <o.5>  DBG_TIM7_STOP            <i> TIM7 counter stopped when core is halted
+//   <o.4>  DBG_TIM6_STOP            <i> TIM6 counter stopped when core is halted
+//   <o.3>  DBG_TIM5_STOP            <i> TIM5 counter stopped when core is halted
+//   <o.2>  DBG_TIM4_STOP            <i> TIM4 counter stopped when core is halted
+//   <o.1>  DBG_TIM3_STOP            <i> TIM3 counter stopped when core is halted
+//   <o.0>  DBG_TIM2_STOP            <i> TIM2 counter stopped when core is halted
+// </h>
+DbgMCU_APB1_Fz = 0x00000000;
+
+// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
+//                                   <i> Reserved bits must be kept at reset value
+//   <o.18> DBG_TIM11_STOP           <i> TIM11 counter stopped when core is halted
+//   <o.17> DBG_TIM10_STOP           <i> TIM10 counter stopped when core is halted
+//   <o.16> DBG_TIM9_STOP            <i> TIM9 counter stopped when core is halted
+//   <o.1>  DBG_TIM8_STOP            <i> TIM8 counter stopped when core is halted
+//   <o.0>  DBG_TIM1_STOP            <i> TIM1 counter stopped when core is halted
+// </h>
+DbgMCU_APB2_Fz = 0x00000000;
+
+// <<< end of configuration section >>>

底盘/底盘-old/底盘/EventRecorderStub.scvd

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

底盘/底盘-old/底盘/Function/CToC.c

@@ -0,0 +1,141 @@
+#include "stm32f4xx.h"                  // Device header
+#include "stm32f4xx_conf.h"
+#include "CToC.h"
+#include "Remote.h"
+#include "RefereeSystem.h"
+
+/*
+ *函数简介:板间通讯从机初始化
+ *参数说明:无
+ *返回类型:无
+ *备注:默认使用CAN2(CAN2-Tx为PB6,CAN2-Rx为PB5)
+ *备注:CAN波特率1M,默认1Tq=1/14us≈0.07us
+ *备注:使用CAN2需要在打开CAN2时钟之前打开CAN1时钟,且CAN2筛选器编号为15~27
+ *备注:主机控制从机的标识符为149,从机回报的标识符为189
+ */
+void CToC_SlaveInit(void)
+{
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1,ENABLE);
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2,ENABLE);
+	RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB,ENABLE);//开启时钟
+	
+	GPIO_InitTypeDef GPIO_InitStructure;
+	GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF;
+	GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//复用推挽
+	GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
+	GPIO_InitStructure.GPIO_Pin=GPIO_Pin_5 | GPIO_Pin_6;
+	GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
+	GPIO_Init(GPIOB,&GPIO_InitStructure);//配置PB5(CAN2-Rx)和PB6(CAN2-Tx)
+
+	GPIO_PinAFConfig(GPIOB,GPIO_PinSource5,GPIO_AF_CAN2);//开启PB5的CAN2复用模式
+	GPIO_PinAFConfig(GPIOB,GPIO_PinSource6,GPIO_AF_CAN2);//开启PB6的CAN2复用模式
+	
+	CAN_InitTypeDef CAN_InitStructure;
+	CAN_InitStructure.CAN_Mode=CAN_Mode_Normal;//正常模式
+	CAN_InitStructure.CAN_Prescaler=3;//时钟分频,1Tq=Prescaler/T_PCLK=Prescaler/42M
+	CAN_InitStructure.CAN_SJW=CAN_SJW_1tq;//SJW极限值
+	CAN_InitStructure.CAN_BS1=CAN_BS1_10tq;//PBS1段长度
+	CAN_InitStructure.CAN_BS2=CAN_BS2_3tq;//PBS2段长度,1/Baudrate=T_1bit=(1+BS1+BS2)Tq
+	CAN_InitStructure.CAN_TTCM=DISABLE;//关闭时间触发功能
+	CAN_InitStructure.CAN_ABOM=ENABLE;//开启自动离线管理功能
+	CAN_InitStructure.CAN_AWUM=ENABLE;//开启自动唤醒功能
+	CAN_InitStructure.CAN_NART=ENABLE;//禁止自动重传功能
+	CAN_InitStructure.CAN_RFLM=DISABLE;//关闭锁定FIFO功能
+	CAN_InitStructure.CAN_TXFP=DISABLE;//配置报文优先级判定为标识符决定
+	CAN_Init(CAN2,&CAN_InitStructure);
+	
+	CAN_FilterInitTypeDef CAN_FilterInitStructure;
+	CAN_FilterInitStructure.CAN_FilterNumber=15;//筛选器编号15(编号0~14属于CAN1,编号15~27属于CAN2)
+	CAN_FilterInitStructure.CAN_FilterFIFOAssignment=CAN_Filter_FIFO1;//存入FIFO1
+	CAN_FilterInitStructure.CAN_FilterMode=CAN_FilterMode_IdMask;//掩码模式
+	CAN_FilterInitStructure.CAN_FilterScale=CAN_FilterScale_16bit;//筛选器尺度为16bits
+	CAN_FilterInitStructure.CAN_FilterIdHigh=(CToC_SlaveID1<<5);//标识符=STID[15:5](189/0001 1000 1001)+RTR[4:4](0)+IDE[3:3](0)+EXID[2:0](000)
+	CAN_FilterInitStructure.CAN_FilterIdLow=(CToC_SlaveID1<<5);
+	CAN_FilterInitStructure.CAN_FilterMaskIdHigh=0xFFE3;//1111 1111 0000 0011
+	CAN_FilterInitStructure.CAN_FilterMaskIdLow=0xFFE3;
+	CAN_FilterInitStructure.CAN_FilterActivation=ENABLE;
+	CAN_FilterInit(&CAN_FilterInitStructure);
+	
+	CAN_ITConfig(CAN2,CAN_IT_FMP1,ENABLE);//打通CAN2_FIFO1到NVIC的通道
+	
+	NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//选择NVIC分组2(2位抢占优先级，2位响应优先级)
+	
+	NVIC_InitTypeDef NVIC_InitStructure;
+	NVIC_InitStructure.NVIC_IRQChannel=CAN2_RX1_IRQn;//选择CAN2_FIFO1接收中断通道
+	NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;//使能中断通道
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=1;//抢占优先级为1
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority=1;//响应优先级为1
+	NVIC_Init(&NVIC_InitStructure);//初始化CAN2_FIFO1的NVIC
+}
+
+/*
+ *函数简介:板间通讯从机发送裁判系统数据
+ *参数说明:无
+ *返回类型:1-发送成功,0-发送失败
+ *备注:默认标准格式数据帧,8字节数据段,主机ID为CToC_MasterID1
+ *发送数据:Data[0]-发射机构状态
+ */
+uint8_t CToC_SlaveSendRefereeSystemData(void)
+{
+	CanTxMsg TxMessage;
+	TxMessage.StdId=CToC_MasterID1;//主机ID
+	TxMessage.RTR=CAN_RTR_Data;//数据帧
+	TxMessage.IDE=CAN_Id_Standard;//标准格式
+	TxMessage.DLC=0x08;//8字节数据段
+	TxMessage.Data[0]=RefereeSystem_ShooterStatus;
+	TxMessage.Data[1]=0;
+	TxMessage.Data[2]=0;
+	TxMessage.Data[3]=0;
+	TxMessage.Data[4]=0;
+	TxMessage.Data[5]=0;
+	TxMessage.Data[6]=0;
+	TxMessage.Data[7]=0;
+	
+	uint8_t mbox=CAN_Transmit(CAN2,&TxMessage);//发送数据并获取邮箱号
+	uint16_t i=0;
+	while((CAN_TransmitStatus(CAN2,mbox)==CAN_TxStatus_Failed)&&(i<0XFFF))i++;//等待发送结束
+	if(i>=0xFFF)return 0;//发送失败
+	return 1;//发送成功
+}
+
+/*
+ *函数简介:板间通讯数据处理
+ *参数说明:CAN数据帧ID号,详情见CToC.h的宏定义
+ *参数说明:反馈数据(8字节)
+ *返回类型:无
+ *备注:无
+ *接收数据:
+ *	CToC_SlaveID1
+ *	Data[0~1]-遥控器右摇杆左右
+ *	Data[2~3]-遥控器右摇杆上下
+ *	Data[4~5]-遥控器左摇杆左右
+ *	Data[6~7]-遥控器左摇杆上下
+ *	CToC_SlaveID2
+ *	Data[0]-遥控器连接状态
+ *	Data[1]-遥控器右侧拨动开关
+ *	Data[2]-键盘Ctrl状态(Remote_KeyPush_Ctrl)
+ *	Data[3]-键盘Shift状态(Remote_KeyPush_Shift)
+ *	Data[4]-遥控器启动标志位
+ *	Data[5]-遥控器左侧拨动开关
+ */
+void CToC_CANDataProcess(uint32_t ID,uint8_t *Data)
+{
+	if(ID==CToC_SlaveID1)//接收遥控器拨杆数据
+	{
+		Remote_RxData.Remote_R_RL=(uint16_t)((uint16_t)Data[0]<<8 | Data[1]);//右摇杆右左
+		Remote_RxData.Remote_R_UD=(uint16_t)((uint16_t)Data[2]<<8 | Data[3]);//右摇杆上下
+		Remote_RxData.Remote_L_RL=(uint16_t)((uint16_t)Data[4]<<8 | Data[5]);//左摇杆右左
+		Remote_RxData.Remote_L_UD=(uint16_t)((uint16_t)Data[6]<<8 | Data[7]);//左摇杆上下
+	}
+	else if(ID==CToC_SlaveID2)//接收遥控器控制数据
+	{
+		Remote_Status=Data[0];//遥控器连接状态
+		Remote_RxData.Remote_RS=Data[1];//遥控器右侧拨动开关
+		Remote_RxData.Remote_KeyPush_Ctrl=Data[2];//键盘Ctrl状态
+		Remote_RxData.Remote_KeyPush_Shift=Data[3];//键盘Shift状态
+		Remote_StartFlag=Data[4];//遥控器启动标志位
+		Remote_RxData.Remote_LS=Data[5];//遥控器左侧拨动开关
+		Remote_RxData.Remote_Key_1=Data[6];
+	    Remote_RxData.Remote_Key_2=Data[7];
+	}
+}

底盘/底盘-old/底盘/Function/CToC.h

@@ -0,0 +1,13 @@
+#ifndef __CTOC_H
+#define __CTOC_H
+
+#define CToC_MasterID1	0x019//主机ID1
+
+#define CToC_SlaveID1	0x149//从机ID1
+#define CToC_SlaveID2	0x189//从机ID2
+
+void CToC_SlaveInit(void);//板间通讯从机初始化
+uint8_t CToC_SlaveSendRefereeSystemData(void);//板间通讯从机发送裁判系统数据
+void CToC_CANDataProcess(uint32_t ID,uint8_t *Data);//板间通讯数据处理
+
+#endif

底盘/底盘-old/底盘/Function/CloseLoopControl.c

@@ -0,0 +1,96 @@
+#include "stm32f4xx.h"                  // Device header
+#include "stm32f4xx_conf.h"
+#include "Remote.h"
+#include "Mecanum.h"
+#include "Warming.h"
+#include "LinkCheck.h"
+#include "UI.h"
+
+uint8_t CloseLoopControl_ErrorFlag;//闭环控制CAN设备故障标志位
+
+/*
+ *函数简介:闭环控制初始化
+ *参数说明:无
+ *返回类型:无
+ *备注:使用定时器TIM6进行闭环,闭环周期2ms
+ */
+void CloseLoopControl_Init(void)
+{
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM6,ENABLE);//开启时钟
+	
+	TIM_InternalClockConfig(TIM6);//选择时基单元的时钟(TIM6)
+	
+	TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure;//配置时基单元（配置参数）
+	TIM_TimeBaseInitStructure.TIM_ClockDivision=TIM_CKD_DIV1;//配置时钟分频为1分频
+	TIM_TimeBaseInitStructure.TIM_CounterMode=TIM_CounterMode_Up;//配置计数器模式为向上计数
+	TIM_TimeBaseInitStructure.TIM_Period=500-1;//配置自动重装值ARR
+	TIM_TimeBaseInitStructure.TIM_Prescaler=336-1;//配置分频值PSC,默认定时2ms
+	TIM_TimeBaseInitStructure.TIM_RepetitionCounter=0;//配置重复计数单元的置为0
+	TIM_TimeBaseInit(TIM6,&TIM_TimeBaseInitStructure);//初始化TIM7
+	
+	TIM_ClearFlag(TIM6,TIM_FLAG_Update);//清除配置时基单元产生的中断标志位
+	
+	TIM_ITConfig(TIM6,TIM_IT_Update,ENABLE);//使能更新中断
+	
+	NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//选择NVIC分组
+	
+	NVIC_InitTypeDef NVIC_InitStructure;//配置NVIC（配置参数）
+	NVIC_InitStructure.NVIC_IRQChannel=TIM6_DAC_IRQn;//选择中断通道为TIM6
+	NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;//使能中断通道
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=3;//TIM2的抢占优先级
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority=3;//TIM2的响应优先级
+	NVIC_Init(&NVIC_InitStructure);//初始化NVIC
+	
+	TIM_Cmd(TIM6,ENABLE);//启动定时器
+	
+	Mecanum_Init();//麦轮初始化
+}
+
+/*
+ *函数简介:TIM6定时器更新中断函数
+ *参数说明:无
+ *返回类型:无
+ *备注:无
+ */
+void TIM6_DAC_IRQHandler(void)
+{
+	static uint8_t Remote_LastStatus,Remote_ThisStatus=0;
+	static uint8_t Count=0;
+	if(TIM_GetITStatus(TIM6,TIM_IT_Update)==SET)//检测TIM6更新
+	{
+		TIM_ClearITPendingBit(TIM6,TIM_IT_Update);//清除标志位
+				
+		/*===============麦轮闭环控制===============*/
+		Remote_LastStatus=Remote_ThisStatus;//遥控器上一次连接状态
+		Remote_ThisStatus=Remote_Status;//遥控器本次连接状态
+		if(LinkCheck_Error==0)//CAN设备正常连接
+		{
+			if(Remote_Status==1)//遥控器处于连接状态
+			{
+				if(Remote_LastStatus==0 && Remote_ThisStatus==1)UI_Init();//遥控器连接瞬间,初始化UI界面
+
+				Mecanum_PowerMoveControl();//底盘功率控制
+				
+				if(Count==50){Count=0;UI_Updata();}//每100ms更新一次UI界面
+				else Count++;
+			}
+			else
+			{
+				Warming_MotorControl();//电机报警状态
+				
+				if(Count==50){Count=0;UI_RemoteNoCheck();}//每100ms更新一次UI界面,显示遥控器未连接
+				else Count++;
+			}
+		}
+		else//CAN设备异常连接
+		{
+			Warming_LinkError();//CAN设备连接错误报警
+			Warming_MotorControl();//电机报警状态
+			
+			CloseLoopControl_ErrorFlag=1;//置闭环控制CAN设备故障标志位
+			
+			if(Count==50){Count=0;Warming_UIShow();}//每100ms更新一次UI界面,显示CAN设备异常连接
+			else Count++;
+		}
+	}
+}

底盘/底盘-old/底盘/Function/CloseLoopControl.h

@@ -0,0 +1,8 @@
+#ifndef __CLOSELOOPCONTROL_H
+#define __CLOSELOOPCONTROL_H
+
+extern uint8_t CloseLoopControl_ErrorFlag;//闭环控制CAN设备故障标志位
+
+void CloseLoopControl_Init(void);//闭环控制初始化
+
+#endif

底盘/底盘-old/底盘/Function/LinkCheck.c

@@ -0,0 +1,94 @@
+/*
+
+连接检查初始化					  --->定时器超时--->连接错误,关闭遥控器---
+开启定时器	   --->等待CAN接收---|										   |
+						^		  --->关闭定时器,更改ID<---等待恢复连接<--
+						|					|
+						---开启定时器-------
+
+*/
+
+#include "stm32f4xx.h"                  // Device header
+#include "stm32f4xx_conf.h"
+#include "TIM.h"
+#include "Remote.h"
+#include "CAN.h"
+
+uint8_t LinkCheck_Error=0;//连接错误标志位
+
+/*
+ *函数简介:CAN设备连接检测初始化
+ *参数说明:无
+ *返回类型:无
+ *备注:Freq=Sys_APB1TIM/(PSC+1)/(ARR+1)=84MHz/(PSC+1)/(ARR+1),T=1/Freq=(ARR+1)*(PSC+1)/84MHz
+ *备注:默认定时2.5ms
+ */
+void LinkCheck_Init(void)
+{
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM13,ENABLE);//开启时钟
+	
+	TIM_InternalClockConfig(TIM13);//选择时基单元的时钟
+	
+	TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure;//配置时基单元（配置参数）
+	TIM_TimeBaseInitStructure.TIM_ClockDivision=TIM_CKD_DIV1;//配置时钟分频为1分频
+	TIM_TimeBaseInitStructure.TIM_CounterMode=TIM_CounterMode_Up;//配置计数器模式为向上计数
+	TIM_TimeBaseInitStructure.TIM_Period=210-1;//配置自动重装值ARR
+	TIM_TimeBaseInitStructure.TIM_Prescaler=1000-1;//配置分频值PSC
+	TIM_TimeBaseInitStructure.TIM_RepetitionCounter=0;//配置重复计数单元的置为0
+	TIM_TimeBaseInit(TIM13,&TIM_TimeBaseInitStructure);//初始化TIM13
+	
+	TIM_ClearFlag(TIM13,TIM_FLAG_Update);//清除配置时基单元产生的中断标志位
+	
+	TIM_ITConfig(TIM13,TIM_IT_Update,ENABLE);//使能更新中断
+	
+	NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//选择NVIC分组
+	
+	NVIC_InitTypeDef NVIC_InitStructure;//配置NVIC（配置参数）
+	NVIC_InitStructure.NVIC_IRQChannel=TIM8_UP_TIM13_IRQn;//选择中断通道为TIM13
+	NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;//使能中断通道
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=1;//TIM13的抢占优先级
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority=2;//TIM13的响应优先级
+	NVIC_Init(&NVIC_InitStructure);//初始化NVIC
+	
+	TIM_Cmd(TIM13,ENABLE);//启动定时器
+	
+	CAN_CANInit();//CAN通讯初始化
+}
+
+/*
+ *函数简介:开启掉线检查
+ *参数说明:无
+ *返回类型:无
+ *备注:无
+ */
+void LinkCheck_ON(void)
+{
+	TIM_SetCounter(TIM13,0);//复位计数器
+	TIM_Cmd(TIM13,ENABLE);
+}
+
+/*
+ *函数简介:关闭掉线检测
+ *参数说明:无
+ *返回类型:无
+ *备注:无
+ */
+void LinkCheck_OFF(void)
+{
+	TIM_Cmd(TIM13,DISABLE);
+}
+
+/*
+ *函数简介:TIM13定时器更新中断函数
+ *参数说明:无
+ *返回类型:无
+ *备注:进入中断即发生CAN设备掉线
+ */
+void TIM8_UP_TIM13_IRQHandler(void)
+{
+	if(TIM_GetITStatus(TIM13,TIM_IT_Update)==SET)//检测TIM2更新
+	{
+		TIM_ClearITPendingBit(TIM13,TIM_IT_Update);//清除标志位
+		LinkCheck_Error=1;//连接错误
+	}
+}

底盘/底盘-old/底盘/Function/LinkCheck.h

@@ -0,0 +1,10 @@
+#ifndef __LINKCHECK_H
+#define __LINKCHECK_H
+
+extern uint8_t LinkCheck_Error;//连接错误标志位
+
+void LinkCheck_Init(void);//CAN设备连接检测初始化
+void LinkCheck_ON(void);//开启掉线检查
+void LinkCheck_OFF(void);//关闭掉线检测
+
+#endif

底盘/底盘-old/底盘/Function/Warming.c

@@ -0,0 +1,188 @@
+#include "stm32f4xx.h"                  // Device header
+#include "stm32f4xx_conf.h"
+#include "LED.h"
+#include "Buzzer.h"
+#include "CAN.h"
+#include "Delay.h"
+#include "M3508.h"
+#include "UI_Library.h"
+
+/*====================	 报警列表	====================
+	遥控器未连接	················1s里红灯连闪两下
+	遥控器数据错误报警	············红灯常亮
+	CAN总线设备连接异常············2s内蜂鸣器以高音6响n下,n为CAN.c文件里ID列表的索引
+	IST8310连接错误	················绿灯以1s为周期闪烁
+	BMI088连接错误	················1s里绿灯连闪两下
+	陀螺仪温度过高报警	············绿灯常亮
+	电机报警状态	················电机静止
+	自定义UI显示警告	············所有状态指示灯变成红或蓝
+  ======================================================*/
+
+/*
+ *函数简介:报警初始化
+ *参数说明:无
+ *返回类型:无
+ *备注:报警功能用于各种错误的提示
+ *备注:报警有两种方式-LED和蜂鸣器
+ */
+void Warming_Init(void)
+{
+	LED_Init();
+	Buzzer_Init();
+}
+
+/*
+ *函数简介:报警关闭
+ *参数说明:无
+ *返回类型:无
+ *备注:无
+ */
+void Warming_Stop(void)
+{
+	TIM_SetCompare1(TIM10,0);
+}
+
+/*
+ *函数简介:报警LED清理
+ *参数说明:无
+ *返回类型:无
+ *备注:关闭所有灯
+ */
+void Warming_LEDClean(void)
+{
+	LED_BOFF();LED_GOFF();LED_ROFF();
+}
+
+/*
+ *函数简介:报警蜂鸣器清理
+ *参数说明:无
+ *返回类型:无
+ *备注:关闭所有蜂鸣器
+ */
+void Warming_BuzzerClean(void)
+{
+	Buzzer_ON(P);
+}
+
+/*
+ *函数简介:遥控器未连接报警
+ *参数说明:无
+ *返回类型:无
+ *备注:遥控器连接检测TIM7定时更新中断调用,定时25ms
+ *报警现象:1s里红灯连闪两下
+ */
+void Warming_RemoteNoCheck(void)
+{
+	static uint8_t Counter=0;
+	Counter++;
+	
+	if(Counter==1)LED_RON();
+	else if(Counter==5)LED_ROFF();
+	else if(Counter==13)LED_RON();
+	else if(Counter==17)LED_ROFF();
+	else if(Counter==40)Counter=0;
+}
+
+/*
+ *函数简介:遥控器数据错误报警
+ *参数说明:无
+ *返回类型:无
+ *报警现象:红灯常量
+ */
+void Warming_RemoteDataERROR(void)
+{
+	LED_RON();
+}
+
+/*
+ *函数简介:CAN总线设备连接异常报警
+ *参数说明:无
+ *返回类型:无
+ 
+ *备注:闭环控制TIM6定时更新中断调用,定时2ms
+ *报警现象:2s内蜂鸣器以高音6响n下,n为连接异常的设备在ID列表的索引(CAN.h文件中CAN_IDSelect变量)
+ */
+void Warming_LinkError(void)
+{
+	static uint8_t i=0;
+	static uint16_t Counter=0;
+	Counter++;
+	
+	if(i<CAN_IDSelect+1)//高音6响CAN_IDSelect下
+	{
+		if(Counter==100*i+1)Buzzer_ON(H6);
+		else if(Counter==100*i+51)Buzzer_ON(P);
+		else if(Counter==100*i+100)i++;
+	}
+	if(Counter==1000){Counter=0;i=0;}
+}
+
+/*
+ *函数简介:IST8310连接错误
+ *参数说明:无
+ *返回类型:无
+ *备注:IST8310初始化调用,周期25ms
+ *报警现象:绿灯以1s为周期闪烁
+ */
+void Warming_IST8310LinkError(void)
+{
+	static uint8_t Counter=0;
+	Counter++;
+	
+	if(Counter==1)LED_GON();
+	else if(Counter==5)LED_GOFF();
+	else if(Counter==40)Counter=0;
+}
+
+/*
+ *函数简介:BMI088连接错误
+ *参数说明:无
+ *返回类型:无
+ *备注:BMI088初始化调用,周期25ms
+ *报警现象:1s里绿灯连闪两下
+ */
+void Warming_BMI088LinkError(void)
+{
+	static uint8_t Counter=0;
+	Counter++;
+	
+	if(Counter==1)LED_GON();
+	else if(Counter==5)LED_GOFF();
+	else if(Counter==13)LED_GON();
+	else if(Counter==17)LED_GOFF();
+	else if(Counter==40)Counter=0;
+}
+
+/*
+ *函数简介:陀螺仪温度过高报警
+ *参数说明:无
+ *返回类型:无
+ *备注:IMU恒温控制调用,温度警戒50℃
+ *报警现象:绿灯常亮
+ */
+void Warming_IMUTemperatureTooHigh(void)
+{
+	LED_GON();
+}
+
+/*
+ *函数简介:电机报警状态
+ *参数说明:无
+ *返回类型:无
+ *报警现象:电机静止
+ */
+void Warming_MotorControl(void)
+{
+	M3508_CANSetLIDCurrent(0,0,0,0);
+}
+
+/*
+ *函数简介:自定义UI显示警告
+ *参数说明:无
+ *返回类型:无
+ *报警现象:所有状态指示灯变成红或蓝
+ */
+void Warming_UIShow(void)
+{
+	_ui_update_default_Ungroup_2_ERROR();
+}

底盘/底盘-old/底盘/Function/Warming.h

@@ -0,0 +1,28 @@
+#ifndef __WARMING_H
+#define __WARMING_H
+
+/*====================	 报警列表	====================
+	遥控器未连接	················1s里红灯连闪两下
+	遥控器数据错误报警	············红灯常亮
+	CAN总线设备连接异常············2s内蜂鸣器以高音6响n下,n为CAN.c文件里ID列表的索引
+	IST8310连接错误	················绿灯以1s为周期闪烁
+	BMI088连接错误	················1s里绿灯连闪两下
+	陀螺仪温度过高报警	············绿灯常亮
+	电机报警状态	················电机静止
+	自定义UI显示警告	············所有状态指示灯变成红或蓝
+  ======================================================*/
+
+void Warming_Init(void);//报警初始化
+void Warming_Stop(void);//报警关闭
+void Warming_LEDClean(void);//报警LED清理
+void Warming_BuzzerClean(void);//报警蜂鸣器清理
+void Warming_RemoteNoCheck(void);//遥控器未连接报警
+void Warming_RemoteDataERROR(void);//遥控器数据错误报警
+void Warming_LinkError(void);//CAN总线设备连接异常报警
+void Warming_IST8310LinkError(void);//IST8310连接错误
+void Warming_BMI088LinkError(void);//BMI088连接错误
+void Warming_IMUTemperatureTooHigh(void);//陀螺仪温度过高报警
+void Warming_MotorControl(void);//电机报警状态
+void Warming_UIShow(void);//自定义UI显示警告
+
+#endif

底盘/底盘-old/底盘/Hardware/Buzzer.c

@@ -0,0 +1,107 @@
+#include "stm32f4xx.h"                  // Device header
+#include "stm32f4xx_conf.h"
+#include "Buzzer.h"
+#include "Delay.h"
+
+int16_t Buzzer_ToneFreq[37]=
+{
+	0,
+	32107,30305,28604,26999,25483,24053,22703,21429,20226,19091,18019,17008,
+	16053,15152,14302,13499,12742,12026,11352,10714,10113,9545,9010,8504,
+	8027,7576,7151,6750,6371,6013,5676,5357,5056,4773,4505,4252,
+};//蜂鸣器音调频率表
+
+/*
+ *函数简介:蜂鸣器初始化
+ *参数说明:无
+ *返回类型:无
+ *备注:无源蜂鸣器
+ *备注:默认TIM4-CH3(PD14)
+ */
+void Buzzer_Init(void)
+{
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4,ENABLE);
+	RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD,ENABLE);//开启时钟
+	
+	TIM_InternalClockConfig(TIM4);//选择时基单元TIM4
+	
+	GPIO_InitTypeDef GPIO_InitStructure;
+	GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF;
+	GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//复用推挽
+	GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
+	GPIO_InitStructure.GPIO_Pin=GPIO_Pin_14;
+	GPIO_InitStructure.GPIO_Speed=GPIO_Speed_50MHz;
+	GPIO_Init(GPIOD,&GPIO_InitStructure);
+	
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource14,GPIO_AF_TIM4);//开启PD14的TIM4复用模式
+	
+	TIM_TimeBaseInitTypeDef TIM_InitStructure;
+	TIM_InitStructure.TIM_ClockDivision=TIM_CKD_DIV1;//配置时钟分频为1分频
+	TIM_InitStructure.TIM_CounterMode=TIM_CounterMode_Up;//配置计数器模式为向上计数
+	TIM_InitStructure.TIM_Period=10-1;//ARR,PWM为十分位
+	TIM_InitStructure.TIM_Prescaler=19091-1;//PSC,默认频率低音6(440Hz)
+	TIM_InitStructure.TIM_RepetitionCounter=0;//配置重复计数单元的置为0
+	TIM_TimeBaseInit(TIM4,&TIM_InitStructure);
+	
+	TIM_OCInitTypeDef TIM_OCInitStructure;
+	TIM_OCStructInit(&TIM_OCInitStructure);
+	TIM_OCInitStructure.TIM_OCMode=TIM_OCMode_PWM1;//配置输出比较模式
+	TIM_OCInitStructure.TIM_OCPolarity=TIM_OCPolarity_High;//配置输出比较的极性
+	TIM_OCInitStructure.TIM_OutputState=TIM_OutputState_Enable;//输出使能
+	TIM_OCInitStructure.TIM_Pulse=0;//配置输出比较寄存器CCR的值,默认占空比0%
+	TIM_OC3Init(TIM4,&TIM_OCInitStructure);//配置PD14输出PWM
+	
+	TIM_Cmd(TIM4,ENABLE);//启动定时器
+}
+
+/*
+ *函数简介:蜂鸣器发声
+ *参数说明:枚举音调
+ *参数说明:持续时间,单位ms
+ *返回类型:无
+ *备注:无
+ */
+void Buzzer_Time(Buzzer_Tone Tone,uint16_t ms)
+{
+	if(Tone!=P)//非停止调
+	{
+		TIM_PrescalerConfig(TIM4,Buzzer_ToneFreq[Tone],TIM_PSCReloadMode_Update);//配置频率
+		TIM_SetCompare3(TIM4,5);//占空比50%
+	}
+	else//停止调(即空拍)
+		TIM_SetCompare3(TIM4,0);//占空比0%,即关闭PWM
+	
+	Delay_ms(ms);
+	TIM_SetCompare3(TIM4,0);//占空比0%,即关闭PWM
+}
+
+/*
+ *函数简介:蜂鸣器打开
+ *参数说明:枚举音调
+ *返回类型:无
+ *备注:无
+ */
+void Buzzer_ON(Buzzer_Tone Tone)
+{
+	TIM_Cmd(TIM4,ENABLE);//打开定时器
+	
+	if(Tone!=P)//非停止调
+	{
+		TIM_PrescalerConfig(TIM4,Buzzer_ToneFreq[Tone],TIM_PSCReloadMode_Update);//配置频率
+		TIM_SetCompare3(TIM4,5);//占空比50%
+	}
+	else//停止调(即空拍)
+		TIM_SetCompare3(TIM4,0);//占空比0%,即关闭PWM
+}
+
+/*
+ *函数简介:蜂鸣器关闭
+ *参数说明:无
+ *返回类型:无
+ *备注:无
+ */
+void Buzzer_OFF(void)
+{
+	TIM_SetCompare3(TIM4,0);//占空比0%,即关闭PWM
+	TIM_Cmd(TIM4,DISABLE);//关闭定时器
+}

底盘/底盘-old/底盘/Hardware/Buzzer.h

@@ -0,0 +1,17 @@
+#ifndef __BUZZER_H
+#define __BUZZER_H
+
+typedef enum
+{
+	P=0,//空拍
+	L1,L1_,L2,L2_,L3,L4,L4_,L5,L5_,L6,L6_,L7,//低音
+	M1,M1_,M2,M2_,M3,M4,M4_,M5,M5_,M6,M6_,M7,//中音
+	H1,H1_,H2,H2_,H3,H4,H4_,H5,H5_,H6,H6_,H7,//高音
+}Buzzer_Tone;//蜂鸣器音调枚举
+
+void Buzzer_Init(void);//蜂鸣器初始化
+void Buzzer_Time(Buzzer_Tone Tone,uint16_t ms);//蜂鸣器发声
+void Buzzer_ON(Buzzer_Tone Tone);//蜂鸣器打开
+void Buzzer_OFF(void);//蜂鸣器关闭
+
+#endif

底盘/底盘-old/底盘/Hardware/LED.c

@@ -0,0 +1,255 @@
+#include "stm32f4xx.h"                  // Device header
+#include "stm32f4xx_conf.h"
+
+/*
+ *函数简介:三色单色LED初始化
+ *参数说明:无
+ *返回类型:无
+ *备注:蓝色-PH10,绿色-PH11,红色-PH12
+ */
+void LED_Init(void)
+{
+	RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOH,ENABLE);//开启时钟
+	
+	GPIO_InitTypeDef GPIO_InitStructure;
+	GPIO_InitStructure.GPIO_Mode=GPIO_Mode_OUT;
+	GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//推挽输出
+	GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
+	GPIO_InitStructure.GPIO_Pin=GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
+	GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
+	GPIO_Init(GPIOH,&GPIO_InitStructure);
+	
+	GPIO_ResetBits(GPIOH,GPIO_Pin_10);
+	GPIO_ResetBits(GPIOH,GPIO_Pin_11);
+	GPIO_ResetBits(GPIOH,GPIO_Pin_12);//默认三灯均熄灭
+}
+
+/*
+ *函数简介:蓝色单色LED初始化
+ *参数说明:无
+ *返回类型:无
+ *备注:引脚PH10
+ */
+void LED_BInit(void)
+{
+	RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOH,ENABLE);//开启时钟
+	
+	GPIO_InitTypeDef GPIO_InitStructure;
+	GPIO_InitStructure.GPIO_Mode=GPIO_Mode_OUT;
+	GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//推挽输出
+	GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
+	GPIO_InitStructure.GPIO_Pin=GPIO_Pin_10;
+	GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
+	GPIO_Init(GPIOH,&GPIO_InitStructure);
+	
+	GPIO_ResetBits(GPIOH,GPIO_Pin_10);//默认熄灭
+}
+
+/*
+ *函数简介:蓝灯点亮
+ *参数说明:无
+ *返回类型:无
+ *备注:无
+ */
+void LED_BON(void)
+{
+	GPIO_SetBits(GPIOH,GPIO_Pin_10);
+}
+
+/*
+ *函数简介:蓝灯熄灭
+ *参数说明:无
+ *返回类型:无
+ *备注:无
+ */
+void LED_BOFF(void)
+{
+	GPIO_ResetBits(GPIOH,GPIO_Pin_10);
+}
+
+/*
+ *函数简介:蓝灯亮灭反转
+ *参数说明:无
+ *返回类型:无
+ *备注:无
+ */
+void LED_BTurn(void)
+{
+	if(GPIO_ReadInputDataBit(GPIOH,GPIO_Pin_10)==0)//当前蓝灯灭
+		GPIO_SetBits(GPIOH,GPIO_Pin_10);
+	else//当前蓝灯亮
+		GPIO_ResetBits(GPIOH,GPIO_Pin_10);
+}
+
+/*
+ *函数简介:绿色单色LED初始化
+ *参数说明:无
+ *返回类型:无
+ *备注:引脚PH11
+ */
+void LED_GInit(void)
+{
+	RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOH,ENABLE);//开启时钟
+	
+	GPIO_InitTypeDef GPIO_InitStructure;
+	GPIO_InitStructure.GPIO_Mode=GPIO_Mode_OUT;
+	GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//推挽输出
+	GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
+	GPIO_InitStructure.GPIO_Pin=GPIO_Pin_11;
+	GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
+	GPIO_Init(GPIOH,&GPIO_InitStructure);
+	
+	GPIO_ResetBits(GPIOH,GPIO_Pin_11);//默认熄灭
+}
+
+/*
+ *函数简介:绿灯点亮
+ *参数说明:无
+ *返回类型:无
+ *备注:无
+ */
+void LED_GON(void)
+{
+	GPIO_SetBits(GPIOH,GPIO_Pin_11);
+}
+
+/*
+ *函数简介:绿灯熄灭
+ *参数说明:无
+ *返回类型:无
+ *备注:无
+ */
+void LED_GOFF(void)
+{
+	GPIO_ResetBits(GPIOH,GPIO_Pin_11);
+}
+
+/*
+ *函数简介:绿灯亮灭反转
+ *参数说明:无
+ *返回类型:无
+ *备注:无
+ */
+void LED_GTurn(void)
+{
+	if(GPIO_ReadInputDataBit(GPIOH,GPIO_Pin_11)==0)//当前绿灯灭
+		GPIO_SetBits(GPIOH,GPIO_Pin_11);
+	else//当前绿灯亮
+		GPIO_ResetBits(GPIOH,GPIO_Pin_11);
+}
+
+/*
+ *函数简介:红色单色LED初始化
+ *参数说明:无
+ *返回类型:无
+ *备注:无
+ */
+void LED_RInit(void)
+{
+	RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOH,ENABLE);//开启时钟
+	
+	GPIO_InitTypeDef GPIO_InitStructure;
+	GPIO_InitStructure.GPIO_Mode=GPIO_Mode_OUT;
+	GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//推挽输出
+	GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
+	GPIO_InitStructure.GPIO_Pin=GPIO_Pin_12;
+	GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
+	GPIO_Init(GPIOH,&GPIO_InitStructure);
+	
+	GPIO_ResetBits(GPIOH,GPIO_Pin_12);//默认熄灭
+}
+
+/*
+ *函数简介:红灯点亮
+ *参数说明:无
+ *返回类型:无
+ *备注:无
+ */
+void LED_RON(void)
+{
+	GPIO_SetBits(GPIOH,GPIO_Pin_12);
+}
+
+/*
+ *函数简介:红灯熄灭
+ *参数说明:无
+ *返回类型:无
+ *备注:无
+ */
+void LED_ROFF(void)
+{
+	GPIO_ResetBits(GPIOH,GPIO_Pin_12);
+}
+
+/*
+ *函数简介:红灯亮灭反转
+ *参数说明:无
+ *返回类型:无
+ *备注:无
+ */
+void LED_RTurn(void)
+{
+	if(GPIO_ReadInputDataBit(GPIOH,GPIO_Pin_12)==0)//当前红灯灭
+		GPIO_SetBits(GPIOH,GPIO_Pin_12);
+	else//当前红灯亮
+		GPIO_ResetBits(GPIOH,GPIO_Pin_12);
+}
+
+/*
+ *函数简介:RGB混色LED初始化
+ *参数说明:无
+ *返回类型:无
+ *备注:蓝色-PH10,绿色-PH11,红色-PH12
+ */
+void LED_MaxInit(void)
+{
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM5,ENABLE);
+	RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOH,ENABLE);//开启时钟
+	
+	TIM_InternalClockConfig(TIM5);//选择时基单元TIM5
+	
+	GPIO_InitTypeDef GPIO_InitStructure;
+	GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF;   
+	GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//复用推挽
+	GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
+	GPIO_InitStructure.GPIO_Pin=GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
+	GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
+	GPIO_Init(GPIOH,&GPIO_InitStructure);//配置TIM5的CH1-3
+	
+	GPIO_PinAFConfig(GPIOH,GPIO_PinSource10,GPIO_AF_TIM5);
+	GPIO_PinAFConfig(GPIOH,GPIO_PinSource11,GPIO_AF_TIM5);
+	GPIO_PinAFConfig(GPIOH,GPIO_PinSource12,GPIO_AF_TIM5);//开启PH10-12的TIM5复用模式
+	
+	TIM_TimeBaseInitTypeDef TIM_InitStructure;
+	TIM_InitStructure.TIM_ClockDivision=TIM_CKD_DIV1;//配置时钟分频为1分频
+	TIM_InitStructure.TIM_CounterMode=TIM_CounterMode_Up;//配置计数器模式为向上计数
+	TIM_InitStructure.TIM_Period=1000-1;//ARR,PWM为千分位
+	TIM_InitStructure.TIM_Prescaler=84-1;//PSC,默认1000Hz
+	TIM_InitStructure.TIM_RepetitionCounter=0;//配置重复计数单元的置为0
+	TIM_TimeBaseInit(TIM5,&TIM_InitStructure);
+	
+	TIM_OCInitTypeDef TIM_OCInitStructure;
+	TIM_OCStructInit(&TIM_OCInitStructure);
+	TIM_OCInitStructure.TIM_OCMode=TIM_OCMode_PWM1;//配置输出比较模式
+	TIM_OCInitStructure.TIM_OCPolarity=TIM_OCPolarity_High;//配置输出比较的极性
+	TIM_OCInitStructure.TIM_OutputState=TIM_OutputState_Enable;//输出使能
+	TIM_OCInitStructure.TIM_Pulse=0;//配置输出比较寄存器CCR的值
+	TIM_OC1Init(TIM5,&TIM_OCInitStructure);
+	TIM_OC2Init(TIM5,&TIM_OCInitStructure);
+	TIM_OC3Init(TIM5,&TIM_OCInitStructure);
+	
+	TIM_Cmd(TIM5,ENABLE);//启动定时器
+}
+
+/*
+ *函数简介:设置混色LED的RGB
+ *参数说明:三个8位整型,表示RGB的三个值
+ *返回类型:无
+ *备注:无
+ */
+void LED_SetColor(uint8_t R,uint8_t G,uint8_t B)
+{
+	TIM_SetCompare1(TIM5,B*1000/255);
+	TIM_SetCompare2(TIM5,G*1000/255);
+	TIM_SetCompare3(TIM5,R*1000/255);
+}

底盘/底盘-old/底盘/Hardware/LED.h

@@ -0,0 +1,20 @@
+#ifndef __LED_H
+#define __LED_H
+
+void LED_Init(void);//三色单色LED初始化
+void LED_BInit(void);//蓝色单色LED初始化
+void LED_BON(void);//蓝灯点亮
+void LED_BOFF(void);//蓝灯熄灭
+void LED_BTurn(void);//蓝灯亮灭反转
+void LED_GInit(void);//绿色单色LED初始化
+void LED_GON(void);//绿灯点亮
+void LED_GOFF(void);//绿灯熄灭
+void LED_GTurn(void);//绿灯亮灭反转
+void LED_RInit(void);//红色单色LED初始化
+void LED_RON(void);//红灯点亮
+void LED_ROFF(void);//红灯熄灭
+void LED_RTurn(void);//红灯亮灭反转
+void LED_MaxInit(void);//RGB混色LED初始化
+void LED_SetColor(uint8_t R,uint8_t G,uint8_t B);//设置混色LED的RGB
+
+#endif

底盘/底盘-old/底盘/Hardware/Remote.c

@@ -0,0 +1,240 @@
+#include "stm32f4xx.h"                  // Device header
+#include "stm32f4xx_conf.h"
+#include "Remote.h"
+#include "UART.h"
+#include "Warming.h"
+
+uint8_t Remote_RxData0[18];//遥控器DMA数据存储器0
+uint8_t Remote_RxData1[18];//遥控器DMA数据存储器1
+
+Remote_Data Remote_RxData;//遥控器接收数据
+Remote_Data Remote_LastRxData;//遥控器上一次接收数据
+uint8_t Remote_Status;//遥控器连接状态,默认未连接(0)
+uint8_t Remote_StartFlag=1;//遥控器启动标志位,0-未在启动阶段,1-准备启动,2-第一次接收到数据
+
+/*
+ *函数简介:遥控器初始化
+ *参数说明:无
+ *返回类型:无
+ *备注:默认接收引脚为PC11(USART3-Rx)
+ *备注:采用串口DMA双缓冲接收
+ *备注:配置定时中断为TIM7 25ms,用来检测遥控器连接情况
+ *备注:加入独立看门狗,用来在数据接收错误时复位(只在上电的一刻可能数据错误)
+ *备注:独立看门狗时钟为LSI(32kHz),预分频数默认为8,故IWDG时钟4kHz,重装载值为0x0FFF(4095)
+ *备注:喂狗时间(溢出时间)T_OUT=Reload/(LSI/Prescaler)=4095/(32k/8)=1.02375s
+ */
+void Remote_Init(void)
+{
+	/*===============配置时钟===============*/
+	RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC,ENABLE);
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3,ENABLE);
+	RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1,ENABLE);
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM7,ENABLE);//开启时钟
+	
+	/*===============配置GPIO===============*/
+	GPIO_InitTypeDef GPIO_InitStructure;
+	GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF;
+	GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//复用推挽
+	GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
+	GPIO_InitStructure.GPIO_Pin=GPIO_Pin_11;
+	GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
+	GPIO_Init(GPIOC,&GPIO_InitStructure);//初始化USART3-Rx(PC11)
+	
+	GPIO_PinAFConfig(GPIOC,GPIO_PinSource11,GPIO_AF_USART3);//开启PC11的USART3复用模式
+	
+	/*===============配置USART和串口接收DMA===============*/
+	USART_InitTypeDef USART_InitStructure;
+	USART_InitStructure.USART_BaudRate=100000;//配置波特率100k
+	USART_InitStructure.USART_HardwareFlowControl=USART_HardwareFlowControl_None;//配置无硬件流控制
+	USART_InitStructure.USART_Mode=USART_Mode_Rx;//配置为接收模式
+	USART_InitStructure.USART_Parity=USART_Parity_Even;//配置为偶校验
+	USART_InitStructure.USART_StopBits=USART_StopBits_1;//配置停止位为1
+	USART_InitStructure.USART_WordLength=USART_WordLength_8b;//配置字长8bit
+	USART_Init(USART3,&USART_InitStructure);//初始化USART3
+	
+	DMA_InitTypeDef DMA_InitStructure;
+	DMA_InitStructure.DMA_Channel=DMA_Channel_4;//选择DMA通道4
+	DMA_InitStructure.DMA_Mode=DMA_Mode_Normal;//普通模式(非自动重装)
+	DMA_InitStructure.DMA_DIR=DMA_DIR_PeripheralToMemory;//转运方向为外设到存储器
+	DMA_InitStructure.DMA_BufferSize=18;//数据传输量为18字节
+	DMA_InitStructure.DMA_Priority=DMA_Priority_VeryHigh;//最高优先级
+	DMA_InitStructure.DMA_PeripheralBaseAddr=(uint32_t)&(USART3->DR);//外设地址(USART的DR数据接收寄存器)
+	DMA_InitStructure.DMA_PeripheralBurst=DMA_PeripheralBurst_Single;//外设突发单次传输
+	DMA_InitStructure.DMA_PeripheralDataSize=DMA_PeripheralDataSize_Byte;//外设数据长度为1字节(8bits)
+	DMA_InitStructure.DMA_PeripheralInc=DMA_PeripheralInc_Disable;//外设地址不自增
+	DMA_InitStructure.DMA_Memory0BaseAddr=(uint32_t)Remote_RxData0;//存储器地址(遥控器DMA数据存储器0)
+	DMA_InitStructure.DMA_MemoryBurst=DMA_MemoryBurst_Single;//存储器突发单次传输
+	DMA_InitStructure.DMA_MemoryDataSize=DMA_MemoryDataSize_Byte;//存储器数据长度为1字节(8bits)
+	DMA_InitStructure.DMA_MemoryInc=DMA_MemoryInc_Enable;//存储器地址自增
+	DMA_InitStructure.DMA_FIFOMode=DMA_FIFOMode_Disable;//不使用FIFO模式
+	DMA_InitStructure.DMA_FIFOThreshold=DMA_FIFOStatus_1QuarterFull;//设置FIFO阈值为1/4(不使用FIFO模式时,此位无意义)
+	DMA_Init(DMA1_Stream1,&DMA_InitStructure);//初始化数据流1
+	
+	DMA_DoubleBufferModeConfig(DMA1_Stream1,(uint32_t)Remote_RxData1,DMA_Memory_0);//设置双缓冲搬运从遥控器DMA数据存储器0开始
+	DMA_DoubleBufferModeCmd(DMA1_Stream1,ENABLE);//使能DMA双缓冲功能
+	
+	/*===============配置定时器===============*/
+	TIM_InternalClockConfig(TIM7);//选择时基单元的时钟(TIM7)
+	
+	TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure;//配置时基单元（配置参数）
+	TIM_TimeBaseInitStructure.TIM_ClockDivision=TIM_CKD_DIV1;//配置时钟分频为1分频
+	TIM_TimeBaseInitStructure.TIM_CounterMode=TIM_CounterMode_Up;//配置计数器模式为向上计数
+	TIM_TimeBaseInitStructure.TIM_Period=2100-1;//配置自动重装值ARR
+	TIM_TimeBaseInitStructure.TIM_Prescaler=1000-1;//配置分频值PSC,默认定时25ms
+	TIM_TimeBaseInitStructure.TIM_RepetitionCounter=0;//配置重复计数单元的置为0
+	TIM_TimeBaseInit(TIM7,&TIM_TimeBaseInitStructure);//初始化TIM7
+	
+	TIM_ClearFlag(TIM7,TIM_FLAG_Update);//清除配置时基单元产生的中断标志位
+	
+	/*===============配置接收中断和定时器中断===============*/
+	USART_ITConfig(USART3,USART_IT_RXNE,ENABLE);//打通USART3到NVIC的串口接收中断通道
+	TIM_ITConfig(TIM7,TIM_IT_Update,ENABLE);//使能TIM7更新中断
+		
+	NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//选择NVIC分组2(2位抢占优先级,2位响应优先级)
+	
+	NVIC_InitTypeDef NVIC_InitStructure;
+	NVIC_InitStructure.NVIC_IRQChannel=USART3_IRQn;//选择USART3中断通道
+	NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;//使能中断通道
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=1;//抢占优先级为1
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority=1;//响应优先级为1
+	NVIC_Init(&NVIC_InitStructure);//初始化USART3的NVIC
+	NVIC_InitStructure.NVIC_IRQChannel=TIM7_IRQn;//选择中断通道为TIM2
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=2;//TIM2的抢占优先级
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority=2;//TIM2的响应优先级
+	NVIC_Init(&NVIC_InitStructure);//初始化NVIC
+	
+	/*===============使能===============*/
+	DMA_Cmd(DMA1_Stream1,ENABLE);//使能DMA1的数据流1
+	USART_DMACmd(USART3,USART_DMAReq_Rx,ENABLE);//使能串口USART3的DMA搬运
+	USART_Cmd(USART3,ENABLE);//启动USART3
+	TIM_Cmd(TIM7,ENABLE);//启动定时器
+	
+	/*===============配置IWDG===============*/
+	IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
+	IWDG_SetPrescaler(IWDG_Prescaler_8);//8分频
+	IWDG_SetReload(0x0FFF);//设置重装载值
+	IWDG_Enable();
+}
+
+/*
+ *函数简介:遥控器开启
+ *参数说明:无
+ *返回类型:无
+ *备注:默认开启串口USART3
+ */
+void Remote_ON(void)
+{
+	USART_Cmd(USART3,ENABLE);//启动USART3
+}
+
+/*
+ *函数简介:遥控器关闭
+ *参数说明:无
+ *返回类型:无
+ *备注:默认关闭串口USART3
+ */
+void Remote_OFF(void)
+{
+	USART_Cmd(USART3,DISABLE);//失能USART3
+	Remote_Status=0;//遥控器连接状态变为未连接
+}
+
+/*
+ *函数简介:遥控器DMA转运复位
+ *参数说明:无
+ *返回类型:无
+ *备注:无
+ */
+void Remote_TransferReset(void)
+{
+	while(DMA_GetFlagStatus(DMA1_Stream1,DMA_FLAG_TCIF1)==RESET);//判断接收完成
+	DMA_ClearFlag(DMA1_Stream1,DMA_FLAG_TCIF1);//清除接收完成标志位
+	DMA_Cmd(DMA1_Stream1,DISABLE);//失能DMA1的数据流1
+	while(DMA_GetCmdStatus(DMA1_Stream1)!=DISABLE);//检测DMA1的数据流1为可配置状态
+	DMA_SetCurrDataCounter(DMA1_Stream1,18);//恢复传输计数器的值
+	DMA_Cmd(DMA1_Stream1,ENABLE);//使能DMA1的数据流1
+}
+
+/*
+ *函数简介:遥控器数据处理
+ *参数说明:无
+ *返回类型:无
+ *备注:遥控器接收数据共18Bytes(144bits)
+ */
+void Remote_DataProcess(void)
+{
+	uint8_t *Data;//选择存储器
+	if(DMA_GetCurrentMemoryTarget(DMA1_Stream1)==0)Data=Remote_RxData1;//若当前转运位于存储器0,则存储器1数据完整,采用存储器1进行数据处理
+	else Data=Remote_RxData0;//若当前转运位于存储器1,则存储器0数据完整,采用存储器0进行数据处理
+	
+	Remote_RxData.Remote_R_RL=(((uint16_t)Data[1]<<8) | Data[0]) & 0x07FF;//B[0:10],11bits
+	Remote_RxData.Remote_R_UD=(((uint16_t)Data[2]<<5) | (Data[1]>>3)) & 0x07FF;//B[11:21],11bits
+	Remote_RxData.Remote_L_RL=(((uint16_t)Data[4]<<10) | (((uint16_t)Data[3]<<2) | (Data[2]>>6))) & 0x07FF;//B[22:32],11bits
+	Remote_RxData.Remote_L_UD=(((uint16_t)Data[5]<<7) | (Data[4]>>1)) & 0x07FF;//B[33:43],11bits
+	
+	Remote_RxData.Remote_RS=(Data[5]>>4) & 0x03;//B[44:45],2bits
+	Remote_RxData.Remote_LS=(Data[5]>>6) & 0x03;//B[46:47],2bits
+	
+	Remote_RxData.Remote_Mouse_RL=(int16_t)(((uint16_t)Data[7]<<8) | Data[6]);//B[48:63],16bits
+	Remote_RxData.Remote_Mouse_DU=(int16_t)(((uint16_t)Data[9]<<8) | Data[8]);//B[64:79],16bits
+	Remote_RxData.Remote_Mouse_Wheel=(int16_t)(((uint16_t)Data[11]<<8) | Data[10]);//B[80:95],16bits
+	Remote_RxData.Remote_Mouse_KeyL=Data[12];//B[96:103],8bits
+	Remote_RxData.Remote_Mouse_KeyR=Data[13];//B[104:111],8bits
+	
+	Remote_RxData.Remote_Key_W=Data[14] & 0x01;//B[112:112],1bits
+	Remote_RxData.Remote_Key_S=(Data[14]>>1) & 0x01;//B[113:113],1bits
+	Remote_RxData.Remote_Key_A=(Data[14]>>2) & 0x01;//B[114:114],1bits
+	Remote_RxData.Remote_Key_D=(Data[14]>>3) & 0x01;//B[115:115],1bits
+	Remote_RxData.Remote_Key_Shift=(Data[14]>>4) & 0x01;//B[116:116],1bits
+	Remote_RxData.Remote_Key_Ctrl=(Data[14]>>5) & 0x01;//B[117:117],1bits
+	Remote_RxData.Remote_Key_Q=(Data[14]>>6) & 0x01;//B[118:118],1bits
+	Remote_RxData.Remote_Key_E=(Data[14]>>7) & 0x01;//B[119:119],1bits
+	
+	Remote_RxData.Remote_ThumbWheel=(int16_t)((uint16_t)Data[17]<<8) | Data[16];//B[120:135],16bits
+}
+
+/*
+ *函数简介:遥控器接收中断
+ *参数说明:无
+ *返回类型:无
+ *备注:USART的接收中断
+ */
+void USART3_IRQHandler(void)
+{
+	TIM_SetCounter(TIM7,0);
+	TIM_Cmd(TIM7,DISABLE);//关闭定时器并重置计数值
+	if(DMA_GetCurrDataCounter(DMA1_Stream1)==18)//转运一次完成,并交换了存储器
+	{
+		Remote_TransferReset();//复位DMA1的数据流1
+		Remote_DataProcess();//数据处理
+		if(Remote_StartFlag==1)//第一次接收数据
+		{
+			while(Remote_RxData.Remote_R_RL!=1024 || Remote_RxData.Remote_R_UD!=1024 || Remote_RxData.Remote_L_RL!=1024 || Remote_RxData.Remote_L_UD!=1024)//数据错误
+				Warming_RemoteDataERROR();//数据错误报错,等待看门狗复位
+			Remote_StartFlag=2;
+			Warming_LEDClean();
+		}
+		Remote_Status=1;//遥控器已连接
+	}
+	TIM_Cmd(TIM7,ENABLE);//开启定时
+	
+	USART_ClearITPendingBit(USART3,USART_IT_RXNE);//清除接收中断标志位
+}
+
+/*
+ *函数简介:TIM7定时器更新中断函数
+ *参数说明:无
+ *返回类型:无
+ *备注:进入中断即遥控器未连接
+ */
+void TIM7_IRQHandler(void)
+{
+	if(TIM_GetITStatus(TIM7,TIM_IT_Update)==SET)//检测TIM2更新
+	{
+		TIM_ClearITPendingBit(TIM7,TIM_IT_Update);//清除标志位
+		Warming_RemoteNoCheck();//遥控器未连接报警
+		Remote_Status=0;//遥控器连接状态变为未连接
+		Remote_StartFlag=1;//遥控器处于准备启动阶段
+	}
+}
+

底盘/底盘-old/底盘/Hardware/Remote.h

@@ -0,0 +1,47 @@
+#ifndef __REMOTE_H
+#define __REMOTE_H
+
+typedef struct
+{
+	uint16_t Remote_R_RL;//通道0-右摇杆左右(右为大),范围364(最左端)~1684(最右端),默认值1024(中间)
+	uint16_t Remote_R_UD;//通道1-右摇杆上下(上为大),范围364(最下端)~1684(最上端),默认值1024(中间)
+	uint16_t Remote_L_RL;//通道2-左摇杆左右(右为大),范围364(最左端)~1684(最右端),默认值1024(中间)
+	uint16_t Remote_L_UD;//通道3-左摇杆上下(上为大),范围364(最下端)~1684(最上端),默认值1024(中间)
+	
+	uint8_t Remote_LS;//S1-左侧拨动开关,范围1~3,上为1,下为2,中间为3
+	uint8_t Remote_RS;//S2-右侧拨动开关,范围1~3,上为1,下为2,中间为3
+	
+	int16_t Remote_Mouse_RL;//鼠标X轴-鼠标左右速度,范围-32768~32767,向右为正,向左为负,静止值为0
+	int16_t Remote_Mouse_DU;//鼠标Y轴-鼠标前后速度,范围-32768~32767,向后为正,向前为负,静止值为0
+	int16_t Remote_Mouse_Wheel;//鼠标Z轴-鼠标滚轮速度,范围-32768~32767,向前为正,向后为负,静止值为0
+	uint8_t Remote_Mouse_KeyL;//鼠标左键,按下为1,未按下为0
+	uint8_t Remote_Mouse_KeyR;//鼠标右键,按下为1,未按下为0
+
+	uint8_t Remote_Key_1;//键盘1键,按下为1,未按下为0
+	uint8_t Remote_Key_2;//键盘2键,按下为1,未按下为0
+	
+	uint8_t Remote_Key_W;//键盘W键,按下为1,未按下为0
+	uint8_t Remote_Key_S;//键盘S键,按下为1,未按下为0
+	uint8_t Remote_Key_A;//键盘A键,按下为1,未按下为0
+	uint8_t Remote_Key_D;//键盘D键,按下为1,未按下为0
+	uint8_t Remote_Key_Q;//键盘Q键,按下为1,未按下为0
+	uint8_t Remote_Key_E;//键盘E键,按下为1,未按下为0
+	uint8_t Remote_Key_Shift;//键盘Shift键,按下为1,未按下为0
+	uint8_t Remote_Key_Ctrl;//键盘Ctrl键,按下为1,未按下为0
+	uint8_t Remote_KeyLast_Shift;//上一次键盘Shift键
+	uint8_t Remote_KeyLast_Ctrl;//上一次键盘Ctrl键
+	uint8_t Remote_KeyPush_Ctrl;//按下键盘Ctrl键,按下时0,1切换
+	uint8_t Remote_KeyPush_Shift;//按下键盘Shift键,按下时0,1切换
+	
+	int16_t Remote_ThumbWheel;//保留字段-遥控器拨轮,范围-3278(最上端)~1684(最下端),默认值1024
+}Remote_Data;//遥控器接收结构体
+
+extern Remote_Data Remote_RxData;//遥控器接收数据
+extern uint8_t Remote_Status;//遥控器连接状态,默认未连接(0)
+extern uint8_t Remote_StartFlag;//遥控器启动标志位,0-未在启动阶段,1-准备启动,2-第一次接收到数据
+
+void Remote_Init(void);//遥控器初始化
+void Remote_ON(void);//遥控器开启
+void Remote_OFF(void);//遥控器关闭
+
+#endif

底盘/底盘-old/底盘/Library/misc.c

@@ -0,0 +1,241 @@
+/**
+  ******************************************************************************
+  * @file    misc.c
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file provides all the miscellaneous firmware functions (add-on
+  *          to CMSIS functions).
+  *          
+  *  @verbatim   
+  *                               
+  *          ===================================================================      
+  *                        How to configure Interrupts using driver 
+  *          ===================================================================      
+  * 
+  *            This section provide functions allowing to configure the NVIC interrupts (IRQ).
+  *            The Cortex-M4 exceptions are managed by CMSIS functions.
+  *
+  *            1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
+  *                function according to the following table.
+ 
+  *  The table below gives the allowed values of the pre-emption priority and subpriority according
+  *  to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+  *    ==========================================================================================================================
+  *      NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
+  *    ==========================================================================================================================
+  *     NVIC_PriorityGroup_0  |                0                  |            0-15             | 0 bits for pre-emption priority
+  *                           |                                   |                             | 4 bits for subpriority
+  *    --------------------------------------------------------------------------------------------------------------------------
+  *     NVIC_PriorityGroup_1  |                0-1                |            0-7              | 1 bits for pre-emption priority
+  *                           |                                   |                             | 3 bits for subpriority
+  *    --------------------------------------------------------------------------------------------------------------------------    
+  *     NVIC_PriorityGroup_2  |                0-3                |            0-3              | 2 bits for pre-emption priority
+  *                           |                                   |                             | 2 bits for subpriority
+  *    --------------------------------------------------------------------------------------------------------------------------    
+  *     NVIC_PriorityGroup_3  |                0-7                |            0-1              | 3 bits for pre-emption priority
+  *                           |                                   |                             | 1 bits for subpriority
+  *    --------------------------------------------------------------------------------------------------------------------------    
+  *     NVIC_PriorityGroup_4  |                0-15               |            0                | 4 bits for pre-emption priority
+  *                           |                                   |                             | 0 bits for subpriority                       
+  *    ==========================================================================================================================     
+  *
+  *            2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init()  
+  *
+  * @note  When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 
+  *        The pending IRQ priority will be managed only by the subpriority.
+  *
+  * @note  IRQ priority order (sorted by highest to lowest priority):
+  *         - Lowest pre-emption priority
+  *         - Lowest subpriority
+  *         - Lowest hardware priority (IRQ number)
+  *
+  *  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "misc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup MISC 
+  * @brief MISC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup MISC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Configures the priority grouping: pre-emption priority and subpriority.
+  * @param  NVIC_PriorityGroup: specifies the priority grouping bits length. 
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
+  *                                4 bits for subpriority
+  *     @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
+  *                                3 bits for subpriority
+  *     @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
+  *                                2 bits for subpriority
+  *     @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
+  *                                1 bits for subpriority
+  *     @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
+  *                                0 bits for subpriority
+  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 
+  *         The pending IRQ priority will be managed only by the subpriority. 
+  * @retval None
+  */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+  
+  /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+  SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+  * @brief  Initializes the NVIC peripheral according to the specified
+  *         parameters in the NVIC_InitStruct.
+  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+  *         function should be called before. 
+  * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
+  *         the configuration information for the specified NVIC peripheral.
+  * @retval None
+  */
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+  uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  
+  assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+    
+  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+  {
+    /* Compute the Corresponding IRQ Priority --------------------------------*/    
+    tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
+    tmppre = (0x4 - tmppriority);
+    tmpsub = tmpsub >> tmppriority;
+
+    tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+    tmppriority |=  (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
+        
+    tmppriority = tmppriority << 0x04;
+        
+    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+    
+    /* Enable the Selected IRQ Channels --------------------------------------*/
+    NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+  else
+  {
+    /* Disable the Selected IRQ Channels -------------------------------------*/
+    NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+}
+
+/**
+  * @brief  Sets the vector table location and Offset.
+  * @param  NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.
+  *     @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.
+  * @param  Offset: Vector Table base offset field. This value must be a multiple of 0x200.
+  * @retval None
+  */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{ 
+  /* Check the parameters */
+  assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+  assert_param(IS_NVIC_OFFSET(Offset));  
+   
+  SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+  * @brief  Selects the condition for the system to enter low power mode.
+  * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
+  *     @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
+  *     @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
+  * @param  NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_LP(LowPowerMode));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  
+  
+  if (NewState != DISABLE)
+  {
+    SCB->SCR |= LowPowerMode;
+  }
+  else
+  {
+    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+  }
+}
+
+/**
+  * @brief  Configures the SysTick clock source.
+  * @param  SysTick_CLKSource: specifies the SysTick clock source.
+  *   This parameter can be one of the following values:
+  *     @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
+  *     @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+  if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+  {
+    SysTick->CTRL |= SysTick_CLKSource_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

底盘/底盘-old/底盘/Library/misc.h

@@ -0,0 +1,170 @@
+/**
+  ******************************************************************************
+  * @file    misc.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the miscellaneous
+  *          firmware library functions (add-on to CMSIS functions).
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MISC_H
+#define __MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup MISC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  NVIC Init Structure definition  
+  */
+
+typedef struct
+{
+  uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
+                                                   This parameter can be an enumerator of @ref IRQn_Type 
+                                                   enumeration (For the complete STM32 Devices IRQ Channels
+                                                   list, please refer to stm32f4xx.h file) */
+
+  uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel
+                                                   specified in NVIC_IRQChannel. This parameter can be a value
+                                                   between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
+                                                   A lower priority value indicates a higher priority */
+
+  uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified
+                                                   in NVIC_IRQChannel. This parameter can be a value
+                                                   between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
+                                                   A lower priority value indicates a higher priority */
+
+  FunctionalState NVIC_IRQChannelCmd;         /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+                                                   will be enabled or disabled. 
+                                                   This parameter can be set either to ENABLE or DISABLE */   
+} NVIC_InitTypeDef;
+ 
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup MISC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup MISC_Vector_Table_Base 
+  * @{
+  */
+
+#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+                                  ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+  * @}
+  */
+
+/** @defgroup MISC_System_Low_Power 
+  * @{
+  */
+
+#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+                        ((LP) == NVIC_LP_SLEEPDEEP) || \
+                        ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Preemption_Priority_Group 
+  * @{
+  */
+
+#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+                                                            4 bits for subpriority */
+#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+                                                            3 bits for subpriority */
+#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+                                                            2 bits for subpriority */
+#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+                                                            1 bits for subpriority */
+#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
+                                                            0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+                                       ((GROUP) == NVIC_PriorityGroup_1) || \
+                                       ((GROUP) == NVIC_PriorityGroup_2) || \
+                                       ((GROUP) == NVIC_PriorityGroup_3) || \
+                                       ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x000FFFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_SysTick_clock_source 
+  * @{
+  */
+
+#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MISC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

底盘/底盘-old/底盘/Library/stm32f4xx_adc.h

@@ -0,0 +1,648 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_adc.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the ADC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_ADC_H
+#define __STM32F4xx_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief   ADC Init structure definition  
+  */ 
+typedef struct
+{
+  uint32_t ADC_Resolution;                /*!< Configures the ADC resolution dual mode. 
+                                               This parameter can be a value of @ref ADC_resolution */                                   
+  FunctionalState ADC_ScanConvMode;       /*!< Specifies whether the conversion 
+                                               is performed in Scan (multichannels) 
+                                               or Single (one channel) mode.
+                                               This parameter can be set to ENABLE or DISABLE */ 
+  FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion 
+                                               is performed in Continuous or Single mode.
+                                               This parameter can be set to ENABLE or DISABLE. */
+  uint32_t ADC_ExternalTrigConvEdge;      /*!< Select the external trigger edge and
+                                               enable the trigger of a regular group. 
+                                               This parameter can be a value of 
+                                               @ref ADC_external_trigger_edge_for_regular_channels_conversion */
+  uint32_t ADC_ExternalTrigConv;          /*!< Select the external event used to trigger 
+                                               the start of conversion of a regular group.
+                                               This parameter can be a value of 
+                                               @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */
+  uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data  alignment
+                                               is left or right. This parameter can be 
+                                               a value of @ref ADC_data_align */
+  uint8_t  ADC_NbrOfConversion;           /*!< Specifies the number of ADC conversions
+                                               that will be done using the sequencer for
+                                               regular channel group.
+                                               This parameter must range from 1 to 16. */
+}ADC_InitTypeDef;
+  
+/** 
+  * @brief   ADC Common Init structure definition  
+  */ 
+typedef struct 
+{
+  uint32_t ADC_Mode;                      /*!< Configures the ADC to operate in 
+                                               independent or multi mode. 
+                                               This parameter can be a value of @ref ADC_Common_mode */                                              
+  uint32_t ADC_Prescaler;                 /*!< Select the frequency of the clock 
+                                               to the ADC. The clock is common for all the ADCs.
+                                               This parameter can be a value of @ref ADC_Prescaler */
+  uint32_t ADC_DMAAccessMode;             /*!< Configures the Direct memory access 
+                                              mode for multi ADC mode.
+                                               This parameter can be a value of 
+                                               @ref ADC_Direct_memory_access_mode_for_multi_mode */
+  uint32_t ADC_TwoSamplingDelay;          /*!< Configures the Delay between 2 sampling phases.
+                                               This parameter can be a value of 
+                                               @ref ADC_delay_between_2_sampling_phases */
+  
+}ADC_CommonInitTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants
+  * @{
+  */ 
+#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+                                   ((PERIPH) == ADC2) || \
+                                   ((PERIPH) == ADC3))  
+
+/** @defgroup ADC_Common_mode 
+  * @{
+  */ 
+#define ADC_Mode_Independent                       ((uint32_t)0x00000000)       
+#define ADC_DualMode_RegSimult_InjecSimult         ((uint32_t)0x00000001)
+#define ADC_DualMode_RegSimult_AlterTrig           ((uint32_t)0x00000002)
+#define ADC_DualMode_InjecSimult                   ((uint32_t)0x00000005)
+#define ADC_DualMode_RegSimult                     ((uint32_t)0x00000006)
+#define ADC_DualMode_Interl                        ((uint32_t)0x00000007)
+#define ADC_DualMode_AlterTrig                     ((uint32_t)0x00000009)
+#define ADC_TripleMode_RegSimult_InjecSimult       ((uint32_t)0x00000011)
+#define ADC_TripleMode_RegSimult_AlterTrig         ((uint32_t)0x00000012)
+#define ADC_TripleMode_InjecSimult                 ((uint32_t)0x00000015)
+#define ADC_TripleMode_RegSimult                   ((uint32_t)0x00000016)
+#define ADC_TripleMode_Interl                      ((uint32_t)0x00000017)
+#define ADC_TripleMode_AlterTrig                   ((uint32_t)0x00000019)
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
+                           ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \
+                           ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \
+                           ((MODE) == ADC_DualMode_InjecSimult) || \
+                           ((MODE) == ADC_DualMode_RegSimult) || \
+                           ((MODE) == ADC_DualMode_Interl) || \
+                           ((MODE) == ADC_DualMode_AlterTrig) || \
+                           ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \
+                           ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \
+                           ((MODE) == ADC_TripleMode_InjecSimult) || \
+                           ((MODE) == ADC_TripleMode_RegSimult) || \
+                           ((MODE) == ADC_TripleMode_Interl) || \
+                           ((MODE) == ADC_TripleMode_AlterTrig))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_Prescaler 
+  * @{
+  */ 
+#define ADC_Prescaler_Div2                         ((uint32_t)0x00000000)
+#define ADC_Prescaler_Div4                         ((uint32_t)0x00010000)
+#define ADC_Prescaler_Div6                         ((uint32_t)0x00020000)
+#define ADC_Prescaler_Div8                         ((uint32_t)0x00030000)
+#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \
+                                     ((PRESCALER) == ADC_Prescaler_Div4) || \
+                                     ((PRESCALER) == ADC_Prescaler_Div6) || \
+                                     ((PRESCALER) == ADC_Prescaler_Div8))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode 
+  * @{
+  */ 
+#define ADC_DMAAccessMode_Disabled      ((uint32_t)0x00000000)     /* DMA mode disabled */
+#define ADC_DMAAccessMode_1             ((uint32_t)0x00004000)     /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
+#define ADC_DMAAccessMode_2             ((uint32_t)0x00008000)     /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
+#define ADC_DMAAccessMode_3             ((uint32_t)0x0000C000)     /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
+#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
+                                      ((MODE) == ADC_DMAAccessMode_1) || \
+                                      ((MODE) == ADC_DMAAccessMode_2) || \
+                                      ((MODE) == ADC_DMAAccessMode_3))
+                                     
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_delay_between_2_sampling_phases 
+  * @{
+  */ 
+#define ADC_TwoSamplingDelay_5Cycles               ((uint32_t)0x00000000)
+#define ADC_TwoSamplingDelay_6Cycles               ((uint32_t)0x00000100)
+#define ADC_TwoSamplingDelay_7Cycles               ((uint32_t)0x00000200)
+#define ADC_TwoSamplingDelay_8Cycles               ((uint32_t)0x00000300)
+#define ADC_TwoSamplingDelay_9Cycles               ((uint32_t)0x00000400)
+#define ADC_TwoSamplingDelay_10Cycles              ((uint32_t)0x00000500)
+#define ADC_TwoSamplingDelay_11Cycles              ((uint32_t)0x00000600)
+#define ADC_TwoSamplingDelay_12Cycles              ((uint32_t)0x00000700)
+#define ADC_TwoSamplingDelay_13Cycles              ((uint32_t)0x00000800)
+#define ADC_TwoSamplingDelay_14Cycles              ((uint32_t)0x00000900)
+#define ADC_TwoSamplingDelay_15Cycles              ((uint32_t)0x00000A00)
+#define ADC_TwoSamplingDelay_16Cycles              ((uint32_t)0x00000B00)
+#define ADC_TwoSamplingDelay_17Cycles              ((uint32_t)0x00000C00)
+#define ADC_TwoSamplingDelay_18Cycles              ((uint32_t)0x00000D00)
+#define ADC_TwoSamplingDelay_19Cycles              ((uint32_t)0x00000E00)
+#define ADC_TwoSamplingDelay_20Cycles              ((uint32_t)0x00000F00)
+#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_20Cycles))
+                                     
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_resolution 
+  * @{
+  */ 
+#define ADC_Resolution_12b                         ((uint32_t)0x00000000)
+#define ADC_Resolution_10b                         ((uint32_t)0x01000000)
+#define ADC_Resolution_8b                          ((uint32_t)0x02000000)
+#define ADC_Resolution_6b                          ((uint32_t)0x03000000)
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
+                                       ((RESOLUTION) == ADC_Resolution_10b) || \
+                                       ((RESOLUTION) == ADC_Resolution_8b) || \
+                                       ((RESOLUTION) == ADC_Resolution_6b))
+                                      
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion 
+  * @{
+  */ 
+#define ADC_ExternalTrigConvEdge_None          ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConvEdge_Rising        ((uint32_t)0x10000000)
+#define ADC_ExternalTrigConvEdge_Falling       ((uint32_t)0x20000000)
+#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
+#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
+                             ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
+                             ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
+                             ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion 
+  * @{
+  */ 
+#define ADC_ExternalTrigConv_T1_CC1                ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConv_T1_CC2                ((uint32_t)0x01000000)
+#define ADC_ExternalTrigConv_T1_CC3                ((uint32_t)0x02000000)
+#define ADC_ExternalTrigConv_T2_CC2                ((uint32_t)0x03000000)
+#define ADC_ExternalTrigConv_T2_CC3                ((uint32_t)0x04000000)
+#define ADC_ExternalTrigConv_T2_CC4                ((uint32_t)0x05000000)
+#define ADC_ExternalTrigConv_T2_TRGO               ((uint32_t)0x06000000)
+#define ADC_ExternalTrigConv_T3_CC1                ((uint32_t)0x07000000)
+#define ADC_ExternalTrigConv_T3_TRGO               ((uint32_t)0x08000000)
+#define ADC_ExternalTrigConv_T4_CC4                ((uint32_t)0x09000000)
+#define ADC_ExternalTrigConv_T5_CC1                ((uint32_t)0x0A000000)
+#define ADC_ExternalTrigConv_T5_CC2                ((uint32_t)0x0B000000)
+#define ADC_ExternalTrigConv_T5_CC3                ((uint32_t)0x0C000000)
+#define ADC_ExternalTrigConv_T8_CC1                ((uint32_t)0x0D000000)
+#define ADC_ExternalTrigConv_T8_TRGO               ((uint32_t)0x0E000000)
+#define ADC_ExternalTrigConv_Ext_IT11              ((uint32_t)0x0F000000)
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_data_align 
+  * @{
+  */ 
+#define ADC_DataAlign_Right                        ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left                         ((uint32_t)0x00000800)
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
+                                  ((ALIGN) == ADC_DataAlign_Left))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_channels 
+  * @{
+  */ 
+#define ADC_Channel_0                               ((uint8_t)0x00)
+#define ADC_Channel_1                               ((uint8_t)0x01)
+#define ADC_Channel_2                               ((uint8_t)0x02)
+#define ADC_Channel_3                               ((uint8_t)0x03)
+#define ADC_Channel_4                               ((uint8_t)0x04)
+#define ADC_Channel_5                               ((uint8_t)0x05)
+#define ADC_Channel_6                               ((uint8_t)0x06)
+#define ADC_Channel_7                               ((uint8_t)0x07)
+#define ADC_Channel_8                               ((uint8_t)0x08)
+#define ADC_Channel_9                               ((uint8_t)0x09)
+#define ADC_Channel_10                              ((uint8_t)0x0A)
+#define ADC_Channel_11                              ((uint8_t)0x0B)
+#define ADC_Channel_12                              ((uint8_t)0x0C)
+#define ADC_Channel_13                              ((uint8_t)0x0D)
+#define ADC_Channel_14                              ((uint8_t)0x0E)
+#define ADC_Channel_15                              ((uint8_t)0x0F)
+#define ADC_Channel_16                              ((uint8_t)0x10)
+#define ADC_Channel_17                              ((uint8_t)0x11)
+#define ADC_Channel_18                              ((uint8_t)0x12)
+
+#if defined (STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_16)
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
+
+#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F410xx) || defined (STM32F411xE)
+#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_18)
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE */
+
+#define ADC_Channel_Vrefint                         ((uint8_t)ADC_Channel_17)
+#define ADC_Channel_Vbat                            ((uint8_t)ADC_Channel_18)
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \
+                                 ((CHANNEL) == ADC_Channel_1) || \
+                                 ((CHANNEL) == ADC_Channel_2) || \
+                                 ((CHANNEL) == ADC_Channel_3) || \
+                                 ((CHANNEL) == ADC_Channel_4) || \
+                                 ((CHANNEL) == ADC_Channel_5) || \
+                                 ((CHANNEL) == ADC_Channel_6) || \
+                                 ((CHANNEL) == ADC_Channel_7) || \
+                                 ((CHANNEL) == ADC_Channel_8) || \
+                                 ((CHANNEL) == ADC_Channel_9) || \
+                                 ((CHANNEL) == ADC_Channel_10) || \
+                                 ((CHANNEL) == ADC_Channel_11) || \
+                                 ((CHANNEL) == ADC_Channel_12) || \
+                                 ((CHANNEL) == ADC_Channel_13) || \
+                                 ((CHANNEL) == ADC_Channel_14) || \
+                                 ((CHANNEL) == ADC_Channel_15) || \
+                                 ((CHANNEL) == ADC_Channel_16) || \
+                                 ((CHANNEL) == ADC_Channel_17) || \
+                                 ((CHANNEL) == ADC_Channel_18))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_sampling_times 
+  * @{
+  */ 
+#define ADC_SampleTime_3Cycles                    ((uint8_t)0x00)
+#define ADC_SampleTime_15Cycles                   ((uint8_t)0x01)
+#define ADC_SampleTime_28Cycles                   ((uint8_t)0x02)
+#define ADC_SampleTime_56Cycles                   ((uint8_t)0x03)
+#define ADC_SampleTime_84Cycles                   ((uint8_t)0x04)
+#define ADC_SampleTime_112Cycles                  ((uint8_t)0x05)
+#define ADC_SampleTime_144Cycles                  ((uint8_t)0x06)
+#define ADC_SampleTime_480Cycles                  ((uint8_t)0x07)
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \
+                                  ((TIME) == ADC_SampleTime_15Cycles) || \
+                                  ((TIME) == ADC_SampleTime_28Cycles) || \
+                                  ((TIME) == ADC_SampleTime_56Cycles) || \
+                                  ((TIME) == ADC_SampleTime_84Cycles) || \
+                                  ((TIME) == ADC_SampleTime_112Cycles) || \
+                                  ((TIME) == ADC_SampleTime_144Cycles) || \
+                                  ((TIME) == ADC_SampleTime_480Cycles))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion 
+  * @{
+  */ 
+#define ADC_ExternalTrigInjecConvEdge_None          ((uint32_t)0x00000000)
+#define ADC_ExternalTrigInjecConvEdge_Rising        ((uint32_t)0x00100000)
+#define ADC_ExternalTrigInjecConvEdge_Falling       ((uint32_t)0x00200000)
+#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
+#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
+                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
+                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
+                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
+                                            
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion 
+  * @{
+  */ 
+#define ADC_ExternalTrigInjecConv_T1_CC4            ((uint32_t)0x00000000)
+#define ADC_ExternalTrigInjecConv_T1_TRGO           ((uint32_t)0x00010000)
+#define ADC_ExternalTrigInjecConv_T2_CC1            ((uint32_t)0x00020000)
+#define ADC_ExternalTrigInjecConv_T2_TRGO           ((uint32_t)0x00030000)
+#define ADC_ExternalTrigInjecConv_T3_CC2            ((uint32_t)0x00040000)
+#define ADC_ExternalTrigInjecConv_T3_CC4            ((uint32_t)0x00050000)
+#define ADC_ExternalTrigInjecConv_T4_CC1            ((uint32_t)0x00060000)
+#define ADC_ExternalTrigInjecConv_T4_CC2            ((uint32_t)0x00070000)
+#define ADC_ExternalTrigInjecConv_T4_CC3            ((uint32_t)0x00080000)
+#define ADC_ExternalTrigInjecConv_T4_TRGO           ((uint32_t)0x00090000)
+#define ADC_ExternalTrigInjecConv_T5_CC4            ((uint32_t)0x000A0000)
+#define ADC_ExternalTrigInjecConv_T5_TRGO           ((uint32_t)0x000B0000)
+#define ADC_ExternalTrigInjecConv_T8_CC2            ((uint32_t)0x000C0000)
+#define ADC_ExternalTrigInjecConv_T8_CC3            ((uint32_t)0x000D0000)
+#define ADC_ExternalTrigInjecConv_T8_CC4            ((uint32_t)0x000E0000)
+#define ADC_ExternalTrigInjecConv_Ext_IT15          ((uint32_t)0x000F0000)
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_injected_channel_selection 
+  * @{
+  */ 
+#define ADC_InjectedChannel_1                       ((uint8_t)0x14)
+#define ADC_InjectedChannel_2                       ((uint8_t)0x18)
+#define ADC_InjectedChannel_3                       ((uint8_t)0x1C)
+#define ADC_InjectedChannel_4                       ((uint8_t)0x20)
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_2) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_3) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_4))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_analog_watchdog_selection 
+  * @{
+  */ 
+#define ADC_AnalogWatchdog_SingleRegEnable         ((uint32_t)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable       ((uint32_t)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable  ((uint32_t)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable            ((uint32_t)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable          ((uint32_t)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable    ((uint32_t)0x00C00000)
+#define ADC_AnalogWatchdog_None                    ((uint32_t)0x00000000)
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_None))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_interrupts_definition 
+  * @{
+  */ 
+#define ADC_IT_EOC                                 ((uint16_t)0x0205)  
+#define ADC_IT_AWD                                 ((uint16_t)0x0106)  
+#define ADC_IT_JEOC                                ((uint16_t)0x0407)  
+#define ADC_IT_OVR                                 ((uint16_t)0x201A)  
+#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
+                       ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_flags_definition 
+  * @{
+  */ 
+#define ADC_FLAG_AWD                               ((uint8_t)0x01)
+#define ADC_FLAG_EOC                               ((uint8_t)0x02)
+#define ADC_FLAG_JEOC                              ((uint8_t)0x04)
+#define ADC_FLAG_JSTRT                             ((uint8_t)0x08)
+#define ADC_FLAG_STRT                              ((uint8_t)0x10)
+#define ADC_FLAG_OVR                               ((uint8_t)0x20)   
+  
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00))   
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \
+                               ((FLAG) == ADC_FLAG_EOC) || \
+                               ((FLAG) == ADC_FLAG_JEOC) || \
+                               ((FLAG)== ADC_FLAG_JSTRT) || \
+                               ((FLAG) == ADC_FLAG_STRT) || \
+                               ((FLAG)== ADC_FLAG_OVR))     
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_thresholds 
+  * @{
+  */ 
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_injected_offset 
+  * @{
+  */ 
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_injected_length 
+  * @{
+  */ 
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_injected_rank 
+  * @{
+  */ 
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_regular_length 
+  * @{
+  */ 
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_regular_rank 
+  * @{
+  */ 
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_regular_discontinuous_mode_number 
+  * @{
+  */ 
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+/**
+  * @}
+  */ 
+
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/  
+
+/*  Function used to set the ADC configuration to the default reset state *****/  
+void ADC_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
+void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
+/* Analog Watchdog configuration functions ************************************/
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
+
+/* Temperature Sensor, Vrefint and VBAT management functions ******************/
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);
+void ADC_VBATCmd(FunctionalState NewState);
+
+/* Regular Channels Configuration functions ***********************************/
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+uint32_t ADC_GetMultiModeConversionValue(void);
+
+/* Regular Channels DMA Configuration functions *******************************/
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState);
+
+/* Injected channels Configuration functions **********************************/
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
+void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
+
+/* Interrupts and flags management functions **********************************/
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_ADC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+

底盘/底盘-old/底盘/Library/stm32f4xx_can.h

@@ -0,0 +1,649 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_can.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the CAN firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_CAN_H
+#define __STM32F4xx_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CAN
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(STM32F413_423xx)
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
+                                   ((PERIPH) == CAN2) || \
+                                   ((PERIPH) == CAN3))
+#else
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
+                                   ((PERIPH) == CAN2))
+#endif /* STM32F413_423xx */
+
+/** 
+  * @brief  CAN init structure definition
+  */
+typedef struct
+{
+  uint16_t CAN_Prescaler;   /*!< Specifies the length of a time quantum. 
+                                 It ranges from 1 to 1024. */
+  
+  uint8_t CAN_Mode;         /*!< Specifies the CAN operating mode.
+                                 This parameter can be a value of @ref CAN_operating_mode */
+
+  uint8_t CAN_SJW;          /*!< Specifies the maximum number of time quanta 
+                                 the CAN hardware is allowed to lengthen or 
+                                 shorten a bit to perform resynchronization.
+                                 This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+  uint8_t CAN_BS1;          /*!< Specifies the number of time quanta in Bit 
+                                 Segment 1. This parameter can be a value of 
+                                 @ref CAN_time_quantum_in_bit_segment_1 */
+
+  uint8_t CAN_BS2;          /*!< Specifies the number of time quanta in Bit Segment 2.
+                                 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+  
+  FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
+                                This parameter can be set either to ENABLE or DISABLE. */
+  
+  FunctionalState CAN_ABOM;  /*!< Enable or disable the automatic bus-off management.
+                                  This parameter can be set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_AWUM;  /*!< Enable or disable the automatic wake-up mode. 
+                                  This parameter can be set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_NART;  /*!< Enable or disable the non-automatic retransmission mode.
+                                  This parameter can be set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_RFLM;  /*!< Enable or disable the Receive FIFO Locked mode.
+                                  This parameter can be set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_TXFP;  /*!< Enable or disable the transmit FIFO priority.
+                                  This parameter can be set either to ENABLE or DISABLE. */
+} CAN_InitTypeDef;
+
+/** 
+  * @brief  CAN filter init structure definition
+  */
+typedef struct
+{
+  uint16_t CAN_FilterIdHigh;         /*!< Specifies the filter identification number (MSBs for a 32-bit
+                                              configuration, first one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterIdLow;          /*!< Specifies the filter identification number (LSBs for a 32-bit
+                                              configuration, second one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterMaskIdHigh;     /*!< Specifies the filter mask number or identification number,
+                                              according to the mode (MSBs for a 32-bit configuration,
+                                              first one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterMaskIdLow;      /*!< Specifies the filter mask number or identification number,
+                                              according to the mode (LSBs for a 32-bit configuration,
+                                              second one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+                                              This parameter can be a value of @ref CAN_filter_FIFO */
+  
+  uint8_t CAN_FilterNumber;          /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
+
+  uint8_t CAN_FilterMode;            /*!< Specifies the filter mode to be initialized.
+                                              This parameter can be a value of @ref CAN_filter_mode */
+
+  uint8_t CAN_FilterScale;           /*!< Specifies the filter scale.
+                                              This parameter can be a value of @ref CAN_filter_scale */
+
+  FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
+                                              This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitTypeDef;
+
+/** 
+  * @brief  CAN Tx message structure definition  
+  */
+typedef struct
+{
+  uint32_t StdId;  /*!< Specifies the standard identifier.
+                        This parameter can be a value between 0 to 0x7FF. */
+
+  uint32_t ExtId;  /*!< Specifies the extended identifier.
+                        This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
+                        will be transmitted. This parameter can be a value 
+                        of @ref CAN_identifier_type */
+
+  uint8_t RTR;     /*!< Specifies the type of frame for the message that will 
+                        be transmitted. This parameter can be a value of 
+                        @ref CAN_remote_transmission_request */
+
+  uint8_t DLC;     /*!< Specifies the length of the frame that will be 
+                        transmitted. This parameter can be a value between 
+                        0 to 8 */
+
+  uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 
+                        to 0xFF. */
+} CanTxMsg;
+
+/** 
+  * @brief  CAN Rx message structure definition  
+  */
+typedef struct
+{
+  uint32_t StdId;  /*!< Specifies the standard identifier.
+                        This parameter can be a value between 0 to 0x7FF. */
+
+  uint32_t ExtId;  /*!< Specifies the extended identifier.
+                        This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
+                        will be received. This parameter can be a value of 
+                        @ref CAN_identifier_type */
+
+  uint8_t RTR;     /*!< Specifies the type of frame for the received message.
+                        This parameter can be a value of 
+                        @ref CAN_remote_transmission_request */
+
+  uint8_t DLC;     /*!< Specifies the length of the frame that will be received.
+                        This parameter can be a value between 0 to 8 */
+
+  uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 
+                        0xFF. */
+
+  uint8_t FMI;     /*!< Specifies the index of the filter the message stored in 
+                        the mailbox passes through. This parameter can be a 
+                        value between 0 to 0xFF */
+} CanRxMsg;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Constants
+  * @{
+  */
+
+/** @defgroup CAN_InitStatus 
+  * @{
+  */
+
+#define CAN_InitStatus_Failed              ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_InitStatus_Success             ((uint8_t)0x01) /*!< CAN initialization OK */
+
+
+/* Legacy defines */
+#define CANINITFAILED    CAN_InitStatus_Failed
+#define CANINITOK        CAN_InitStatus_Success
+/**
+  * @}
+  */
+
+/** @defgroup CAN_operating_mode 
+  * @{
+  */
+
+#define CAN_Mode_Normal             ((uint8_t)0x00)  /*!< normal mode */
+#define CAN_Mode_LoopBack           ((uint8_t)0x01)  /*!< loopback mode */
+#define CAN_Mode_Silent             ((uint8_t)0x02)  /*!< silent mode */
+#define CAN_Mode_Silent_LoopBack    ((uint8_t)0x03)  /*!< loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
+                           ((MODE) == CAN_Mode_LoopBack)|| \
+                           ((MODE) == CAN_Mode_Silent) || \
+                           ((MODE) == CAN_Mode_Silent_LoopBack))
+/**
+  * @}
+  */
+
+
+ /**
+  * @defgroup CAN_operating_mode 
+  * @{
+  */  
+#define CAN_OperatingMode_Initialization  ((uint8_t)0x00) /*!< Initialization mode */
+#define CAN_OperatingMode_Normal          ((uint8_t)0x01) /*!< Normal mode */
+#define CAN_OperatingMode_Sleep           ((uint8_t)0x02) /*!< sleep mode */
+
+
+#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
+                                    ((MODE) == CAN_OperatingMode_Normal)|| \
+																		((MODE) == CAN_OperatingMode_Sleep))
+/**
+  * @}
+  */
+  
+/**
+  * @defgroup CAN_operating_mode_status
+  * @{
+  */  
+
+#define CAN_ModeStatus_Failed    ((uint8_t)0x00)                /*!< CAN entering the specific mode failed */
+#define CAN_ModeStatus_Success   ((uint8_t)!CAN_ModeStatus_Failed)   /*!< CAN entering the specific mode Succeed */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_synchronisation_jump_width 
+  * @{
+  */
+#define CAN_SJW_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_SJW_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_SJW_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_SJW_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
+                         ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1 
+  * @{
+  */
+#define CAN_BS1_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_BS1_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_BS1_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_BS1_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_BS1_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_BS1_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_BS1_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_BS1_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
+#define CAN_BS1_9tq                 ((uint8_t)0x08)  /*!< 9 time quantum */
+#define CAN_BS1_10tq                ((uint8_t)0x09)  /*!< 10 time quantum */
+#define CAN_BS1_11tq                ((uint8_t)0x0A)  /*!< 11 time quantum */
+#define CAN_BS1_12tq                ((uint8_t)0x0B)  /*!< 12 time quantum */
+#define CAN_BS1_13tq                ((uint8_t)0x0C)  /*!< 13 time quantum */
+#define CAN_BS1_14tq                ((uint8_t)0x0D)  /*!< 14 time quantum */
+#define CAN_BS1_15tq                ((uint8_t)0x0E)  /*!< 15 time quantum */
+#define CAN_BS1_16tq                ((uint8_t)0x0F)  /*!< 16 time quantum */
+
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2 
+  * @{
+  */
+#define CAN_BS2_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_BS2_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_BS2_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_BS2_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_BS2_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_BS2_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_BS2_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_BS2_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
+
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_clock_prescaler 
+  * @{
+  */
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_number 
+  * @{
+  */
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_mode 
+  * @{
+  */
+#define CAN_FilterMode_IdMask       ((uint8_t)0x00)  /*!< identifier/mask mode */
+#define CAN_FilterMode_IdList       ((uint8_t)0x01)  /*!< identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
+                                  ((MODE) == CAN_FilterMode_IdList))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_scale 
+  * @{
+  */
+#define CAN_FilterScale_16bit       ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FilterScale_32bit       ((uint8_t)0x01) /*!< One 32-bit filter */
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
+                                    ((SCALE) == CAN_FilterScale_32bit))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_FIFO
+  * @{
+  */
+#define CAN_Filter_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
+                                  ((FIFO) == CAN_FilterFIFO1))
+
+/* Legacy defines */
+#define CAN_FilterFIFO0  CAN_Filter_FIFO0
+#define CAN_FilterFIFO1  CAN_Filter_FIFO1
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Start_bank_filter_for_slave_CAN 
+  * @{
+  */
+#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Tx 
+  * @{
+  */
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_identifier_type 
+  * @{
+  */
+#define CAN_Id_Standard             ((uint32_t)0x00000000)  /*!< Standard Id */
+#define CAN_Id_Extended             ((uint32_t)0x00000004)  /*!< Extended Id */
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
+                               ((IDTYPE) == CAN_Id_Extended))
+
+/* Legacy defines */
+#define CAN_ID_STD      CAN_Id_Standard           
+#define CAN_ID_EXT      CAN_Id_Extended
+/**
+  * @}
+  */
+
+/** @defgroup CAN_remote_transmission_request 
+  * @{
+  */
+#define CAN_RTR_Data                ((uint32_t)0x00000000)  /*!< Data frame */
+#define CAN_RTR_Remote              ((uint32_t)0x00000002)  /*!< Remote frame */
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
+
+/* Legacy defines */
+#define CAN_RTR_DATA     CAN_RTR_Data         
+#define CAN_RTR_REMOTE   CAN_RTR_Remote
+/**
+  * @}
+  */
+
+/** @defgroup CAN_transmit_constants 
+  * @{
+  */
+#define CAN_TxStatus_Failed         ((uint8_t)0x00)/*!< CAN transmission failed */
+#define CAN_TxStatus_Ok             ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CAN_TxStatus_Pending        ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_TxStatus_NoMailBox      ((uint8_t)0x04) /*!< CAN cell did not provide 
+                                                         an empty mailbox */
+/* Legacy defines */	
+#define CANTXFAILED                  CAN_TxStatus_Failed
+#define CANTXOK                      CAN_TxStatus_Ok
+#define CANTXPENDING                 CAN_TxStatus_Pending
+#define CAN_NO_MB                    CAN_TxStatus_NoMailBox
+/**
+  * @}
+  */
+
+/** @defgroup CAN_receive_FIFO_number_constants 
+  * @{
+  */
+#define CAN_FIFO0                 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1                 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_sleep_constants 
+  * @{
+  */
+#define CAN_Sleep_Failed     ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
+#define CAN_Sleep_Ok         ((uint8_t)0x01) /*!< CAN entered the sleep mode */
+
+/* Legacy defines */	
+#define CANSLEEPFAILED   CAN_Sleep_Failed
+#define CANSLEEPOK       CAN_Sleep_Ok
+/**
+  * @}
+  */
+
+/** @defgroup CAN_wake_up_constants 
+  * @{
+  */
+#define CAN_WakeUp_Failed        ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
+#define CAN_WakeUp_Ok            ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
+
+/* Legacy defines */
+#define CANWAKEUPFAILED   CAN_WakeUp_Failed        
+#define CANWAKEUPOK       CAN_WakeUp_Ok        
+/**
+  * @}
+  */
+
+/**
+  * @defgroup CAN_Error_Code_constants
+  * @{
+  */                                                         
+#define CAN_ErrorCode_NoErr           ((uint8_t)0x00) /*!< No Error */ 
+#define	CAN_ErrorCode_StuffErr        ((uint8_t)0x10) /*!< Stuff Error */ 
+#define	CAN_ErrorCode_FormErr         ((uint8_t)0x20) /*!< Form Error */ 
+#define	CAN_ErrorCode_ACKErr          ((uint8_t)0x30) /*!< Acknowledgment Error */ 
+#define	CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ 
+#define	CAN_ErrorCode_BitDominantErr  ((uint8_t)0x50) /*!< Bit Dominant Error */ 
+#define	CAN_ErrorCode_CRCErr          ((uint8_t)0x60) /*!< CRC Error  */ 
+#define	CAN_ErrorCode_SoftwareSetErr  ((uint8_t)0x70) /*!< Software Set Error */ 
+/**
+  * @}
+  */
+
+/** @defgroup CAN_flags 
+  * @{
+  */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+   and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with 
+   CAN_GetFlagStatus() function.  */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0             ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
+#define CAN_FLAG_RQCP1             ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
+#define CAN_FLAG_RQCP2             ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FMP0              ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
+#define CAN_FLAG_FF0               ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag            */
+#define CAN_FLAG_FOV0              ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag         */
+#define CAN_FLAG_FMP1              ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
+#define CAN_FLAG_FF1               ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag            */
+#define CAN_FLAG_FOV1              ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag         */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU               ((uint32_t)0x31000008) /*!< Wake up Flag */
+#define CAN_FLAG_SLAK              ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. 
+         In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG               ((uint32_t)0x10F00001) /*!< Error Warning Flag   */
+#define CAN_FLAG_EPV               ((uint32_t)0x10F00002) /*!< Error Passive Flag   */
+#define CAN_FLAG_BOF               ((uint32_t)0x10F00004) /*!< Bus-Off Flag         */
+#define CAN_FLAG_LEC               ((uint32_t)0x30F00070) /*!< Last error code Flag */
+
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC)  || ((FLAG) == CAN_FLAG_BOF)   || \
+                               ((FLAG) == CAN_FLAG_EPV)  || ((FLAG) == CAN_FLAG_EWG)   || \
+                               ((FLAG) == CAN_FLAG_WKU)  || ((FLAG) == CAN_FLAG_FOV0)  || \
+                               ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FMP0)  || \
+                               ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1)   || \
+                               ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
+                               ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
+                               ((FLAG) == CAN_FLAG_SLAK ))
+
+#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
+                                ((FLAG) == CAN_FLAG_RQCP1)  || ((FLAG) == CAN_FLAG_RQCP0) || \
+                                ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FOV0) ||\
+                                ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
+                                ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
+/**
+  * @}
+  */
+
+  
+/** @defgroup CAN_interrupts 
+  * @{
+  */ 
+#define CAN_IT_TME                  ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0                 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
+#define CAN_IT_FF0                  ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
+#define CAN_IT_FOV0                 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
+#define CAN_IT_FMP1                 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
+#define CAN_IT_FF1                  ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
+#define CAN_IT_FOV1                 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU                  ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
+#define CAN_IT_SLK                  ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
+
+/* Error Interrupts */
+#define CAN_IT_EWG                  ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
+#define CAN_IT_EPV                  ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
+#define CAN_IT_BOF                  ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
+#define CAN_IT_LEC                  ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
+#define CAN_IT_ERR                  ((uint32_t)0x00008000) /*!< Error Interrupt*/
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_IT_RQCP0   CAN_IT_TME
+#define CAN_IT_RQCP1   CAN_IT_TME
+#define CAN_IT_RQCP2   CAN_IT_TME
+
+
+#define IS_CAN_IT(IT)        (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0)  ||\
+                             ((IT) == CAN_IT_FF0)  || ((IT) == CAN_IT_FOV0)  ||\
+                             ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1)   ||\
+                             ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG)   ||\
+                             ((IT) == CAN_IT_EPV)  || ((IT) == CAN_IT_BOF)   ||\
+                             ((IT) == CAN_IT_LEC)  || ((IT) == CAN_IT_ERR)   ||\
+                             ((IT) == CAN_IT_WKU)  || ((IT) == CAN_IT_SLK))
+
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0)    ||\
+                             ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1)    ||\
+                             ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG)    ||\
+                             ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)    ||\
+                             ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR)    ||\
+                             ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/  
+
+/*  Function used to set the CAN configuration to the default reset state *****/ 
+void CAN_DeInit(CAN_TypeDef* CANx);
+
+/* Initialization and Configuration functions *********************************/ 
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
+#if defined(STM32F413_423xx)
+void CAN_FilterInit(CAN_TypeDef* CANx, CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+#else
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+#endif /* STM32F413_423xx */
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
+#if defined(STM32F413_423xx)
+void CAN_SlaveStartBank(CAN_TypeDef* CANx, uint8_t CAN_BankNumber);
+#else
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
+#endif /* STM32F413_423xx */
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
+
+/* CAN Frames Transmission functions ******************************************/
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
+
+/* CAN Frames Reception functions *********************************************/
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
+
+/* Operation modes functions **************************************************/
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
+uint8_t CAN_Sleep(CAN_TypeDef* CANx);
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
+
+/* CAN Bus Error management functions *****************************************/
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
+
+/* Interrupts and flags management functions **********************************/
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_CAN_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

底盘/底盘-old/底盘/Library/stm32f4xx_cec.c

@@ -0,0 +1,600 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_cec.c
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Consumer Electronics Control (CEC) peripheral
+  *          applicable only on STM32F446xx devices:
+  *            + Initialization and Configuration
+  *            + Data transfers functions
+  *            + Interrupts and flags management
+  *               
+  *  @verbatim
+  ==============================================================================
+                            ##### CEC features #####
+  ==============================================================================
+      [..] This device provides some features:
+           (#) Supports HDMI-CEC specification 1.4.
+           (#) Supports two source clocks(HSI/244 or LSE).
+           (#) Works in stop mode(without APB clock, but with CEC clock 32KHz).
+               It can genarate an interrupt in the CEC clock domain that the CPU 
+               wakes up from the low power mode.
+           (#) Configurable Signal Free Time before of transmission start. The 
+               number of nominal data bit periods waited before transmission can be
+               ruled by Hardware or Software.
+           (#) Configurable Peripheral Address (multi-addressing configuration).
+           (#) Supports listen mode.The CEC Messages addressed to different destination
+               can be received without interfering with CEC bus when Listen mode option is enabled.
+           (#) Configurable Rx-Tolerance(Standard and Extended tolerance margin).
+           (#) Error detection with configurable error bit generation.
+           (#) Arbitration lost error in the case of two CEC devices starting at the same time.
+
+                            ##### How to use this driver ##### 
+  ==============================================================================
+      [..] This driver provides functions to configure and program the CEC device,
+       follow steps below:
+           (#) The source clock can be configured using:
+               (++) RCC_CECCLKConfig(RCC_CECCLK_HSI_Div244) for HSI(Default) 
+               (++) RCC_CECCLKConfig(RCC_CECCLK_LSE) for LSE.
+           (#) Enable CEC peripheral clock using RCC_APBPeriphClockCmd(RCC_APBPeriph_CEC, ENABLE).
+           (#) Peripherals alternate function.
+               (++) Connect the pin to the desired peripherals' Alternate Function (AF) using 
+               GPIO_PinAFConfig() function.
+               (++) Configure the desired pin in alternate function by:
+               GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
+               (++) Select the type open-drain and output speed via GPIO_OType 
+               and GPIO_Speed members.
+               (++) Call GPIO_Init() function.
+           (#) Configure the Signal Free Time, Rx Tolerance, Stop reception generation 
+               and Bit error generation using the CEC_Init() function.
+               The function CEC_Init() must be called when the CEC peripheral is disabled.
+           (#) Configure the CEC own address by calling the fuction CEC_OwnAddressConfig().
+           (#) Optionally, you can configure the Listen mode using the function CEC_ListenModeCmd().
+           (#) Enable the NVIC and the corresponding interrupt using the function 
+               CEC_ITConfig() if you need to use interrupt mode.
+               CEC_ITConfig() must be called before enabling the CEC peripheral.
+           (#) Enable the CEC using the CEC_Cmd() function.
+           (#) Charge the first data byte in the TXDR register using CEC_SendDataByte().
+           (#) Enable the transmission of the Byte of a CEC message using CEC_StartOfMessage() 
+           (#) Transmit single data through the CEC peripheral using CEC_SendDataByte() 
+               and Receive the last transmitted byte using CEC_ReceiveDataByte().
+           (#) Enable the CEC_EndOfMessage() in order to indicate the last byte of the message.
+      [..]
+           (@) If the listen mode is enabled, Stop reception generation and Bit error generation 
+               must be in reset state.
+           (@) If the CEC message consists of only 1 byte, the function CEC_EndOfMessage()
+               must be called before CEC_StartOfMessage().
+  
+   @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_cec.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CEC 
+  * @brief CEC driver modules
+  * @{
+  */
+#if defined(STM32F446xx)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define BROADCAST_ADDRESS      ((uint32_t)0x0000F)
+#define CFGR_CLEAR_MASK        ((uint32_t)0x7000FE00)   /* CFGR register Mask */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CEC_Private_Functions 
+  * @{
+  */
+
+/** @defgroup CEC_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions
+ *
+@verbatim  
+ ===============================================================================
+                            ##### Initialization and Configuration functions #####
+ ===============================================================================
+      [..] This section provides functions allowing to initialize:
+            (+) CEC own addresses
+            (+) CEC Signal Free Time
+            (+) CEC Rx Tolerance
+            (+) CEC Stop Reception
+            (+) CEC Bit Rising Error
+            (+) CEC Long Bit Period Error
+      [..] This section provides also a function to configure the CEC peripheral in Listen Mode.
+           Messages addressed to different destination can be received when Listen mode is 
+           enabled without interfering with CEC bus.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the CEC peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void CEC_DeInit(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
+}
+
+/**
+  * @brief  Initializes the CEC peripheral according to the specified parameters
+  *         in the CEC_InitStruct.
+  * @note   The CEC parameters must be configured before enabling the CEC peripheral.
+  * @param  CEC_InitStruct: pointer to an CEC_InitTypeDef structure that contains
+  *         the configuration information for the specified CEC peripheral.
+  * @retval None
+  */
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_CEC_SIGNAL_FREE_TIME(CEC_InitStruct->CEC_SignalFreeTime));
+  assert_param(IS_CEC_RX_TOLERANCE(CEC_InitStruct->CEC_RxTolerance));
+  assert_param(IS_CEC_STOP_RECEPTION(CEC_InitStruct->CEC_StopReception));
+  assert_param(IS_CEC_BIT_RISING_ERROR(CEC_InitStruct->CEC_BitRisingError));
+  assert_param(IS_CEC_LONG_BIT_PERIOD_ERROR(CEC_InitStruct->CEC_LongBitPeriodError));
+  assert_param(IS_CEC_BDR_NO_GEN_ERROR(CEC_InitStruct->CEC_BRDNoGen));
+  assert_param(IS_CEC_SFT_OPTION(CEC_InitStruct->CEC_SFTOption));
+
+  /* Get the CEC CFGR value */
+  tmpreg = CEC->CFGR;
+
+  /* Clear CFGR bits */
+  tmpreg &= CFGR_CLEAR_MASK;
+
+  /* Configure the CEC peripheral */
+  tmpreg |= (CEC_InitStruct->CEC_SignalFreeTime | CEC_InitStruct->CEC_RxTolerance |
+             CEC_InitStruct->CEC_StopReception  | CEC_InitStruct->CEC_BitRisingError |
+             CEC_InitStruct->CEC_LongBitPeriodError| CEC_InitStruct->CEC_BRDNoGen |
+             CEC_InitStruct->CEC_SFTOption);
+
+  /* Write to CEC CFGR  register */
+  CEC->CFGR = tmpreg;
+}
+
+/**
+  * @brief  Fills each CEC_InitStruct member with its default value.
+  * @param  CEC_InitStruct: pointer to a CEC_InitTypeDef structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct)
+{
+  CEC_InitStruct->CEC_SignalFreeTime = CEC_SignalFreeTime_Standard;
+  CEC_InitStruct->CEC_RxTolerance = CEC_RxTolerance_Standard;
+  CEC_InitStruct->CEC_StopReception = CEC_StopReception_Off;
+  CEC_InitStruct->CEC_BitRisingError = CEC_BitRisingError_Off;
+  CEC_InitStruct->CEC_LongBitPeriodError = CEC_LongBitPeriodError_Off;
+  CEC_InitStruct->CEC_BRDNoGen = CEC_BRDNoGen_Off;
+  CEC_InitStruct->CEC_SFTOption = CEC_SFTOption_Off;
+}
+
+/**
+  * @brief  Enables or disables the CEC peripheral.
+  * @param  NewState: new state of the CEC peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CEC_Cmd(FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the CEC peripheral */
+    CEC->CR |= CEC_CR_CECEN;
+  }
+  else
+  {
+    /* Disable the CEC peripheral */
+    CEC->CR &= ~CEC_CR_CECEN;
+  }
+}
+
+/**
+  * @brief  Enables or disables the CEC Listen Mode.
+  * @param  NewState: new state of the Listen Mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CEC_ListenModeCmd(FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Listen Mode */
+    CEC->CFGR |= CEC_CFGR_LSTN;
+  }
+  else
+  {
+    /* Disable the Listen Mode */
+    CEC->CFGR &= ~CEC_CFGR_LSTN;
+  }
+}
+
+/**
+  * @brief  Defines the Own Address of the CEC device.
+  * @param  CEC_OwnAddress: The CEC own address.
+  * @retval None
+  */
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
+{
+  uint32_t tmp =0x00;
+  /* Check the parameters */
+  assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
+  tmp = 1 <<(CEC_OwnAddress + 16);
+  /* Set the CEC own address */
+  CEC->CFGR |= tmp;
+}
+
+/**
+  * @brief  Clears the Own Address of the CEC device.
+  * @param  CEC_OwnAddress: The CEC own address.
+  * @retval None
+  */
+void CEC_OwnAddressClear(void)
+{
+  /* Set the CEC own address */
+  CEC->CFGR = 0x0;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Group2 Data transfers functions
+ *  @brief    Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+                            ##### Data transfers functions #####
+ ===============================================================================
+    [..] This section provides functions allowing the CEC data transfers.The read 
+         access of the CEC_RXDR register can be done using the CEC_ReceiveData()function 
+         and returns the Rx buffered value. Whereas a write access to the CEC_TXDR can be 
+         done using CEC_SendData() function.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits single data through the CEC peripheral.
+  * @param  Data: the data to transmit.
+  * @retval None
+  */
+void CEC_SendData(uint8_t Data)
+{
+  /* Transmit Data */
+  CEC->TXDR = Data;
+}
+
+/**
+  * @brief  Returns the most recent received data by the CEC peripheral.
+  * @param  None
+  * @retval The received data.
+  */
+uint8_t CEC_ReceiveData(void)
+{
+  /* Receive Data */
+  return (uint8_t)(CEC->RXDR);
+}
+
+/**
+  * @brief  Starts a new message.
+  * @param  None
+  * @retval None
+  */
+void CEC_StartOfMessage(void)
+{
+  /* Starts of new message */
+  CEC->CR |= CEC_CR_TXSOM; 
+}
+
+/**
+  * @brief  Transmits message with an EOM bit.
+  * @param  None
+  * @retval None
+  */
+void CEC_EndOfMessage(void)
+{
+  /* The data byte will be transmitted with an EOM bit */
+  CEC->CR |= CEC_CR_TXEOM;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Group3 Interrupts and flags management functions
+ *  @brief    Interrupts and flags management functions
+*
+@verbatim
+ ===============================================================================
+                            ##### Interrupts and flags management functions ##### 
+ ===============================================================================
+    [..] This section provides functions allowing to configure the CEC Interrupts
+         sources and check or clear the flags or pending bits status.
+    [..] The user should identify which mode will be used in his application to manage
+         the communication: Polling mode or Interrupt mode.
+  
+    [..] In polling mode, the CEC can be managed by the following flags:
+            (+) CEC_FLAG_TXACKE : to indicate a missing acknowledge in transmission mode.
+            (+) CEC_FLAG_TXERR  : to indicate an error occurs during transmission mode.
+                                  The initiator detects low impedance in the CEC line.
+            (+) CEC_FLAG_TXUDR  : to indicate if an underrun error occurs in transmission mode.
+                                  The transmission is enabled while the software has not yet 
+                                  loaded any value into the TXDR register.
+            (+) CEC_FLAG_TXEND  : to indicate the end of successful transmission.
+            (+) CEC_FLAG_TXBR   : to indicate the next transmission data has to be written to TXDR.
+            (+) CEC_FLAG_ARBLST : to indicate arbitration lost in the case of two CEC devices
+                                  starting at the same time.
+            (+) CEC_FLAG_RXACKE : to indicate a missing acknowledge in receive mode.
+            (+) CEC_FLAG_LBPE   : to indicate a long bit period error generated during receive mode.
+            (+) CEC_FLAG_SBPE   : to indicate a short bit period error generated during receive mode.
+            (+) CEC_FLAG_BRE    : to indicate a bit rising error generated during receive mode.
+            (+) CEC_FLAG_RXOVR  : to indicate if an overrun error occur while receiving a CEC message.
+                                  A byte is not yet received while a new byte is stored in the RXDR register.
+            (+) CEC_FLAG_RXEND  : to indicate the end Of reception
+            (+) CEC_FLAG_RXBR   : to indicate a new byte has been received from the CEC line and 
+                                  stored into the RXDR buffer.
+    [..]
+           (@)In this Mode, it is advised to use the following functions:
+              FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG);
+              void CEC_ClearFlag(uint16_t CEC_FLAG);
+
+    [..] In Interrupt mode, the CEC can be managed by the following interrupt sources:
+           (+) CEC_IT_TXACKE : to indicate a TX Missing acknowledge 
+           (+) CEC_IT_TXACKE : to indicate a missing acknowledge in transmission mode.
+           (+) CEC_IT_TXERR  : to indicate an error occurs during transmission mode.
+                               The initiator detects low impedance in the CEC line.
+           (+) CEC_IT_TXUDR  : to indicate if an underrun error occurs in transmission mode.
+                               The transmission is enabled while the software has not yet 
+                               loaded any value into the TXDR register.
+           (+) CEC_IT_TXEND  : to indicate the end of successful transmission.
+           (+) CEC_IT_TXBR   : to indicate the next transmission data has to be written to TXDR register.
+           (+) CEC_IT_ARBLST : to indicate arbitration lost in the case of two CEC devices
+                                starting at the same time.
+           (+) CEC_IT_RXACKE : to indicate a missing acknowledge in receive mode.
+           (+) CEC_IT_LBPE   : to indicate a long bit period error generated during receive mode.
+           (+) CEC_IT_SBPE   : to indicate a short bit period error generated during receive mode.
+           (+) CEC_IT_BRE    : to indicate a bit rising error generated during receive mode.
+           (+) CEC_IT_RXOVR  : to indicate if an overrun error occur while receiving a CEC message.
+                               A byte is not yet received while a new byte is stored in the RXDR register.
+           (+) CEC_IT_RXEND  : to indicate the end Of reception
+           (+) CEC_IT_RXBR   : to indicate a new byte has been received from the CEC line and 
+                                stored into the RXDR buffer.
+    [..]
+           (@)In this Mode it is advised to use the following functions:
+              void CEC_ITConfig( uint16_t CEC_IT, FunctionalState NewState);
+              ITStatus CEC_GetITStatus(uint16_t CEC_IT);
+              void CEC_ClearITPendingBit(uint16_t CEC_IT);
+              
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the selected CEC interrupts.
+  * @param  CEC_IT: specifies the CEC interrupt source to be enabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
+  *            @arg CEC_IT_TXERR: Tx Error.
+  *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun.
+  *            @arg CEC_IT_TXEND: End of Transmission (successful transmission of the last byte).
+  *            @arg CEC_IT_TXBR: Tx-Byte Request.
+  *            @arg CEC_IT_ARBLST: Arbitration Lost
+  *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge
+  *            @arg CEC_IT_LBPE: Rx Long period Error
+  *            @arg CEC_IT_SBPE: Rx Short period Error
+  *            @arg CEC_IT_BRE: Rx Bit Rising Error
+  *            @arg CEC_IT_RXOVR: Rx Overrun.
+  *            @arg CEC_IT_RXEND: End Of Reception
+  *            @arg CEC_IT_RXBR: Rx-Byte Received
+  * @param  NewState: new state of the selected CEC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_CEC_IT(CEC_IT));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected CEC interrupt */
+    CEC->IER |= CEC_IT;
+  }
+  else
+  {
+    CEC_IT =~CEC_IT;
+    /* Disable the selected CEC interrupt */
+    CEC->IER &= CEC_IT;
+  }
+}
+
+/**
+  * @brief  Gets the CEC flag status.
+  * @param  CEC_FLAG: specifies the CEC flag to check.
+  *     This parameter can be one of the following values:
+  *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
+  *            @arg CEC_FLAG_TXERR: Tx Error.
+  *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
+  *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
+  *            @arg CEC_FLAG_TXBR: Tx-Byte Request.
+  *            @arg CEC_FLAG_ARBLST: Arbitration Lost
+  *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge 
+  *            @arg CEC_FLAG_LBPE: Rx Long period Error
+  *            @arg CEC_FLAG_SBPE: Rx Short period Error
+  *            @arg CEC_FLAG_BRE: Rx Bit Rissing Error
+  *            @arg CEC_FLAG_RXOVR: Rx Overrun.
+  *            @arg CEC_FLAG_RXEND: End Of Reception.
+  *            @arg CEC_FLAG_RXBR: Rx-Byte Received.
+  * @retval The new state of CEC_FLAG (SET or RESET)
+  */
+FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG) 
+{
+  FlagStatus bitstatus = RESET;
+  
+  assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
+  
+  /* Check the status of the specified CEC flag */
+  if ((CEC->ISR & CEC_FLAG) != (uint16_t)RESET)
+  {
+    /* CEC flag is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* CEC flag is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the CEC flag status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the CEC's pending flags.
+  * @param  CEC_FLAG: specifies the flag to clear. 
+  *          This parameter can be any combination of the following values:
+  *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
+  *            @arg CEC_FLAG_TXERR: Tx Error
+  *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun
+  *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
+  *            @arg CEC_FLAG_TXBR: Tx-Byte Request
+  *            @arg CEC_FLAG_ARBLST: Arbitration Lost
+  *            @arg CEC_FLAG_RXACKE: Rx Missing Acknowledge 
+  *            @arg CEC_FLAG_LBPE: Rx Long period Error
+  *            @arg CEC_FLAG_SBPE: Rx Short period Error
+  *            @arg CEC_FLAG_BRE: Rx Bit Rising Error
+  *            @arg CEC_FLAG_RXOVR: Rx Overrun
+  *            @arg CEC_FLAG_RXEND: End Of Reception
+  *            @arg CEC_FLAG_RXBR: Rx-Byte Received
+  * @retval None
+  */
+void CEC_ClearFlag(uint32_t CEC_FLAG)
+{
+  assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
+
+  /* Clear the selected CEC flag */
+  CEC->ISR = CEC_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified CEC interrupt has occurred or not.
+  * @param  CEC_IT: specifies the CEC interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
+  *            @arg CEC_IT_TXERR: Tx Error.
+  *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun.
+  *            @arg CEC_IT_TXEND: End of transmission (successful transmission of the last byte).
+  *            @arg CEC_IT_TXBR: Tx-Byte Request.
+  *            @arg CEC_IT_ARBLST: Arbitration Lost.
+  *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge.
+  *            @arg CEC_IT_LBPE: Rx Long period Error.
+  *            @arg CEC_IT_SBPE: Rx Short period Error.
+  *            @arg CEC_IT_BRE: Rx Bit Rising Error.
+  *            @arg CEC_IT_RXOVR: Rx Overrun.
+  *            @arg CEC_IT_RXEND: End Of Reception.
+  *            @arg CEC_IT_RXBR: Rx-Byte Received 
+  * @retval The new state of CEC_IT (SET or RESET).
+  */
+ITStatus CEC_GetITStatus(uint16_t CEC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_CEC_GET_IT(CEC_IT));
+
+  /* Get the CEC IT enable bit status */
+  enablestatus = (CEC->IER & CEC_IT);
+
+  /* Check the status of the specified CEC interrupt */
+  if (((CEC->ISR & CEC_IT) != (uint32_t)RESET) && enablestatus)
+  {
+    /* CEC interrupt is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* CEC interrupt is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the CEC interrupt status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the CEC's interrupt pending bits.
+  * @param  CEC_IT: specifies the CEC interrupt pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
+  *            @arg CEC_IT_TXERR: Tx Error
+  *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun
+  *            @arg CEC_IT_TXEND: End of Transmission
+  *            @arg CEC_IT_TXBR: Tx-Byte Request
+  *            @arg CEC_IT_ARBLST: Arbitration Lost
+  *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge
+  *            @arg CEC_IT_LBPE: Rx Long period Error
+  *            @arg CEC_IT_SBPE: Rx Short period Error
+  *            @arg CEC_IT_BRE: Rx Bit Rising Error
+  *            @arg CEC_IT_RXOVR: Rx Overrun
+  *            @arg CEC_IT_RXEND: End Of Reception
+  *            @arg CEC_IT_RXBR: Rx-Byte Received
+  * @retval None
+  */
+void CEC_ClearITPendingBit(uint16_t CEC_IT)
+{
+  assert_param(IS_CEC_IT(CEC_IT));
+
+  /* Clear the selected CEC interrupt pending bits */
+  CEC->ISR = CEC_IT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* STM32F446xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

底盘/底盘-old/底盘/Library/stm32f4xx_cec.h

@@ -0,0 +1,293 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_cec.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the CEC firmware 
+  *          library, applicable only for STM32F466xx devices.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4XX_CEC_H
+#define __STM32F4XX_CEC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CEC
+  * @{
+  */
+#if defined(STM32F446xx)
+/* Exported types ------------------------------------------------------------*/
+  
+/** 
+  * @brief CEC Init structure definition 
+  */
+typedef struct
+{
+  uint32_t CEC_SignalFreeTime;     /*!< Specifies the CEC Signal Free Time configuration.
+                                   This parameter can be a value of @ref CEC_Signal_Free_Time */
+  uint32_t CEC_RxTolerance;        /*!< Specifies the CEC Reception Tolerance.
+                                   This parameter can be a value of @ref CEC_RxTolerance */
+  uint32_t CEC_StopReception;      /*!< Specifies the CEC Stop Reception.
+                                   This parameter can be a value of @ref CEC_Stop_Reception */
+  uint32_t CEC_BitRisingError;     /*!< Specifies the CEC Bit Rising Error generation.
+                                   This parameter can be a value of @ref CEC_Bit_Rising_Error_Generation */
+  uint32_t CEC_LongBitPeriodError; /*!< Specifies the CEC Long Bit Error generation.
+                                   This parameter can be a value of @ref CEC_Long_Bit_Error_Generation */
+  uint32_t CEC_BRDNoGen;           /*!< Specifies the CEC Broadcast Error generation.
+                                   This parameter can be a value of @ref CEC_BDR_No_Gen */
+  uint32_t CEC_SFTOption;          /*!< Specifies the CEC Signal Free Time option.
+                                   This parameter can be a value of @ref CEC_SFT_Option */
+
+}CEC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CEC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup CEC_Signal_Free_Time
+  * @{
+  */
+#define CEC_SignalFreeTime_Standard     ((uint32_t)0x00000000) /*!< CEC Signal Free Time Standard         */
+#define CEC_SignalFreeTime_1T           ((uint32_t)0x00000001) /*!< CEC  1.5 nominal data bit periods     */
+#define CEC_SignalFreeTime_2T           ((uint32_t)0x00000002) /*!< CEC  2.5 nominal data bit periods     */
+#define CEC_SignalFreeTime_3T           ((uint32_t)0x00000003) /*!< CEC  3.5 nominal data bit periods     */
+#define CEC_SignalFreeTime_4T           ((uint32_t)0x00000004) /*!< CEC  4.5 nominal data bit periods     */
+#define CEC_SignalFreeTime_5T           ((uint32_t)0x00000005) /*!< CEC  5.5 nominal data bit periods     */
+#define CEC_SignalFreeTime_6T           ((uint32_t)0x00000006) /*!< CEC  6.5 nominal data bit periods     */
+#define CEC_SignalFreeTime_7T           ((uint32_t)0x00000007) /*!< CEC  7.5 nominal data bit periods     */
+
+#define IS_CEC_SIGNAL_FREE_TIME(TIME) (((TIME) == CEC_SignalFreeTime_Standard) || \
+                                       ((TIME) == CEC_SignalFreeTime_1T)|| \
+                                       ((TIME) == CEC_SignalFreeTime_2T)|| \
+                                       ((TIME) == CEC_SignalFreeTime_3T)|| \
+                                       ((TIME) == CEC_SignalFreeTime_4T)|| \
+                                       ((TIME) == CEC_SignalFreeTime_5T)|| \
+                                       ((TIME) == CEC_SignalFreeTime_6T)|| \
+                                       ((TIME) == CEC_SignalFreeTime_7T))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_RxTolerance
+  * @{
+  */
+#define CEC_RxTolerance_Standard        ((uint32_t)0x00000000) /*!< Standard Tolerance Margin            */
+#define CEC_RxTolerance_Extended        CEC_CFGR_RXTOL         /*!< Extended Tolerance Margin            */
+
+#define IS_CEC_RX_TOLERANCE(TOLERANCE) (((TOLERANCE) == CEC_RxTolerance_Standard) || \
+                                        ((TOLERANCE) == CEC_RxTolerance_Extended))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Stop_Reception
+  * @{
+  */
+#define CEC_StopReception_Off           ((uint32_t)0x00000000) /*!< No RX Stop on bit Rising Error (BRE) */
+#define CEC_StopReception_On            CEC_CFGR_BRESTP        /*!< RX Stop on bit Rising Error (BRE)    */
+
+#define IS_CEC_STOP_RECEPTION(RECEPTION) (((RECEPTION) == CEC_StopReception_On) || \
+                                          ((RECEPTION) == CEC_StopReception_Off))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Bit_Rising_Error_Generation
+  * @{
+  */
+#define CEC_BitRisingError_Off          ((uint32_t)0x00000000) /*!< Bit Rising Error generation turned Off */
+#define CEC_BitRisingError_On           CEC_CFGR_BREGEN        /*!< Bit Rising Error generation turned On  */
+
+#define IS_CEC_BIT_RISING_ERROR(ERROR) (((ERROR) == CEC_BitRisingError_Off) || \
+                                        ((ERROR) == CEC_BitRisingError_On))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Long_Bit_Error_Generation
+  * @{
+  */
+#define CEC_LongBitPeriodError_Off      ((uint32_t)0x00000000)  /*!< Long Bit Period Error generation turned Off */
+#define CEC_LongBitPeriodError_On       CEC_CFGR_LREGEN         /*!< Long Bit Period Error generation turned On  */
+
+#define IS_CEC_LONG_BIT_PERIOD_ERROR(ERROR) (((ERROR) == CEC_LongBitPeriodError_Off) || \
+                                             ((ERROR) == CEC_LongBitPeriodError_On))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_BDR_No_Gen
+  * @{
+  */
+
+#define CEC_BRDNoGen_Off      ((uint32_t)0x00000000)  /*!< Broadcast Bit Rising Error generation turned Off */
+#define CEC_BRDNoGen_On       CEC_CFGR_BRDNOGEN       /*!< Broadcast Bit Rising Error generation turned On  */
+
+#define IS_CEC_BDR_NO_GEN_ERROR(ERROR) (((ERROR) == CEC_BRDNoGen_Off) || \
+                                        ((ERROR) == CEC_BRDNoGen_On))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_SFT_Option
+  * @{
+  */
+#define CEC_SFTOption_Off              ((uint32_t)0x00000000)  /*!< SFT option turned Off                   */
+#define CEC_SFTOption_On               CEC_CFGR_SFTOPT         /*!< SFT option turned On                    */
+
+#define IS_CEC_SFT_OPTION(OPTION) (((OPTION) == CEC_SFTOption_Off) || \
+                                  ((OPTION) == CEC_SFTOption_On))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Own_Address
+  * @{
+  */
+#define IS_CEC_ADDRESS(ADDRESS)         ((ADDRESS) < 0x10)
+
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Interrupt_Configuration_definition
+  * @{
+  */
+#define CEC_IT_TXACKE                   CEC_IER_TXACKEIE
+#define CEC_IT_TXERR                    CEC_IER_TXERRIE
+#define CEC_IT_TXUDR                    CEC_IER_TXUDRIE
+#define CEC_IT_TXEND                    CEC_IER_TXENDIE
+#define CEC_IT_TXBR                     CEC_IER_TXBRIE
+#define CEC_IT_ARBLST                   CEC_IER_ARBLSTIE
+#define CEC_IT_RXACKE                   CEC_IER_RXACKEIE
+#define CEC_IT_LBPE                     CEC_IER_LBPEIE
+#define CEC_IT_SBPE                     CEC_IER_SBPEIE
+#define CEC_IT_BRE                      CEC_IER_BREIEIE
+#define CEC_IT_RXOVR                    CEC_IER_RXOVRIE
+#define CEC_IT_RXEND                    CEC_IER_RXENDIE
+#define CEC_IT_RXBR                     CEC_IER_RXBRIE
+
+#define IS_CEC_IT(IT) ((((IT) & (uint32_t)0xFFFFE000) == 0x00) && ((IT) != 0x00))
+
+#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TXACKE) || \
+                           ((IT) == CEC_IT_TXERR)|| \
+                           ((IT) == CEC_IT_TXUDR)|| \
+                           ((IT) == CEC_IT_TXEND)|| \
+                           ((IT) == CEC_IT_TXBR)|| \
+                           ((IT) == CEC_IT_ARBLST)|| \
+                           ((IT) == CEC_IT_RXACKE)|| \
+                           ((IT) == CEC_IT_LBPE)|| \
+                           ((IT) == CEC_IT_SBPE)|| \
+                           ((IT) == CEC_IT_BRE)|| \
+                           ((IT) == CEC_IT_RXOVR)|| \
+                           ((IT) == CEC_IT_RXEND)|| \
+                           ((IT) == CEC_IT_RXBR))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_ISR_register_flags_definition
+  * @{
+  */
+#define CEC_FLAG_TXACKE                 CEC_ISR_TXACKE
+#define CEC_FLAG_TXERR                  CEC_ISR_TXERR
+#define CEC_FLAG_TXUDR                  CEC_ISR_TXUDR
+#define CEC_FLAG_TXEND                  CEC_ISR_TXEND
+#define CEC_FLAG_TXBR                   CEC_ISR_TXBR
+#define CEC_FLAG_ARBLST                 CEC_ISR_ARBLST
+#define CEC_FLAG_RXACKE                 CEC_ISR_RXACKE
+#define CEC_FLAG_LBPE                   CEC_ISR_LBPE
+#define CEC_FLAG_SBPE                   CEC_ISR_SBPE
+#define CEC_FLAG_BRE                    CEC_ISR_BRE
+#define CEC_FLAG_RXOVR                  CEC_ISR_RXOVR
+#define CEC_FLAG_RXEND                  CEC_ISR_RXEND
+#define CEC_FLAG_RXBR                   CEC_ISR_RXBR
+
+#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE000) == 0x00) && ((FLAG) != 0x00))
+
+#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_TXACKE) || \
+                               ((FLAG) == CEC_FLAG_TXERR)|| \
+                               ((FLAG) == CEC_FLAG_TXUDR)|| \
+                               ((FLAG) == CEC_FLAG_TXEND)|| \
+                               ((FLAG) == CEC_FLAG_TXBR)|| \
+                               ((FLAG) == CEC_FLAG_ARBLST)|| \
+                               ((FLAG) == CEC_FLAG_RXACKE)|| \
+                               ((FLAG) == CEC_FLAG_LBPE)|| \
+                               ((FLAG) == CEC_FLAG_SBPE)|| \
+                               ((FLAG) == CEC_FLAG_BRE)|| \
+                               ((FLAG) == CEC_FLAG_RXOVR)|| \
+                               ((FLAG) == CEC_FLAG_RXEND)|| \
+                               ((FLAG) == CEC_FLAG_RXBR))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the CEC configuration to the default reset state *****/
+void CEC_DeInit(void);
+
+/* CEC_Initialization and Configuration functions *****************************/
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
+void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct);
+void CEC_Cmd(FunctionalState NewState);
+void CEC_ListenModeCmd(FunctionalState NewState);
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
+void CEC_OwnAddressClear(void);
+
+/* CEC_Data transfers functions ***********************************************/
+void CEC_SendData(uint8_t Data);
+uint8_t CEC_ReceiveData(void);
+void CEC_StartOfMessage(void);
+void CEC_EndOfMessage(void);
+
+/* CEC_Interrupts and flags management functions ******************************/
+void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState);
+FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG);
+void CEC_ClearFlag(uint32_t CEC_FLAG);
+ITStatus CEC_GetITStatus(uint16_t CEC_IT);
+void CEC_ClearITPendingBit(uint16_t CEC_IT);
+#endif /* STM32F446xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_CEC_H */
+

底盘/底盘-old/底盘/Library/stm32f4xx_crc.c

@@ -0,0 +1,125 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_crc.c
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file provides all the CRC firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_crc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CRC 
+  * @brief CRC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CRC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Resets the CRC Data register (DR).
+  * @param  None
+  * @retval None
+  */
+void CRC_ResetDR(void)
+{
+  /* Reset CRC generator */
+  CRC->CR = CRC_CR_RESET;
+}
+
+/**
+  * @brief  Computes the 32-bit CRC of a given data word(32-bit).
+  * @param  Data: data word(32-bit) to compute its CRC
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_CalcCRC(uint32_t Data)
+{
+  CRC->DR = Data;
+  
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
+  * @param  pBuffer: pointer to the buffer containing the data to be computed
+  * @param  BufferLength: length of the buffer to be computed					
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index = 0;
+  
+  for(index = 0; index < BufferLength; index++)
+  {
+    CRC->DR = pBuffer[index];
+  }
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Returns the current CRC value.
+  * @param  None
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_GetCRC(void)
+{
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Stores a 8-bit data in the Independent Data(ID) register.
+  * @param  IDValue: 8-bit value to be stored in the ID register 					
+  * @retval None
+  */
+void CRC_SetIDRegister(uint8_t IDValue)
+{
+  CRC->IDR = IDValue;
+}
+
+/**
+  * @brief  Returns the 8-bit data stored in the Independent Data(ID) register
+  * @param  None
+  * @retval 8-bit value of the ID register 
+  */
+uint8_t CRC_GetIDRegister(void)
+{
+  return (CRC->IDR);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

底盘/底盘-old/底盘/Library/stm32f4xx_crc.h

@@ -0,0 +1,75 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_crc.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the CRC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_CRC_H
+#define __STM32F4xx_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CRC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRC_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/  
+
+void CRC_ResetDR(void);
+uint32_t CRC_CalcCRC(uint32_t Data);
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+void CRC_SetIDRegister(uint8_t IDValue);
+uint8_t CRC_GetIDRegister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_CRC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

底盘/底盘-old/底盘/Library/stm32f4xx_cryp.c

@@ -0,0 +1,926 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_cryp.c
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the  Cryptographic processor (CRYP) peripheral:
+  *           + Initialization and Configuration functions
+  *           + Data treatment functions 
+  *           + Context swapping functions     
+  *           + DMA interface function       
+  *           + Interrupts and flags management       
+  *
+@verbatim
+ ===================================================================      
+                 ##### How to use this driver #####
+ =================================================================== 
+ [..]
+   (#) Enable the CRYP controller clock using 
+       RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
+  
+   (#) Initialize the CRYP using CRYP_Init(), CRYP_KeyInit() and if needed 
+       CRYP_IVInit(). 
+  
+   (#) Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function.
+  
+   (#) Enable the CRYP controller using the CRYP_Cmd() function. 
+  
+   (#) If using DMA for Data input and output transfer, activate the needed DMA 
+       Requests using CRYP_DMACmd() function 
+  
+   (#) If DMA is not used for data transfer, use CRYP_DataIn() and  CRYP_DataOut() 
+       functions to enter data to IN FIFO and get result from OUT FIFO.
+  
+   (#) To control CRYP events you can use one of the following two methods:
+       (++) Check on CRYP flags using the CRYP_GetFlagStatus() function.  
+       (++) Use CRYP interrupts through the function CRYP_ITConfig() at 
+            initialization phase and CRYP_GetITStatus() function into interrupt 
+            routines in processing phase.
+         
+   (#) Save and restore Cryptographic processor context using CRYP_SaveContext() 
+       and CRYP_RestoreContext() functions.     
+  
+  
+ *** Procedure to perform an encryption or a decryption ***
+ ========================================================== 
+  
+ *** Initialization ***
+ ====================== 
+ [..] 
+   (#) Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and CRYP_IVInit 
+       functions:
+       (++) Configure the key size (128-, 192- or 256-bit, in the AES only) 
+       (++) Enter the symmetric key 
+       (++) Configure the data type
+       (++) In case of decryption in AES-ECB or AES-CBC, you must prepare 
+            the key: configure the key preparation mode. Then Enable the CRYP 
+            peripheral using CRYP_Cmd() function: the BUSY flag is set. 
+            Wait until BUSY flag is reset : the key is prepared for decryption
+       (++) Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the 
+            AES in ECB/CBC/CTR) 
+       (++) Configure the direction (encryption/decryption).
+       (++) Write the initialization vectors (in CBC or CTR modes only)
+  
+   (#) Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function
+  
+  
+  *** Basic Processing mode (polling mode) *** 
+  ============================================  
+  [..]
+    (#) Enable the cryptographic processor using CRYP_Cmd() function.
+  
+    (#) Write the first blocks in the input FIFO (2 to 8 words) using 
+        CRYP_DataIn() function.
+  
+    (#) Repeat the following sequence until the complete message has been 
+        processed:
+  
+        (++) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus() 
+            function), then read the OUT-FIFO using CRYP_DataOut() function
+            (1 block or until the FIFO is empty)
+  
+         (++) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus() 
+            function then write the IN FIFO using CRYP_DataIn() function 
+            (1 block or until the FIFO is full)
+  
+    (#) At the end of the processing, CRYP_FLAG_BUSY flag will be reset and 
+          both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is 
+          reset). You can disable the peripheral using CRYP_Cmd() function.
+  
+ *** Interrupts Processing mode *** 
+ ==================================
+ [..] In this mode, Processing is done when the data are transferred by the 
+      CPU during interrupts.
+  
+    (#) Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using CRYP_ITConfig()
+        function.
+  
+    (#) Enable the cryptographic processor using CRYP_Cmd() function.
+  
+    (#) In the CRYP_IT_INI interrupt handler : load the input message into the 
+         IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a 
+         time, or load data until the IN FIFO is full. When the last word of
+         the message has been entered into the IN FIFO, disable the CRYP_IT_INI 
+         interrupt (using CRYP_ITConfig() function).
+  
+    (#) In the CRYP_IT_OUTI interrupt handler : read the output message from 
+         the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or 
+         4 words) at a time or read data until the FIFO is empty.
+         When the last word has been read, INIM=0, BUSY=0 and both FIFOs are 
+         empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset). 
+         You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig() 
+         function) and you can disable the peripheral using CRYP_Cmd() function.
+  
+ *** DMA Processing mode *** 
+ ===========================
+ [..] In this mode, Processing is done when the DMA is used to transfer the 
+      data from/to the memory.
+  
+    (#) Configure the DMA controller to transfer the input data from the 
+         memory using DMA_Init() function. 
+         The transfer length is the length of the message. 
+         As message padding is not managed by the peripheral, the message 
+         length must be an entire number of blocks. The data are transferred 
+         in burst mode. The burst length is 4 words in the AES and 2 or 4 
+         words in the DES/TDES. The DMA should be configured to set an 
+         interrupt on transfer completion of the output data to indicate that 
+         the processing is finished. 
+         Refer to DMA peripheral driver for more details.  
+  
+     (#) Enable the cryptographic processor using CRYP_Cmd() function. 
+         Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT 
+         using CRYP_DMACmd() function.
+  
+     (#) All the transfers and processing are managed by the DMA and the 
+         cryptographic processor. The DMA transfer complete interrupt indicates 
+         that the processing is complete. Both FIFOs are normally empty and 
+         CRYP_FLAG_BUSY flag is reset.
+  
+    @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_cryp.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CRYP 
+  * @brief CRYP driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define FLAG_MASK     ((uint8_t)0x20)
+#define MAX_TIMEOUT   ((uint16_t)0xFFFF)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CRYP_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup CRYP_Group1 Initialization and Configuration functions
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+             ##### Initialization and Configuration functions #####
+ ===============================================================================  
+ [..] This section provides functions allowing to 
+   (+) Initialize the cryptographic Processor using CRYP_Init() function 
+       (++)  Encrypt or Decrypt 
+       (++)  mode : TDES-ECB, TDES-CBC, 
+                    DES-ECB, DES-CBC, 
+                    AES-ECB, AES-CBC, AES-CTR, AES-Key, AES-GCM, AES-CCM 
+       (++) DataType :  32-bit data, 16-bit data, bit data or bit-string
+       (++) Key Size (only in AES modes)
+   (+) Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function 
+   (+) Configure the Initialization Vectors(IV) for CBC and CTR modes using 
+       CRYP_IVInit() function.  
+   (+) Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function.                         
+   (+) Enable or disable the CRYP Processor using CRYP_Cmd() function 
+       
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Deinitializes the CRYP peripheral registers to their default reset values
+  * @param  None
+  * @retval None
+  */
+void CRYP_DeInit(void)
+{
+  /* Enable CRYP reset state */
+  RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, ENABLE);
+
+  /* Release CRYP from reset state */
+  RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, DISABLE);
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral according to the specified parameters
+  *         in the CRYP_InitStruct.
+  * @param  CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure that contains
+  *         the configuration information for the CRYP peripheral.
+  * @retval None
+  */
+void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_CRYP_ALGOMODE(CRYP_InitStruct->CRYP_AlgoMode));
+  assert_param(IS_CRYP_DATATYPE(CRYP_InitStruct->CRYP_DataType));
+  assert_param(IS_CRYP_ALGODIR(CRYP_InitStruct->CRYP_AlgoDir));
+
+  /* Select Algorithm mode*/  
+  CRYP->CR &= ~CRYP_CR_ALGOMODE;
+  CRYP->CR |= CRYP_InitStruct->CRYP_AlgoMode;
+
+  /* Select dataType */ 
+  CRYP->CR &= ~CRYP_CR_DATATYPE;
+  CRYP->CR |= CRYP_InitStruct->CRYP_DataType;
+
+  /* select Key size (used only with AES algorithm) */
+  if ((CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_TDES_ECB) &&
+      (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_TDES_CBC) &&
+      (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_DES_ECB) &&
+      (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_DES_CBC))
+  {
+    assert_param(IS_CRYP_KEYSIZE(CRYP_InitStruct->CRYP_KeySize));
+    CRYP->CR &= ~CRYP_CR_KEYSIZE;
+    CRYP->CR |= CRYP_InitStruct->CRYP_KeySize; /* Key size and value must be 
+                                                  configured once the key has 
+                                                  been prepared */
+  }
+
+  /* Select data Direction */ 
+  CRYP->CR &= ~CRYP_CR_ALGODIR;
+  CRYP->CR |= CRYP_InitStruct->CRYP_AlgoDir;
+}
+
+/**
+  * @brief  Fills each CRYP_InitStruct member with its default value.
+  * @param  CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct)
+{
+  /* Initialize the CRYP_AlgoDir member */
+  CRYP_InitStruct->CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
+
+  /* initialize the CRYP_AlgoMode member */
+  CRYP_InitStruct->CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB;
+
+  /* initialize the CRYP_DataType member */
+  CRYP_InitStruct->CRYP_DataType = CRYP_DataType_32b;
+  
+  /* Initialize the CRYP_KeySize member */
+  CRYP_InitStruct->CRYP_KeySize = CRYP_KeySize_128b;
+}
+
+/**
+  * @brief  Initializes the CRYP Keys according to the specified parameters in
+  *         the CRYP_KeyInitStruct.
+  * @param  CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that
+  *         contains the configuration information for the CRYP Keys.
+  * @retval None
+  */
+void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
+{
+  /* Key Initialisation */
+  CRYP->K0LR = CRYP_KeyInitStruct->CRYP_Key0Left;
+  CRYP->K0RR = CRYP_KeyInitStruct->CRYP_Key0Right;
+  CRYP->K1LR = CRYP_KeyInitStruct->CRYP_Key1Left;
+  CRYP->K1RR = CRYP_KeyInitStruct->CRYP_Key1Right;
+  CRYP->K2LR = CRYP_KeyInitStruct->CRYP_Key2Left;
+  CRYP->K2RR = CRYP_KeyInitStruct->CRYP_Key2Right;
+  CRYP->K3LR = CRYP_KeyInitStruct->CRYP_Key3Left;
+  CRYP->K3RR = CRYP_KeyInitStruct->CRYP_Key3Right;
+}
+
+/**
+  * @brief  Fills each CRYP_KeyInitStruct member with its default value.
+  * @param  CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure 
+  *         which will be initialized.
+  * @retval None
+  */
+void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
+{
+  CRYP_KeyInitStruct->CRYP_Key0Left  = 0;
+  CRYP_KeyInitStruct->CRYP_Key0Right = 0;
+  CRYP_KeyInitStruct->CRYP_Key1Left  = 0;
+  CRYP_KeyInitStruct->CRYP_Key1Right = 0;
+  CRYP_KeyInitStruct->CRYP_Key2Left  = 0;
+  CRYP_KeyInitStruct->CRYP_Key2Right = 0;
+  CRYP_KeyInitStruct->CRYP_Key3Left  = 0;
+  CRYP_KeyInitStruct->CRYP_Key3Right = 0;
+}
+/**
+  * @brief  Initializes the CRYP Initialization Vectors(IV) according to the
+  *         specified parameters in the CRYP_IVInitStruct.
+  * @param  CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef structure that contains
+  *         the configuration information for the CRYP Initialization Vectors(IV).
+  * @retval None
+  */
+void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct)
+{
+  CRYP->IV0LR = CRYP_IVInitStruct->CRYP_IV0Left;
+  CRYP->IV0RR = CRYP_IVInitStruct->CRYP_IV0Right;
+  CRYP->IV1LR = CRYP_IVInitStruct->CRYP_IV1Left;
+  CRYP->IV1RR = CRYP_IVInitStruct->CRYP_IV1Right;
+}
+
+/**
+  * @brief  Fills each CRYP_IVInitStruct member with its default value.
+  * @param  CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef Initialization 
+  *         Vectors(IV) structure which will be initialized.
+  * @retval None
+  */
+void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct)
+{
+  CRYP_IVInitStruct->CRYP_IV0Left  = 0;
+  CRYP_IVInitStruct->CRYP_IV0Right = 0;
+  CRYP_IVInitStruct->CRYP_IV1Left  = 0;
+  CRYP_IVInitStruct->CRYP_IV1Right = 0;
+}
+
+/**
+  * @brief  Configures the AES-CCM and AES-GCM phases
+  * @note   This function is used only with AES-CCM or AES-GCM Algorithms  
+  * @param  CRYP_Phase: specifies the CRYP AES-CCM and AES-GCM phase to be configured.
+  *           This parameter can be one of the following values:
+  *            @arg CRYP_Phase_Init: Initialization phase
+  *            @arg CRYP_Phase_Header: Header phase
+  *            @arg CRYP_Phase_Payload: Payload phase
+  *            @arg CRYP_Phase_Final: Final phase 
+  * @retval None
+  */
+void CRYP_PhaseConfig(uint32_t CRYP_Phase)
+{ uint32_t tempcr = 0;
+
+  /* Check the parameter */
+  assert_param(IS_CRYP_PHASE(CRYP_Phase));
+
+  /* Get the CR register */
+  tempcr = CRYP->CR;
+  
+  /* Reset the phase configuration bits: GCMP_CCMPH */
+  tempcr &= (uint32_t)(~CRYP_CR_GCM_CCMPH);
+  /* Set the selected phase */
+  tempcr |= (uint32_t)CRYP_Phase;
+
+  /* Set the CR register */ 
+  CRYP->CR = tempcr;    
+}
+
+/**
+  * @brief  Flushes the IN and OUT FIFOs (that is read and write pointers of the 
+  *         FIFOs are reset)
+  * @note   The FIFOs must be flushed only when BUSY flag is reset.  
+  * @param  None
+  * @retval None
+  */
+void CRYP_FIFOFlush(void)
+{
+  /* Reset the read and write pointers of the FIFOs */
+  CRYP->CR |= CRYP_CR_FFLUSH;
+}
+
+/**
+  * @brief  Enables or disables the CRYP peripheral.
+  * @param  NewState: new state of the CRYP peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CRYP_Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Cryptographic processor */
+    CRYP->CR |= CRYP_CR_CRYPEN;
+  }
+  else
+  {
+    /* Disable the Cryptographic processor */
+    CRYP->CR &= ~CRYP_CR_CRYPEN;
+  }
+}
+/**
+  * @}
+  */
+  
+/** @defgroup CRYP_Group2 CRYP Data processing functions
+ *  @brief    CRYP Data processing functions
+ *
+@verbatim    
+ ===============================================================================
+                    ##### CRYP Data processing functions #####
+ ===============================================================================  
+ [..] This section provides functions allowing the encryption and decryption 
+      operations: 
+   (+) Enter data to be treated in the IN FIFO : using CRYP_DataIn() function.
+   (+) Get the data result from the OUT FIFO : using CRYP_DataOut() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Writes data in the Data Input register (DIN).
+  * @note   After the DIN register has been read once or several times, 
+  *         the FIFO must be flushed (using CRYP_FIFOFlush() function).  
+  * @param  Data: data to write in Data Input register
+  * @retval None
+  */
+void CRYP_DataIn(uint32_t Data)
+{
+  CRYP->DR = Data;
+}
+
+/**
+  * @brief  Returns the last data entered into the output FIFO.
+  * @param  None
+  * @retval Last data entered into the output FIFO.
+  */
+uint32_t CRYP_DataOut(void)
+{
+  return CRYP->DOUT;
+}
+/**
+  * @}
+  */
+  
+/** @defgroup CRYP_Group3 Context swapping functions
+ *  @brief   Context swapping functions
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Context swapping functions #####
+ ===============================================================================  
+ [..] This section provides functions allowing to save and store CRYP Context
+
+ [..] It is possible to interrupt an encryption/ decryption/ key generation process 
+      to perform another processing with a higher priority, and to complete the 
+      interrupted process later on, when the higher-priority task is complete. To do 
+      so, the context of the interrupted task must be saved from the CRYP registers 
+      to memory, and then be restored from memory to the CRYP registers.
+   
+   (#) To save the current context, use CRYP_SaveContext() function
+   (#) To restore the saved context, use CRYP_RestoreContext() function 
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Saves the CRYP peripheral Context. 
+  * @note   This function stops DMA transfer before to save the context. After 
+  *         restoring the context, you have to enable the DMA again (if the DMA
+  *         was previously used).
+  * @param  CRYP_ContextSave: pointer to a CRYP_Context structure that contains
+  *         the repository for current context.
+  * @param  CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that 
+  *         contains the configuration information for the CRYP Keys.  
+  * @retval None
+  */
+ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,
+                             CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
+{
+  __IO uint32_t timeout = 0;
+  uint32_t ckeckmask = 0, bitstatus;    
+  ErrorStatus status = ERROR;
+
+  /* Stop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR */
+  CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DIEN;
+    
+  /* Wait until both the IN and OUT FIFOs are empty  
+    (IFEM=1 and OFNE=0 in the CRYP_SR register) and the 
+     BUSY bit is cleared. */
+
+  if ((CRYP->CR & (uint32_t)(CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE_TDES_CBC)) != (uint32_t)0 )/* TDES */
+  { 
+    ckeckmask =  CRYP_SR_IFEM | CRYP_SR_BUSY ;
+  }
+  else /* AES or DES */
+  {
+    ckeckmask =  CRYP_SR_IFEM | CRYP_SR_BUSY | CRYP_SR_OFNE;
+  }           
+   
+  do 
+  {
+    bitstatus = CRYP->SR & ckeckmask;
+    timeout++;
+  }
+  while ((timeout != MAX_TIMEOUT) && (bitstatus != CRYP_SR_IFEM));
+     
+  if ((CRYP->SR & ckeckmask) != CRYP_SR_IFEM)
+  {
+    status = ERROR;
+  }
+  else
+  {      
+    /* Stop DMA transfers on the OUT FIFO by 
+       - writing the DOEN bit to 0 in the CRYP_DMACR register 
+       - and clear the CRYPEN bit. */
+
+    CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DOEN;
+    CRYP->CR &= ~(uint32_t)CRYP_CR_CRYPEN;
+
+    /* Save the current configuration (bit 19, bit[17:16] and bits [9:2] in the CRYP_CR register) */
+    CRYP_ContextSave->CR_CurrentConfig  = CRYP->CR & (CRYP_CR_GCM_CCMPH |
+                                                      CRYP_CR_KEYSIZE  |
+                                                      CRYP_CR_DATATYPE |
+                                                      CRYP_CR_ALGOMODE |
+                                                      CRYP_CR_ALGODIR);
+
+    /* and, if not in ECB mode, the initialization vectors. */
+    CRYP_ContextSave->CRYP_IV0LR = CRYP->IV0LR;
+    CRYP_ContextSave->CRYP_IV0RR = CRYP->IV0RR;
+    CRYP_ContextSave->CRYP_IV1LR = CRYP->IV1LR;
+    CRYP_ContextSave->CRYP_IV1RR = CRYP->IV1RR;
+
+    /* save The key value */
+    CRYP_ContextSave->CRYP_K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; 
+    CRYP_ContextSave->CRYP_K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; 
+    CRYP_ContextSave->CRYP_K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; 
+    CRYP_ContextSave->CRYP_K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; 
+    CRYP_ContextSave->CRYP_K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; 
+    CRYP_ContextSave->CRYP_K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; 
+    CRYP_ContextSave->CRYP_K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; 
+    CRYP_ContextSave->CRYP_K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; 
+
+    /* Save the content of context swap registers */
+    CRYP_ContextSave->CRYP_CSGCMCCMR[0] = CRYP->CSGCMCCM0R;
+    CRYP_ContextSave->CRYP_CSGCMCCMR[1] = CRYP->CSGCMCCM1R;
+    CRYP_ContextSave->CRYP_CSGCMCCMR[2] = CRYP->CSGCMCCM2R;
+    CRYP_ContextSave->CRYP_CSGCMCCMR[3] = CRYP->CSGCMCCM3R;
+    CRYP_ContextSave->CRYP_CSGCMCCMR[4] = CRYP->CSGCMCCM4R;
+    CRYP_ContextSave->CRYP_CSGCMCCMR[5] = CRYP->CSGCMCCM5R;
+    CRYP_ContextSave->CRYP_CSGCMCCMR[6] = CRYP->CSGCMCCM6R;
+    CRYP_ContextSave->CRYP_CSGCMCCMR[7] = CRYP->CSGCMCCM7R;
+    
+    CRYP_ContextSave->CRYP_CSGCMR[0] = CRYP->CSGCM0R;
+    CRYP_ContextSave->CRYP_CSGCMR[1] = CRYP->CSGCM1R;
+    CRYP_ContextSave->CRYP_CSGCMR[2] = CRYP->CSGCM2R;
+    CRYP_ContextSave->CRYP_CSGCMR[3] = CRYP->CSGCM3R;
+    CRYP_ContextSave->CRYP_CSGCMR[4] = CRYP->CSGCM4R;
+    CRYP_ContextSave->CRYP_CSGCMR[5] = CRYP->CSGCM5R;
+    CRYP_ContextSave->CRYP_CSGCMR[6] = CRYP->CSGCM6R;
+    CRYP_ContextSave->CRYP_CSGCMR[7] = CRYP->CSGCM7R;
+    
+   /* When needed, save the DMA status (pointers for IN and OUT messages, 
+      number of remaining bytes, etc.) */
+     
+    status = SUCCESS;
+  }
+
+   return status;
+}
+
+/**
+  * @brief  Restores the CRYP peripheral Context.
+  * @note   Since the DMA transfer is stopped in CRYP_SaveContext() function,
+  *         after restoring the context, you have to enable the DMA again (if the
+  *         DMA was previously used).  
+  * @param  CRYP_ContextRestore: pointer to a CRYP_Context structure that contains
+  *         the repository for saved context.
+  * @note   The data that were saved during context saving must be rewritten into
+  *         the IN FIFO.
+  * @retval None
+  */
+void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore)  
+{
+
+  /* Configure the processor with the saved configuration */
+  CRYP->CR = CRYP_ContextRestore->CR_CurrentConfig;
+
+  /* restore The key value */
+  CRYP->K0LR = CRYP_ContextRestore->CRYP_K0LR; 
+  CRYP->K0RR = CRYP_ContextRestore->CRYP_K0RR;
+  CRYP->K1LR = CRYP_ContextRestore->CRYP_K1LR;
+  CRYP->K1RR = CRYP_ContextRestore->CRYP_K1RR;
+  CRYP->K2LR = CRYP_ContextRestore->CRYP_K2LR;
+  CRYP->K2RR = CRYP_ContextRestore->CRYP_K2RR;
+  CRYP->K3LR = CRYP_ContextRestore->CRYP_K3LR;
+  CRYP->K3RR = CRYP_ContextRestore->CRYP_K3RR;
+
+  /* and the initialization vectors. */
+  CRYP->IV0LR = CRYP_ContextRestore->CRYP_IV0LR;
+  CRYP->IV0RR = CRYP_ContextRestore->CRYP_IV0RR;
+  CRYP->IV1LR = CRYP_ContextRestore->CRYP_IV1LR;
+  CRYP->IV1RR = CRYP_ContextRestore->CRYP_IV1RR;
+
+  /* Restore the content of context swap registers */
+  CRYP->CSGCMCCM0R = CRYP_ContextRestore->CRYP_CSGCMCCMR[0];
+  CRYP->CSGCMCCM1R = CRYP_ContextRestore->CRYP_CSGCMCCMR[1];
+  CRYP->CSGCMCCM2R = CRYP_ContextRestore->CRYP_CSGCMCCMR[2];
+  CRYP->CSGCMCCM3R = CRYP_ContextRestore->CRYP_CSGCMCCMR[3];
+  CRYP->CSGCMCCM4R = CRYP_ContextRestore->CRYP_CSGCMCCMR[4];
+  CRYP->CSGCMCCM5R = CRYP_ContextRestore->CRYP_CSGCMCCMR[5];
+  CRYP->CSGCMCCM6R = CRYP_ContextRestore->CRYP_CSGCMCCMR[6];
+  CRYP->CSGCMCCM7R = CRYP_ContextRestore->CRYP_CSGCMCCMR[7];
+  
+  CRYP->CSGCM0R = CRYP_ContextRestore->CRYP_CSGCMR[0];
+  CRYP->CSGCM1R = CRYP_ContextRestore->CRYP_CSGCMR[1];
+  CRYP->CSGCM2R = CRYP_ContextRestore->CRYP_CSGCMR[2];
+  CRYP->CSGCM3R = CRYP_ContextRestore->CRYP_CSGCMR[3];
+  CRYP->CSGCM4R = CRYP_ContextRestore->CRYP_CSGCMR[4];
+  CRYP->CSGCM5R = CRYP_ContextRestore->CRYP_CSGCMR[5];
+  CRYP->CSGCM6R = CRYP_ContextRestore->CRYP_CSGCMR[6];
+  CRYP->CSGCM7R = CRYP_ContextRestore->CRYP_CSGCMR[7];
+  
+  /* Enable the cryptographic processor */
+  CRYP->CR |= CRYP_CR_CRYPEN;
+}
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Group4 CRYP's DMA interface Configuration function
+ *  @brief   CRYP's DMA interface Configuration function 
+ *
+@verbatim   
+ ===============================================================================
+             ##### CRYP's DMA interface Configuration function #####
+ ===============================================================================  
+ [..] This section provides functions allowing to configure the DMA interface for 
+      CRYP data input and output transfer.
+   
+ [..] When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be 
+      transferred:
+   (+) From memory to the CRYP IN FIFO using the DMA peripheral by enabling 
+       the CRYP_DMAReq_DataIN request.
+   (+) From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling 
+       the CRYP_DMAReq_DataOUT request.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the CRYP DMA interface.
+  * @param  CRYP_DMAReq: specifies the CRYP DMA transfer request to be enabled or disabled.
+  *           This parameter can be any combination of the following values:
+  *            @arg CRYP_DMAReq_DataOUT: DMA for outgoing(Tx) data transfer
+  *            @arg CRYP_DMAReq_DataIN: DMA for incoming(Rx) data transfer
+  * @param  NewState: new state of the selected CRYP DMA transfer request.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_CRYP_DMAREQ(CRYP_DMAReq));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected CRYP DMA request */
+    CRYP->DMACR |= CRYP_DMAReq;
+  }
+  else
+  {
+    /* Disable the selected CRYP DMA request */
+    CRYP->DMACR &= (uint8_t)~CRYP_DMAReq;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Group5 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+              ##### Interrupts and flags management functions #####
+ ===============================================================================  
+ 
+ [..] This section provides functions allowing to configure the CRYP Interrupts and 
+      to get the status and Interrupts pending bits.
+
+ [..] The CRYP provides 2 Interrupts sources and 7 Flags:
+
+ *** Flags : ***
+ ===============
+ [..] 
+   (#) CRYP_FLAG_IFEM :  Set when Input FIFO is empty. This Flag is cleared only
+       by hardware.
+      
+   (#) CRYP_FLAG_IFNF :  Set when Input FIFO is not full. This Flag is cleared 
+       only by hardware.
+
+
+   (#) CRYP_FLAG_INRIS  : Set when Input FIFO Raw interrupt is pending it gives 
+       the raw interrupt state prior to masking of the input FIFO service interrupt.
+       This Flag is cleared only by hardware.
+     
+   (#) CRYP_FLAG_OFNE   : Set when Output FIFO not empty. This Flag is cleared 
+       only by hardware.
+        
+   (#) CRYP_FLAG_OFFU   : Set when Output FIFO is full. This Flag is cleared only 
+       by hardware.
+                           
+   (#) CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending it gives 
+       the raw interrupt state prior to masking of the output FIFO service interrupt.
+       This Flag is cleared only by hardware.
+                               
+   (#) CRYP_FLAG_BUSY   : Set when the CRYP core is currently processing a block 
+       of data or a key preparation (for AES decryption). This Flag is cleared 
+       only by hardware. To clear it, the CRYP core must be disabled and the last
+       processing has completed. 
+
+ *** Interrupts : ***
+ ====================
+ [..]
+   (#) CRYP_IT_INI   : The input FIFO service interrupt is asserted when there 
+      are less than 4 words in the input FIFO. This interrupt is associated to 
+      CRYP_FLAG_INRIS flag.
+
+      -@- This interrupt is cleared by performing write operations to the input FIFO 
+          until it holds 4 or more words. The input FIFO service interrupt INMIS is 
+          enabled with the CRYP enable bit. Consequently, when CRYP is disabled, the 
+          INMIS signal is low even if the input FIFO is empty.
+
+
+
+   (#) CRYP_IT_OUTI  : The output FIFO service interrupt is asserted when there 
+       is one or more (32-bit word) data items in the output FIFO. This interrupt 
+       is associated to CRYP_FLAG_OUTRIS flag.
+
+       -@- This interrupt is cleared by reading data from the output FIFO until there 
+           is no valid (32-bit) word left (that is, the interrupt follows the state 
+           of the OFNE (output FIFO not empty) flag).
+
+ *** Managing the CRYP controller events : ***
+ =============================================
+ [..] The user should identify which mode will be used in his application to manage 
+      the CRYP controller events: Polling mode or Interrupt mode.
+
+   (#) In the Polling Mode it is advised to use the following functions:
+       (++) CRYP_GetFlagStatus() : to check if flags events occur. 
+
+       -@@- The CRYPT flags do not need to be cleared since they are cleared as 
+            soon as the associated event are reset.   
+
+
+   (#) In the Interrupt Mode it is advised to use the following functions:
+       (++) CRYP_ITConfig()       : to enable or disable the interrupt source.
+       (++) CRYP_GetITStatus()    : to check if Interrupt occurs.
+
+       -@@- The CRYPT interrupts have no pending bits, the interrupt is cleared as 
+             soon as the associated event is reset. 
+
+@endverbatim
+  * @{
+  */ 
+
+/**
+  * @brief  Enables or disables the specified CRYP interrupts.
+  * @param  CRYP_IT: specifies the CRYP interrupt source to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg CRYP_IT_INI: Input FIFO interrupt
+  *            @arg CRYP_IT_OUTI: Output FIFO interrupt
+  * @param  NewState: new state of the specified CRYP interrupt.
+  *           This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_CRYP_CONFIG_IT(CRYP_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected CRYP interrupt */
+    CRYP->IMSCR |= CRYP_IT;
+  }
+  else
+  {
+    /* Disable the selected CRYP interrupt */
+    CRYP->IMSCR &= (uint8_t)~CRYP_IT;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified CRYP interrupt has occurred or not.
+  * @note   This function checks the status of the masked interrupt (i.e the 
+  *         interrupt should be previously enabled).     
+  * @param  CRYP_IT: specifies the CRYP (masked) interrupt source to check.
+  *           This parameter can be one of the following values:
+  *            @arg CRYP_IT_INI: Input FIFO interrupt
+  *            @arg CRYP_IT_OUTI: Output FIFO interrupt
+  * @retval The new state of CRYP_IT (SET or RESET).
+  */
+ITStatus CRYP_GetITStatus(uint8_t CRYP_IT)
+{
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_CRYP_GET_IT(CRYP_IT));
+
+  /* Check the status of the specified CRYP interrupt */
+  if ((CRYP->MISR &  CRYP_IT) != (uint8_t)RESET)
+  {
+    /* CRYP_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* CRYP_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the CRYP_IT status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Returns whether CRYP peripheral is enabled or disabled.
+  * @param  none.
+  * @retval Current state of the CRYP peripheral (ENABLE or DISABLE).
+  */
+FunctionalState CRYP_GetCmdStatus(void)
+{
+  FunctionalState state = DISABLE;
+
+  if ((CRYP->CR & CRYP_CR_CRYPEN) != 0)
+  {
+    /* CRYPEN bit is set */
+    state = ENABLE;
+  }
+  else
+  {
+    /* CRYPEN bit is reset */
+    state = DISABLE;
+  }
+  return state;
+}
+
+/**
+  * @brief  Checks whether the specified CRYP flag is set or not.
+  * @param  CRYP_FLAG: specifies the CRYP flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg CRYP_FLAG_IFEM: Input FIFO Empty flag.
+  *            @arg CRYP_FLAG_IFNF: Input FIFO Not Full flag.
+  *            @arg CRYP_FLAG_OFNE: Output FIFO Not Empty flag.
+  *            @arg CRYP_FLAG_OFFU: Output FIFO Full flag.
+  *            @arg CRYP_FLAG_BUSY: Busy flag.
+  *            @arg CRYP_FLAG_OUTRIS: Output FIFO raw interrupt flag.
+  *            @arg CRYP_FLAG_INRIS: Input FIFO raw interrupt flag.
+  * @retval The new state of CRYP_FLAG (SET or RESET).
+  */
+FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tempreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_CRYP_GET_FLAG(CRYP_FLAG));
+
+  /* check if the FLAG is in RISR register */
+  if ((CRYP_FLAG & FLAG_MASK) != 0x00) 
+  {
+    tempreg = CRYP->RISR;
+  }
+  else  /* The FLAG is in SR register */
+  {
+    tempreg = CRYP->SR;
+  }
+
+
+  /* Check the status of the specified CRYP flag */
+  if ((tempreg & CRYP_FLAG ) != (uint8_t)RESET)
+  {
+    /* CRYP_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* CRYP_FLAG is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the CRYP_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+

底盘/底盘-old/底盘/Library/stm32f4xx_cryp.h

@@ -0,0 +1,376 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_cryp.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the Cryptographic
+  *          processor(CRYP) firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_CRYP_H
+#define __STM32F4xx_CRYP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CRYP
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief   CRYP Init structure definition  
+  */ 
+typedef struct
+{
+  uint32_t CRYP_AlgoDir;   /*!< Encrypt or Decrypt. This parameter can be a 
+                                value of @ref CRYP_Algorithm_Direction */
+  uint32_t CRYP_AlgoMode;  /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, 
+                                AES-CBC, AES-CTR, AES-Key, AES-GCM and AES-CCM.
+                                This parameter can be a value of @ref CRYP_Algorithm_Mode */
+  uint32_t CRYP_DataType;  /*!< 32-bit data, 16-bit data, bit data or bit string.
+                                This parameter can be a value of @ref CRYP_Data_Type */ 
+  uint32_t CRYP_KeySize;   /*!< Used only in AES mode only : 128, 192 or 256 bit 
+                                key length. This parameter can be a value of 
+                                @ref CRYP_Key_Size_for_AES_only */
+}CRYP_InitTypeDef;
+
+/** 
+  * @brief   CRYP Key(s) structure definition  
+  */ 
+typedef struct
+{
+  uint32_t CRYP_Key0Left;  /*!< Key 0 Left  */
+  uint32_t CRYP_Key0Right; /*!< Key 0 Right */
+  uint32_t CRYP_Key1Left;  /*!< Key 1 left  */
+  uint32_t CRYP_Key1Right; /*!< Key 1 Right */
+  uint32_t CRYP_Key2Left;  /*!< Key 2 left  */
+  uint32_t CRYP_Key2Right; /*!< Key 2 Right */
+  uint32_t CRYP_Key3Left;  /*!< Key 3 left  */
+  uint32_t CRYP_Key3Right; /*!< Key 3 Right */
+}CRYP_KeyInitTypeDef;
+/** 
+  * @brief   CRYP Initialization Vectors (IV) structure definition  
+  */ 
+typedef struct
+{
+  uint32_t CRYP_IV0Left;  /*!< Init Vector 0 Left  */
+  uint32_t CRYP_IV0Right; /*!< Init Vector 0 Right */
+  uint32_t CRYP_IV1Left;  /*!< Init Vector 1 left  */
+  uint32_t CRYP_IV1Right; /*!< Init Vector 1 Right */
+}CRYP_IVInitTypeDef;
+
+/** 
+  * @brief  CRYP context swapping structure definition  
+  */ 
+typedef struct
+{
+  /*!< Current Configuration */
+  uint32_t CR_CurrentConfig;
+  /*!< IV */
+  uint32_t CRYP_IV0LR;
+  uint32_t CRYP_IV0RR;
+  uint32_t CRYP_IV1LR;
+  uint32_t CRYP_IV1RR;
+  /*!< KEY */
+  uint32_t CRYP_K0LR;
+  uint32_t CRYP_K0RR;
+  uint32_t CRYP_K1LR;
+  uint32_t CRYP_K1RR;
+  uint32_t CRYP_K2LR;
+  uint32_t CRYP_K2RR;
+  uint32_t CRYP_K3LR;
+  uint32_t CRYP_K3RR;
+  uint32_t CRYP_CSGCMCCMR[8];
+  uint32_t CRYP_CSGCMR[8];
+}CRYP_Context;
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRYP_Exported_Constants
+  * @{
+  */
+
+/** @defgroup CRYP_Algorithm_Direction 
+  * @{
+  */
+#define CRYP_AlgoDir_Encrypt      ((uint16_t)0x0000)
+#define CRYP_AlgoDir_Decrypt      ((uint16_t)0x0004)
+#define IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) || \
+                                  ((ALGODIR) == CRYP_AlgoDir_Decrypt))
+
+/**
+  * @}
+  */ 
+ 
+/** @defgroup CRYP_Algorithm_Mode 
+  * @{
+  */
+
+/*!< TDES Modes */
+#define CRYP_AlgoMode_TDES_ECB    ((uint32_t)0x00000000)
+#define CRYP_AlgoMode_TDES_CBC    ((uint32_t)0x00000008)
+
+/*!< DES Modes */
+#define CRYP_AlgoMode_DES_ECB     ((uint32_t)0x00000010)
+#define CRYP_AlgoMode_DES_CBC     ((uint32_t)0x00000018)
+
+/*!< AES Modes */
+#define CRYP_AlgoMode_AES_ECB     ((uint32_t)0x00000020)
+#define CRYP_AlgoMode_AES_CBC     ((uint32_t)0x00000028)
+#define CRYP_AlgoMode_AES_CTR     ((uint32_t)0x00000030)
+#define CRYP_AlgoMode_AES_Key     ((uint32_t)0x00000038)
+#define CRYP_AlgoMode_AES_GCM     ((uint32_t)0x00080000)
+#define CRYP_AlgoMode_AES_CCM     ((uint32_t)0x00080008)
+
+#define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \
+                                   ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \
+                                   ((ALGOMODE) == CRYP_AlgoMode_DES_ECB) || \
+                                   ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \
+                                   ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \
+                                   ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \
+                                   ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \
+                                   ((ALGOMODE) == CRYP_AlgoMode_AES_Key) || \
+                                   ((ALGOMODE) == CRYP_AlgoMode_AES_GCM) || \
+                                   ((ALGOMODE) == CRYP_AlgoMode_AES_CCM))
+/**
+  * @}
+  */ 
+
+/** @defgroup CRYP_Phase 
+  * @{
+  */
+
+/*!< The phases are valid only for AES-GCM and AES-CCM modes */
+#define CRYP_Phase_Init           ((uint32_t)0x00000000)
+#define CRYP_Phase_Header         CRYP_CR_GCM_CCMPH_0
+#define CRYP_Phase_Payload        CRYP_CR_GCM_CCMPH_1
+#define CRYP_Phase_Final          CRYP_CR_GCM_CCMPH
+
+#define IS_CRYP_PHASE(PHASE) (((PHASE) == CRYP_Phase_Init)    || \
+                              ((PHASE) == CRYP_Phase_Header)  || \
+                              ((PHASE) == CRYP_Phase_Payload) || \
+                              ((PHASE) == CRYP_Phase_Final))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup CRYP_Data_Type 
+  * @{
+  */
+#define CRYP_DataType_32b         ((uint16_t)0x0000)
+#define CRYP_DataType_16b         ((uint16_t)0x0040)
+#define CRYP_DataType_8b          ((uint16_t)0x0080)
+#define CRYP_DataType_1b          ((uint16_t)0x00C0)
+#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) || \
+                                    ((DATATYPE) == CRYP_DataType_16b)|| \
+                                    ((DATATYPE) == CRYP_DataType_8b)|| \
+                                    ((DATATYPE) == CRYP_DataType_1b))  
+/**
+  * @}
+  */
+                                     
+/** @defgroup CRYP_Key_Size_for_AES_only 
+  * @{
+  */
+#define CRYP_KeySize_128b         ((uint16_t)0x0000)
+#define CRYP_KeySize_192b         ((uint16_t)0x0100)
+#define CRYP_KeySize_256b         ((uint16_t)0x0200)
+#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)|| \
+                                  ((KEYSIZE) == CRYP_KeySize_192b)|| \
+                                  ((KEYSIZE) == CRYP_KeySize_256b))
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_flags_definition 
+  * @{
+  */
+#define CRYP_FLAG_BUSY            ((uint8_t)0x10)  /*!< The CRYP core is currently 
+                                                        processing a block of data 
+                                                        or a key preparation (for 
+                                                        AES decryption). */
+#define CRYP_FLAG_IFEM            ((uint8_t)0x01)  /*!< Input Fifo Empty */
+#define CRYP_FLAG_IFNF            ((uint8_t)0x02)  /*!< Input Fifo is Not Full */
+#define CRYP_FLAG_INRIS           ((uint8_t)0x22)  /*!< Raw interrupt pending */
+#define CRYP_FLAG_OFNE            ((uint8_t)0x04)  /*!< Input Fifo service raw 
+                                                        interrupt status */
+#define CRYP_FLAG_OFFU            ((uint8_t)0x08)  /*!< Output Fifo is Full */
+#define CRYP_FLAG_OUTRIS          ((uint8_t)0x21)  /*!< Output Fifo service raw 
+                                                        interrupt status */
+
+#define IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM)  || \
+                                ((FLAG) == CRYP_FLAG_IFNF)  || \
+                                ((FLAG) == CRYP_FLAG_OFNE)  || \
+                                ((FLAG) == CRYP_FLAG_OFFU)  || \
+                                ((FLAG) == CRYP_FLAG_BUSY)  || \
+                                ((FLAG) == CRYP_FLAG_OUTRIS)|| \
+                                ((FLAG) == CRYP_FLAG_INRIS))
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_interrupts_definition 
+  * @{
+  */
+#define CRYP_IT_INI               ((uint8_t)0x01) /*!< IN Fifo Interrupt */
+#define CRYP_IT_OUTI              ((uint8_t)0x02) /*!< OUT Fifo Interrupt */
+#define IS_CRYP_CONFIG_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00))
+#define IS_CRYP_GET_IT(IT) (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI))
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Encryption_Decryption_modes_definition 
+  * @{
+  */
+#define MODE_ENCRYPT             ((uint8_t)0x01)
+#define MODE_DECRYPT             ((uint8_t)0x00)
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_DMA_transfer_requests 
+  * @{
+  */
+#define CRYP_DMAReq_DataIN             ((uint8_t)0x01)
+#define CRYP_DMAReq_DataOUT            ((uint8_t)0x02)
+#define IS_CRYP_DMAREQ(DMAREQ) ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00))
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/*  Function used to set the CRYP configuration to the default reset state ****/
+void CRYP_DeInit(void);
+
+/* CRYP Initialization and Configuration functions ****************************/
+void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct);
+void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct);
+void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
+void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
+void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);
+void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);
+void CRYP_Cmd(FunctionalState NewState);
+void CRYP_PhaseConfig(uint32_t CRYP_Phase);
+void CRYP_FIFOFlush(void);
+/* CRYP Data processing functions *********************************************/
+void CRYP_DataIn(uint32_t Data);
+uint32_t CRYP_DataOut(void);
+
+/* CRYP Context swapping functions ********************************************/
+ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,
+                             CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
+void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore);
+
+/* CRYP DMA interface function ************************************************/
+void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState);
+ITStatus CRYP_GetITStatus(uint8_t CRYP_IT);
+FunctionalState CRYP_GetCmdStatus(void);
+FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG);
+
+/* High Level AES functions **************************************************/
+ErrorStatus CRYP_AES_ECB(uint8_t Mode,
+                         uint8_t *Key, uint16_t Keysize,
+                         uint8_t *Input, uint32_t Ilength,
+                         uint8_t *Output);
+
+ErrorStatus CRYP_AES_CBC(uint8_t Mode,
+                         uint8_t InitVectors[16],
+                         uint8_t *Key, uint16_t Keysize,
+                         uint8_t *Input, uint32_t Ilength,
+                         uint8_t *Output);
+
+ErrorStatus CRYP_AES_CTR(uint8_t Mode,
+                         uint8_t InitVectors[16],
+                         uint8_t *Key, uint16_t Keysize,
+                         uint8_t *Input, uint32_t Ilength,
+                         uint8_t *Output);
+
+ErrorStatus CRYP_AES_GCM(uint8_t Mode, uint8_t InitVectors[16],
+                         uint8_t *Key, uint16_t Keysize,
+                         uint8_t *Input, uint32_t ILength,
+                         uint8_t *Header, uint32_t HLength,
+                         uint8_t *Output, uint8_t *AuthTAG);
+
+ErrorStatus CRYP_AES_CCM(uint8_t Mode, 
+                         uint8_t* Nonce, uint32_t NonceSize,
+                         uint8_t* Key, uint16_t Keysize,
+                         uint8_t* Input, uint32_t ILength,
+                         uint8_t* Header, uint32_t HLength, uint8_t *HBuffer,
+                         uint8_t* Output,
+                         uint8_t* AuthTAG, uint32_t TAGSize);
+
+/* High Level TDES functions **************************************************/
+ErrorStatus CRYP_TDES_ECB(uint8_t Mode,
+                           uint8_t Key[24], 
+                           uint8_t *Input, uint32_t Ilength,
+                           uint8_t *Output);
+
+ErrorStatus CRYP_TDES_CBC(uint8_t Mode,
+                          uint8_t Key[24],
+                          uint8_t InitVectors[8],
+                          uint8_t *Input, uint32_t Ilength,
+                          uint8_t *Output);
+
+/* High Level DES functions **************************************************/
+ErrorStatus CRYP_DES_ECB(uint8_t Mode,
+                         uint8_t Key[8],
+                         uint8_t *Input, uint32_t Ilength,
+                         uint8_t *Output);
+
+ErrorStatus CRYP_DES_CBC(uint8_t Mode,
+                         uint8_t Key[8],
+                         uint8_t InitVectors[8],
+                         uint8_t *Input,uint32_t Ilength,
+                         uint8_t *Output);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_CRYP_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+

底盘/底盘-old/底盘/Library/stm32f4xx_cryp_des.c

@@ -0,0 +1,304 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_cryp_des.c
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file provides high level functions to encrypt and decrypt an 
+  *          input message using DES in ECB/CBC modes.
+  *          It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
+  *          peripheral.
+  *
+@verbatim
+  
+ ===================================================================
+                  ##### How to use this driver #####
+ ===================================================================
+ [..] 
+   (#) Enable The CRYP controller clock using 
+       RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
+  
+   (#) Encrypt and decrypt using DES in ECB Mode using CRYP_DES_ECB() function.
+  
+   (#) Encrypt and decrypt using DES in CBC Mode using CRYP_DES_CBC() function.
+  
+@endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_cryp.h"
+
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CRYP 
+  * @brief CRYP driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define DESBUSY_TIMEOUT    ((uint32_t) 0x00010000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/** @defgroup CRYP_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup CRYP_Group8 High Level DES functions
+ *  @brief   High Level DES functions 
+ *
+@verbatim   
+ ===============================================================================
+                       ##### High Level DES functions #####
+ ===============================================================================
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Encrypt and decrypt using DES in ECB Mode
+  * @param  Mode: encryption or decryption Mode.
+  *           This parameter can be one of the following values:
+  *            @arg MODE_ENCRYPT: Encryption
+  *            @arg MODE_DECRYPT: Decryption
+  * @param  Key: Key used for DES algorithm.
+  * @param  Ilength: length of the Input buffer, must be a multiple of 8.
+  * @param  Input: pointer to the Input buffer.
+  * @param  Output: pointer to the returned buffer.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Operation done
+  *          - ERROR: Operation failed
+  */
+ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input, 
+                         uint32_t Ilength, uint8_t *Output)
+{
+  CRYP_InitTypeDef DES_CRYP_InitStructure;
+  CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure;
+  __IO uint32_t counter = 0;
+  uint32_t busystatus = 0;
+  ErrorStatus status = SUCCESS;
+  uint32_t keyaddr    = (uint32_t)Key;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+  uint32_t i = 0;
+
+  /* Crypto structures initialisation*/
+  CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure);
+
+  /* Crypto Init for Encryption process */
+  if( Mode == MODE_ENCRYPT ) /* DES encryption */
+  {
+     DES_CRYP_InitStructure.CRYP_AlgoDir  = CRYP_AlgoDir_Encrypt;
+  }
+  else/* if( Mode == MODE_DECRYPT )*/ /* DES decryption */
+  {      
+     DES_CRYP_InitStructure.CRYP_AlgoDir  = CRYP_AlgoDir_Decrypt;
+  }
+
+  DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_ECB;
+  DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
+  CRYP_Init(&DES_CRYP_InitStructure);
+
+  /* Key Initialisation */
+  DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4;
+  DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
+  CRYP_KeyInit(& DES_CRYP_KeyInitStructure);
+
+  /* Flush IN/OUT FIFO */
+  CRYP_FIFOFlush();
+
+  /* Enable Crypto processor */
+  CRYP_Cmd(ENABLE);
+
+  if(CRYP_GetCmdStatus() == DISABLE)
+  {
+    /* The CRYP peripheral clock is not enabled or the device doesn't embed 
+    the CRYP peripheral (please check the device sales type. */
+    status = ERROR;
+  }
+  else
+  {
+    for(i=0; ((i<Ilength) && (status != ERROR)); i+=8)
+    {
+      
+      /* Write the Input block in the Input FIFO */
+      CRYP_DataIn(*(uint32_t*)(inputaddr));
+      inputaddr+=4;
+      CRYP_DataIn(*(uint32_t*)(inputaddr));
+      inputaddr+=4;
+      
+      /* Wait until the complete message has been processed */
+      counter = 0;
+      do
+      {
+        busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
+        counter++;
+      }while ((counter != DESBUSY_TIMEOUT) && (busystatus != RESET));
+      
+      if (busystatus != RESET)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        
+        /* Read the Output block from the Output FIFO */
+        *(uint32_t*)(outputaddr) = CRYP_DataOut();
+        outputaddr+=4;
+        *(uint32_t*)(outputaddr) = CRYP_DataOut();
+        outputaddr+=4;
+      }
+    }
+    
+    /* Disable Crypto */
+    CRYP_Cmd(DISABLE);
+  }
+  return status; 
+}
+
+/**
+  * @brief  Encrypt and decrypt using DES in CBC Mode
+  * @param  Mode: encryption or decryption Mode.
+  *          This parameter can be one of the following values:
+  *            @arg MODE_ENCRYPT: Encryption
+  *            @arg MODE_DECRYPT: Decryption
+  * @param  Key: Key used for DES algorithm.
+  * @param  InitVectors: Initialisation Vectors used for DES algorithm.
+  * @param  Ilength: length of the Input buffer, must be a multiple of 8.
+  * @param  Input: pointer to the Input buffer.
+  * @param  Output: pointer to the returned buffer.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Operation done
+  *          - ERROR: Operation failed
+  */
+ErrorStatus CRYP_DES_CBC(uint8_t Mode, uint8_t Key[8], uint8_t InitVectors[8],
+                         uint8_t *Input, uint32_t Ilength, uint8_t *Output)
+{
+  CRYP_InitTypeDef DES_CRYP_InitStructure;
+  CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure;
+  CRYP_IVInitTypeDef DES_CRYP_IVInitStructure;
+  __IO uint32_t counter = 0;
+  uint32_t busystatus = 0;
+  ErrorStatus status = SUCCESS;
+  uint32_t keyaddr    = (uint32_t)Key;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+  uint32_t ivaddr     = (uint32_t)InitVectors;
+  uint32_t i = 0;
+
+  /* Crypto structures initialisation*/
+  CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure);
+
+  /* Crypto Init for Encryption process */
+  if(Mode == MODE_ENCRYPT) /* DES encryption */
+  {
+     DES_CRYP_InitStructure.CRYP_AlgoDir  = CRYP_AlgoDir_Encrypt;
+  }
+  else /*if(Mode == MODE_DECRYPT)*/ /* DES decryption */
+  {
+     DES_CRYP_InitStructure.CRYP_AlgoDir  = CRYP_AlgoDir_Decrypt;
+  }
+
+  DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_CBC;
+  DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
+  CRYP_Init(&DES_CRYP_InitStructure);
+
+  /* Key Initialisation */
+  DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4;
+  DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
+  CRYP_KeyInit(& DES_CRYP_KeyInitStructure);
+
+  /* Initialization Vectors */
+  DES_CRYP_IVInitStructure.CRYP_IV0Left = __REV(*(uint32_t*)(ivaddr));
+  ivaddr+=4;
+  DES_CRYP_IVInitStructure.CRYP_IV0Right= __REV(*(uint32_t*)(ivaddr));
+  CRYP_IVInit(&DES_CRYP_IVInitStructure);
+
+  /* Flush IN/OUT FIFO */
+  CRYP_FIFOFlush();
+  
+  /* Enable Crypto processor */
+  CRYP_Cmd(ENABLE);
+
+  if(CRYP_GetCmdStatus() == DISABLE)
+  {
+    /* The CRYP peripheral clock is not enabled or the device doesn't embed 
+    the CRYP peripheral (please check the device sales type. */
+    status = ERROR;
+  }
+  else
+  {
+    for(i=0; ((i<Ilength) && (status != ERROR)); i+=8)
+    {
+      /* Write the Input block in the Input FIFO */
+      CRYP_DataIn(*(uint32_t*)(inputaddr));
+      inputaddr+=4;
+      CRYP_DataIn(*(uint32_t*)(inputaddr));
+      inputaddr+=4;
+      
+      /* Wait until the complete message has been processed */
+      counter = 0;
+      do
+      {
+        busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
+        counter++;
+      }while ((counter != DESBUSY_TIMEOUT) && (busystatus != RESET));
+      
+      if (busystatus != RESET)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        /* Read the Output block from the Output FIFO */
+        *(uint32_t*)(outputaddr) = CRYP_DataOut();
+        outputaddr+=4;
+        *(uint32_t*)(outputaddr) = CRYP_DataOut();
+        outputaddr+=4;
+      }
+    }
+    
+    /* Disable Crypto */
+    CRYP_Cmd(DISABLE);
+  }
+  return status; 
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+

底盘/底盘-old/底盘/Library/stm32f4xx_cryp_tdes.c

@@ -0,0 +1,320 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_cryp_tdes.c
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file provides high level functions to encrypt and decrypt an 
+  *          input message using TDES in ECB/CBC modes .
+  *          It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
+  *          peripheral.
+  *
+@verbatim
+
+ ===============================================================================
+                           ##### How to use this driver #####
+ ===============================================================================
+ [..]
+   (#) Enable The CRYP controller clock using 
+       RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
+  
+   (#) Encrypt and decrypt using TDES in ECB Mode using CRYP_TDES_ECB() function.
+  
+   (#) Encrypt and decrypt using TDES in CBC Mode using CRYP_TDES_CBC() function.
+  
+@endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_cryp.h"
+
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CRYP 
+  * @brief CRYP driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define TDESBUSY_TIMEOUT    ((uint32_t) 0x00010000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/** @defgroup CRYP_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup CRYP_Group7 High Level TDES functions
+ *  @brief   High Level TDES functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### High Level TDES functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Encrypt and decrypt using TDES in ECB Mode
+  * @param  Mode: encryption or decryption Mode.
+  *           This parameter can be one of the following values:
+  *            @arg MODE_ENCRYPT: Encryption
+  *            @arg MODE_DECRYPT: Decryption
+  * @param  Key: Key used for TDES algorithm.
+  * @param  Ilength: length of the Input buffer, must be a multiple of 8.
+  * @param  Input: pointer to the Input buffer.
+  * @param  Output: pointer to the returned buffer.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Operation done
+  *          - ERROR: Operation failed
+  */
+ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input, 
+                          uint32_t Ilength, uint8_t *Output)
+{
+  CRYP_InitTypeDef TDES_CRYP_InitStructure;
+  CRYP_KeyInitTypeDef TDES_CRYP_KeyInitStructure;
+  __IO uint32_t counter = 0;
+  uint32_t busystatus = 0;
+  ErrorStatus status = SUCCESS;
+  uint32_t keyaddr    = (uint32_t)Key;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+  uint32_t i = 0;
+
+  /* Crypto structures initialisation*/
+  CRYP_KeyStructInit(&TDES_CRYP_KeyInitStructure);
+
+  /* Crypto Init for Encryption process */
+  if(Mode == MODE_ENCRYPT) /* TDES encryption */
+  {
+     TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
+  }
+  else /*if(Mode == MODE_DECRYPT)*/ /* TDES decryption */
+  {
+     TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
+  }
+
+  TDES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB;
+  TDES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
+  CRYP_Init(&TDES_CRYP_InitStructure);
+
+  /* Key Initialisation */
+  TDES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4;
+  TDES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4;
+  TDES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4;
+  TDES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4;
+  TDES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4;
+  TDES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
+  CRYP_KeyInit(& TDES_CRYP_KeyInitStructure);
+
+  /* Flush IN/OUT FIFO */
+  CRYP_FIFOFlush();
+
+  /* Enable Crypto processor */
+  CRYP_Cmd(ENABLE);
+
+  if(CRYP_GetCmdStatus() == DISABLE)
+  {
+    /* The CRYP peripheral clock is not enabled or the device doesn't embed 
+    the CRYP peripheral (please check the device sales type. */
+    status = ERROR;
+  }
+  else
+  {
+    for(i=0; ((i<Ilength) && (status != ERROR)); i+=8)
+    {
+      /* Write the Input block in the Input FIFO */
+      CRYP_DataIn(*(uint32_t*)(inputaddr));
+      inputaddr+=4;
+      CRYP_DataIn(*(uint32_t*)(inputaddr));
+      inputaddr+=4;
+      
+      /* Wait until the complete message has been processed */
+      counter = 0;
+      do
+      {
+        busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
+        counter++;
+      }while ((counter != TDESBUSY_TIMEOUT) && (busystatus != RESET));
+      
+      if (busystatus != RESET)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        
+        /* Read the Output block from the Output FIFO */
+        *(uint32_t*)(outputaddr) = CRYP_DataOut();
+        outputaddr+=4;
+        *(uint32_t*)(outputaddr) = CRYP_DataOut();
+        outputaddr+=4;
+      }
+    }
+    
+    /* Disable Crypto */
+    CRYP_Cmd(DISABLE);
+  }
+  return status; 
+}
+
+/**
+  * @brief  Encrypt and decrypt using TDES in CBC Mode
+  * @param  Mode: encryption or decryption Mode.
+  *           This parameter can be one of the following values:
+  *            @arg MODE_ENCRYPT: Encryption
+  *            @arg MODE_DECRYPT: Decryption
+  * @param  Key: Key used for TDES algorithm.
+  * @param  InitVectors: Initialisation Vectors used for TDES algorithm.
+  * @param  Input: pointer to the Input buffer.
+  * @param  Ilength: length of the Input buffer, must be a multiple of 8.
+  * @param  Output: pointer to the returned buffer.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Operation done
+  *          - ERROR: Operation failed
+  */
+ErrorStatus CRYP_TDES_CBC(uint8_t Mode, uint8_t Key[24], uint8_t InitVectors[8],
+                          uint8_t *Input, uint32_t Ilength, uint8_t *Output)
+{
+  CRYP_InitTypeDef TDES_CRYP_InitStructure;
+  CRYP_KeyInitTypeDef TDES_CRYP_KeyInitStructure;
+  CRYP_IVInitTypeDef TDES_CRYP_IVInitStructure;
+  __IO uint32_t counter = 0;
+  uint32_t busystatus = 0;
+  ErrorStatus status = SUCCESS;
+  uint32_t keyaddr    = (uint32_t)Key;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+  uint32_t ivaddr     = (uint32_t)InitVectors;
+  uint32_t i = 0;
+
+  /* Crypto structures initialisation*/
+  CRYP_KeyStructInit(&TDES_CRYP_KeyInitStructure);
+
+  /* Crypto Init for Encryption process */
+  if(Mode == MODE_ENCRYPT) /* TDES encryption */
+  {
+    TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
+  }
+  else
+  {
+    TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
+  }
+  TDES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_CBC;
+  TDES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
+
+  CRYP_Init(&TDES_CRYP_InitStructure);
+
+  /* Key Initialisation */
+  TDES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4;
+  TDES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4;
+  TDES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4;
+  TDES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4;
+  TDES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4;
+  TDES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
+  CRYP_KeyInit(& TDES_CRYP_KeyInitStructure);
+  
+  /* Initialization Vectors */
+  TDES_CRYP_IVInitStructure.CRYP_IV0Left = __REV(*(uint32_t*)(ivaddr));
+  ivaddr+=4;
+  TDES_CRYP_IVInitStructure.CRYP_IV0Right= __REV(*(uint32_t*)(ivaddr));
+  CRYP_IVInit(&TDES_CRYP_IVInitStructure);
+  
+  /* Flush IN/OUT FIFO */
+  CRYP_FIFOFlush();
+  
+  /* Enable Crypto processor */
+  CRYP_Cmd(ENABLE);
+  
+  if(CRYP_GetCmdStatus() == DISABLE)
+  {
+    /* The CRYP peripheral clock is not enabled or the device doesn't embed 
+    the CRYP peripheral (please check the device sales type. */
+    status = ERROR;
+  }
+  else
+  {
+    for(i=0; ((i<Ilength) && (status != ERROR)); i+=8)
+    {
+      /* Write the Input block in the Input FIFO */
+      CRYP_DataIn(*(uint32_t*)(inputaddr));
+      inputaddr+=4;
+      CRYP_DataIn(*(uint32_t*)(inputaddr));
+      inputaddr+=4;
+      
+      /* Wait until the complete message has been processed */
+      counter = 0;
+      do
+      {
+        busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
+        counter++;
+      }while ((counter != TDESBUSY_TIMEOUT) && (busystatus != RESET));
+      
+      if (busystatus != RESET)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        
+        /* Read the Output block from the Output FIFO */
+        *(uint32_t*)(outputaddr) = CRYP_DataOut();
+        outputaddr+=4;
+        *(uint32_t*)(outputaddr) = CRYP_DataOut();
+        outputaddr+=4;
+      }
+    }
+    
+    /* Disable Crypto */
+    CRYP_Cmd(DISABLE);
+  }
+  return status; 
+}
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+

底盘/底盘-old/底盘/Library/stm32f4xx_dac.c

@@ -0,0 +1,706 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_dac.c
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+   * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Digital-to-Analog Converter (DAC) peripheral: 
+  *           + DAC channels configuration: trigger, output buffer, data format
+  *           + DMA management      
+  *           + Interrupts and flags management
+  *
+ @verbatim      
+ ===============================================================================
+                      ##### DAC Peripheral features #####
+ ===============================================================================
+    [..]        
+      *** DAC Channels ***
+      ====================  
+    [..]  
+    The device integrates two 12-bit Digital Analog Converters that can 
+    be used independently or simultaneously (dual mode):
+      (#) DAC channel1 with DAC_OUT1 (PA4) as output
+      (#) DAC channel2 with DAC_OUT2 (PA5) as output
+  
+      *** DAC Triggers ***
+      ====================
+    [..]
+    Digital to Analog conversion can be non-triggered using DAC_Trigger_None
+    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register 
+    using DAC_SetChannel1Data() / DAC_SetChannel2Data() functions.
+    [..] 
+    Digital to Analog conversion can be triggered by:
+      (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
+          The used pin (GPIOx_Pin9) must be configured in input mode.
+  
+      (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 
+          (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
+          The timer TRGO event should be selected using TIM_SelectOutputTrigger()
+  
+      (#) Software using DAC_Trigger_Software
+  
+      *** DAC Buffer mode feature ***
+      =============================== 
+      [..] 
+      Each DAC channel integrates an output buffer that can be used to 
+      reduce the output impedance, and to drive external loads directly
+      without having to add an external operational amplifier.
+      To enable, the output buffer use  
+      DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+      [..]           
+      (@) Refer to the device datasheet for more details about output 
+          impedance value with and without output buffer.
+            
+       *** DAC wave generation feature ***
+       =================================== 
+       [..]     
+       Both DAC channels can be used to generate
+         (#) Noise wave using DAC_WaveGeneration_Noise
+         (#) Triangle wave using DAC_WaveGeneration_Triangle
+          
+          -@-  Wave generation can be disabled using DAC_WaveGeneration_None
+  
+       *** DAC data format ***
+       =======================
+       [..]   
+       The DAC data format can be:
+         (#) 8-bit right alignment using DAC_Align_8b_R
+         (#) 12-bit left alignment using DAC_Align_12b_L
+         (#) 12-bit right alignment using DAC_Align_12b_R
+  
+       *** DAC data value to voltage correspondence ***  
+       ================================================ 
+       [..] 
+       The analog output voltage on each DAC channel pin is determined
+       by the following equation: 
+       DAC_OUTx = VREF+ * DOR / 4095
+       with  DOR is the Data Output Register
+          VEF+ is the input voltage reference (refer to the device datasheet)
+        e.g. To set DAC_OUT1 to 0.7V, use
+          DAC_SetChannel1Data(DAC_Align_12b_R, 868);
+          Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
+  
+       *** DMA requests  ***
+       =====================
+       [..]    
+       A DMA1 request can be generated when an external trigger (but not
+       a software trigger) occurs if DMA1 requests are enabled using
+       DAC_DMACmd()
+       [..]
+       DMA1 requests are mapped as following:
+         (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be 
+             already configured
+         (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be 
+             already configured
+  
+      
+                      ##### How to use this driver #####
+ ===============================================================================
+    [..]          
+      (+) DAC APB clock must be enabled to get write access to DAC
+          registers using
+          RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
+      (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
+      (+) Configure the DAC channel using DAC_Init() function
+      (+) Enable the DAC channel using DAC_Cmd() function
+   
+ @endverbatim    
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_dac.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DAC 
+  * @brief DAC driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* CR register Mask */
+#define CR_CLEAR_MASK              ((uint32_t)0x00000FFE)
+
+/* DAC Dual Channels SWTRIG masks */
+#define DUAL_SWTRIG_SET            ((uint32_t)0x00000003)
+#define DUAL_SWTRIG_RESET          ((uint32_t)0xFFFFFFFC)
+
+/* DHR registers offsets */
+#define DHR12R1_OFFSET             ((uint32_t)0x00000008)
+#define DHR12R2_OFFSET             ((uint32_t)0x00000014)
+#define DHR12RD_OFFSET             ((uint32_t)0x00000020)
+
+/* DOR register offset */
+#define DOR_OFFSET                 ((uint32_t)0x0000002C)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DAC_Private_Functions
+  * @{
+  */
+
+/** @defgroup DAC_Group1 DAC channels configuration
+ *  @brief   DAC channels configuration: trigger, output buffer, data format 
+ *
+@verbatim   
+ ===============================================================================
+   ##### DAC channels configuration: trigger, output buffer, data format #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the DAC peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void DAC_DeInit(void)
+{
+  /* Enable DAC reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
+  /* Release DAC from reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
+}
+
+/**
+  * @brief  Initializes the DAC peripheral according to the specified parameters
+  *         in the DAC_InitStruct.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains
+  *         the configuration information for the  specified DAC channel.
+  * @retval None
+  */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
+
+  /* Check the DAC parameters */
+  assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
+  assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
+  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
+
+/*---------------------------- DAC CR Configuration --------------------------*/
+  /* Get the DAC CR value */
+  tmpreg1 = DAC->CR;
+  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+  tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
+  /* Configure for the selected DAC channel: buffer output, trigger, 
+     wave generation, mask/amplitude for wave generation */
+  /* Set TSELx and TENx bits according to DAC_Trigger value */
+  /* Set WAVEx bits according to DAC_WaveGeneration value */
+  /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ 
+  /* Set BOFFx bit according to DAC_OutputBuffer value */   
+  tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
+             DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \
+             DAC_InitStruct->DAC_OutputBuffer);
+  /* Calculate CR register value depending on DAC_Channel */
+  tmpreg1 |= tmpreg2 << DAC_Channel;
+  /* Write to DAC CR */
+  DAC->CR = tmpreg1;
+}
+
+/**
+  * @brief  Fills each DAC_InitStruct member with its default value.
+  * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
+{
+/*--------------- Reset DAC init structure parameters values -----------------*/
+  /* Initialize the DAC_Trigger member */
+  DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
+  /* Initialize the DAC_WaveGeneration member */
+  DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
+  /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
+  DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
+  /* Initialize the DAC_OutputBuffer member */
+  DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+}
+
+/**
+  * @brief  Enables or disables the specified DAC channel.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the DAC channel. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When the DAC channel is enabled the trigger source can no more be modified.
+  * @retval None
+  */
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel */
+    DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC channel */
+    DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel software trigger.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the selected DAC channel software trigger.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for the selected DAC channel */
+    DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
+  }
+  else
+  {
+    /* Disable software trigger for the selected DAC channel */
+    DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
+  }
+}
+
+/**
+  * @brief  Enables or disables simultaneously the two DAC channels software triggers.
+  * @param  NewState: new state of the DAC channels software triggers.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for both DAC channels */
+    DAC->SWTRIGR |= DUAL_SWTRIG_SET;
+  }
+  else
+  {
+    /* Disable software trigger for both DAC channels */
+    DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel wave generation.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_Wave: specifies the wave type to enable or disable.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Wave_Noise: noise wave generation
+  *            @arg DAC_Wave_Triangle: triangle wave generation
+  * @param  NewState: new state of the selected DAC channel wave generation.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_WAVE(DAC_Wave)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected wave generation for the selected DAC channel */
+    DAC->CR |= DAC_Wave << DAC_Channel;
+  }
+  else
+  {
+    /* Disable the selected wave generation for the selected DAC channel */
+    DAC->CR &= ~(DAC_Wave << DAC_Channel);
+  }
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel1.
+  * @param  DAC_Align: Specifies the data alignment for DAC channel1.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data: Data to be loaded in the selected data holding register.
+  * @retval None
+  */
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
+{  
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data));
+  
+  tmp = (uint32_t)DAC_BASE; 
+  tmp += DHR12R1_OFFSET + DAC_Align;
+
+  /* Set the DAC channel1 selected data holding register */
+  *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel2.
+  * @param  DAC_Align: Specifies the data alignment for DAC channel2.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data: Data to be loaded in the selected data holding register.
+  * @retval None
+  */
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data));
+  
+  tmp = (uint32_t)DAC_BASE;
+  tmp += DHR12R2_OFFSET + DAC_Align;
+
+  /* Set the DAC channel2 selected data holding register */
+  *(__IO uint32_t *)tmp = Data;
+}
+
+/**
+  * @brief  Set the specified data holding register value for dual channel DAC.
+  * @param  DAC_Align: Specifies the data alignment for dual channel DAC.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data2: Data for DAC Channel2 to be loaded in the selected data holding register.
+  * @param  Data1: Data for DAC Channel1 to be loaded in the selected data  holding register.
+  * @note   In dual mode, a unique register access is required to write in both
+  *          DAC channels at the same time.
+  * @retval None
+  */
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
+{
+  uint32_t data = 0, tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data1));
+  assert_param(IS_DAC_DATA(Data2));
+  
+  /* Calculate and set dual DAC data holding register value */
+  if (DAC_Align == DAC_Align_8b_R)
+  {
+    data = ((uint32_t)Data2 << 8) | Data1; 
+  }
+  else
+  {
+    data = ((uint32_t)Data2 << 16) | Data1;
+  }
+  
+  tmp = (uint32_t)DAC_BASE;
+  tmp += DHR12RD_OFFSET + DAC_Align;
+
+  /* Set the dual DAC selected data holding register */
+  *(__IO uint32_t *)tmp = data;
+}
+
+/**
+  * @brief  Returns the last data output value of the selected DAC channel.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @retval The selected DAC channel data output value.
+  */
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  
+  tmp = (uint32_t) DAC_BASE ;
+  tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
+  
+  /* Returns the DAC channel data output register value */
+  return (uint16_t) (*(__IO uint32_t*) tmp);
+}
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Group2 DMA management functions
+ *  @brief   DMA management functions
+ *
+@verbatim   
+ ===============================================================================
+                       ##### DMA management functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified DAC channel DMA request.
+  * @note   When enabled DMA1 is generated when an external trigger (EXTI Line9,
+  *         TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8  but not a software trigger) occurs.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the selected DAC channel DMA request.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be
+  *          already configured.
+  * @note   The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be
+  *          already configured.    
+  * @retval None
+  */
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel DMA request */
+    DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC channel DMA request */
+    DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Group3 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+             ##### Interrupts and flags management functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified DAC interrupts.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. 
+  *          This parameter can be the following values:
+  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).
+  * @param  NewState: new state of the specified DAC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */ 
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)  
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_DAC_IT(DAC_IT)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC interrupts */
+    DAC->CR |=  (DAC_IT << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC interrupts */
+    DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
+  }
+}
+
+/**
+  * @brief  Checks whether the specified DAC flag is set or not.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_FLAG: specifies the flag to check. 
+  *          This parameter can be only of the following value:
+  *            @arg DAC_FLAG_DMAUDR: DMA underrun flag
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).
+  * @retval The new state of DAC_FLAG (SET or RESET).
+  */
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+  /* Check the status of the specified DAC flag */
+  if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
+  {
+    /* DAC_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DAC_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DAC_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DAC channel's pending flags.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_FLAG: specifies the flag to clear. 
+  *          This parameter can be of the following value:
+  *            @arg DAC_FLAG_DMAUDR: DMA underrun flag 
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).                           
+  * @retval None
+  */
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+  /* Clear the selected DAC flags */
+  DAC->SR = (DAC_FLAG << DAC_Channel);
+}
+
+/**
+  * @brief  Checks whether the specified DAC interrupt has occurred or not.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt source to check. 
+  *          This parameter can be the following values:
+  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).
+  * @retval The new state of DAC_IT (SET or RESET).
+  */
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_IT(DAC_IT));
+
+  /* Get the DAC_IT enable bit status */
+  enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
+  
+  /* Check the status of the specified DAC interrupt */
+  if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
+  {
+    /* DAC_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DAC_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DAC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DAC channel's interrupt pending bits.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt pending bit to clear.
+  *          This parameter can be the following values:
+  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask                         
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).                           
+  * @retval None
+  */
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_IT(DAC_IT)); 
+
+  /* Clear the selected DAC interrupt pending bits */
+  DAC->SR = (DAC_IT << DAC_Channel);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

底盘/底盘-old/底盘/Library/stm32f4xx_dac.h

@@ -0,0 +1,296 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_dac.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the DAC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_DAC_H
+#define __STM32F4xx_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DAC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  DAC Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t DAC_Trigger;                      /*!< Specifies the external trigger for the selected DAC channel.
+                                                  This parameter can be a value of @ref DAC_trigger_selection */
+
+  uint32_t DAC_WaveGeneration;               /*!< Specifies whether DAC channel noise waves or triangle waves
+                                                  are generated, or whether no wave is generated.
+                                                  This parameter can be a value of @ref DAC_wave_generation */
+
+  uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
+                                                  the maximum amplitude triangle generation for the DAC channel. 
+                                                  This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+  uint32_t DAC_OutputBuffer;                 /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+                                                  This parameter can be a value of @ref DAC_output_buffer */
+}DAC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup DAC_trigger_selection 
+  * @{
+  */
+
+#define DAC_Trigger_None                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
+                                                                       has been loaded, and not by external trigger */
+#define DAC_Trigger_T2_TRGO                ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T4_TRGO                ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T5_TRGO                ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T6_TRGO                ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T7_TRGO                ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T8_TRGO                ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */                                                                       
+
+#define DAC_Trigger_Ext_IT9                ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Software               ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
+                                 ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
+                                 ((TRIGGER) == DAC_Trigger_Software))
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation 
+  * @{
+  */
+
+#define DAC_WaveGeneration_None            ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise           ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle        ((uint32_t)0x00000080)
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
+                                    ((WAVE) == DAC_WaveGeneration_Noise) || \
+                                    ((WAVE) == DAC_WaveGeneration_Triangle))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_lfsrunmask_triangleamplitude
+  * @{
+  */
+
+#define DAC_LFSRUnmask_Bit0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUnmask_Bits1_0             ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits2_0             ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits3_0             ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits4_0             ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits5_0             ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits6_0             ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits7_0             ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits8_0             ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits9_0             ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits10_0            ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits11_0            ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TriangleAmplitude_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TriangleAmplitude_3            ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TriangleAmplitude_7            ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TriangleAmplitude_15           ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TriangleAmplitude_31           ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TriangleAmplitude_63           ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TriangleAmplitude_127          ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TriangleAmplitude_255          ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TriangleAmplitude_511          ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TriangleAmplitude_1023         ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TriangleAmplitude_2047         ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TriangleAmplitude_4095         ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_1) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_3) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_7) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_15) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_31) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_63) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_127) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_255) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_511) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_1023) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_2047) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_4095))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_output_buffer 
+  * @{
+  */
+
+#define DAC_OutputBuffer_Enable            ((uint32_t)0x00000000)
+#define DAC_OutputBuffer_Disable           ((uint32_t)0x00000002)
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
+                                           ((STATE) == DAC_OutputBuffer_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Channel_selection 
+  * @{
+  */
+
+#define DAC_Channel_1                      ((uint32_t)0x00000000)
+#define DAC_Channel_2                      ((uint32_t)0x00000010)
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
+                                 ((CHANNEL) == DAC_Channel_2))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data_alignement 
+  * @{
+  */
+
+#define DAC_Align_12b_R                    ((uint32_t)0x00000000)
+#define DAC_Align_12b_L                    ((uint32_t)0x00000004)
+#define DAC_Align_8b_R                     ((uint32_t)0x00000008)
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
+                             ((ALIGN) == DAC_Align_12b_L) || \
+                             ((ALIGN) == DAC_Align_8b_R))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation 
+  * @{
+  */
+
+#define DAC_Wave_Noise                     ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle                  ((uint32_t)0x00000080)
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
+                           ((WAVE) == DAC_Wave_Triangle))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data 
+  * @{
+  */
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) 
+/**
+  * @}
+  */
+  
+/** @defgroup DAC_interrupts_definition 
+  * @{
+  */   
+#define DAC_IT_DMAUDR                      ((uint32_t)0x00002000)  
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup DAC_flags_definition 
+  * @{
+  */ 
+  
+#define DAC_FLAG_DMAUDR                    ((uint32_t)0x00002000)  
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))  
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/  
+
+/*  Function used to set the DAC configuration to the default reset state *****/  
+void DAC_DeInit(void);
+
+/*  DAC channels configuration: trigger, output buffer, data format functions */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
+
+/* DMA management functions ***************************************************/
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_DAC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

底盘/底盘-old/底盘/Library/stm32f4xx_dbgmcu.c

@@ -0,0 +1,172 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_dbgmcu.c
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file provides all the DBGMCU firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_dbgmcu.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DBGMCU 
+  * @brief DBGMCU driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  Returns the device revision identifier.
+  * @param  None
+  * @retval Device revision identifier
+  */
+uint32_t DBGMCU_GetREVID(void)
+{
+   return(DBGMCU->IDCODE >> 16);
+}
+
+/**
+  * @brief  Returns the device identifier.
+  * @param  None
+  * @retval Device identifier
+  */
+uint32_t DBGMCU_GetDEVID(void)
+{
+   return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
+}
+
+/**
+  * @brief  Configures low power mode behavior when the MCU is in Debug mode.
+  * @param  DBGMCU_Periph: specifies the low power mode.
+  *   This parameter can be any combination of the following values:
+  *     @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode              
+  *     @arg DBGMCU_STOP: Keep debugger connection during STOP mode               
+  *     @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode        
+  * @param  NewState: new state of the specified low power mode in Debug mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    DBGMCU->CR |= DBGMCU_Periph;
+  }
+  else
+  {
+    DBGMCU->CR &= ~DBGMCU_Periph;
+  }
+}
+
+/**
+  * @brief  Configures APB1 peripheral behavior when the MCU is in Debug mode.
+  * @param  DBGMCU_Periph: specifies the APB1 peripheral.
+  *   This parameter can be any combination of the following values:        
+  *     @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted  
+  *     @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted  
+  *     @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted 
+  *     @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped when Core is halted.                                                                                
+  *     @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
+  *     @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted        
+  *     @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
+  *     @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
+  *     @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted
+  *     @arg DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted           
+  *     @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted        
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    DBGMCU->APB1FZ |= DBGMCU_Periph;
+  }
+  else
+  {
+    DBGMCU->APB1FZ &= ~DBGMCU_Periph;
+  }
+}
+
+/**
+  * @brief  Configures APB2 peripheral behavior when the MCU is in Debug mode.
+  * @param  DBGMCU_Periph: specifies the APB2 peripheral.
+  *   This parameter can be any combination of the following values:       
+  *     @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted                
+  *     @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted   
+  *     @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted   
+  *     @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted                                                                                  
+  * @param  NewState: new state of the specified peripheral in Debug mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    DBGMCU->APB2FZ |= DBGMCU_Periph;
+  }
+  else
+  {
+    DBGMCU->APB2FZ &= ~DBGMCU_Periph;
+  }
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+

底盘/底盘-old/底盘/Library/stm32f4xx_dbgmcu.h

@@ -0,0 +1,101 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_dbgmcu.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the DBGMCU firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_DBGMCU_H
+#define __STM32F4xx_DBGMCU_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DBGMCU
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Exported_Constants
+  * @{
+  */ 
+#define DBGMCU_SLEEP                 ((uint32_t)0x00000001)
+#define DBGMCU_STOP                  ((uint32_t)0x00000002)
+#define DBGMCU_STANDBY               ((uint32_t)0x00000004)
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM2_STOP             ((uint32_t)0x00000001)
+#define DBGMCU_TIM3_STOP             ((uint32_t)0x00000002)
+#define DBGMCU_TIM4_STOP             ((uint32_t)0x00000004)
+#define DBGMCU_TIM5_STOP             ((uint32_t)0x00000008)
+#define DBGMCU_TIM6_STOP             ((uint32_t)0x00000010)
+#define DBGMCU_TIM7_STOP             ((uint32_t)0x00000020)
+#define DBGMCU_TIM12_STOP            ((uint32_t)0x00000040)
+#define DBGMCU_TIM13_STOP            ((uint32_t)0x00000080)
+#define DBGMCU_TIM14_STOP            ((uint32_t)0x00000100)
+#define DBGMCU_RTC_STOP              ((uint32_t)0x00000400)
+#define DBGMCU_WWDG_STOP             ((uint32_t)0x00000800)
+#define DBGMCU_IWDG_STOP             ((uint32_t)0x00001000)
+#define DBGMCU_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)
+#define DBGMCU_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00400000)
+#define DBGMCU_I2C3_SMBUS_TIMEOUT    ((uint32_t)0x00800000)
+#define DBGMCU_CAN1_STOP             ((uint32_t)0x02000000)
+#define DBGMCU_CAN2_STOP             ((uint32_t)0x04000000)
+#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM1_STOP             ((uint32_t)0x00000001)
+#define DBGMCU_TIM8_STOP             ((uint32_t)0x00000002)
+#define DBGMCU_TIM9_STOP             ((uint32_t)0x00010000)
+#define DBGMCU_TIM10_STOP            ((uint32_t)0x00020000)
+#define DBGMCU_TIM11_STOP            ((uint32_t)0x00040000)
+#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00))
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+uint32_t DBGMCU_GetREVID(void);
+uint32_t DBGMCU_GetDEVID(void);
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_DBGMCU_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+

底盘/底盘-old/底盘/Library/stm32f4xx_dcmi.c

@@ -0,0 +1,530 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_dcmi.c
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the DCMI peripheral:           
+  *           + Initialization and Configuration
+  *           + Image capture functions  
+  *           + Interrupts and flags management
+  *
+ @verbatim          
+ ===============================================================================
+                        ##### How to use this driver #####
+ ===============================================================================  
+    [..]       
+      The sequence below describes how to use this driver to capture image
+      from a camera module connected to the DCMI Interface.
+      This sequence does not take into account the configuration of the  
+      camera module, which should be made before to configure and enable
+      the DCMI to capture images.
+             
+      (#) Enable the clock for the DCMI and associated GPIOs using the following 
+          functions:
+          RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE);
+          RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+  
+      (#) DCMI pins configuration 
+        (++) Connect the involved DCMI pins to AF13 using the following function 
+            GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI); 
+        (++) Configure these DCMI pins in alternate function mode by calling 
+            the function GPIO_Init();
+      
+      (#) Declare a DCMI_InitTypeDef structure, for example:
+          DCMI_InitTypeDef  DCMI_InitStructure;
+          and fill the DCMI_InitStructure variable with the allowed values
+          of the structure member.
+    
+      (#) Initialize the DCMI interface by calling the function
+          DCMI_Init(&DCMI_InitStructure); 
+    
+      (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR
+          register to the destination memory buffer.
+    
+      (#) Enable DCMI interface using the function
+          DCMI_Cmd(ENABLE);
+                   
+      (#) Start the image capture using the function
+          DCMI_CaptureCmd(ENABLE);
+                   
+      (#) At this stage the DCMI interface waits for the first start of frame,
+          then a DMA request is generated continuously/once (depending on the
+          mode used, Continuous/Snapshot) to transfer the received data into
+          the destination memory. 
+     
+      -@-  If you need to capture only a rectangular window from the received
+           image, you have to use the DCMI_CROPConfig() function to configure 
+           the coordinates and size of the window to be captured, then enable 
+           the Crop feature using DCMI_CROPCmd(ENABLE);  
+           In this case, the Crop configuration should be made before to enable
+           and start the DCMI interface. 
+
+ @endverbatim     
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_dcmi.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DCMI 
+  * @brief DCMI driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DCMI_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup DCMI_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+              ##### Initialization and Configuration functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the DCMI registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void DCMI_DeInit(void)
+{
+  DCMI->CR = 0x0;
+  DCMI->IER = 0x0;
+  DCMI->ICR = 0x1F;
+  DCMI->ESCR = 0x0;
+  DCMI->ESUR = 0x0;
+  DCMI->CWSTRTR = 0x0;
+  DCMI->CWSIZER = 0x0;
+}
+
+/**
+  * @brief  Initializes the DCMI according to the specified parameters in the DCMI_InitStruct.
+  * @param  DCMI_InitStruct: pointer to a DCMI_InitTypeDef structure that contains 
+  *         the configuration information for the DCMI.
+  * @retval None
+  */
+void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct)
+{
+  uint32_t temp = 0x0;
+  
+  /* Check the parameters */
+  assert_param(IS_DCMI_CAPTURE_MODE(DCMI_InitStruct->DCMI_CaptureMode));
+  assert_param(IS_DCMI_SYNCHRO(DCMI_InitStruct->DCMI_SynchroMode));
+  assert_param(IS_DCMI_PCKPOLARITY(DCMI_InitStruct->DCMI_PCKPolarity));
+  assert_param(IS_DCMI_VSPOLARITY(DCMI_InitStruct->DCMI_VSPolarity));
+  assert_param(IS_DCMI_HSPOLARITY(DCMI_InitStruct->DCMI_HSPolarity));
+  assert_param(IS_DCMI_CAPTURE_RATE(DCMI_InitStruct->DCMI_CaptureRate));
+  assert_param(IS_DCMI_EXTENDED_DATA(DCMI_InitStruct->DCMI_ExtendedDataMode));
+
+  /* The DCMI configuration registers should be programmed correctly before 
+  enabling the CR_ENABLE Bit and the CR_CAPTURE Bit */
+  DCMI->CR &= ~(DCMI_CR_ENABLE | DCMI_CR_CAPTURE);
+   
+  /* Reset the old DCMI configuration */
+  temp = DCMI->CR;
+  
+  temp &= ~((uint32_t)DCMI_CR_CM     | DCMI_CR_ESS   | DCMI_CR_PCKPOL |
+                      DCMI_CR_HSPOL  | DCMI_CR_VSPOL | DCMI_CR_FCRC_0 | 
+                      DCMI_CR_FCRC_1 | DCMI_CR_EDM_0 | DCMI_CR_EDM_1); 
+                  
+  /* Sets the new configuration of the DCMI peripheral */
+  temp |= ((uint32_t)DCMI_InitStruct->DCMI_CaptureMode |
+                     DCMI_InitStruct->DCMI_SynchroMode |
+                     DCMI_InitStruct->DCMI_PCKPolarity |
+                     DCMI_InitStruct->DCMI_VSPolarity |
+                     DCMI_InitStruct->DCMI_HSPolarity |
+                     DCMI_InitStruct->DCMI_CaptureRate |
+                     DCMI_InitStruct->DCMI_ExtendedDataMode);
+
+  DCMI->CR = temp;                              
+}
+
+/**
+  * @brief  Fills each DCMI_InitStruct member with its default value.
+  * @param  DCMI_InitStruct : pointer to a DCMI_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct)
+{
+  /* Set the default configuration */
+  DCMI_InitStruct->DCMI_CaptureMode = DCMI_CaptureMode_Continuous;
+  DCMI_InitStruct->DCMI_SynchroMode = DCMI_SynchroMode_Hardware;
+  DCMI_InitStruct->DCMI_PCKPolarity = DCMI_PCKPolarity_Falling;
+  DCMI_InitStruct->DCMI_VSPolarity = DCMI_VSPolarity_Low;
+  DCMI_InitStruct->DCMI_HSPolarity = DCMI_HSPolarity_Low;
+  DCMI_InitStruct->DCMI_CaptureRate = DCMI_CaptureRate_All_Frame;
+  DCMI_InitStruct->DCMI_ExtendedDataMode = DCMI_ExtendedDataMode_8b;
+}
+
+/**
+  * @brief  Initializes the DCMI peripheral CROP mode according to the specified
+  *         parameters in the DCMI_CROPInitStruct.
+  * @note   This function should be called before to enable and start the DCMI interface.   
+  * @param  DCMI_CROPInitStruct:  pointer to a DCMI_CROPInitTypeDef structure that 
+  *         contains the configuration information for the DCMI peripheral CROP mode.
+  * @retval None
+  */
+void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct)
+{  
+  /* Sets the CROP window coordinates */
+  DCMI->CWSTRTR = (uint32_t)((uint32_t)DCMI_CROPInitStruct->DCMI_HorizontalOffsetCount |
+                  ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalStartLine << 16));
+
+  /* Sets the CROP window size */
+  DCMI->CWSIZER = (uint32_t)(DCMI_CROPInitStruct->DCMI_CaptureCount |
+                  ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalLineCount << 16));
+}
+
+/**
+  * @brief  Enables or disables the DCMI Crop feature.
+  * @note   This function should be called before to enable and start the DCMI interface.
+  * @param  NewState: new state of the DCMI Crop feature. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DCMI_CROPCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+    
+  if (NewState != DISABLE)
+  {
+    /* Enable the DCMI Crop feature */
+    DCMI->CR |= (uint32_t)DCMI_CR_CROP;
+  }
+  else
+  {
+    /* Disable the DCMI Crop feature */
+    DCMI->CR &= ~(uint32_t)DCMI_CR_CROP;
+  }
+}
+
+/**
+  * @brief  Sets the embedded synchronization codes
+  * @param  DCMI_CodesInitTypeDef: pointer to a DCMI_CodesInitTypeDef structure that
+  *         contains the embedded synchronization codes for the DCMI peripheral.
+  * @retval None
+  */
+void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct)
+{
+  DCMI->ESCR = (uint32_t)(DCMI_CodesInitStruct->DCMI_FrameStartCode |
+                          ((uint32_t)DCMI_CodesInitStruct->DCMI_LineStartCode << 8)|
+                          ((uint32_t)DCMI_CodesInitStruct->DCMI_LineEndCode << 16)|
+                          ((uint32_t)DCMI_CodesInitStruct->DCMI_FrameEndCode << 24));
+}
+
+/**
+  * @brief  Enables or disables the DCMI JPEG format.
+  * @note   The Crop and Embedded Synchronization features cannot be used in this mode.  
+  * @param  NewState: new state of the DCMI JPEG format. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DCMI_JPEGCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+ 
+  if (NewState != DISABLE)
+  {
+    /* Enable the DCMI JPEG format */
+    DCMI->CR |= (uint32_t)DCMI_CR_JPEG;
+  }
+  else
+  {
+    /* Disable the DCMI JPEG format */
+    DCMI->CR &= ~(uint32_t)DCMI_CR_JPEG;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Group2 Image capture functions
+ *  @brief   Image capture functions
+ *
+@verbatim   
+ ===============================================================================
+                    ##### Image capture functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Enables or disables the DCMI interface.
+  * @param  NewState: new state of the DCMI interface. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DCMI_Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the DCMI by setting ENABLE bit */
+    DCMI->CR |= (uint32_t)DCMI_CR_ENABLE;
+  }
+  else
+  {
+    /* Disable the DCMI by clearing ENABLE bit */
+    DCMI->CR &= ~(uint32_t)DCMI_CR_ENABLE;
+  }
+}
+
+/**
+  * @brief  Enables or disables the DCMI Capture.
+  * @param  NewState: new state of the DCMI capture. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DCMI_CaptureCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+    
+  if (NewState != DISABLE)
+  {
+    /* Enable the DCMI Capture */
+    DCMI->CR |= (uint32_t)DCMI_CR_CAPTURE;
+  }
+  else
+  {
+    /* Disable the DCMI Capture */
+    DCMI->CR &= ~(uint32_t)DCMI_CR_CAPTURE;
+  }
+}
+
+/**
+  * @brief  Reads the data stored in the DR register.
+  * @param  None 
+  * @retval Data register value
+  */
+uint32_t DCMI_ReadData(void)
+{
+  return DCMI->DR;
+}
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Group3 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+             ##### Interrupts and flags management functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the DCMI interface interrupts.
+  * @param  DCMI_IT: specifies the DCMI interrupt sources to be enabled or disabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+  *            @arg DCMI_IT_OVF: Overflow interrupt mask
+  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+  *            @arg DCMI_IT_LINE: Line interrupt mask
+  * @param  NewState: new state of the specified DCMI interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DCMI_CONFIG_IT(DCMI_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the Interrupt sources */
+    DCMI->IER |= DCMI_IT;
+  }
+  else
+  {
+    /* Disable the Interrupt sources */
+    DCMI->IER &= (uint16_t)(~DCMI_IT);
+  }  
+}
+
+/**
+  * @brief  Checks whether the  DCMI interface flag is set or not.
+  * @param  DCMI_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask
+  *            @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask
+  *            @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask
+  *            @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask
+  *            @arg DCMI_FLAG_LINERI: Line Raw flag mask
+  *            @arg DCMI_FLAG_FRAMEMI: Frame capture complete Masked flag mask
+  *            @arg DCMI_FLAG_OVFMI: Overflow Masked flag mask
+  *            @arg DCMI_FLAG_ERRMI: Synchronization error Masked flag mask
+  *            @arg DCMI_FLAG_VSYNCMI: VSYNC Masked flag mask
+  *            @arg DCMI_FLAG_LINEMI: Line Masked flag mask
+  *            @arg DCMI_FLAG_HSYNC: HSYNC flag mask
+  *            @arg DCMI_FLAG_VSYNC: VSYNC flag mask
+  *            @arg DCMI_FLAG_FNE: Fifo not empty flag mask
+  * @retval The new state of DCMI_FLAG (SET or RESET).
+  */
+FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t dcmireg, tempreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DCMI_GET_FLAG(DCMI_FLAG));
+  
+  /* Get the DCMI register index */
+  dcmireg = (((uint16_t)DCMI_FLAG) >> 12);
+  
+  if (dcmireg == 0x00) /* The FLAG is in RISR register */
+  {
+    tempreg= DCMI->RISR;
+  }
+  else if (dcmireg == 0x02) /* The FLAG is in SR register */
+  {
+    tempreg = DCMI->SR;
+  }
+  else /* The FLAG is in MISR register */
+  {
+    tempreg = DCMI->MISR;
+  }
+  
+  if ((tempreg & DCMI_FLAG) != (uint16_t)RESET )
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the DCMI_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DCMI's pending flags.
+  * @param  DCMI_FLAG: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask
+  *            @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask
+  *            @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask
+  *            @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask
+  *            @arg DCMI_FLAG_LINERI: Line Raw flag mask
+  * @retval None
+  */
+void DCMI_ClearFlag(uint16_t DCMI_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_DCMI_CLEAR_FLAG(DCMI_FLAG));
+  
+  /* Clear the flag by writing in the ICR register 1 in the corresponding 
+  Flag position*/
+  
+  DCMI->ICR = DCMI_FLAG;
+}
+
+/**
+  * @brief  Checks whether the DCMI interrupt has occurred or not.
+  * @param  DCMI_IT: specifies the DCMI interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+  *            @arg DCMI_IT_OVF: Overflow interrupt mask
+  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+  *            @arg DCMI_IT_LINE: Line interrupt mask
+  * @retval The new state of DCMI_IT (SET or RESET).
+  */
+ITStatus DCMI_GetITStatus(uint16_t DCMI_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t itstatus = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DCMI_GET_IT(DCMI_IT));
+  
+  itstatus = DCMI->MISR & DCMI_IT; /* Only masked interrupts are checked */
+  
+  if ((itstatus != (uint16_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the DCMI's interrupt pending bits.
+  * @param  DCMI_IT: specifies the DCMI interrupt pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+  *            @arg DCMI_IT_OVF: Overflow interrupt mask
+  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+  *            @arg DCMI_IT_LINE: Line interrupt mask
+  * @retval None
+  */
+void DCMI_ClearITPendingBit(uint16_t DCMI_IT)
+{
+  /* Clear the interrupt pending Bit by writing in the ICR register 1 in the 
+  corresponding pending Bit position*/
+  
+  DCMI->ICR = DCMI_IT;
+}
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+

底盘/底盘-old/底盘/Library/stm32f4xx_dcmi.h

@@ -0,0 +1,304 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_dcmi.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the DCMI firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_DCMI_H
+#define __STM32F4xx_DCMI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DCMI
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** 
+  * @brief   DCMI Init structure definition  
+  */ 
+typedef struct
+{
+  uint16_t DCMI_CaptureMode;      /*!< Specifies the Capture Mode: Continuous or Snapshot.
+                                       This parameter can be a value of @ref DCMI_Capture_Mode */
+
+  uint16_t DCMI_SynchroMode;      /*!< Specifies the Synchronization Mode: Hardware or Embedded.
+                                       This parameter can be a value of @ref DCMI_Synchronization_Mode */
+
+  uint16_t DCMI_PCKPolarity;      /*!< Specifies the Pixel clock polarity: Falling or Rising.
+                                       This parameter can be a value of @ref DCMI_PIXCK_Polarity */
+
+  uint16_t DCMI_VSPolarity;       /*!< Specifies the Vertical synchronization polarity: High or Low.
+                                       This parameter can be a value of @ref DCMI_VSYNC_Polarity */
+
+  uint16_t DCMI_HSPolarity;       /*!< Specifies the Horizontal synchronization polarity: High or Low.
+                                       This parameter can be a value of @ref DCMI_HSYNC_Polarity */
+
+  uint16_t DCMI_CaptureRate;      /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
+                                       This parameter can be a value of @ref DCMI_Capture_Rate */
+
+  uint16_t DCMI_ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
+                                       This parameter can be a value of @ref DCMI_Extended_Data_Mode */
+} DCMI_InitTypeDef;
+
+/** 
+  * @brief   DCMI CROP Init structure definition  
+  */ 
+typedef struct
+{
+  uint16_t DCMI_VerticalStartLine;      /*!< Specifies the Vertical start line count from which the image capture
+                                             will start. This parameter can be a value between 0x00 and 0x1FFF */
+
+  uint16_t DCMI_HorizontalOffsetCount;  /*!< Specifies the number of pixel clocks to count before starting a capture.
+                                             This parameter can be a value between 0x00 and 0x3FFF */
+
+  uint16_t DCMI_VerticalLineCount;      /*!< Specifies the number of lines to be captured from the starting point.
+                                             This parameter can be a value between 0x00 and 0x3FFF */
+
+  uint16_t DCMI_CaptureCount;           /*!< Specifies the number of pixel clocks to be captured from the starting
+                                             point on the same line.
+                                             This parameter can be a value between 0x00 and 0x3FFF */
+} DCMI_CROPInitTypeDef;
+
+/** 
+  * @brief   DCMI Embedded Synchronisation CODE Init structure definition  
+  */ 
+typedef struct
+{
+  uint8_t DCMI_FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
+  uint8_t DCMI_LineStartCode;  /*!< Specifies the code of the line start delimiter. */
+  uint8_t DCMI_LineEndCode;    /*!< Specifies the code of the line end delimiter. */
+  uint8_t DCMI_FrameEndCode;   /*!< Specifies the code of the frame end delimiter. */
+} DCMI_CodesInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DCMI_Exported_Constants
+  * @{
+  */
+
+/** @defgroup DCMI_Capture_Mode 
+  * @{
+  */ 
+#define DCMI_CaptureMode_Continuous    ((uint16_t)0x0000) /*!< The received data are transferred continuously 
+                                                               into the destination memory through the DMA */
+#define DCMI_CaptureMode_SnapShot      ((uint16_t)0x0002) /*!< Once activated, the interface waits for the start of 
+                                                               frame and then transfers a single frame through the DMA */
+#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) || \
+                                   ((MODE) == DCMI_CaptureMode_SnapShot))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DCMI_Synchronization_Mode
+  * @{
+  */ 
+#define DCMI_SynchroMode_Hardware    ((uint16_t)0x0000) /*!< Hardware synchronization data capture (frame/line start/stop)
+                                                             is synchronized with the HSYNC/VSYNC signals */
+#define DCMI_SynchroMode_Embedded    ((uint16_t)0x0010) /*!< Embedded synchronization data capture is synchronized with 
+                                                             synchronization codes embedded in the data flow */
+#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) || \
+                              ((MODE) == DCMI_SynchroMode_Embedded))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DCMI_PIXCK_Polarity 
+  * @{
+  */ 
+#define DCMI_PCKPolarity_Falling    ((uint16_t)0x0000) /*!< Pixel clock active on Falling edge */
+#define DCMI_PCKPolarity_Rising     ((uint16_t)0x0020) /*!< Pixel clock active on Rising edge */
+#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) || \
+                                      ((POLARITY) == DCMI_PCKPolarity_Rising))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DCMI_VSYNC_Polarity 
+  * @{
+  */ 
+#define DCMI_VSPolarity_Low     ((uint16_t)0x0000) /*!< Vertical synchronization active Low */
+#define DCMI_VSPolarity_High    ((uint16_t)0x0080) /*!< Vertical synchronization active High */
+#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) || \
+                                     ((POLARITY) == DCMI_VSPolarity_High))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DCMI_HSYNC_Polarity 
+  * @{
+  */ 
+#define DCMI_HSPolarity_Low     ((uint16_t)0x0000) /*!< Horizontal synchronization active Low */
+#define DCMI_HSPolarity_High    ((uint16_t)0x0040) /*!< Horizontal synchronization active High */
+#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) || \
+                                     ((POLARITY) == DCMI_HSPolarity_High))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DCMI_Capture_Rate 
+  * @{
+  */ 
+#define DCMI_CaptureRate_All_Frame     ((uint16_t)0x0000) /*!< All frames are captured */
+#define DCMI_CaptureRate_1of2_Frame    ((uint16_t)0x0100) /*!< Every alternate frame captured */
+#define DCMI_CaptureRate_1of4_Frame    ((uint16_t)0x0200) /*!< One frame in 4 frames captured */
+#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || \
+                                    ((RATE) == DCMI_CaptureRate_1of2_Frame) ||\
+                                    ((RATE) == DCMI_CaptureRate_1of4_Frame))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DCMI_Extended_Data_Mode 
+  * @{
+  */ 
+#define DCMI_ExtendedDataMode_8b     ((uint16_t)0x0000) /*!< Interface captures 8-bit data on every pixel clock */
+#define DCMI_ExtendedDataMode_10b    ((uint16_t)0x0400) /*!< Interface captures 10-bit data on every pixel clock */
+#define DCMI_ExtendedDataMode_12b    ((uint16_t)0x0800) /*!< Interface captures 12-bit data on every pixel clock */
+#define DCMI_ExtendedDataMode_14b    ((uint16_t)0x0C00) /*!< Interface captures 14-bit data on every pixel clock */
+#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_ExtendedDataMode_8b) || \
+                                    ((DATA) == DCMI_ExtendedDataMode_10b) ||\
+                                    ((DATA) == DCMI_ExtendedDataMode_12b) ||\
+                                    ((DATA) == DCMI_ExtendedDataMode_14b))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DCMI_interrupt_sources 
+  * @{
+  */ 
+#define DCMI_IT_FRAME    ((uint16_t)0x0001)
+#define DCMI_IT_OVF      ((uint16_t)0x0002)
+#define DCMI_IT_ERR      ((uint16_t)0x0004)
+#define DCMI_IT_VSYNC    ((uint16_t)0x0008)
+#define DCMI_IT_LINE     ((uint16_t)0x0010)
+#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000))
+#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \
+                            ((IT) == DCMI_IT_OVF) || \
+                            ((IT) == DCMI_IT_ERR) || \
+                            ((IT) == DCMI_IT_VSYNC) || \
+                            ((IT) == DCMI_IT_LINE))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DCMI_Flags 
+  * @{
+  */ 
+/** 
+  * @brief   DCMI SR register  
+  */ 
+#define DCMI_FLAG_HSYNC     ((uint16_t)0x2001)
+#define DCMI_FLAG_VSYNC     ((uint16_t)0x2002)
+#define DCMI_FLAG_FNE       ((uint16_t)0x2004)
+/** 
+  * @brief   DCMI RISR register  
+  */ 
+#define DCMI_FLAG_FRAMERI    ((uint16_t)0x0001)
+#define DCMI_FLAG_OVFRI      ((uint16_t)0x0002)
+#define DCMI_FLAG_ERRRI      ((uint16_t)0x0004)
+#define DCMI_FLAG_VSYNCRI    ((uint16_t)0x0008)
+#define DCMI_FLAG_LINERI     ((uint16_t)0x0010)
+/** 
+  * @brief   DCMI MISR register  
+  */ 
+#define DCMI_FLAG_FRAMEMI    ((uint16_t)0x1001)
+#define DCMI_FLAG_OVFMI      ((uint16_t)0x1002)
+#define DCMI_FLAG_ERRMI      ((uint16_t)0x1004)
+#define DCMI_FLAG_VSYNCMI    ((uint16_t)0x1008)
+#define DCMI_FLAG_LINEMI     ((uint16_t)0x1010)
+#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \
+                                ((FLAG) == DCMI_FLAG_VSYNC) || \
+                                ((FLAG) == DCMI_FLAG_FNE) || \
+                                ((FLAG) == DCMI_FLAG_FRAMERI) || \
+                                ((FLAG) == DCMI_FLAG_OVFRI) || \
+                                ((FLAG) == DCMI_FLAG_ERRRI) || \
+                                ((FLAG) == DCMI_FLAG_VSYNCRI) || \
+                                ((FLAG) == DCMI_FLAG_LINERI) || \
+                                ((FLAG) == DCMI_FLAG_FRAMEMI) || \
+                                ((FLAG) == DCMI_FLAG_OVFMI) || \
+                                ((FLAG) == DCMI_FLAG_ERRMI) || \
+                                ((FLAG) == DCMI_FLAG_VSYNCMI) || \
+                                ((FLAG) == DCMI_FLAG_LINEMI))
+                                
+#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000))
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/*  Function used to set the DCMI configuration to the default reset state ****/ 
+void DCMI_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct);
+void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct);
+void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct);
+void DCMI_CROPCmd(FunctionalState NewState);
+void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct);
+void DCMI_JPEGCmd(FunctionalState NewState);
+
+/* Image capture functions ****************************************************/
+void DCMI_Cmd(FunctionalState NewState);
+void DCMI_CaptureCmd(FunctionalState NewState);
+uint32_t DCMI_ReadData(void);
+
+/* Interrupts and flags management functions **********************************/
+void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState);
+FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG);
+void DCMI_ClearFlag(uint16_t DCMI_FLAG);
+ITStatus DCMI_GetITStatus(uint16_t DCMI_IT);
+void DCMI_ClearITPendingBit(uint16_t DCMI_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_DCMI_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+

底盘/底盘-old/底盘/Library/stm32f4xx_dfsdm.h

@@ -0,0 +1,821 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_dfsdm.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the DFSDM
+  *          firmware library
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4XX_DFSDM_H
+#define __STM32F4XX_DFSDM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DFSDM
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  DFSDM Transceiver init structure definition
+  */
+typedef struct
+{
+  uint32_t DFSDM_Interface;                 /*!< Selects the serial interface type and input clock phase.
+                                            This parameter can be a value of @ref DFSDM_Interface_Selection */
+
+  uint32_t DFSDM_Clock;                     /*!< Specifies the clock source for the serial interface transceiver.
+                                            This parameter can be a value of @ref DFSDM_Clock_Selection */
+
+  uint32_t DFSDM_Input;                     /*!< Specifies the Input mode for the serial interface transceiver.
+                                            This parameter can be a value of @ref DFSDM_Input_Selection */
+
+  uint32_t DFSDM_Redirection;               /*!< Specifies if the channel input is redirected from channel channel (y+1).
+                                            This parameter can be a value of @ref DFSDM_Redirection_Selection */
+
+  uint32_t DFSDM_PackingMode;               /*!< Specifies the packing mode for the serial interface transceiver.
+                                            This parameter can be a value of @ref DFSDM_Pack_Selection */
+
+  uint32_t DFSDM_DataRightShift;            /*!< Defines the final data right bit shift.
+                                            This parameter can be a value between 0 and 31 */
+
+  uint32_t DFSDM_Offset;                    /*!< Sets the calibration offset.
+                                            This parameter can be a value between 0 and 0xFFFFFF */
+
+  uint32_t DFSDM_CLKAbsenceDetector;        /*!< Enables or disables the Clock Absence Detector.
+                                            This parameter can be a value of @ref DFSDM_Clock_Absence_Detector_state */
+
+  uint32_t DFSDM_ShortCircuitDetector;      /*!< Enables or disables the Short Circuit Detector.
+                                            This parameter can be a value of @ref DFSDM_Short_Circuit_Detector_state */
+}DFSDM_TransceiverInitTypeDef;
+
+/** 
+  * @brief  DFSDM filter analog parameters structure definition  
+  */
+typedef struct
+{
+  uint32_t DFSDM_SincOrder;                  /*!< Sets the Sinc Filter Order .
+                                             This parameter can be a value of @ref DFSDM_Sinc_Order */
+
+  uint32_t DFSDM_FilterOversamplingRatio;    /*!< Sets the Sinc Filter Oversampling Ratio.
+                                             This parameter can be a value between 1 and 1024 */
+
+  uint32_t DFSDM_IntegratorOversamplingRatio;/*!< Sets the Integrator Oversampling Ratio.
+                                             This parameter can be a value between 1 and 256 */
+}DFSDM_FilterInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DFSDM_Interface_Selection
+  * @{
+  */
+#define DFSDM_Interface_SPI_RisingEdge   ((uint32_t)0x00000000)  /*!<  DFSDM SPI interface with rising edge to strobe data */
+#define DFSDM_Interface_SPI_FallingEdge  ((uint32_t)0x00000001)  /*!<  DFSDM SPI interface with falling edge to strobe data */
+#define DFSDM_Interface_Manchester1      ((uint32_t)0x00000002)  /*!<  DFSDM Manchester coded input, rising edge = logic 0, falling edge = logic 1 */
+#define DFSDM_Interface_Manchester2      ((uint32_t)0x00000003)  /*!<  DFSDM Manchester coded input, rising edge = logic 1, falling edge = logic 0 */
+
+#define IS_DFSDM_INTERFACE(INTERFACE)    (((INTERFACE) == DFSDM_Interface_SPI_RisingEdge) || \
+                                         ((INTERFACE) == DFSDM_Interface_SPI_FallingEdge) || \
+                                         ((INTERFACE) == DFSDM_Interface_Manchester1)     || \
+                                         ((INTERFACE) == DFSDM_Interface_Manchester2))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Clock_Selection
+  * @{
+  */
+#define DFSDM_Clock_External             ((uint32_t)0x00000000)  /*!<  DFSDM clock coming from external DFSDM_CKINy input */
+#define DFSDM_Clock_Internal             ((uint32_t)0x00000004)  /*!<  DFSDM clock coming from internal DFSDM_CKOUT output */
+#define DFSDM_Clock_InternalDiv2_Mode1   ((uint32_t)0x00000008)  /*!<  DFSDM clock coming from internal DFSDM_CKOUT output divided by 2
+                                                                       and clock change is on every rising edge of DFSDM_CKOUT output signal */
+#define DFSDM_Clock_InternalDiv2_Mode2   ((uint32_t)0x0000000C)  /*!<  DFSDM clock coming from internal DFSDM_CKOUT output divided by 2
+                                                                       and clock change is on every falling edge of DFSDM_CKOUT output signal */
+
+#define IS_DFSDM_CLOCK(CLOCK)            (((CLOCK) == DFSDM_Clock_External)          || \
+                                         ((CLOCK) == DFSDM_Clock_Internal)           || \
+                                         ((CLOCK) == DFSDM_Clock_InternalDiv2_Mode1) || \
+                                         ((CLOCK) == DFSDM_Clock_InternalDiv2_Mode2))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Input_Selection
+  * @{
+  */
+#define DFSDM_Input_External     ((uint32_t)0x00000000)  /*!<  DFSDM clock coming from external DFSDM_CKINy input */
+#define DFSDM_Input_ADC          ((uint32_t)0x00001000)  /*!<  DFSDM clock coming from internal DFSDM_CKOUT output */
+#define DFSDM_Input_Internal     ((uint32_t)0x00002000)  /*!<  DFSDM clock coming from internal DFSDM_CKOUT output divided by 2
+                                                               and clock change is on every rising edge of DFSDM_CKOUT output signal */
+
+#define IS_DFSDM_Input_MODE(INPUT)      (((INPUT) == DFSDM_Input_External) || \
+                                         ((INPUT) == DFSDM_Input_ADC)      || \
+                                         ((INPUT) == DFSDM_Input_Internal))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Redirection_Selection
+  * @{
+  */
+#define DFSDM_Redirection_Disabled       ((uint32_t)0x00000000)  /*!< DFSDM Channel serial inputs are taken from pins of the same channel y */
+#define DFSDM_Redirection_Enabled         DFSDM_CHCFGR1_CHINSEL  /*!< DFSDM Channel serial inputs are taken from pins of the channel (y+1) modulo 8 */
+
+#define IS_DFSDM_Redirection_STATE(STATE)      (((STATE) == DFSDM_Redirection_Disabled) || \
+                                                ((STATE) == DFSDM_Redirection_Enabled))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Pack_Selection
+  * @{
+  */
+#define DFSDM_PackingMode_Standard     ((uint32_t)0x00000000)  /*!<  DFSDM Input data in DFSDM_CHDATINyR register are stored only in INDAT0[15:0] */
+#define DFSDM_PackingMode_Interleaved  ((uint32_t)0x00004000)  /*!<  DFSDM Input data in DFSDM_CHDATINyR register are stored as two samples:
+                                                                        - first sample in INDAT0[15:0] - assigned to channel y
+                                                                        - second sample INDAT1[15:0]   - assigned to channel y */
+#define DFSDM_PackingMode_Dual         ((uint32_t)0x00008000)  /*!<  DFSDM Input data in DFSDM_CHDATINyR register are stored as two samples:
+                                                                        - first sample INDAT0[15:0]    - assigned to channel y
+                                                                        - second sample INDAT1[15:0]   - assigned to channel (y+1) */
+
+#define IS_DFSDM_PACK_MODE(MODE)        (((MODE) == DFSDM_PackingMode_Standard)    || \
+                                         ((MODE) == DFSDM_PackingMode_Interleaved) || \
+                                         ((MODE) == DFSDM_PackingMode_Dual))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Clock_Absence_Detector_state
+  * @{
+  */
+#define DFSDM_CLKAbsenceDetector_Enable     DFSDM_CHCFGR1_CKABEN    /*!<  DFSDM Clock Absence Detector is Enabled */
+#define DFSDM_CLKAbsenceDetector_Disable    ((uint32_t)0x00000000)  /*!<  DFSDM Clock Absence Detector is Disabled */
+
+#define IS_DFSDM_CLK_DETECTOR_STATE(STATE)  (((STATE) == DFSDM_CLKAbsenceDetector_Enable) || \
+                                             ((STATE) == DFSDM_CLKAbsenceDetector_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Short_Circuit_Detector_state
+  * @{
+  */
+#define DFSDM_ShortCircuitDetector_Enable   DFSDM_CHCFGR1_SCDEN     /*!<  DFSDM Short Circuit Detector is Enabled */
+#define DFSDM_ShortCircuitDetector_Disable  ((uint32_t)0x00000000)  /*!<  DFSDM Short Circuit Detector is Disabled */
+
+#define IS_DFSDM_SC_DETECTOR_STATE(STATE)  (((STATE) == DFSDM_ShortCircuitDetector_Enable) || \
+                                            ((STATE) == DFSDM_ShortCircuitDetector_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Sinc_Order
+  * @{
+  */
+#define DFSDM_SincOrder_FastSinc        ((uint32_t)0x00000000)  /*!<  DFSDM Sinc filter order = Fast sinc */
+#define DFSDM_SincOrder_Sinc1           ((uint32_t)0x20000000)  /*!<  DFSDM Sinc filter order = 1 */
+#define DFSDM_SincOrder_Sinc2           ((uint32_t)0x40000000)  /*!<  DFSDM Sinc filter order = 2 */
+#define DFSDM_SincOrder_Sinc3           ((uint32_t)0x60000000)  /*!<  DFSDM Sinc filter order = 3 */
+#define DFSDM_SincOrder_Sinc4           ((uint32_t)0x80000000)  /*!<  DFSDM Sinc filter order = 4 */
+#define DFSDM_SincOrder_Sinc5           ((uint32_t)0xA0000000)  /*!<  DFSDM Sinc filter order = 5 */
+
+#define IS_DFSDM_SINC_ORDER(ORDER)        (((ORDER) == DFSDM_SincOrder_FastSinc) || \
+                                          ((ORDER) == DFSDM_SincOrder_Sinc1)     || \
+                                          ((ORDER) == DFSDM_SincOrder_Sinc2)     || \
+                                          ((ORDER) == DFSDM_SincOrder_Sinc3)     || \
+                                          ((ORDER) == DFSDM_SincOrder_Sinc4)     || \
+                                          ((ORDER) == DFSDM_SincOrder_Sinc5))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Break_Signal_Assignment
+  * @{
+  */
+#define DFSDM_SCDBreak_0                 ((uint32_t)0x00001000)  /*!<  DFSDM Break 0 signal assigned to short circuit detector */
+#define DFSDM_SCDBreak_1                 ((uint32_t)0x00002000)  /*!<  DFSDM Break 1 signal assigned to short circuit detector */
+#define DFSDM_SCDBreak_2                 ((uint32_t)0x00004000)  /*!<  DFSDM Break 2 signal assigned to short circuit detector */
+#define DFSDM_SCDBreak_3                 ((uint32_t)0x00008000)  /*!<  DFSDM Break 3 signal assigned to short circuit detector */
+
+#define IS_DFSDM_SCD_BREAK_SIGNAL(RANK)    (((RANK) == DFSDM_SCDBreak_0) || \
+                                           ((RANK) == DFSDM_SCDBreak_1)  || \
+                                           ((RANK) == DFSDM_SCDBreak_2)  || \
+                                           ((RANK) == DFSDM_SCDBreak_3))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_AWD_Sinc_Order
+  * @{
+  */
+#define DFSDM_AWDSincOrder_Fast            ((uint32_t)0x00000000)  /*!<  DFSDM Fast sinc filter */
+#define DFSDM_AWDSincOrder_Sinc1           ((uint32_t)0x00400000)  /*!<  DFSDM sinc1 filter */
+#define DFSDM_AWDSincOrder_Sinc2           ((uint32_t)0x00800000)  /*!<  DFSDM sinc2 filter */
+#define DFSDM_AWDSincOrder_Sinc3           ((uint32_t)0x00C00000)  /*!<  DFSDM sinc3 filter */
+
+#define IS_DFSDM_AWD_SINC_ORDER(ORDER)    (((ORDER) == DFSDM_AWDSincOrder_Fast)  || \
+                                           ((ORDER) == DFSDM_AWDSincOrder_Sinc1) || \
+                                           ((ORDER) == DFSDM_AWDSincOrder_Sinc2) || \
+                                           ((ORDER) == DFSDM_AWDSincOrder_Sinc3))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_AWD_CHANNEL
+  * @{
+  */
+#define DFSDM_AWDChannel0               ((uint32_t)0x00010000)  /*!<  DFSDM AWDx guard channel 0 */
+#define DFSDM_AWDChannel1               ((uint32_t)0x00020000)  /*!<  DFSDM AWDx guard channel 1 */
+#define DFSDM_AWDChannel2               ((uint32_t)0x00040000)  /*!<  DFSDM AWDx guard channel 2 */
+#define DFSDM_AWDChannel3               ((uint32_t)0x00080000)  /*!<  DFSDM AWDx guard channel 3 */
+#define DFSDM_AWDChannel4               ((uint32_t)0x00100000)  /*!<  DFSDM AWDx guard channel 4 */
+#define DFSDM_AWDChannel5               ((uint32_t)0x00200000)  /*!<  DFSDM AWDx guard channel 5 */
+#define DFSDM_AWDChannel6               ((uint32_t)0x00400000)  /*!<  DFSDM AWDx guard channel 6 */
+#define DFSDM_AWDChannel7               ((uint32_t)0x00800000)  /*!<  DFSDM AWDx guard channel 7 */
+
+#define IS_DFSDM_AWD_CHANNEL(CHANNEL)    (((CHANNEL) == DFSDM_AWDChannel0) || \
+                                          ((CHANNEL) == DFSDM_AWDChannel1) || \
+                                          ((CHANNEL) == DFSDM_AWDChannel2) || \
+                                          ((CHANNEL) == DFSDM_AWDChannel3) || \
+                                          ((CHANNEL) == DFSDM_AWDChannel4) || \
+                                          ((CHANNEL) == DFSDM_AWDChannel5) || \
+                                          ((CHANNEL) == DFSDM_AWDChannel6) || \
+                                          ((CHANNEL) == DFSDM_AWDChannel7))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Threshold_Selection
+  * @{
+  */
+#define DFSDM_Threshold_Low               ((uint8_t)0x00)  /*!<  DFSDM Low threshold */
+#define DFSDM_Threshold_High              ((uint8_t)0x08)  /*!<  DFSDM High threshold */
+
+#define IS_DFSDM_Threshold(THR)          (((THR) == DFSDM_Threshold_Low) || \
+                                          ((THR) == DFSDM_Threshold_High))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_AWD_Fast_Mode_Selection
+  * @{
+  */
+#define DFSDM_AWDFastMode_Disable         ((uint32_t)0x00000000)  /*!<  DFSDM Fast mode for AWD is disabled */
+#define DFSDM_AWDFastMode_Enable          ((uint32_t)0x40000000)  /*!<  DFSDM Fast mode for AWD is enabled */
+
+#define IS_DFSDM_AWD_MODE(MODE)          (((MODE) == DFSDM_AWDFastMode_Disable) || \
+                                          ((MODE) == DFSDM_AWDFastMode_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Clock_Output_Source_Selection
+  * @{
+  */
+#define DFSDM_ClkOutSource_SysClock        ((uint32_t)0x00000000)  /*!<  DFSDM Source for output clock is comming from system clock */
+#define DFSDM_ClkOutSource_AudioClock      DFSDM_CHCFGR1_CKOUTSRC  /*!<  DFSDM Source for output clock is comming from audio clock */
+
+#define IS_DFSDM_CLOCK_OUT_SOURCE(SRC)    (((SRC) == DFSDM_ClkOutSource_SysClock) || \
+                                           ((SRC) == DFSDM_ClkOutSource_AudioClock))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Conversion_Mode
+  * @{
+  */
+#define DFSDM_DMAConversionMode_Regular     ((uint32_t)0x00000010)  /*!<  DFSDM Regular mode */
+#define DFSDM_DMAConversionMode_Injected    ((uint32_t)0x00000000)  /*!<  DFSDM Injected mode */
+
+#define IS_DFSDM_CONVERSION_MODE(MODE)    (((MODE) == DFSDM_DMAConversionMode_Regular) || \
+                                           ((MODE) == DFSDM_DMAConversionMode_Injected))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Extremes_Channel_Selection
+  * @{
+  */
+#define DFSDM_ExtremChannel0              ((uint32_t)0x00000100)  /*!<  DFSDM Extreme detector guard channel 0 */
+#define DFSDM_ExtremChannel1              ((uint32_t)0x00000200)  /*!<  DFSDM Extreme detector guard channel 1 */
+#define DFSDM_ExtremChannel2              ((uint32_t)0x00000400)  /*!<  DFSDM Extreme detector guard channel 2 */
+#define DFSDM_ExtremChannel3              ((uint32_t)0x00000800)  /*!<  DFSDM Extreme detector guard channel 3 */
+#define DFSDM_ExtremChannel4              ((uint32_t)0x00001000)  /*!<  DFSDM Extreme detector guard channel 4 */
+#define DFSDM_ExtremChannel5              ((uint32_t)0x00002000)  /*!<  DFSDM Extreme detector guard channel 5 */
+#define DFSDM_ExtremChannel6              ((uint32_t)0x00004000)  /*!<  DFSDM Extreme detector guard channel 6 */
+#define DFSDM_ExtremChannel7              ((uint32_t)0x00008000)  /*!<  DFSDM Extreme detector guard channel 7 */
+
+#define IS_DFSDM_EXTREM_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_ExtremChannel0) || \
+                                          ((CHANNEL) == DFSDM_ExtremChannel1) || \
+                                          ((CHANNEL) == DFSDM_ExtremChannel2) || \
+                                          ((CHANNEL) == DFSDM_ExtremChannel3) || \
+                                          ((CHANNEL) == DFSDM_ExtremChannel4) || \
+                                          ((CHANNEL) == DFSDM_ExtremChannel5) || \
+                                          ((CHANNEL) == DFSDM_ExtremChannel6) || \
+                                          ((CHANNEL) == DFSDM_ExtremChannel7))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Injected_Channel_Selection
+  * @{
+  */
+#define DFSDM_InjectedChannel0            ((uint32_t)0x00000001)  /*!<  DFSDM channel 0 is selected as injected channel */
+#define DFSDM_InjectedChannel1            ((uint32_t)0x00000002)  /*!<  DFSDM channel 1 is selected as injected channel */
+#define DFSDM_InjectedChannel2            ((uint32_t)0x00000004)  /*!<  DFSDM channel 2 is selected as injected channel */
+#define DFSDM_InjectedChannel3            ((uint32_t)0x00000008)  /*!<  DFSDM channel 3 is selected as injected channel */
+#define DFSDM_InjectedChannel4            ((uint32_t)0x00000010)  /*!<  DFSDM channel 4 is selected as injected channel */
+#define DFSDM_InjectedChannel5            ((uint32_t)0x00000020)  /*!<  DFSDM channel 5 is selected as injected channel */
+#define DFSDM_InjectedChannel6            ((uint32_t)0x00000040)  /*!<  DFSDM channel 6 is selected as injected channel */
+#define DFSDM_InjectedChannel7            ((uint32_t)0x00000080)  /*!<  DFSDM channel 7 is selected as injected channel */
+
+#define IS_DFSDM_INJECT_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_InjectedChannel0) || \
+                                          ((CHANNEL) == DFSDM_InjectedChannel1) || \
+                                          ((CHANNEL) == DFSDM_InjectedChannel2) || \
+                                          ((CHANNEL) == DFSDM_InjectedChannel3) || \
+                                          ((CHANNEL) == DFSDM_InjectedChannel4) || \
+                                          ((CHANNEL) == DFSDM_InjectedChannel5) || \
+                                          ((CHANNEL) == DFSDM_InjectedChannel6) || \
+                                          ((CHANNEL) == DFSDM_InjectedChannel7))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Regular_Channel_Selection
+  * @{
+  */
+#define DFSDM_RegularChannel0             ((uint32_t)0x00000000)  /*!<  DFSDM channel 0 is selected as regular channel */
+#define DFSDM_RegularChannel1             ((uint32_t)0x01000000)  /*!<  DFSDM channel 1 is selected as regular channel */
+#define DFSDM_RegularChannel2             ((uint32_t)0x02000000)  /*!<  DFSDM channel 2 is selected as regular channel */
+#define DFSDM_RegularChannel3             ((uint32_t)0x03000000)  /*!<  DFSDM channel 3 is selected as regular channel */
+#define DFSDM_RegularChannel4             ((uint32_t)0x04000000)  /*!<  DFSDM channel 4 is selected as regular channel */
+#define DFSDM_RegularChannel5             ((uint32_t)0x05000000)  /*!<  DFSDM channel 5 is selected as regular channel */
+#define DFSDM_RegularChannel6             ((uint32_t)0x06000000)  /*!<  DFSDM channel 6 is selected as regular channel */
+#define DFSDM_RegularChannel7             ((uint32_t)0x07000000)  /*!<  DFSDM channel 7 is selected as regular channel */
+
+#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_RegularChannel0) || \
+                                           ((CHANNEL) == DFSDM_RegularChannel1) || \
+                                           ((CHANNEL) == DFSDM_RegularChannel2) || \
+                                           ((CHANNEL) == DFSDM_RegularChannel3) || \
+                                           ((CHANNEL) == DFSDM_RegularChannel4) || \
+                                           ((CHANNEL) == DFSDM_RegularChannel5) || \
+                                           ((CHANNEL) == DFSDM_RegularChannel6) || \
+                                           ((CHANNEL) == DFSDM_RegularChannel7))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Injected_Trigger_signal
+  * @{
+  */
+#define DFSDM_Trigger_TIM1_TRGO          ((uint32_t)0x00000000)  /*!<  DFSDM Internal trigger 0 */
+#define DFSDM_Trigger_TIM1_TRGO2         ((uint32_t)0x00000100)  /*!<  DFSDM Internal trigger 1 */
+#define DFSDM_Trigger_TIM8_TRGO          ((uint32_t)0x00000200)  /*!<  DFSDM Internal trigger 2 */
+#define DFSDM_Trigger_TIM8_TRGO2         ((uint32_t)0x00000300)  /*!<  DFSDM Internal trigger 3 */
+#define DFSDM_Trigger_TIM3_TRGO          ((uint32_t)0x00000300)  /*!<  DFSDM Internal trigger 4 */
+#define DFSDM_Trigger_TIM4_TRGO          ((uint32_t)0x00000400)  /*!<  DFSDM Internal trigger 5 */
+#define DFSDM_Trigger_TIM16_OC1          ((uint32_t)0x00000400)  /*!<  DFSDM Internal trigger 6 */
+#define DFSDM_Trigger_TIM6_TRGO          ((uint32_t)0x00000500)  /*!<  DFSDM Internal trigger 7 */
+#define DFSDM_Trigger_TIM7_TRGO          ((uint32_t)0x00000500)  /*!<  DFSDM Internal trigger 8 */
+#define DFSDM_Trigger_EXTI11             ((uint32_t)0x00000600)  /*!<  DFSDM External trigger 0 */
+#define DFSDM_Trigger_EXTI15             ((uint32_t)0x00000700)  /*!<  DFSDM External trigger 1 */
+
+#define IS_DFSDM0_INJ_TRIGGER(TRIG)      (((TRIG) == DFSDM_Trigger_TIM1_TRGO)  || \
+                                          ((TRIG) == DFSDM_Trigger_TIM1_TRGO2) || \
+                                          ((TRIG) == DFSDM_Trigger_TIM8_TRGO)  || \
+                                          ((TRIG) == DFSDM_Trigger_TIM8_TRGO2) || \
+                                          ((TRIG) == DFSDM_Trigger_TIM4_TRGO)  || \
+                                          ((TRIG) == DFSDM_Trigger_TIM6_TRGO)  || \
+                                          ((TRIG) == DFSDM_Trigger_TIM7_TRGO)  || \
+                                          ((TRIG) == DFSDM_Trigger_EXTI15)     || \
+                                          ((TRIG) == DFSDM_Trigger_TIM3_TRGO)  || \
+                                          ((TRIG) == DFSDM_Trigger_TIM16_OC1)  || \
+                                          ((TRIG) == DFSDM_Trigger_EXTI11))  
+
+#define IS_DFSDM1_INJ_TRIGGER(TRIG)      IS_DFSDM0_INJ_TRIGGER(TRIG)
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Trigger_Edge_selection
+  * @{
+  */
+#define DFSDM_TriggerEdge_Disabled        ((uint32_t)0x00000000)  /*!<  DFSDM Trigger detection disabled */
+#define DFSDM_TriggerEdge_Rising          ((uint32_t)0x00002000)  /*!<  DFSDM Each rising edge makes a request to launch an injected conversion */
+#define DFSDM_TriggerEdge_Falling         ((uint32_t)0x00004000)  /*!<  DFSDM Each falling edge makes a request to launch an injected conversion */
+#define DFSDM_TriggerEdge_BothEdges       ((uint32_t)0x00006000)  /*!<  DFSDM Both edges make a request to launch an injected conversion */
+
+#define IS_DFSDM_TRIGGER_EDGE(EDGE)      (((EDGE) == DFSDM_TriggerEdge_Disabled) || \
+                                          ((EDGE) == DFSDM_TriggerEdge_Rising) || \
+                                          ((EDGE) == DFSDM_TriggerEdge_Falling) || \
+                                          ((EDGE) == DFSDM_TriggerEdge_BothEdges))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Injected_Conversion_Mode_Selection
+  * @{
+  */
+#define DFSDM_InjectConvMode_Single        ((uint32_t)0x00000000)  /*!<  DFSDM Trigger detection disabled */
+#define DFSDM_InjectConvMode_Scan          ((uint32_t)0x00000010)  /*!<  DFSDM Each rising edge makes a request to launch an injected conversion */
+
+#define IS_DFSDM_INJ_CONV_MODE(MODE)      (((MODE) == DFSDM_InjectConvMode_Single) || \
+                                           ((MODE) == DFSDM_InjectConvMode_Scan))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Interrupts_Definition
+  * @{
+  */
+#define DFSDM_IT_JEOC                            DFSDM_FLTCR2_JEOCIE
+#define DFSDM_IT_REOC                            DFSDM_FLTCR2_REOCIE
+#define DFSDM_IT_JOVR                            DFSDM_FLTCR2_JOVRIE
+#define DFSDM_IT_ROVR                            DFSDM_FLTCR2_ROVRIE
+#define DFSDM_IT_AWD                             DFSDM_FLTCR2_AWDIE
+#define DFSDM_IT_SCD                             DFSDM_FLTCR2_SCDIE
+#define DFSDM_IT_CKAB                            DFSDM_FLTCR2_CKABIE
+
+#define IS_DFSDM_IT(IT)                         (((IT) == DFSDM_IT_JEOC) || \
+                                                 ((IT) == DFSDM_IT_REOC) || \
+                                                 ((IT) == DFSDM_IT_JOVR) || \
+                                                 ((IT) == DFSDM_IT_ROVR) || \
+                                                 ((IT) == DFSDM_IT_AWD)  || \
+                                                 ((IT) == DFSDM_IT_SCD)  || \
+                                                 ((IT) == DFSDM_IT_CKAB))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Flag_Definition
+  * @{
+  */
+#define DFSDM_FLAG_JEOC                          DFSDM_FLTISR_JEOCF
+#define DFSDM_FLAG_REOC                          DFSDM_FLTISR_REOCF
+#define DFSDM_FLAG_JOVR                          DFSDM_FLTISR_JOVRF
+#define DFSDM_FLAG_ROVR                          DFSDM_FLTISR_ROVRF
+#define DFSDM_FLAG_AWD                           DFSDM_FLTISR_AWDF
+#define DFSDM_FLAG_JCIP                          DFSDM_FLTISR_JCIP
+#define DFSDM_FLAG_RCIP                          DFSDM_FLTISR_RCIP
+
+#define IS_DFSDM_FLAG(FLAG)                     (((FLAG) == DFSDM_FLAG_JEOC) || \
+                                                 ((FLAG) == DFSDM_FLAG_REOC) || \
+                                                 ((FLAG) == DFSDM_FLAG_JOVR) || \
+                                                 ((FLAG) == DFSDM_FLAG_ROVR) || \
+                                                 ((FLAG) == DFSDM_FLAG_AWD)  || \
+                                                 ((FLAG) == DFSDM_FLAG_JCIP) || \
+                                                 ((FLAG) == DFSDM_FLAG_RCIP))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Clock_Absence_Flag_Definition
+  * @{
+  */
+#define DFSDM_FLAG_CLKAbsence_Channel0           ((uint32_t)0x00010000)
+#define DFSDM_FLAG_CLKAbsence_Channel1           ((uint32_t)0x00020000)
+#define DFSDM_FLAG_CLKAbsence_Channel2           ((uint32_t)0x00040000)
+#define DFSDM_FLAG_CLKAbsence_Channel3           ((uint32_t)0x00080000)
+#define DFSDM_FLAG_CLKAbsence_Channel4           ((uint32_t)0x00100000)
+#define DFSDM_FLAG_CLKAbsence_Channel5           ((uint32_t)0x00200000)
+#define DFSDM_FLAG_CLKAbsence_Channel6           ((uint32_t)0x00400000)
+#define DFSDM_FLAG_CLKAbsence_Channel7           ((uint32_t)0x00800000)
+
+#define IS_DFSDM_CLK_ABS_FLAG(FLAG)             (((FLAG) == DFSDM_FLAG_CLKAbsence_Channel0) || \
+                                                 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel1) || \
+                                                 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel2) || \
+                                                 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel3) || \
+                                                 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel4) || \
+                                                 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel5) || \
+                                                 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel6) || \
+                                                 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel7))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_SCD_Flag_Definition
+  * @{
+  */
+#define DFSDM_FLAG_SCD_Channel0                  ((uint32_t)0x01000000)
+#define DFSDM_FLAG_SCD_Channel1                  ((uint32_t)0x02000000)
+#define DFSDM_FLAG_SCD_Channel2                  ((uint32_t)0x04000000)
+#define DFSDM_FLAG_SCD_Channel3                  ((uint32_t)0x08000000)
+#define DFSDM_FLAG_SCD_Channel4                  ((uint32_t)0x10000000)
+#define DFSDM_FLAG_SCD_Channel5                  ((uint32_t)0x20000000)
+#define DFSDM_FLAG_SCD_Channel6                  ((uint32_t)0x40000000)
+#define DFSDM_FLAG_SCD_Channel7                  ((uint32_t)0x80000000)
+
+#define IS_DFSDM_SCD_FLAG(FLAG)                 (((FLAG) == DFSDM_FLAG_SCD_Channel0) || \
+                                                 ((FLAG) == DFSDM_FLAG_SCD_Channel1) || \
+                                                 ((FLAG) == DFSDM_FLAG_SCD_Channel2) || \
+                                                 ((FLAG) == DFSDM_FLAG_SCD_Channel3) || \
+                                                 ((FLAG) == DFSDM_FLAG_SCD_Channel4) || \
+                                                 ((FLAG) == DFSDM_FLAG_SCD_Channel5) || \
+                                                 ((FLAG) == DFSDM_FLAG_SCD_Channel6) || \
+                                                 ((FLAG) == DFSDM_FLAG_SCD_Channel7))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Clear_Flag_Definition
+  * @{
+  */
+#define DFSDM_CLEARF_JOVR                          DFSDM_FLTICR_CLRJOVRF
+#define DFSDM_CLEARF_ROVR                          DFSDM_FLTICR_CLRROVRF
+
+#define IS_DFSDM_CLEAR_FLAG(FLAG)                (((FLAG) == DFSDM_CLEARF_JOVR) || \
+                                                  ((FLAG) == DFSDM_CLEARF_ROVR))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Clear_ClockAbs_Flag_Definition
+  * @{
+  */
+#define DFSDM_CLEARF_CLKAbsence_Channel0           ((uint32_t)0x00010000)
+#define DFSDM_CLEARF_CLKAbsence_Channel1           ((uint32_t)0x00020000)
+#define DFSDM_CLEARF_CLKAbsence_Channel2           ((uint32_t)0x00040000)
+#define DFSDM_CLEARF_CLKAbsence_Channel3           ((uint32_t)0x00080000)
+#define DFSDM_CLEARF_CLKAbsence_Channel4           ((uint32_t)0x00100000)
+#define DFSDM_CLEARF_CLKAbsence_Channel5           ((uint32_t)0x00200000)
+#define DFSDM_CLEARF_CLKAbsence_Channel6           ((uint32_t)0x00400000)
+#define DFSDM_CLEARF_CLKAbsence_Channel7           ((uint32_t)0x00800000)
+
+#define IS_DFSDM_CLK_ABS_CLEARF(FLAG)           (((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel0) || \
+                                                 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel1) || \
+                                                 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel2) || \
+                                                 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel3) || \
+                                                 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel4) || \
+                                                 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel5) || \
+                                                 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel6) || \
+                                                 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel7))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Clear_Short_Circuit_Flag_Definition
+  * @{
+  */
+#define DFSDM_CLEARF_SCD_Channel0           ((uint32_t)0x01000000)
+#define DFSDM_CLEARF_SCD_Channel1           ((uint32_t)0x02000000)
+#define DFSDM_CLEARF_SCD_Channel2           ((uint32_t)0x04000000)
+#define DFSDM_CLEARF_SCD_Channel3           ((uint32_t)0x08000000)
+#define DFSDM_CLEARF_SCD_Channel4           ((uint32_t)0x10000000)
+#define DFSDM_CLEARF_SCD_Channel5           ((uint32_t)0x20000000)
+#define DFSDM_CLEARF_SCD_Channel6           ((uint32_t)0x40000000)
+#define DFSDM_CLEARF_SCD_Channel7           ((uint32_t)0x80000000)
+
+#define IS_DFSDM_SCD_CHANNEL_FLAG(FLAG)         (((FLAG) == DFSDM_CLEARF_SCD_Channel0) || \
+                                                 ((FLAG) == DFSDM_CLEARF_SCD_Channel1) || \
+                                                 ((FLAG) == DFSDM_CLEARF_SCD_Channel2) || \
+                                                 ((FLAG) == DFSDM_CLEARF_SCD_Channel3) || \
+                                                 ((FLAG) == DFSDM_CLEARF_SCD_Channel4) || \
+                                                 ((FLAG) == DFSDM_CLEARF_SCD_Channel5) || \
+                                                 ((FLAG) == DFSDM_CLEARF_SCD_Channel6) || \
+                                                 ((FLAG) == DFSDM_CLEARF_SCD_Channel7))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Clock_Absence_Interrupt_Definition
+  * @{
+  */
+#define DFSDM_IT_CLKAbsence_Channel0           ((uint32_t)0x00010000)
+#define DFSDM_IT_CLKAbsence_Channel1           ((uint32_t)0x00020000)
+#define DFSDM_IT_CLKAbsence_Channel2           ((uint32_t)0x00040000)
+#define DFSDM_IT_CLKAbsence_Channel3           ((uint32_t)0x00080000)
+#define DFSDM_IT_CLKAbsence_Channel4           ((uint32_t)0x00100000)
+#define DFSDM_IT_CLKAbsence_Channel5           ((uint32_t)0x00200000)
+#define DFSDM_IT_CLKAbsence_Channel6           ((uint32_t)0x00400000)
+#define DFSDM_IT_CLKAbsence_Channel7           ((uint32_t)0x00800000)
+
+#define IS_DFSDM_CLK_ABS_IT(IT)               (((IT) == DFSDM_IT_CLKAbsence_Channel0) || \
+                                               ((IT) == DFSDM_IT_CLKAbsence_Channel1) || \
+                                               ((IT) == DFSDM_IT_CLKAbsence_Channel2) || \
+                                               ((IT) == DFSDM_IT_CLKAbsence_Channel3) || \
+                                               ((IT) == DFSDM_IT_CLKAbsence_Channel4) || \
+                                               ((IT) == DFSDM_IT_CLKAbsence_Channel5) || \
+                                               ((IT) == DFSDM_IT_CLKAbsence_Channel6) || \
+                                               ((IT) == DFSDM_IT_CLKAbsence_Channel7))
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_SCD_Interrupt_Definition
+  * @{
+  */
+#define DFSDM_IT_SCD_Channel0                  ((uint32_t)0x01000000)
+#define DFSDM_IT_SCD_Channel1                  ((uint32_t)0x02000000)
+#define DFSDM_IT_SCD_Channel2                  ((uint32_t)0x04000000)
+#define DFSDM_IT_SCD_Channel3                  ((uint32_t)0x08000000)
+#define DFSDM_IT_SCD_Channel4                  ((uint32_t)0x10000000)
+#define DFSDM_IT_SCD_Channel5                  ((uint32_t)0x20000000)
+#define DFSDM_IT_SCD_Channel6                  ((uint32_t)0x40000000)
+#define DFSDM_IT_SCD_Channel7                  ((uint32_t)0x80000000)
+
+#define IS_DFSDM_SCD_IT(IT)                   (((IT) == DFSDM_IT_SCD_Channel0) || \
+                                               ((IT) == DFSDM_IT_SCD_Channel1) || \
+                                               ((IT) == DFSDM_IT_SCD_Channel2) || \
+                                               ((IT) == DFSDM_IT_SCD_Channel3) || \
+                                               ((IT) == DFSDM_IT_SCD_Channel4) || \
+                                               ((IT) == DFSDM_IT_SCD_Channel5) || \
+                                               ((IT) == DFSDM_IT_SCD_Channel6) || \
+                                               ((IT) == DFSDM_IT_SCD_Channel7))
+/**
+  * @}
+  */
+
+#define IS_DFSDM_DATA_RIGHT_BIT_SHIFT(SHIFT)  ((SHIFT) < 0x20 )
+
+#define IS_DFSDM_OFFSET(OFFSET)               ((OFFSET) < 0x01000000 )
+
+#if defined(STM32F413_423xx)
+#define IS_DFSDM_ALL_CHANNEL(CHANNEL)   (((CHANNEL) == DFSDM1_Channel0) || \
+                                         ((CHANNEL) == DFSDM1_Channel1) || \
+                                         ((CHANNEL) == DFSDM1_Channel2) || \
+                                         ((CHANNEL) == DFSDM1_Channel3) || \
+                                         ((CHANNEL) == DFSDM2_Channel0) || \
+                                         ((CHANNEL) == DFSDM2_Channel1) || \
+                                         ((CHANNEL) == DFSDM2_Channel2) || \
+                                         ((CHANNEL) == DFSDM2_Channel3) || \
+                                         ((CHANNEL) == DFSDM2_Channel4) || \
+                                         ((CHANNEL) == DFSDM2_Channel5) || \
+                                         ((CHANNEL) == DFSDM2_Channel6) || \
+                                         ((CHANNEL) == DFSDM2_Channel7))
+
+#define IS_DFSDM_ALL_FILTER(FILTER)     (((FILTER) == DFSDM1_0) || \
+                                         ((FILTER) == DFSDM1_1) || \
+                                         ((FILTER) == DFSDM2_0) || \
+                                         ((FILTER) == DFSDM2_1) || \
+                                         ((FILTER) == DFSDM2_2) || \
+                                         ((FILTER) == DFSDM2_3))
+
+#define IS_DFSDM_SYNC_FILTER(FILTER)    (((FILTER) == DFSDM1_0) || \
+                                         ((FILTER) == DFSDM1_1) || \
+                                         ((FILTER) == DFSDM2_0) || \
+                                         ((FILTER) == DFSDM2_1) || \
+                                         ((FILTER) == DFSDM2_2) || \
+                                         ((FILTER) == DFSDM2_3))
+#else
+#define IS_DFSDM_ALL_CHANNEL(CHANNEL)   (((CHANNEL) == DFSDM1_Channel0) || \
+                                         ((CHANNEL) == DFSDM1_Channel1) || \
+                                         ((CHANNEL) == DFSDM1_Channel2) || \
+                                         ((CHANNEL) == DFSDM1_Channel3))
+
+#define IS_DFSDM_ALL_FILTER(FILTER)     (((FILTER) == DFSDM1_0) || \
+                                         ((FILTER) == DFSDM1_1))
+
+#define IS_DFSDM_SYNC_FILTER(FILTER)    (((FILTER) == DFSDM1_0) || \
+                                         ((FILTER) == DFSDM1_1))
+#endif /* STM32F413_423xx */
+
+
+
+
+#define IS_DFSDM_SINC_OVRSMPL_RATIO(RATIO)  (((RATIO) < 0x401) && ((RATIO) >= 0x001))
+
+#define IS_DFSDM_INTG_OVRSMPL_RATIO(RATIO)  (((RATIO) < 0x101 ) && ((RATIO) >= 0x001))
+
+#define IS_DFSDM_CLOCK_OUT_DIVIDER(DIVIDER) ((DIVIDER) < 0x101 )
+
+#define IS_DFSDM_CSD_THRESHOLD_VALUE(VALUE) ((VALUE) < 256)
+
+#define IS_DFSDM_AWD_OVRSMPL_RATIO(RATIO)   ((RATIO) < 33) && ((RATIO) >= 0x001)
+
+#define IS_DFSDM_HIGH_THRESHOLD(VALUE)      ((VALUE) < 0x1000000)
+#define IS_DFSDM_LOW_THRESHOLD(VALUE)       ((VALUE) < 0x1000000)
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Initialization functions ***************************************************/
+void DFSDM_DeInit(void);
+void DFSDM_TransceiverInit(DFSDM_Channel_TypeDef* DFSDM_Channelx, DFSDM_TransceiverInitTypeDef* DFSDM_TransceiverInitStruct);
+void DFSDM_TransceiverStructInit(DFSDM_TransceiverInitTypeDef* DFSDM_TransceiverInitStruct);
+void DFSDM_FilterInit(DFSDM_Filter_TypeDef* DFSDMx, DFSDM_FilterInitTypeDef* DFSDM_FilterInitStruct);
+void DFSDM_FilterStructInit(DFSDM_FilterInitTypeDef* DFSDM_FilterInitStruct);
+
+/* Configuration functions ****************************************************/
+#if defined(STM32F412xG)
+void DFSDM_Command(FunctionalState NewState);
+#else /* STM32F413_423xx */
+void DFSDM_Cmd(uint32_t Instance, FunctionalState NewState);
+#endif /* STM32F412xG */
+void DFSDM_ChannelCmd(DFSDM_Channel_TypeDef* DFSDM_Channelx, FunctionalState NewState);
+void DFSDM_FilterCmd(DFSDM_Filter_TypeDef* DFSDMx, FunctionalState NewState);
+#if defined(STM32F412xG)
+void DFSDM_ConfigClkOutputDivider(uint32_t DFSDM_ClkOutDivision);
+void DFSDM_ConfigClkOutputSource(uint32_t DFSDM_ClkOutSource);
+#else
+void DFSDM_ConfigClkOutputDivider(uint32_t Instance, uint32_t DFSDM_ClkOutDivision);
+void DFSDM_ConfigClkOutputSource(uint32_t Instance, uint32_t DFSDM_ClkOutSource);
+#endif /* STM32F412xG */
+void DFSDM_SelectInjectedConversionMode(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_InjectConvMode);
+void DFSDM_SelectInjectedChannel(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_InjectedChannelx);
+void DFSDM_SelectRegularChannel(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_RegularChannelx);
+void DFSDM_StartSoftwareInjectedConversion(DFSDM_Filter_TypeDef* DFSDMx);
+void DFSDM_StartSoftwareRegularConversion(DFSDM_Filter_TypeDef* DFSDMx);
+void DFSDM_SynchronousFilter0InjectedStart(DFSDM_Filter_TypeDef* DFSDMx);
+void DFSDM_SynchronousFilter0RegularStart(DFSDM_Filter_TypeDef* DFSDMx);
+void DFSDM_RegularContinuousModeCmd(DFSDM_Filter_TypeDef* DFSDMx, FunctionalState NewState);
+void DFSDM_InjectedContinuousModeCmd(DFSDM_Filter_TypeDef* DFSDMx, FunctionalState NewState);
+void DFSDM_FastModeCmd(DFSDM_Filter_TypeDef* DFSDMx, FunctionalState NewState);
+void DFSDM_ConfigInjectedTrigger(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_Trigger, uint32_t DFSDM_TriggerEdge);
+void DFSDM_ConfigBRKShortCircuitDetector(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDBreak_i, FunctionalState NewState);
+void DFSDM_ConfigBRKAnalogWatchDog(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDBreak_i, FunctionalState NewState);
+void DFSDM_ConfigShortCircuitThreshold(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDThreshold);
+void DFSDM_ConfigAnalogWatchdog(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint32_t DFSDM_AWDFastMode);
+void DFSDM_ConfigAWDFilter(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_AWDSincOrder, uint32_t DFSDM_AWDSincOverSampleRatio);
+uint32_t DFSDM_GetAWDConversionValue(DFSDM_Channel_TypeDef* DFSDM_Channelx);
+void DFSDM_SetAWDThreshold(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_HighThreshold, uint32_t DFSDM_LowThreshold);
+void DFSDM_SelectExtremesDetectorChannel(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_ExtremChannelx);
+int32_t DFSDM_GetRegularConversionData(DFSDM_Filter_TypeDef* DFSDMx);
+int32_t DFSDM_GetInjectedConversionData(DFSDM_Filter_TypeDef* DFSDMx);
+int32_t DFSDM_GetMaxValue(DFSDM_Filter_TypeDef* DFSDMx);
+int32_t DFSDM_GetMinValue(DFSDM_Filter_TypeDef* DFSDMx);
+int32_t DFSDM_GetMaxValueChannel(DFSDM_Filter_TypeDef* DFSDMx);
+int32_t DFSDM_GetMinValueChannel(DFSDM_Filter_TypeDef* DFSDMx);
+uint32_t DFSDM_GetConversionTime(DFSDM_Filter_TypeDef* DFSDMx);
+void DFSDM_DMATransferConfig(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_DMAConversionMode, FunctionalState NewState);
+/* Interrupts and flags management functions **********************************/
+void DFSDM_ITConfig(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_IT, FunctionalState NewState);
+#if defined(STM32F412xG)
+void DFSDM_ITClockAbsenceCmd(FunctionalState NewState);
+void DFSDM_ITShortCircuitDetectorCmd(FunctionalState NewState);
+#else /* STM32F413_423xx */
+void DFSDM_ITClockAbsenceCmd(uint32_t Instance, FunctionalState NewState);
+void DFSDM_ITShortCircuitDetectorCmd(uint32_t Instance, FunctionalState NewState);
+#endif /* STM32F412xG */
+
+FlagStatus DFSDM_GetFlagStatus(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_FLAG);
+#if defined(STM32F412xG)
+FlagStatus DFSDM_GetClockAbsenceFlagStatus(uint32_t DFSDM_FLAG_CLKAbsence);
+FlagStatus DFSDM_GetShortCircuitFlagStatus(uint32_t DFSDM_FLAG_SCD);
+#else /* STM32F413_423xx */
+FlagStatus DFSDM_GetClockAbsenceFlagStatus(uint32_t Instance, uint32_t DFSDM_FLAG_CLKAbsence);
+FlagStatus DFSDM_GetShortCircuitFlagStatus(uint32_t Instance, uint32_t DFSDM_FLAG_SCD);
+#endif /* STM32F412xG */
+FlagStatus DFSDM_GetWatchdogFlagStatus(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint8_t DFSDM_Threshold);
+
+void DFSDM_ClearFlag(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_CLEARF);
+#if defined(STM32F412xG)
+void DFSDM_ClearClockAbsenceFlag(uint32_t DFSDM_CLEARF_CLKAbsence);
+void DFSDM_ClearShortCircuitFlag(uint32_t DFSDM_CLEARF_SCD);
+#else /* STM32F413_423xx */
+void DFSDM_ClearClockAbsenceFlag(uint32_t Instance, uint32_t DFSDM_CLEARF_CLKAbsence);
+void DFSDM_ClearShortCircuitFlag(uint32_t Instance, uint32_t DFSDM_CLEARF_SCD);
+#endif /* STM32F412xG */
+void DFSDM_ClearAnalogWatchdogFlag(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint8_t DFSDM_Threshold);
+
+ITStatus DFSDM_GetITStatus(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_IT);
+#if defined(STM32F412xG)
+ITStatus DFSDM_GetClockAbsenceITStatus(uint32_t DFSDM_IT_CLKAbsence);
+ITStatus DFSDM_GetShortCircuitITStatus(uint32_t DFSDM_IT_SCR);
+#else /* STM32F413_423xx */
+ITStatus DFSDM_GetClockAbsenceITStatus(uint32_t Instance, uint32_t DFSDM_IT_CLKAbsence);
+ITStatus DFSDM_GetShortCircuitITStatus(uint32_t Instance, uint32_t DFSDM_IT_SCR);
+#endif /* STM32F412xG */
+
+#endif /* STM32F412xG || STM32F413_423xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4XX_DFSDM_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

底盘/底盘-old/底盘/Library/stm32f4xx_dma.h

@@ -0,0 +1,601 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_dma.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the DMA firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_DMA_H
+#define __STM32F4xx_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  DMA Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t DMA_Channel;            /*!< Specifies the channel used for the specified stream. 
+                                        This parameter can be a value of @ref DMA_channel */
+ 
+  uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */
+
+  uint32_t DMA_Memory0BaseAddr;    /*!< Specifies the memory 0 base address for DMAy Streamx. 
+                                        This memory is the default memory used when double buffer mode is
+                                        not enabled. */
+
+  uint32_t DMA_DIR;                /*!< Specifies if the data will be transferred from memory to peripheral, 
+                                        from memory to memory or from peripheral to memory.
+                                        This parameter can be a value of @ref DMA_data_transfer_direction */
+
+  uint32_t DMA_BufferSize;         /*!< Specifies the buffer size, in data unit, of the specified Stream. 
+                                        The data unit is equal to the configuration set in DMA_PeripheralDataSize
+                                        or DMA_MemoryDataSize members depending in the transfer direction. */
+
+  uint32_t DMA_PeripheralInc;      /*!< Specifies whether the Peripheral address register should be incremented or not.
+                                        This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+  uint32_t DMA_MemoryInc;          /*!< Specifies whether the memory address register should be incremented or not.
+                                        This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+  uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
+                                        This parameter can be a value of @ref DMA_peripheral_data_size */
+
+  uint32_t DMA_MemoryDataSize;     /*!< Specifies the Memory data width.
+                                        This parameter can be a value of @ref DMA_memory_data_size */
+
+  uint32_t DMA_Mode;               /*!< Specifies the operation mode of the DMAy Streamx.
+                                        This parameter can be a value of @ref DMA_circular_normal_mode
+                                        @note The circular buffer mode cannot be used if the memory-to-memory
+                                              data transfer is configured on the selected Stream */
+
+  uint32_t DMA_Priority;           /*!< Specifies the software priority for the DMAy Streamx.
+                                        This parameter can be a value of @ref DMA_priority_level */
+
+  uint32_t DMA_FIFOMode;          /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream.
+                                        This parameter can be a value of @ref DMA_fifo_direct_mode
+                                        @note The Direct mode (FIFO mode disabled) cannot be used if the 
+                                               memory-to-memory data transfer is configured on the selected Stream */
+
+  uint32_t DMA_FIFOThreshold;      /*!< Specifies the FIFO threshold level.
+                                        This parameter can be a value of @ref DMA_fifo_threshold_level */
+
+  uint32_t DMA_MemoryBurst;        /*!< Specifies the Burst transfer configuration for the memory transfers. 
+                                        It specifies the amount of data to be transferred in a single non interruptable 
+                                        transaction. This parameter can be a value of @ref DMA_memory_burst 
+                                        @note The burst mode is possible only if the address Increment mode is enabled. */
+
+  uint32_t DMA_PeripheralBurst;    /*!< Specifies the Burst transfer configuration for the peripheral transfers. 
+                                        It specifies the amount of data to be transferred in a single non interruptable 
+                                        transaction. This parameter can be a value of @ref DMA_peripheral_burst
+                                        @note The burst mode is possible only if the address Increment mode is enabled. */  
+}DMA_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants
+  * @{
+  */
+
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \
+                                   ((PERIPH) == DMA1_Stream1) || \
+                                   ((PERIPH) == DMA1_Stream2) || \
+                                   ((PERIPH) == DMA1_Stream3) || \
+                                   ((PERIPH) == DMA1_Stream4) || \
+                                   ((PERIPH) == DMA1_Stream5) || \
+                                   ((PERIPH) == DMA1_Stream6) || \
+                                   ((PERIPH) == DMA1_Stream7) || \
+                                   ((PERIPH) == DMA2_Stream0) || \
+                                   ((PERIPH) == DMA2_Stream1) || \
+                                   ((PERIPH) == DMA2_Stream2) || \
+                                   ((PERIPH) == DMA2_Stream3) || \
+                                   ((PERIPH) == DMA2_Stream4) || \
+                                   ((PERIPH) == DMA2_Stream5) || \
+                                   ((PERIPH) == DMA2_Stream6) || \
+                                   ((PERIPH) == DMA2_Stream7))
+
+#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \
+                                           ((CONTROLLER) == DMA2))
+
+/** @defgroup DMA_channel 
+  * @{
+  */ 
+#define DMA_Channel_0                     ((uint32_t)0x00000000)
+#define DMA_Channel_1                     ((uint32_t)0x02000000)
+#define DMA_Channel_2                     ((uint32_t)0x04000000)
+#define DMA_Channel_3                     ((uint32_t)0x06000000)
+#define DMA_Channel_4                     ((uint32_t)0x08000000)
+#define DMA_Channel_5                     ((uint32_t)0x0A000000)
+#define DMA_Channel_6                     ((uint32_t)0x0C000000)
+#define DMA_Channel_7                     ((uint32_t)0x0E000000)
+
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \
+                                 ((CHANNEL) == DMA_Channel_1) || \
+                                 ((CHANNEL) == DMA_Channel_2) || \
+                                 ((CHANNEL) == DMA_Channel_3) || \
+                                 ((CHANNEL) == DMA_Channel_4) || \
+                                 ((CHANNEL) == DMA_Channel_5) || \
+                                 ((CHANNEL) == DMA_Channel_6) || \
+                                 ((CHANNEL) == DMA_Channel_7))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_data_transfer_direction 
+  * @{
+  */ 
+#define DMA_DIR_PeripheralToMemory        ((uint32_t)0x00000000)
+#define DMA_DIR_MemoryToPeripheral        ((uint32_t)0x00000040) 
+#define DMA_DIR_MemoryToMemory            ((uint32_t)0x00000080)
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \
+                                     ((DIRECTION) == DMA_DIR_MemoryToPeripheral)  || \
+                                     ((DIRECTION) == DMA_DIR_MemoryToMemory)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_data_buffer_size 
+  * @{
+  */ 
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_peripheral_incremented_mode 
+  * @{
+  */ 
+#define DMA_PeripheralInc_Enable          ((uint32_t)0x00000200)
+#define DMA_PeripheralInc_Disable         ((uint32_t)0x00000000)
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
+                                            ((STATE) == DMA_PeripheralInc_Disable))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_memory_incremented_mode 
+  * @{
+  */ 
+#define DMA_MemoryInc_Enable              ((uint32_t)0x00000400)
+#define DMA_MemoryInc_Disable             ((uint32_t)0x00000000)
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
+                                        ((STATE) == DMA_MemoryInc_Disable))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_peripheral_data_size 
+  * @{
+  */ 
+#define DMA_PeripheralDataSize_Byte       ((uint32_t)0x00000000) 
+#define DMA_PeripheralDataSize_HalfWord   ((uint32_t)0x00000800) 
+#define DMA_PeripheralDataSize_Word       ((uint32_t)0x00001000)
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte)  || \
+                                           ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
+                                           ((SIZE) == DMA_PeripheralDataSize_Word))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_memory_data_size 
+  * @{
+  */ 
+#define DMA_MemoryDataSize_Byte           ((uint32_t)0x00000000) 
+#define DMA_MemoryDataSize_HalfWord       ((uint32_t)0x00002000) 
+#define DMA_MemoryDataSize_Word           ((uint32_t)0x00004000)
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte)  || \
+                                       ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
+                                       ((SIZE) == DMA_MemoryDataSize_Word ))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_circular_normal_mode 
+  * @{
+  */ 
+#define DMA_Mode_Normal                   ((uint32_t)0x00000000) 
+#define DMA_Mode_Circular                 ((uint32_t)0x00000100)
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \
+                           ((MODE) == DMA_Mode_Circular)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_priority_level 
+  * @{
+  */ 
+#define DMA_Priority_Low                  ((uint32_t)0x00000000)
+#define DMA_Priority_Medium               ((uint32_t)0x00010000) 
+#define DMA_Priority_High                 ((uint32_t)0x00020000)
+#define DMA_Priority_VeryHigh             ((uint32_t)0x00030000)
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low )   || \
+                                   ((PRIORITY) == DMA_Priority_Medium) || \
+                                   ((PRIORITY) == DMA_Priority_High)   || \
+                                   ((PRIORITY) == DMA_Priority_VeryHigh)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_fifo_direct_mode 
+  * @{
+  */ 
+#define DMA_FIFOMode_Disable              ((uint32_t)0x00000000) 
+#define DMA_FIFOMode_Enable               ((uint32_t)0x00000004)
+
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \
+                                       ((STATE) == DMA_FIFOMode_Enable)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_fifo_threshold_level 
+  * @{
+  */ 
+#define DMA_FIFOThreshold_1QuarterFull    ((uint32_t)0x00000000)
+#define DMA_FIFOThreshold_HalfFull        ((uint32_t)0x00000001) 
+#define DMA_FIFOThreshold_3QuartersFull   ((uint32_t)0x00000002)
+#define DMA_FIFOThreshold_Full            ((uint32_t)0x00000003)
+
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \
+                                          ((THRESHOLD) == DMA_FIFOThreshold_HalfFull)      || \
+                                          ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \
+                                          ((THRESHOLD) == DMA_FIFOThreshold_Full)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_memory_burst 
+  * @{
+  */ 
+#define DMA_MemoryBurst_Single            ((uint32_t)0x00000000)
+#define DMA_MemoryBurst_INC4              ((uint32_t)0x00800000)  
+#define DMA_MemoryBurst_INC8              ((uint32_t)0x01000000)
+#define DMA_MemoryBurst_INC16             ((uint32_t)0x01800000)
+
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \
+                                    ((BURST) == DMA_MemoryBurst_INC4)  || \
+                                    ((BURST) == DMA_MemoryBurst_INC8)  || \
+                                    ((BURST) == DMA_MemoryBurst_INC16))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_peripheral_burst 
+  * @{
+  */ 
+#define DMA_PeripheralBurst_Single        ((uint32_t)0x00000000)
+#define DMA_PeripheralBurst_INC4          ((uint32_t)0x00200000)  
+#define DMA_PeripheralBurst_INC8          ((uint32_t)0x00400000)
+#define DMA_PeripheralBurst_INC16         ((uint32_t)0x00600000)
+
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \
+                                        ((BURST) == DMA_PeripheralBurst_INC4)  || \
+                                        ((BURST) == DMA_PeripheralBurst_INC8)  || \
+                                        ((BURST) == DMA_PeripheralBurst_INC16))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_fifo_status_level 
+  * @{
+  */
+#define DMA_FIFOStatus_Less1QuarterFull   ((uint32_t)0x00000000 << 3)
+#define DMA_FIFOStatus_1QuarterFull       ((uint32_t)0x00000001 << 3)
+#define DMA_FIFOStatus_HalfFull           ((uint32_t)0x00000002 << 3) 
+#define DMA_FIFOStatus_3QuartersFull      ((uint32_t)0x00000003 << 3)
+#define DMA_FIFOStatus_Empty              ((uint32_t)0x00000004 << 3)
+#define DMA_FIFOStatus_Full               ((uint32_t)0x00000005 << 3)
+
+#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \
+                                    ((STATUS) == DMA_FIFOStatus_HalfFull)          || \
+                                    ((STATUS) == DMA_FIFOStatus_1QuarterFull)      || \
+                                    ((STATUS) == DMA_FIFOStatus_3QuartersFull)     || \
+                                    ((STATUS) == DMA_FIFOStatus_Full)              || \
+                                    ((STATUS) == DMA_FIFOStatus_Empty)) 
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_flags_definition 
+  * @{
+  */
+#define DMA_FLAG_FEIF0                    ((uint32_t)0x10800001)
+#define DMA_FLAG_DMEIF0                   ((uint32_t)0x10800004)
+#define DMA_FLAG_TEIF0                    ((uint32_t)0x10000008)
+#define DMA_FLAG_HTIF0                    ((uint32_t)0x10000010)
+#define DMA_FLAG_TCIF0                    ((uint32_t)0x10000020)
+#define DMA_FLAG_FEIF1                    ((uint32_t)0x10000040)
+#define DMA_FLAG_DMEIF1                   ((uint32_t)0x10000100)
+#define DMA_FLAG_TEIF1                    ((uint32_t)0x10000200)
+#define DMA_FLAG_HTIF1                    ((uint32_t)0x10000400)
+#define DMA_FLAG_TCIF1                    ((uint32_t)0x10000800)
+#define DMA_FLAG_FEIF2                    ((uint32_t)0x10010000)
+#define DMA_FLAG_DMEIF2                   ((uint32_t)0x10040000)
+#define DMA_FLAG_TEIF2                    ((uint32_t)0x10080000)
+#define DMA_FLAG_HTIF2                    ((uint32_t)0x10100000)
+#define DMA_FLAG_TCIF2                    ((uint32_t)0x10200000)
+#define DMA_FLAG_FEIF3                    ((uint32_t)0x10400000)
+#define DMA_FLAG_DMEIF3                   ((uint32_t)0x11000000)
+#define DMA_FLAG_TEIF3                    ((uint32_t)0x12000000)
+#define DMA_FLAG_HTIF3                    ((uint32_t)0x14000000)
+#define DMA_FLAG_TCIF3                    ((uint32_t)0x18000000)
+#define DMA_FLAG_FEIF4                    ((uint32_t)0x20000001)
+#define DMA_FLAG_DMEIF4                   ((uint32_t)0x20000004)
+#define DMA_FLAG_TEIF4                    ((uint32_t)0x20000008)
+#define DMA_FLAG_HTIF4                    ((uint32_t)0x20000010)
+#define DMA_FLAG_TCIF4                    ((uint32_t)0x20000020)
+#define DMA_FLAG_FEIF5                    ((uint32_t)0x20000040)
+#define DMA_FLAG_DMEIF5                   ((uint32_t)0x20000100)
+#define DMA_FLAG_TEIF5                    ((uint32_t)0x20000200)
+#define DMA_FLAG_HTIF5                    ((uint32_t)0x20000400)
+#define DMA_FLAG_TCIF5                    ((uint32_t)0x20000800)
+#define DMA_FLAG_FEIF6                    ((uint32_t)0x20010000)
+#define DMA_FLAG_DMEIF6                   ((uint32_t)0x20040000)
+#define DMA_FLAG_TEIF6                    ((uint32_t)0x20080000)
+#define DMA_FLAG_HTIF6                    ((uint32_t)0x20100000)
+#define DMA_FLAG_TCIF6                    ((uint32_t)0x20200000)
+#define DMA_FLAG_FEIF7                    ((uint32_t)0x20400000)
+#define DMA_FLAG_DMEIF7                   ((uint32_t)0x21000000)
+#define DMA_FLAG_TEIF7                    ((uint32_t)0x22000000)
+#define DMA_FLAG_HTIF7                    ((uint32_t)0x24000000)
+#define DMA_FLAG_TCIF7                    ((uint32_t)0x28000000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \
+                                 (((FLAG) & 0xC002F082) == 0x00) && ((FLAG) != 0x00))
+
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0)  || ((FLAG) == DMA_FLAG_HTIF0)  || \
+                               ((FLAG) == DMA_FLAG_TEIF0)  || ((FLAG) == DMA_FLAG_DMEIF0) || \
+                               ((FLAG) == DMA_FLAG_FEIF0)  || ((FLAG) == DMA_FLAG_TCIF1)  || \
+                               ((FLAG) == DMA_FLAG_HTIF1)  || ((FLAG) == DMA_FLAG_TEIF1)  || \
+                               ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1)  || \
+                               ((FLAG) == DMA_FLAG_TCIF2)  || ((FLAG) == DMA_FLAG_HTIF2)  || \
+                               ((FLAG) == DMA_FLAG_TEIF2)  || ((FLAG) == DMA_FLAG_DMEIF2) || \
+                               ((FLAG) == DMA_FLAG_FEIF2)  || ((FLAG) == DMA_FLAG_TCIF3)  || \
+                               ((FLAG) == DMA_FLAG_HTIF3)  || ((FLAG) == DMA_FLAG_TEIF3)  || \
+                               ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3)  || \
+                               ((FLAG) == DMA_FLAG_TCIF4)  || ((FLAG) == DMA_FLAG_HTIF4)  || \
+                               ((FLAG) == DMA_FLAG_TEIF4)  || ((FLAG) == DMA_FLAG_DMEIF4) || \
+                               ((FLAG) == DMA_FLAG_FEIF4)  || ((FLAG) == DMA_FLAG_TCIF5)  || \
+                               ((FLAG) == DMA_FLAG_HTIF5)  || ((FLAG) == DMA_FLAG_TEIF5)  || \
+                               ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5)  || \
+                               ((FLAG) == DMA_FLAG_TCIF6)  || ((FLAG) == DMA_FLAG_HTIF6)  || \
+                               ((FLAG) == DMA_FLAG_TEIF6)  || ((FLAG) == DMA_FLAG_DMEIF6) || \
+                               ((FLAG) == DMA_FLAG_FEIF6)  || ((FLAG) == DMA_FLAG_TCIF7)  || \
+                               ((FLAG) == DMA_FLAG_HTIF7)  || ((FLAG) == DMA_FLAG_TEIF7)  || \
+                               ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_interrupt_enable_definitions 
+  * @{
+  */ 
+#define DMA_IT_TC                         ((uint32_t)0x00000010)
+#define DMA_IT_HT                         ((uint32_t)0x00000008)
+#define DMA_IT_TE                         ((uint32_t)0x00000004)
+#define DMA_IT_DME                        ((uint32_t)0x00000002)
+#define DMA_IT_FE                         ((uint32_t)0x00000080)
+
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_interrupts_definitions 
+  * @{
+  */ 
+#define DMA_IT_FEIF0                      ((uint32_t)0x90000001)
+#define DMA_IT_DMEIF0                     ((uint32_t)0x10001004)
+#define DMA_IT_TEIF0                      ((uint32_t)0x10002008)
+#define DMA_IT_HTIF0                      ((uint32_t)0x10004010)
+#define DMA_IT_TCIF0                      ((uint32_t)0x10008020)
+#define DMA_IT_FEIF1                      ((uint32_t)0x90000040)
+#define DMA_IT_DMEIF1                     ((uint32_t)0x10001100)
+#define DMA_IT_TEIF1                      ((uint32_t)0x10002200)
+#define DMA_IT_HTIF1                      ((uint32_t)0x10004400)
+#define DMA_IT_TCIF1                      ((uint32_t)0x10008800)
+#define DMA_IT_FEIF2                      ((uint32_t)0x90010000)
+#define DMA_IT_DMEIF2                     ((uint32_t)0x10041000)
+#define DMA_IT_TEIF2                      ((uint32_t)0x10082000)
+#define DMA_IT_HTIF2                      ((uint32_t)0x10104000)
+#define DMA_IT_TCIF2                      ((uint32_t)0x10208000)
+#define DMA_IT_FEIF3                      ((uint32_t)0x90400000)
+#define DMA_IT_DMEIF3                     ((uint32_t)0x11001000)
+#define DMA_IT_TEIF3                      ((uint32_t)0x12002000)
+#define DMA_IT_HTIF3                      ((uint32_t)0x14004000)
+#define DMA_IT_TCIF3                      ((uint32_t)0x18008000)
+#define DMA_IT_FEIF4                      ((uint32_t)0xA0000001)
+#define DMA_IT_DMEIF4                     ((uint32_t)0x20001004)
+#define DMA_IT_TEIF4                      ((uint32_t)0x20002008)
+#define DMA_IT_HTIF4                      ((uint32_t)0x20004010)
+#define DMA_IT_TCIF4                      ((uint32_t)0x20008020)
+#define DMA_IT_FEIF5                      ((uint32_t)0xA0000040)
+#define DMA_IT_DMEIF5                     ((uint32_t)0x20001100)
+#define DMA_IT_TEIF5                      ((uint32_t)0x20002200)
+#define DMA_IT_HTIF5                      ((uint32_t)0x20004400)
+#define DMA_IT_TCIF5                      ((uint32_t)0x20008800)
+#define DMA_IT_FEIF6                      ((uint32_t)0xA0010000)
+#define DMA_IT_DMEIF6                     ((uint32_t)0x20041000)
+#define DMA_IT_TEIF6                      ((uint32_t)0x20082000)
+#define DMA_IT_HTIF6                      ((uint32_t)0x20104000)
+#define DMA_IT_TCIF6                      ((uint32_t)0x20208000)
+#define DMA_IT_FEIF7                      ((uint32_t)0xA0400000)
+#define DMA_IT_DMEIF7                     ((uint32_t)0x21001000)
+#define DMA_IT_TEIF7                      ((uint32_t)0x22002000)
+#define DMA_IT_HTIF7                      ((uint32_t)0x24004000)
+#define DMA_IT_TCIF7                      ((uint32_t)0x28008000)
+
+#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \
+                             (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \
+                             (((IT) & 0x40820082) == 0x00))
+
+#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0)  || \
+                           ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \
+                           ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1)  || \
+                           ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1)  || \
+                           ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1)  || \
+                           ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2)  || \
+                           ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \
+                           ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3)  || \
+                           ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3)  || \
+                           ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3)  || \
+                           ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4)  || \
+                           ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \
+                           ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5)  || \
+                           ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5)  || \
+                           ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5)  || \
+                           ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6)  || \
+                           ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \
+                           ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7)  || \
+                           ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7)  || \
+                           ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_peripheral_increment_offset 
+  * @{
+  */ 
+#define DMA_PINCOS_Psize                  ((uint32_t)0x00000000)
+#define DMA_PINCOS_WordAligned            ((uint32_t)0x00008000)
+
+#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \
+                                  ((SIZE) == DMA_PINCOS_WordAligned))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_flow_controller_definitions 
+  * @{
+  */ 
+#define DMA_FlowCtrl_Memory               ((uint32_t)0x00000000)
+#define DMA_FlowCtrl_Peripheral           ((uint32_t)0x00000020)
+
+#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \
+                                ((CTRL) == DMA_FlowCtrl_Peripheral))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_memory_targets_definitions 
+  * @{
+  */ 
+#define DMA_Memory_0                      ((uint32_t)0x00000000)
+#define DMA_Memory_1                      ((uint32_t)0x00080000)
+
+#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/*  Function used to set the DMA configuration to the default reset state *****/ 
+void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx);
+
+/* Initialization and Configuration functions *********************************/
+void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
+
+/* Optional Configuration functions *******************************************/
+void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos);
+void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl);
+
+/* Data Counter functions *****************************************************/
+void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
+uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
+
+/* Double Buffer mode functions ***********************************************/
+void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
+                                uint32_t DMA_CurrentMemory);
+void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
+void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
+                            uint32_t DMA_MemoryTarget);
+uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
+
+/* Interrupts and flags management functions **********************************/
+FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);
+uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);
+FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
+void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
+void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
+ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
+void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_DMA_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

底盘/底盘-old/底盘/Library/stm32f4xx_dma2d.c

@@ -0,0 +1,776 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_dma2d.c
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the DMA2D controller (DMA2D) peripheral:
+  *           + Initialization and configuration
+  *           + Interrupts and flags management
+  *           
+  @verbatim  
+ ===============================================================================
+                      ##### How to use this driver #####
+ ===============================================================================
+    [..]
+        (#) Enable DMA2D clock using 
+            RCC_APB2PeriphResetCmd(RCC_APB2Periph_DMA2D, ENABLE) function.
+            
+        (#) Configures DMA2D
+          (++) transfer mode 
+          (++) pixel format, line_number, pixel_per_line
+          (++) output memory address
+          (++) alpha value
+          (++) output offset
+          (++) Default color (RGB)
+           
+        (#) Configures Foreground or/and background
+          (++) memory address
+          (++) alpha value
+          (++) offset and default color
+  
+        (#) Call the DMA2D_Start() to enable the DMA2D controller.
+        
+    @endverbatim
+  
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_dma2d.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DMA2D 
+  * @brief DMA2D driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+#define CR_MASK                     ((uint32_t)0xFFFCE0FC)  /* DMA2D CR Mask */
+#define PFCCR_MASK                  ((uint32_t)0x00FC00C0)  /* DMA2D FGPFCCR Mask */
+#define DEAD_MASK                   ((uint32_t)0xFFFF00FE)  /* DMA2D DEAD Mask */
+
+/** @defgroup DMA2D_Private_Functions
+  * @{
+  */
+
+/** @defgroup DMA2D_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim
+ ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the DMA2D
+      (+) Start/Abort/Suspend Transfer
+      (+) Initialize, configure and set Foreground and background
+      (+) configure and enable DeadTime
+      (+) configure lineWatermark
+    
+    
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the DMA2D peripheral registers to their default reset
+  *         values.
+  * @param  None
+  * @retval None
+  */
+
+void DMA2D_DeInit(void)
+{
+  /* Enable DMA2D reset state */
+  RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2D, ENABLE);
+  /* Release DMA2D from reset state */
+  RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2D, DISABLE);
+}
+
+
+/**
+  * @brief  Initializes the DMA2D peripheral according to the specified parameters
+  *         in the DMA2D_InitStruct.
+  * @note   This function can be used only when the DMA2D is disabled.
+  * @param  DMA2D_InitStruct: pointer to a DMA2D_InitTypeDef structure that contains
+  *         the configuration information for the specified DMA2D peripheral.
+  * @retval None
+  */
+void DMA2D_Init(DMA2D_InitTypeDef* DMA2D_InitStruct)
+{
+
+  uint32_t outgreen = 0;
+  uint32_t outred   = 0;
+  uint32_t outalpha = 0;
+  uint32_t pixline  = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_MODE(DMA2D_InitStruct->DMA2D_Mode));
+  assert_param(IS_DMA2D_CMODE(DMA2D_InitStruct->DMA2D_CMode));
+  assert_param(IS_DMA2D_OGREEN(DMA2D_InitStruct->DMA2D_OutputGreen));
+  assert_param(IS_DMA2D_ORED(DMA2D_InitStruct->DMA2D_OutputRed));
+  assert_param(IS_DMA2D_OBLUE(DMA2D_InitStruct->DMA2D_OutputBlue));
+  assert_param(IS_DMA2D_OALPHA(DMA2D_InitStruct->DMA2D_OutputAlpha));
+  assert_param(IS_DMA2D_OUTPUT_OFFSET(DMA2D_InitStruct->DMA2D_OutputOffset));
+  assert_param(IS_DMA2D_LINE(DMA2D_InitStruct->DMA2D_NumberOfLine));
+  assert_param(IS_DMA2D_PIXEL(DMA2D_InitStruct->DMA2D_PixelPerLine));
+
+  /* Configures the DMA2D operation mode */
+  DMA2D->CR &= (uint32_t)CR_MASK;
+  DMA2D->CR |= (DMA2D_InitStruct->DMA2D_Mode);
+
+  /* Configures the color mode of the output image */
+  DMA2D->OPFCCR &= ~(uint32_t)DMA2D_OPFCCR_CM;
+  DMA2D->OPFCCR |= (DMA2D_InitStruct->DMA2D_CMode);
+
+  /* Configures the output color */
+
+  if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_ARGB8888)
+  {
+    outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 8;
+    outred = DMA2D_InitStruct->DMA2D_OutputRed << 16;
+    outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 24;
+  }
+  else
+  
+    if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_RGB888)
+    {
+      outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 8;
+      outred = DMA2D_InitStruct->DMA2D_OutputRed << 16;
+      outalpha = (uint32_t)0x00000000;
+    }
+     
+  else
+
+    if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_RGB565)
+    {
+      outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 5;
+      outred = DMA2D_InitStruct->DMA2D_OutputRed << 11;
+      outalpha = (uint32_t)0x00000000;
+    }
+
+  else
+
+    if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_ARGB1555)
+    {  
+      outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 5;
+      outred = DMA2D_InitStruct->DMA2D_OutputRed << 10;
+      outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 15;
+    }
+
+  else /* DMA2D_CMode = DMA2D_ARGB4444 */
+  {
+    outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 4;
+    outred = DMA2D_InitStruct->DMA2D_OutputRed << 8;
+    outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 12;
+  }  
+  DMA2D->OCOLR = ((outgreen) | (outred) | (DMA2D_InitStruct->DMA2D_OutputBlue) | (outalpha));
+
+  /* Configures the output memory address */
+  DMA2D->OMAR = (DMA2D_InitStruct->DMA2D_OutputMemoryAdd);
+
+  /* Configure  the line Offset */
+  DMA2D->OOR &= ~(uint32_t)DMA2D_OOR_LO;
+  DMA2D->OOR |= (DMA2D_InitStruct->DMA2D_OutputOffset);
+
+  /* Configure the number of line and pixel per line */
+  pixline = DMA2D_InitStruct->DMA2D_PixelPerLine << 16; 
+  DMA2D->NLR &= ~(DMA2D_NLR_NL | DMA2D_NLR_PL);
+  DMA2D->NLR |= ((DMA2D_InitStruct->DMA2D_NumberOfLine) | (pixline));
+
+/**
+  * @brief  Fills each DMA2D_InitStruct member with its default value.
+  * @param  DMA2D_InitStruct: pointer to a DMA2D_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+}
+void DMA2D_StructInit(DMA2D_InitTypeDef* DMA2D_InitStruct)
+{
+  /* Initialize the transfer mode member */
+  DMA2D_InitStruct->DMA2D_Mode = DMA2D_M2M;
+
+  /* Initialize the output color mode members */
+  DMA2D_InitStruct->DMA2D_CMode = DMA2D_ARGB8888;
+
+  /* Initialize the alpha and RGB values */
+  DMA2D_InitStruct->DMA2D_OutputGreen = 0x00;
+  DMA2D_InitStruct->DMA2D_OutputBlue = 0x00;
+  DMA2D_InitStruct->DMA2D_OutputRed = 0x00;
+  DMA2D_InitStruct->DMA2D_OutputAlpha = 0x00;
+
+  /* Initialize the output memory address */
+  DMA2D_InitStruct->DMA2D_OutputMemoryAdd = 0x00;
+
+  /* Initialize the output offset */
+  DMA2D_InitStruct->DMA2D_OutputOffset = 0x00;
+
+  /* Initialize the number of line and the number of pixel per line */
+  DMA2D_InitStruct->DMA2D_NumberOfLine = 0x00;
+  DMA2D_InitStruct->DMA2D_PixelPerLine = 0x00;
+}
+
+/**
+  * @brief  Start the DMA2D transfer.
+  * @param 
+  * @retval None
+  */
+
+void DMA2D_StartTransfer(void)
+{
+    /* Start DMA2D transfer by setting START bit */
+    DMA2D->CR |= (uint32_t)DMA2D_CR_START;
+}
+
+/**
+  * @brief  Abort the DMA2D transfer.
+  * @param
+  * @retval None
+  */
+
+void DMA2D_AbortTransfer(void)
+{
+    /* Start DMA2D transfer by setting START bit */
+    DMA2D->CR |= (uint32_t)DMA2D_CR_ABORT;
+
+}
+
+/**
+  * @brief  Stop or continue the DMA2D transfer.
+  * @param  NewState: new state of the DMA2D peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DMA2D_Suspend(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Suspend DMA2D transfer by setting STOP bit */
+    DMA2D->CR |= (uint32_t)DMA2D_CR_SUSP;
+  }
+  else
+  {
+    /* Continue DMA2D transfer by clearing STOP bit */
+    DMA2D->CR &= ~(uint32_t)DMA2D_CR_SUSP;
+  }
+}
+
+/**
+  * @brief  Configures the Foreground according to the specified parameters
+  *         in the DMA2D_FGStruct.
+  * @note   This function can be used only when the transfer is disabled.
+  * @param  DMA2D_FGStruct: pointer to a DMA2D_FGTypeDef structure that contains
+  *         the configuration information for the specified Background.
+  * @retval None
+  */
+void DMA2D_FGConfig(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct)
+{
+
+  uint32_t fg_clutcolormode = 0;
+  uint32_t fg_clutsize = 0;
+  uint32_t fg_alpha_mode = 0;
+  uint32_t fg_alphavalue = 0;
+  uint32_t fg_colorgreen = 0;
+  uint32_t fg_colorred = 0;
+
+  assert_param(IS_DMA2D_FGO(DMA2D_FG_InitStruct->DMA2D_FGO));
+  assert_param(IS_DMA2D_FGCM(DMA2D_FG_InitStruct->DMA2D_FGCM));
+  assert_param(IS_DMA2D_FG_CLUT_CM(DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM));
+  assert_param(IS_DMA2D_FG_CLUT_SIZE(DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE));
+  assert_param(IS_DMA2D_FG_ALPHA_MODE(DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE));
+  assert_param(IS_DMA2D_FG_ALPHA_VALUE(DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE));
+  assert_param(IS_DMA2D_FGC_BLUE(DMA2D_FG_InitStruct->DMA2D_FGC_BLUE));
+  assert_param(IS_DMA2D_FGC_GREEN(DMA2D_FG_InitStruct->DMA2D_FGC_GREEN));
+  assert_param(IS_DMA2D_FGC_RED(DMA2D_FG_InitStruct->DMA2D_FGC_RED));
+
+  /* Configures the FG memory address */
+  DMA2D->FGMAR = (DMA2D_FG_InitStruct->DMA2D_FGMA);
+
+  /* Configures the FG offset */
+  DMA2D->FGOR &= ~(uint32_t)DMA2D_FGOR_LO;
+  DMA2D->FGOR |= (DMA2D_FG_InitStruct->DMA2D_FGO);
+
+  /* Configures foreground Pixel Format Convertor */
+  DMA2D->FGPFCCR &= (uint32_t)PFCCR_MASK;
+  fg_clutcolormode = DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM << 4;
+  fg_clutsize = DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE << 8;
+  fg_alpha_mode = DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE << 16;
+  fg_alphavalue = DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE << 24;
+  DMA2D->FGPFCCR |= (DMA2D_FG_InitStruct->DMA2D_FGCM | fg_clutcolormode | fg_clutsize | \
+                    fg_alpha_mode | fg_alphavalue);
+
+  /* Configures foreground color */
+  DMA2D->FGCOLR &= ~(DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_RED);
+  fg_colorgreen = DMA2D_FG_InitStruct->DMA2D_FGC_GREEN << 8;
+  fg_colorred = DMA2D_FG_InitStruct->DMA2D_FGC_RED << 16;
+  DMA2D->FGCOLR |= (DMA2D_FG_InitStruct->DMA2D_FGC_BLUE | fg_colorgreen | fg_colorred);
+
+  /* Configures foreground CLUT memory address */
+  DMA2D->FGCMAR = DMA2D_FG_InitStruct->DMA2D_FGCMAR;
+}
+
+/**
+  * @brief  Fills each DMA2D_FGStruct member with its default value.
+  * @param  DMA2D_FGStruct: pointer to a DMA2D_FGTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void DMA2D_FG_StructInit(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct)
+{
+  /*!< Initialize the DMA2D foreground memory address */
+  DMA2D_FG_InitStruct->DMA2D_FGMA = 0x00;
+
+  /*!< Initialize the DMA2D foreground offset */
+  DMA2D_FG_InitStruct->DMA2D_FGO = 0x00;
+
+  /*!< Initialize the DMA2D foreground color mode */
+  DMA2D_FG_InitStruct->DMA2D_FGCM = CM_ARGB8888;
+
+  /*!< Initialize the DMA2D foreground CLUT color mode */
+  DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM = CLUT_CM_ARGB8888;
+
+  /*!< Initialize the DMA2D foreground CLUT size */
+  DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE = 0x00;
+
+  /*!< Initialize the DMA2D foreground alpha mode */
+  DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE;
+
+  /*!< Initialize the DMA2D foreground alpha value */
+  DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE = 0x00;
+
+  /*!< Initialize the DMA2D foreground blue value */
+  DMA2D_FG_InitStruct->DMA2D_FGC_BLUE = 0x00;
+
+  /*!< Initialize the DMA2D foreground green value */
+  DMA2D_FG_InitStruct->DMA2D_FGC_GREEN = 0x00;
+
+  /*!< Initialize the DMA2D foreground red value */
+  DMA2D_FG_InitStruct->DMA2D_FGC_RED = 0x00;
+
+  /*!< Initialize the DMA2D foreground CLUT memory address */
+  DMA2D_FG_InitStruct->DMA2D_FGCMAR = 0x00;
+}
+
+
+/**
+  * @brief  Configures the Background according to the specified parameters
+  *         in the DMA2D_BGStruct.
+  * @note   This function can be used only when the transfer is disabled.
+  * @param  DMA2D_BGStruct: pointer to a DMA2D_BGTypeDef structure that contains
+  *         the configuration information for the specified Background.
+  * @retval None
+  */
+void DMA2D_BGConfig(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct)
+{
+
+  uint32_t bg_clutcolormode = 0;
+  uint32_t bg_clutsize = 0;
+  uint32_t bg_alpha_mode = 0;
+  uint32_t bg_alphavalue = 0;
+  uint32_t bg_colorgreen = 0;
+  uint32_t bg_colorred = 0;
+
+  assert_param(IS_DMA2D_BGO(DMA2D_BG_InitStruct->DMA2D_BGO));
+  assert_param(IS_DMA2D_BGCM(DMA2D_BG_InitStruct->DMA2D_BGCM));
+  assert_param(IS_DMA2D_BG_CLUT_CM(DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM));
+  assert_param(IS_DMA2D_BG_CLUT_SIZE(DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE));
+  assert_param(IS_DMA2D_BG_ALPHA_MODE(DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE));
+  assert_param(IS_DMA2D_BG_ALPHA_VALUE(DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE));
+  assert_param(IS_DMA2D_BGC_BLUE(DMA2D_BG_InitStruct->DMA2D_BGC_BLUE));
+  assert_param(IS_DMA2D_BGC_GREEN(DMA2D_BG_InitStruct->DMA2D_BGC_GREEN));
+  assert_param(IS_DMA2D_BGC_RED(DMA2D_BG_InitStruct->DMA2D_BGC_RED));
+
+  /* Configures the BG memory address */
+  DMA2D->BGMAR = (DMA2D_BG_InitStruct->DMA2D_BGMA);
+
+  /* Configures the BG offset */
+  DMA2D->BGOR &= ~(uint32_t)DMA2D_BGOR_LO;
+  DMA2D->BGOR |= (DMA2D_BG_InitStruct->DMA2D_BGO);
+
+  /* Configures background Pixel Format Convertor */
+  DMA2D->BGPFCCR &= (uint32_t)PFCCR_MASK;
+  bg_clutcolormode = DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM << 4;
+  bg_clutsize = DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE << 8;
+  bg_alpha_mode = DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE << 16;
+  bg_alphavalue = DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE << 24;
+  DMA2D->BGPFCCR |= (DMA2D_BG_InitStruct->DMA2D_BGCM | bg_clutcolormode | bg_clutsize | \
+                    bg_alpha_mode | bg_alphavalue);
+
+  /* Configures background color */
+  DMA2D->BGCOLR &= ~(DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_RED);
+  bg_colorgreen = DMA2D_BG_InitStruct->DMA2D_BGC_GREEN << 8;
+  bg_colorred = DMA2D_BG_InitStruct->DMA2D_BGC_RED << 16;
+  DMA2D->BGCOLR |= (DMA2D_BG_InitStruct->DMA2D_BGC_BLUE | bg_colorgreen | bg_colorred);
+  
+  /* Configures background CLUT memory address */
+  DMA2D->BGCMAR = DMA2D_BG_InitStruct->DMA2D_BGCMAR;
+
+}
+
+/**
+  * @brief  Fills each DMA2D_BGStruct member with its default value.
+  * @param  DMA2D_BGStruct: pointer to a DMA2D_BGTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void DMA2D_BG_StructInit(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct)
+{
+  /*!< Initialize the DMA2D background memory address */
+  DMA2D_BG_InitStruct->DMA2D_BGMA = 0x00;
+
+  /*!< Initialize the DMA2D background offset */
+  DMA2D_BG_InitStruct->DMA2D_BGO = 0x00;
+
+  /*!< Initialize the DMA2D background color mode */
+  DMA2D_BG_InitStruct->DMA2D_BGCM = CM_ARGB8888;
+
+  /*!< Initialize the DMA2D background CLUT color mode */
+  DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM = CLUT_CM_ARGB8888;
+
+  /*!< Initialize the DMA2D background CLUT size */
+  DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE = 0x00;
+
+  /*!< Initialize the DMA2D background alpha mode */
+  DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE;
+
+  /*!< Initialize the DMA2D background alpha value */
+  DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE = 0x00;
+
+  /*!< Initialize the DMA2D background blue value */
+  DMA2D_BG_InitStruct->DMA2D_BGC_BLUE = 0x00;
+
+  /*!< Initialize the DMA2D background green value */
+  DMA2D_BG_InitStruct->DMA2D_BGC_GREEN = 0x00;
+
+  /*!< Initialize the DMA2D background red value */
+  DMA2D_BG_InitStruct->DMA2D_BGC_RED = 0x00;
+
+  /*!< Initialize the DMA2D background CLUT memory address */
+  DMA2D_BG_InitStruct->DMA2D_BGCMAR = 0x00;
+}
+
+/**
+  * @brief  Start the automatic loading of the CLUT or abort the transfer.
+  * @param  NewState: new state of the DMA2D peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+
+void DMA2D_FGStart(FunctionalState NewState) 
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Start the automatic loading of the CLUT */
+    DMA2D->FGPFCCR |= DMA2D_FGPFCCR_START;
+  }
+  else
+  {
+    /* abort the transfer */
+    DMA2D->FGPFCCR &= (uint32_t)~DMA2D_FGPFCCR_START;
+  }
+}
+
+/**
+  * @brief  Start the automatic loading of the CLUT or abort the transfer.
+  * @param  NewState: new state of the DMA2D peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+  
+void DMA2D_BGStart(FunctionalState NewState) 
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Start the automatic loading of the CLUT */
+    DMA2D->BGPFCCR |= DMA2D_BGPFCCR_START;
+  }
+  else
+  {
+    /* abort the transfer */
+    DMA2D->BGPFCCR &= (uint32_t)~DMA2D_BGPFCCR_START;
+  }
+}
+
+/**
+  * @brief  Configures the DMA2D dead time.
+  * @param  DMA2D_DeadTime: specifies the DMA2D dead time.
+  *   This parameter can be one of the following values:
+  * @retval None
+  */
+void DMA2D_DeadTimeConfig(uint32_t DMA2D_DeadTime, FunctionalState NewState)
+{
+   uint32_t DeadTime;
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_DEAD_TIME(DMA2D_DeadTime));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable and Configures the dead time */
+    DMA2D->AMTCR &= (uint32_t)DEAD_MASK;
+    DeadTime = DMA2D_DeadTime << 8;
+    DMA2D->AMTCR |= (DeadTime | DMA2D_AMTCR_EN);
+  }
+  else
+  {
+     DMA2D->AMTCR &= ~(uint32_t)DMA2D_AMTCR_EN;
+  }
+}
+
+/**
+  * @brief  Define the configuration of the line watermark .
+  * @param  DMA2D_LWatermarkConfig: Line Watermark configuration.
+  * @retval None
+  */
+
+void DMA2D_LineWatermarkConfig(uint32_t DMA2D_LWatermarkConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LineWatermark(DMA2D_LWatermarkConfig));
+
+  /* Sets the Line watermark configuration */
+  DMA2D->LWR = (uint32_t)DMA2D_LWatermarkConfig;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Group2 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================
+
+    [..] This section provides functions allowing to configure the DMA2D 
+         Interrupts and to get the status and clear flags and Interrupts 
+         pending bits.
+    [..] The DMA2D provides 6 Interrupts sources and 6 Flags
+    
+    *** Flags ***
+    =============
+    [..]
+      (+) DMA2D_FLAG_CE : Configuration Error Interrupt flag
+      (+) DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag
+      (+) DMA2D_FLAG_TW:  Transfer Watermark Interrupt flag
+      (+) DMA2D_FLAG_TC:  Transfer Complete interrupt flag
+      (+) DMA2D_FLAG_TE:  Transfer Error interrupt flag
+      (+) DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag
+      
+    *** Interrupts ***
+    ==================
+    [..]
+      (+) DMA2D_IT_CE: Configuration Error Interrupt is generated when a wrong 
+                       configuration is detected
+      (+) DMA2D_IT_CAE: CLUT Access Error Interrupt
+      (+) DMA2D_IT_TW: Transfer Watermark Interrupt is generated when 
+                       the programmed watermark is reached 
+      (+) DMA2D_IT_TE: Transfer Error interrupt is generated when the CPU trying 
+                       to access the CLUT while a CLUT loading or a DMA2D1 transfer 
+                       is on going       
+      (+) DMA2D_IT_CTC: CLUT Transfer Complete Interrupt 
+      (+) DMA2D_IT_TC: Transfer Complete interrupt         
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Enables or disables the specified DMA2D's interrupts.
+  * @param  DMA2D_IT: specifies the DMA2D interrupts sources to be enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg DMA2D_IT_CE:   Configuration Error Interrupt Enable.
+  *     @arg DMA2D_IT_CTC:  CLUT Transfer Complete Interrupt Enable.
+  *     @arg DMA2D_IT_CAE:  CLUT Access Error Interrupt Enable.
+  *     @arg DMA2D_IT_TW:   Transfer Watermark Interrupt Enable.
+  *     @arg DMA2D_IT_TC:   Transfer Complete interrupt enable.
+  *     @arg DMA2D_IT_TE:   Transfer Error interrupt enable.
+  * @param NewState: new state of the specified DMA2D interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+
+void DMA2D_ITConfig(uint32_t DMA2D_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_IT(DMA2D_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA2D interrupts */
+    DMA2D->CR |= DMA2D_IT;
+  }
+  else
+  {
+    /* Disable the selected DMA2D interrupts */
+    DMA2D->CR &= (uint32_t)~DMA2D_IT;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified DMA2D's flag is set or not.
+  * @param  DMA2D_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg DMA2D_FLAG_CE:   Configuration Error Interrupt flag.
+  *     @arg DMA2D_FLAG_CTC:  CLUT Transfer Complete Interrupt flag.
+  *     @arg DMA2D_FLAG_CAE:  CLUT Access Error Interrupt flag.
+  *     @arg DMA2D_FLAG_TW:   Transfer Watermark Interrupt flag.
+  *     @arg DMA2D_FLAG_TC:   Transfer Complete interrupt flag.
+  *     @arg DMA2D_FLAG_TE:   Transfer Error interrupt flag.
+  * @retval The new state of DMA2D_FLAG (SET or RESET).
+  */
+
+FlagStatus DMA2D_GetFlagStatus(uint32_t DMA2D_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA2D_GET_FLAG(DMA2D_FLAG));
+  
+  /* Check the status of the specified DMA2D flag */
+  if (((DMA2D->ISR) & DMA2D_FLAG) != (uint32_t)RESET)
+  {
+    /* DMA2D_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DMA2D_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DMA2D_FLAG status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the DMA2D's pending flags.
+  * @param  DMA2D_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg DMA2D_FLAG_CE:   Configuration Error Interrupt flag.
+  *     @arg DMA2D_FLAG_CTC:  CLUT Transfer Complete Interrupt flag.
+  *     @arg DMA2D_FLAG_CAE:  CLUT Access Error Interrupt flag.
+  *     @arg DMA2D_FLAG_TW:   Transfer Watermark Interrupt flag.
+  *     @arg DMA2D_FLAG_TC:   Transfer Complete interrupt flag.
+  *     @arg DMA2D_FLAG_TE:   Transfer Error interrupt flag.
+  * @retval None
+  */
+void DMA2D_ClearFlag(uint32_t DMA2D_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_GET_FLAG(DMA2D_FLAG));
+    
+  /* Clear the corresponding DMA2D flag */
+  DMA2D->IFCR = (uint32_t)DMA2D_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified DMA2D's interrupt has occurred or not.
+  * @param  DMA2D_IT: specifies the DMA2D interrupts sources to check.
+  *   This parameter can be one of the following values:
+  *     @arg DMA2D_IT_CE:   Configuration Error Interrupt Enable.
+  *     @arg DMA2D_IT_CTC:  CLUT Transfer Complete Interrupt Enable.
+  *     @arg DMA2D_IT_CAE:  CLUT Access Error Interrupt Enable.
+  *     @arg DMA2D_IT_TW:   Transfer Watermark Interrupt Enable.
+  *     @arg DMA2D_IT_TC:   Transfer Complete interrupt enable.
+  *     @arg DMA2D_IT_TE:   Transfer Error interrupt enable.
+  * @retval The new state of the DMA2D_IT (SET or RESET).
+  */
+ITStatus DMA2D_GetITStatus(uint32_t DMA2D_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t DMA2D_IT_FLAG = DMA2D_IT >> 8;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA2D_IT(DMA2D_IT));
+
+  if ((DMA2D->ISR & DMA2D_IT_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  
+  if (((DMA2D->CR & DMA2D_IT) != (uint32_t)RESET) && (bitstatus != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the DMA2D's interrupt pending bits.
+  * @param  DMA2D_IT: specifies the interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg DMA2D_IT_CE:   Configuration Error Interrupt.
+  *     @arg DMA2D_IT_CTC:  CLUT Transfer Complete Interrupt.
+  *     @arg DMA2D_IT_CAE:  CLUT Access Error Interrupt.
+  *     @arg DMA2D_IT_TW:   Transfer Watermark Interrupt.
+  *     @arg DMA2D_IT_TC:   Transfer Complete interrupt.
+  *     @arg DMA2D_IT_TE:   Transfer Error interrupt.
+  * @retval None
+  */
+void DMA2D_ClearITPendingBit(uint32_t DMA2D_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_IT(DMA2D_IT));
+  DMA2D_IT = DMA2D_IT >> 8;
+    
+  /* Clear the corresponding DMA2D Interrupt */
+  DMA2D->IFCR = (uint32_t)DMA2D_IT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

底盘/底盘-old/底盘/Library/stm32f4xx_dma2d.h

@@ -0,0 +1,467 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_dma2d.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the DMA2D firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_DMA2D_H
+#define __STM32F4xx_DMA2D_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DMA2D
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+ 
+/** 
+  * @brief  DMA2D Init structure definition  
+  */
+
+typedef struct
+{
+  uint32_t DMA2D_Mode;                           /*!< configures the DMA2D transfer mode.
+                                                 This parameter can be one value of @ref DMA2D_MODE */
+  
+  uint32_t DMA2D_CMode;                          /*!< configures the color format of the output image.
+                                                 This parameter can be one value of @ref DMA2D_CMODE */
+
+  uint32_t DMA2D_OutputBlue;                     /*!< configures the blue value of the output image. 
+                                                 This parameter must range:
+                                                 - from 0x00 to 0xFF if ARGB8888 color mode is slected
+                                                 - from 0x00 to 0xFF if RGB888 color mode is slected
+                                                 - from 0x00 to 0x1F if RGB565 color mode is slected
+                                                 - from 0x00 to 0x1F if ARGB1555 color mode is slected
+                                                 - from 0x00 to 0x0F if ARGB4444 color mode is slected  */
+
+  uint32_t DMA2D_OutputGreen;                    /*!< configures the green value of the output image. 
+                                                 This parameter must range:
+                                                 - from 0x00 to 0xFF if ARGB8888 color mode is selected
+                                                 - from 0x00 to 0xFF if RGB888 color mode is selected
+                                                 - from 0x00 to 0x2F if RGB565 color mode is selected
+                                                 - from 0x00 to 0x1F if ARGB1555 color mode is selected
+                                                 - from 0x00 to 0x0F if ARGB4444 color mode is selected  */
+            
+  uint32_t DMA2D_OutputRed;                      /*!< configures the red value of the output image. 
+                                                 This parameter must range:
+                                                 - from 0x00 to 0xFF if ARGB8888 color mode is slected
+                                                 - from 0x00 to 0xFF if RGB888 color mode is slected
+                                                 - from 0x00 to 0x1F if RGB565 color mode is slected
+                                                 - from 0x00 to 0x1F if ARGB1555 color mode is slected
+                                                 - from 0x00 to 0x0F if ARGB4444 color mode is slected  */
+  
+  uint32_t DMA2D_OutputAlpha;                    /*!< configures the alpha channel of the output color. 
+                                                 This parameter must range:
+                                                 - from 0x00 to 0xFF if ARGB8888 color mode is selected
+                                                 - from 0x00 to 0x01 if ARGB1555 color mode is selected
+                                                 - from 0x00 to 0x0F if ARGB4444 color mode is selected  */
+
+  uint32_t DMA2D_OutputMemoryAdd;                /*!< Specifies the memory address. This parameter 
+                                                 must be range from 0x00000000 to 0xFFFFFFFF. */
+
+  uint32_t DMA2D_OutputOffset;                   /*!< Specifies the Offset value. This parameter must be range from
+                                                 0x0000 to 0x3FFF. */
+
+  uint32_t DMA2D_NumberOfLine;                   /*!< Configures the number of line of the area to be transfered.
+                                                 This parameter must range from 0x0000 to 0xFFFF */
+            
+  uint32_t DMA2D_PixelPerLine;                   /*!< Configures the number pixel per line of the area to be transferred.
+                                                 This parameter must range from 0x0000 to 0x3FFF */
+} DMA2D_InitTypeDef;
+
+
+
+typedef struct
+{
+  uint32_t DMA2D_FGMA;                           /*!< configures the DMA2D foreground memory address.
+                                                 This parameter must be range from 0x00000000 to 0xFFFFFFFF. */
+  
+  uint32_t DMA2D_FGO;                            /*!< configures the DMA2D foreground offset.
+                                                 This parameter must be range from 0x0000 to 0x3FFF. */
+
+  uint32_t DMA2D_FGCM;                           /*!< configures the DMA2D foreground color mode . 
+                                                 This parameter can be one value of @ref DMA2D_FGCM */
+
+  uint32_t DMA2D_FG_CLUT_CM;                     /*!< configures the DMA2D foreground CLUT color mode. 
+                                                 This parameter can be one value of @ref DMA2D_FG_CLUT_CM */
+            
+  uint32_t DMA2D_FG_CLUT_SIZE;                   /*!< configures the DMA2D foreground CLUT size. 
+                                                 This parameter must range from 0x00 to 0xFF. */
+  
+  uint32_t DMA2D_FGPFC_ALPHA_MODE;               /*!< configures the DMA2D foreground alpha mode. 
+                                                 This parameter can be one value of @ref DMA2D_FGPFC_ALPHA_MODE */
+
+  uint32_t DMA2D_FGPFC_ALPHA_VALUE;              /*!< Specifies the DMA2D foreground alpha value 
+                                                 must be range from 0x00 to 0xFF. */
+
+  uint32_t DMA2D_FGC_BLUE;                       /*!< Specifies the DMA2D foreground blue value 
+                                                 must be range from 0x00 to 0xFF. */
+
+  uint32_t DMA2D_FGC_GREEN;                      /*!< Specifies the DMA2D foreground green value 
+                                                 must be range from 0x00 to 0xFF. */
+
+  uint32_t DMA2D_FGC_RED;                        /*!< Specifies the DMA2D foreground red value 
+                                                 must be range from 0x00 to 0xFF. */
+            
+  uint32_t DMA2D_FGCMAR;                         /*!< Configures the DMA2D foreground CLUT memory address.
+                                                 This parameter must range from 0x00000000 to 0xFFFFFFFF. */
+} DMA2D_FG_InitTypeDef;
+
+
+typedef struct
+{
+  uint32_t DMA2D_BGMA;                           /*!< configures the DMA2D background memory address.
+                                                 This parameter must be range from 0x00000000 to 0xFFFFFFFF. */
+  
+  uint32_t DMA2D_BGO;                            /*!< configures the DMA2D background offset.
+                                                 This parameter must be range from 0x0000 to 0x3FFF. */
+
+  uint32_t DMA2D_BGCM;                           /*!< configures the DMA2D background color mode . 
+                                                 This parameter can be one value of @ref DMA2D_FGCM */
+
+  uint32_t DMA2D_BG_CLUT_CM;                     /*!< configures the DMA2D background CLUT color mode. 
+                                                 This parameter can be one value of @ref DMA2D_FG_CLUT_CM */
+            
+  uint32_t DMA2D_BG_CLUT_SIZE;                   /*!< configures the DMA2D background CLUT size. 
+                                                 This parameter must range from 0x00 to 0xFF. */
+  
+  uint32_t DMA2D_BGPFC_ALPHA_MODE;               /*!< configures the DMA2D background alpha mode. 
+                                                 This parameter can be one value of @ref DMA2D_FGPFC_ALPHA_MODE */
+
+  uint32_t DMA2D_BGPFC_ALPHA_VALUE;              /*!< Specifies the DMA2D background alpha value 
+                                                 must be range from 0x00 to 0xFF. */
+
+  uint32_t DMA2D_BGC_BLUE;                       /*!< Specifies the DMA2D background blue value 
+                                                 must be range from 0x00 to 0xFF. */
+
+  uint32_t DMA2D_BGC_GREEN;                      /*!< Specifies the DMA2D background green value 
+                                                 must be range from 0x00 to 0xFF. */
+
+  uint32_t DMA2D_BGC_RED;                        /*!< Specifies the DMA2D background red value 
+                                                 must be range from 0x00 to 0xFF. */
+            
+  uint32_t DMA2D_BGCMAR;                         /*!< Configures the DMA2D background CLUT memory address.
+                                                 This parameter must range from 0x00000000 to 0xFFFFFFFF. */
+} DMA2D_BG_InitTypeDef;
+
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA2D_Exported_Constants
+  * @{
+  */  
+
+/** @defgroup DMA2D_MODE 
+  * @{
+  */
+
+
+#define DMA2D_M2M                            ((uint32_t)0x00000000)
+#define DMA2D_M2M_PFC                        ((uint32_t)0x00010000)
+#define DMA2D_M2M_BLEND                      ((uint32_t)0x00020000)
+#define DMA2D_R2M                            ((uint32_t)0x00030000)
+
+#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
+                             ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
+
+
+/**
+  * @}
+  */  
+
+/** @defgroup DMA2D_CMODE 
+  * @{
+  */
+#define DMA2D_ARGB8888                       ((uint32_t)0x00000000)
+#define DMA2D_RGB888                         ((uint32_t)0x00000001)
+#define DMA2D_RGB565                         ((uint32_t)0x00000002)
+#define DMA2D_ARGB1555                       ((uint32_t)0x00000003)
+#define DMA2D_ARGB4444                       ((uint32_t)0x00000004)
+
+#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \
+                                   ((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \
+                                   ((MODE_ARGB) == DMA2D_ARGB4444))
+
+
+/**
+  * @}
+  */  
+
+/** @defgroup DMA2D_OUTPUT_COLOR 
+  * @{
+  */
+#define DMA2D_Output_Color                 ((uint32_t)0x000000FF)
+
+#define IS_DMA2D_OGREEN(OGREEN) ((OGREEN) <= DMA2D_Output_Color)
+#define IS_DMA2D_ORED(ORED)     ((ORED) <= DMA2D_Output_Color)
+#define IS_DMA2D_OBLUE(OBLUE)   ((OBLUE) <= DMA2D_Output_Color)
+#define IS_DMA2D_OALPHA(OALPHA) ((OALPHA) <= DMA2D_Output_Color)
+
+/**
+  * @}
+  */  
+
+/** @defgroup DMA2D_OUTPUT_OFFSET 
+  * @{
+  */
+#define DMA2D_OUTPUT_OFFSET      ((uint32_t)0x00003FFF)
+
+#define IS_DMA2D_OUTPUT_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OUTPUT_OFFSET)
+
+
+/**
+  * @}
+  */  
+
+/** @defgroup DMA2D_SIZE 
+  * @{
+  */
+
+#define DMA2D_pixel          ((uint32_t)0x00003FFF)
+#define DMA2D_Line           ((uint32_t)0x0000FFFF)
+
+#define IS_DMA2D_LINE(LINE)  ((LINE) <= DMA2D_Line)
+#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_pixel)
+
+
+/**
+  * @}
+  */  
+
+/** @defgroup DMA2D_OFFSET
+  * @{
+  */
+#define OFFSET               ((uint32_t)0x00003FFF)
+
+#define IS_DMA2D_FGO(FGO)  ((FGO) <= OFFSET)
+
+#define IS_DMA2D_BGO(BGO)  ((BGO) <= OFFSET) 
+
+/**
+  * @}
+  */  
+
+
+/** @defgroup DMA2D_FGCM
+  * @{
+  */
+
+#define CM_ARGB8888        ((uint32_t)0x00000000)
+#define CM_RGB888          ((uint32_t)0x00000001)
+#define CM_RGB565          ((uint32_t)0x00000002)
+#define CM_ARGB1555        ((uint32_t)0x00000003)
+#define CM_ARGB4444        ((uint32_t)0x00000004)
+#define CM_L8              ((uint32_t)0x00000005)
+#define CM_AL44            ((uint32_t)0x00000006)
+#define CM_AL88            ((uint32_t)0x00000007)
+#define CM_L4              ((uint32_t)0x00000008)
+#define CM_A8              ((uint32_t)0x00000009)
+#define CM_A4              ((uint32_t)0x0000000A)
+
+#define IS_DMA2D_FGCM(FGCM) (((FGCM) == CM_ARGB8888) || ((FGCM) == CM_RGB888) || \
+                             ((FGCM) == CM_RGB565) || ((FGCM) == CM_ARGB1555) || \
+                             ((FGCM) == CM_ARGB4444) || ((FGCM) == CM_L8) || \
+                             ((FGCM) == CM_AL44) || ((FGCM) == CM_AL88) || \
+                             ((FGCM) == CM_L4) || ((FGCM) == CM_A8) || \
+                             ((FGCM) == CM_A4))
+
+#define IS_DMA2D_BGCM(BGCM) (((BGCM) == CM_ARGB8888) || ((BGCM) == CM_RGB888) || \
+                             ((BGCM) == CM_RGB565) || ((BGCM) == CM_ARGB1555) || \
+                             ((BGCM) == CM_ARGB4444) || ((BGCM) == CM_L8) || \
+                             ((BGCM) == CM_AL44) || ((BGCM) == CM_AL88) || \
+                             ((BGCM) == CM_L4) || ((BGCM) == CM_A8) || \
+                             ((BGCM) == CM_A4))
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_FG_CLUT_CM
+  * @{
+  */
+
+#define CLUT_CM_ARGB8888        ((uint32_t)0x00000000)
+#define CLUT_CM_RGB888          ((uint32_t)0x00000001)
+
+#define IS_DMA2D_FG_CLUT_CM(FG_CLUT_CM) (((FG_CLUT_CM) == CLUT_CM_ARGB8888) || ((FG_CLUT_CM) == CLUT_CM_RGB888))
+
+#define IS_DMA2D_BG_CLUT_CM(BG_CLUT_CM) (((BG_CLUT_CM) == CLUT_CM_ARGB8888) || ((BG_CLUT_CM) == CLUT_CM_RGB888))
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_FG_COLOR_VALUE
+  * @{
+  */
+
+#define COLOR_VALUE             ((uint32_t)0x000000FF)
+
+#define IS_DMA2D_FG_CLUT_SIZE(FG_CLUT_SIZE) ((FG_CLUT_SIZE) <= COLOR_VALUE)
+
+#define IS_DMA2D_FG_ALPHA_VALUE(FG_ALPHA_VALUE) ((FG_ALPHA_VALUE) <= COLOR_VALUE)
+#define IS_DMA2D_FGC_BLUE(FGC_BLUE) ((FGC_BLUE) <= COLOR_VALUE)
+#define IS_DMA2D_FGC_GREEN(FGC_GREEN) ((FGC_GREEN) <= COLOR_VALUE)
+#define IS_DMA2D_FGC_RED(FGC_RED) ((FGC_RED) <= COLOR_VALUE)
+
+#define IS_DMA2D_BG_CLUT_SIZE(BG_CLUT_SIZE) ((BG_CLUT_SIZE) <= COLOR_VALUE)
+
+#define IS_DMA2D_BG_ALPHA_VALUE(BG_ALPHA_VALUE) ((BG_ALPHA_VALUE) <= COLOR_VALUE)
+#define IS_DMA2D_BGC_BLUE(BGC_BLUE) ((BGC_BLUE) <= COLOR_VALUE)
+#define IS_DMA2D_BGC_GREEN(BGC_GREEN) ((BGC_GREEN) <= COLOR_VALUE)
+#define IS_DMA2D_BGC_RED(BGC_RED) ((BGC_RED) <= COLOR_VALUE)
+
+/**
+  * @}
+  */
+
+/** DMA2D_FGPFC_ALPHA_MODE
+  * @{
+  */
+
+#define NO_MODIF_ALPHA_VALUE       ((uint32_t)0x00000000)
+#define REPLACE_ALPHA_VALUE        ((uint32_t)0x00000001)
+#define COMBINE_ALPHA_VALUE        ((uint32_t)0x00000002)
+
+#define IS_DMA2D_FG_ALPHA_MODE(FG_ALPHA_MODE) (((FG_ALPHA_MODE) ==  NO_MODIF_ALPHA_VALUE) || \
+                                              ((FG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \
+                                              ((FG_ALPHA_MODE) == COMBINE_ALPHA_VALUE))
+
+#define IS_DMA2D_BG_ALPHA_MODE(BG_ALPHA_MODE) (((BG_ALPHA_MODE) ==  NO_MODIF_ALPHA_VALUE) || \
+                                              ((BG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \
+                                              ((BG_ALPHA_MODE) == COMBINE_ALPHA_VALUE))
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Interrupts 
+  * @{
+  */
+
+#define DMA2D_IT_CE                      DMA2D_CR_CEIE
+#define DMA2D_IT_CTC                     DMA2D_CR_CTCIE
+#define DMA2D_IT_CAE                     DMA2D_CR_CAEIE
+#define DMA2D_IT_TW                      DMA2D_CR_TWIE
+#define DMA2D_IT_TC                      DMA2D_CR_TCIE
+#define DMA2D_IT_TE                      DMA2D_CR_TEIE
+
+#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
+                        ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
+                        ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
+
+/**
+  * @}
+  */
+      
+/** @defgroup DMA2D_Flag 
+  * @{
+  */
+
+#define DMA2D_FLAG_CE                      DMA2D_ISR_CEIF
+#define DMA2D_FLAG_CTC                     DMA2D_ISR_CTCIF
+#define DMA2D_FLAG_CAE                     DMA2D_ISR_CAEIF
+#define DMA2D_FLAG_TW                      DMA2D_ISR_TWIF
+#define DMA2D_FLAG_TC                      DMA2D_ISR_TCIF
+#define DMA2D_FLAG_TE                      DMA2D_ISR_TEIF
+
+
+#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
+                                ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
+                                ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) 
+
+
+/**
+  * @}
+  */
+      
+/** @defgroup DMA2D_DeadTime 
+  * @{
+  */
+
+#define DEADTIME                  ((uint32_t)0x000000FF)
+  
+#define IS_DMA2D_DEAD_TIME(DEAD_TIME) ((DEAD_TIME) <= DEADTIME)
+
+
+#define LINE_WATERMARK            DMA2D_LWR_LW
+
+#define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the DMA2D configuration to the default reset state *****/
+void DMA2D_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void DMA2D_Init(DMA2D_InitTypeDef* DMA2D_InitStruct);
+void DMA2D_StructInit(DMA2D_InitTypeDef* DMA2D_InitStruct);
+void DMA2D_StartTransfer(void);
+void DMA2D_AbortTransfer(void);
+void DMA2D_Suspend(FunctionalState NewState);
+void DMA2D_FGConfig(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct);
+void DMA2D_FG_StructInit(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct);
+void DMA2D_BGConfig(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct);
+void DMA2D_BG_StructInit(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct);
+void DMA2D_FGStart(FunctionalState NewState);
+void DMA2D_BGStart(FunctionalState NewState);
+void DMA2D_DeadTimeConfig(uint32_t DMA2D_DeadTime, FunctionalState NewState);
+void DMA2D_LineWatermarkConfig(uint32_t DMA2D_LWatermarkConfig);
+
+/* Interrupts and flags management functions **********************************/
+void DMA2D_ITConfig(uint32_t DMA2D_IT, FunctionalState NewState);
+FlagStatus DMA2D_GetFlagStatus(uint32_t DMA2D_FLAG);
+void DMA2D_ClearFlag(uint32_t DMA2D_FLAG);
+ITStatus DMA2D_GetITStatus(uint32_t DMA2D_IT);
+void DMA2D_ClearITPendingBit(uint32_t DMA2D_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_DMA2D_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

底盘/底盘-old/底盘/Library/stm32f4xx_exti.c

@@ -0,0 +1,304 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_exti.c
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the EXTI peripheral:
+  *           + Initialization and Configuration
+  *           + Interrupts and flags management
+  *
+@verbatim  
+
+ ===============================================================================
+                              ##### EXTI features #####
+ ===============================================================================
+
+ [..] External interrupt/event lines are mapped as following:
+   (#) All available GPIO pins are connected to the 16 external 
+       interrupt/event lines from EXTI0 to EXTI15.
+   (#) EXTI line 16 is connected to the PVD Output
+   (#) EXTI line 17 is connected to the RTC Alarm event
+   (#) EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event
+   (#) EXTI line 19 is connected to the Ethernet Wakeup event
+   (#) EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event 
+   (#) EXTI line 21 is connected to the RTC Tamper and Time Stamp events
+   (#) EXTI line 22 is connected to the RTC Wakeup event
+   (#) EXTI line 23 is connected to the LPTIM Wakeup event 
+
+                       ##### How to use this driver #####
+ ===============================================================================
+ 
+ [..] In order to use an I/O pin as an external interrupt source, follow steps 
+      below:
+   (#) Configure the I/O in input mode using GPIO_Init()
+   (#) Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig()
+   (#) Select the mode(interrupt, event) and configure the trigger 
+       selection (Rising, falling or both) using EXTI_Init()
+   (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()
+
+ [..]     
+   (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
+       registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+
+@endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_exti.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup EXTI 
+  * @brief EXTI driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+#define EXTI_LINENONE    ((uint32_t)0x00000)  /* No interrupt selected */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup EXTI_Private_Functions
+  * @{
+  */
+
+/** @defgroup EXTI_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+             ##### Initialization and Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the EXTI peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void EXTI_DeInit(void)
+{
+  EXTI->IMR = 0x00000000;
+  EXTI->EMR = 0x00000000;
+  EXTI->RTSR = 0x00000000;
+  EXTI->FTSR = 0x00000000;
+  EXTI->PR = 0x007FFFFF;
+}
+
+/**
+  * @brief  Initializes the EXTI peripheral according to the specified
+  *         parameters in the EXTI_InitStruct.
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
+  *         that contains the configuration information for the EXTI peripheral.
+  * @retval None
+  */
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+  uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+  assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+  assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));  
+  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+  tmp = (uint32_t)EXTI_BASE;
+     
+  if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+  {
+    /* Clear EXTI line configuration */
+    EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
+    EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
+    
+    tmp += EXTI_InitStruct->EXTI_Mode;
+
+    *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+
+    /* Clear Rising Falling edge configuration */
+    EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
+    EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
+    
+    /* Select the trigger for the selected external interrupts */
+    if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+    {
+      /* Rising Falling edge */
+      EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
+      EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
+    }
+    else
+    {
+      tmp = (uint32_t)EXTI_BASE;
+      tmp += EXTI_InitStruct->EXTI_Trigger;
+
+      *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+    }
+  }
+  else
+  {
+    tmp += EXTI_InitStruct->EXTI_Mode;
+
+    /* Disable the selected external lines */
+    *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
+  }
+}
+
+/**
+  * @brief  Fills each EXTI_InitStruct member with its reset value.
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+  EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+  EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+  EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+  EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param  EXTI_Line: specifies the EXTI line on which the software interrupt
+  *         will be generated.
+  *         This parameter can be any combination of EXTI_Linex where x can be (0..22)
+  * @retval None
+  */
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+  
+  EXTI->SWIER |= EXTI_Line;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Group2 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+             ##### Interrupts and flags management functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  EXTI_Line: specifies the EXTI line flag to check.
+  *          This parameter can be EXTI_Linex where x can be(0..22)
+  * @retval The new state of EXTI_Line (SET or RESET).
+  */
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+  
+  if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  EXTI_Line: specifies the EXTI lines flags to clear.
+  *          This parameter can be any combination of EXTI_Linex where x can be (0..22)
+  * @retval None
+  */
+void EXTI_ClearFlag(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+  
+  EXTI->PR = EXTI_Line;
+}
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  EXTI_Line: specifies the EXTI line to check.
+  *          This parameter can be EXTI_Linex where x can be(0..22)
+  * @retval The new state of EXTI_Line (SET or RESET).
+  */
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+  
+  if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+  
+}
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  EXTI_Line: specifies the EXTI lines to clear.
+  *          This parameter can be any combination of EXTI_Linex where x can be (0..22)
+  * @retval None
+  */
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+  
+  EXTI->PR = EXTI_Line;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

底盘/底盘-old/底盘/Library/stm32f4xx_exti.h

@@ -0,0 +1,177 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_exti.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the EXTI firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_EXTI_H
+#define __STM32F4xx_EXTI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup EXTI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  EXTI mode enumeration  
+  */
+
+typedef enum
+{
+  EXTI_Mode_Interrupt = 0x00,
+  EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/** 
+  * @brief  EXTI Trigger enumeration  
+  */
+
+typedef enum
+{
+  EXTI_Trigger_Rising = 0x08,
+  EXTI_Trigger_Falling = 0x0C,  
+  EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
+                                  ((TRIGGER) == EXTI_Trigger_Falling) || \
+                                  ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/** 
+  * @brief  EXTI Init Structure definition  
+  */
+
+typedef struct
+{
+  uint32_t EXTI_Line;               /*!< Specifies the EXTI lines to be enabled or disabled.
+                                         This parameter can be any combination value of @ref EXTI_Lines */
+   
+  EXTIMode_TypeDef EXTI_Mode;       /*!< Specifies the mode for the EXTI lines.
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */
+
+  EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                         This parameter can be a value of @ref EXTITrigger_TypeDef */
+
+  FunctionalState EXTI_LineCmd;     /*!< Specifies the new state of the selected EXTI lines.
+                                         This parameter can be set either to ENABLE or DISABLE */ 
+}EXTI_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Constants
+  * @{
+  */
+
+/** @defgroup EXTI_Lines 
+  * @{
+  */
+
+#define EXTI_Line0       ((uint32_t)0x00001)     /*!< External interrupt line 0 */
+#define EXTI_Line1       ((uint32_t)0x00002)     /*!< External interrupt line 1 */
+#define EXTI_Line2       ((uint32_t)0x00004)     /*!< External interrupt line 2 */
+#define EXTI_Line3       ((uint32_t)0x00008)     /*!< External interrupt line 3 */
+#define EXTI_Line4       ((uint32_t)0x00010)     /*!< External interrupt line 4 */
+#define EXTI_Line5       ((uint32_t)0x00020)     /*!< External interrupt line 5 */
+#define EXTI_Line6       ((uint32_t)0x00040)     /*!< External interrupt line 6 */
+#define EXTI_Line7       ((uint32_t)0x00080)     /*!< External interrupt line 7 */
+#define EXTI_Line8       ((uint32_t)0x00100)     /*!< External interrupt line 8 */
+#define EXTI_Line9       ((uint32_t)0x00200)     /*!< External interrupt line 9 */
+#define EXTI_Line10      ((uint32_t)0x00400)     /*!< External interrupt line 10 */
+#define EXTI_Line11      ((uint32_t)0x00800)     /*!< External interrupt line 11 */
+#define EXTI_Line12      ((uint32_t)0x01000)     /*!< External interrupt line 12 */
+#define EXTI_Line13      ((uint32_t)0x02000)     /*!< External interrupt line 13 */
+#define EXTI_Line14      ((uint32_t)0x04000)     /*!< External interrupt line 14 */
+#define EXTI_Line15      ((uint32_t)0x08000)     /*!< External interrupt line 15 */
+#define EXTI_Line16      ((uint32_t)0x10000)     /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_Line17      ((uint32_t)0x20000)     /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_Line18      ((uint32_t)0x40000)     /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */                                    
+#define EXTI_Line19      ((uint32_t)0x80000)     /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+#define EXTI_Line20      ((uint32_t)0x00100000)  /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event  */
+#define EXTI_Line21      ((uint32_t)0x00200000)  /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */                                               
+#define EXTI_Line22      ((uint32_t)0x00400000)  /*!< External interrupt line 22 Connected to the RTC Wakeup event */
+#define EXTI_Line23      ((uint32_t)0x00800000)  /*!< External interrupt line 23 Connected to the LPTIM Wakeup event */
+
+                                          
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))
+
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
+                                ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
+                                ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
+                                ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
+                                ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
+                                ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+                                ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+                                ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+                                ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+                                ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
+                                ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\
+                                ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23))
+                    
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/*  Function used to set the EXTI configuration to the default reset state *****/
+void EXTI_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_EXTI_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

底盘/底盘-old/底盘/Library/stm32f4xx_flash.h

@@ -0,0 +1,489 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_flash.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the FLASH 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_FLASH_H
+#define __STM32F4xx_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** 
+  * @brief FLASH Status  
+  */ 
+typedef enum
+{ 
+  FLASH_BUSY = 1,
+  FLASH_ERROR_RD,
+  FLASH_ERROR_PGS,
+  FLASH_ERROR_PGP,
+  FLASH_ERROR_PGA,
+  FLASH_ERROR_WRP,
+  FLASH_ERROR_PROGRAM,
+  FLASH_ERROR_OPERATION,
+  FLASH_COMPLETE
+}FLASH_Status;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Constants
+  * @{
+  */  
+
+/** @defgroup Flash_Latency 
+  * @{
+  */ 
+#define FLASH_Latency_0                ((uint8_t)0x0000)  /*!< FLASH Zero Latency cycle      */
+#define FLASH_Latency_1                ((uint8_t)0x0001)  /*!< FLASH One Latency cycle       */
+#define FLASH_Latency_2                ((uint8_t)0x0002)  /*!< FLASH Two Latency cycles      */
+#define FLASH_Latency_3                ((uint8_t)0x0003)  /*!< FLASH Three Latency cycles    */
+#define FLASH_Latency_4                ((uint8_t)0x0004)  /*!< FLASH Four Latency cycles     */
+#define FLASH_Latency_5                ((uint8_t)0x0005)  /*!< FLASH Five Latency cycles     */
+#define FLASH_Latency_6                ((uint8_t)0x0006)  /*!< FLASH Six Latency cycles      */
+#define FLASH_Latency_7                ((uint8_t)0x0007)  /*!< FLASH Seven Latency cycles    */
+#define FLASH_Latency_8                ((uint8_t)0x0008)  /*!< FLASH Eight Latency cycles    */
+#define FLASH_Latency_9                ((uint8_t)0x0009)  /*!< FLASH Nine Latency cycles     */
+#define FLASH_Latency_10               ((uint8_t)0x000A)  /*!< FLASH Ten Latency cycles      */
+#define FLASH_Latency_11               ((uint8_t)0x000B)  /*!< FLASH Eleven Latency cycles   */
+#define FLASH_Latency_12               ((uint8_t)0x000C)  /*!< FLASH Twelve Latency cycles   */
+#define FLASH_Latency_13               ((uint8_t)0x000D)  /*!< FLASH Thirteen Latency cycles */
+#define FLASH_Latency_14               ((uint8_t)0x000E)  /*!< FLASH Fourteen Latency cycles */
+#define FLASH_Latency_15               ((uint8_t)0x000F)  /*!< FLASH Fifteen Latency cycles  */
+
+
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0)  || \
+                                   ((LATENCY) == FLASH_Latency_1)  || \
+                                   ((LATENCY) == FLASH_Latency_2)  || \
+                                   ((LATENCY) == FLASH_Latency_3)  || \
+                                   ((LATENCY) == FLASH_Latency_4)  || \
+                                   ((LATENCY) == FLASH_Latency_5)  || \
+                                   ((LATENCY) == FLASH_Latency_6)  || \
+                                   ((LATENCY) == FLASH_Latency_7)  || \
+                                   ((LATENCY) == FLASH_Latency_8)  || \
+                                   ((LATENCY) == FLASH_Latency_9)  || \
+                                   ((LATENCY) == FLASH_Latency_10) || \
+                                   ((LATENCY) == FLASH_Latency_11) || \
+                                   ((LATENCY) == FLASH_Latency_12) || \
+                                   ((LATENCY) == FLASH_Latency_13) || \
+                                   ((LATENCY) == FLASH_Latency_14) || \
+                                   ((LATENCY) == FLASH_Latency_15))
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Voltage_Range 
+  * @{
+  */ 
+#define VoltageRange_1        ((uint8_t)0x00)  /*!< Device operating range: 1.8V to 2.1V */
+#define VoltageRange_2        ((uint8_t)0x01)  /*!<Device operating range: 2.1V to 2.7V */
+#define VoltageRange_3        ((uint8_t)0x02)  /*!<Device operating range: 2.7V to 3.6V */
+#define VoltageRange_4        ((uint8_t)0x03)  /*!<Device operating range: 2.7V to 3.6V + External Vpp */
+
+#define IS_VOLTAGERANGE(RANGE)(((RANGE) == VoltageRange_1) || \
+                               ((RANGE) == VoltageRange_2) || \
+                               ((RANGE) == VoltageRange_3) || \
+                               ((RANGE) == VoltageRange_4))
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Sectors
+  * @{
+  */
+#define FLASH_Sector_0     ((uint16_t)0x0000) /*!< Sector Number 0   */
+#define FLASH_Sector_1     ((uint16_t)0x0008) /*!< Sector Number 1   */
+#define FLASH_Sector_2     ((uint16_t)0x0010) /*!< Sector Number 2   */
+#define FLASH_Sector_3     ((uint16_t)0x0018) /*!< Sector Number 3   */
+#define FLASH_Sector_4     ((uint16_t)0x0020) /*!< Sector Number 4   */
+#define FLASH_Sector_5     ((uint16_t)0x0028) /*!< Sector Number 5   */
+#define FLASH_Sector_6     ((uint16_t)0x0030) /*!< Sector Number 6   */
+#define FLASH_Sector_7     ((uint16_t)0x0038) /*!< Sector Number 7   */
+#define FLASH_Sector_8     ((uint16_t)0x0040) /*!< Sector Number 8   */
+#define FLASH_Sector_9     ((uint16_t)0x0048) /*!< Sector Number 9   */
+#define FLASH_Sector_10    ((uint16_t)0x0050) /*!< Sector Number 10  */
+#define FLASH_Sector_11    ((uint16_t)0x0058) /*!< Sector Number 11  */
+#define FLASH_Sector_12    ((uint16_t)0x0080) /*!< Sector Number 12  */
+#define FLASH_Sector_13    ((uint16_t)0x0088) /*!< Sector Number 13  */
+#define FLASH_Sector_14    ((uint16_t)0x0090) /*!< Sector Number 14  */
+#define FLASH_Sector_15    ((uint16_t)0x0098) /*!< Sector Number 15  */
+#define FLASH_Sector_16    ((uint16_t)0x00A0) /*!< Sector Number 16  */
+#define FLASH_Sector_17    ((uint16_t)0x00A8) /*!< Sector Number 17  */
+#define FLASH_Sector_18    ((uint16_t)0x00B0) /*!< Sector Number 18  */
+#define FLASH_Sector_19    ((uint16_t)0x00B8) /*!< Sector Number 19  */
+#define FLASH_Sector_20    ((uint16_t)0x00C0) /*!< Sector Number 20  */
+#define FLASH_Sector_21    ((uint16_t)0x00C8) /*!< Sector Number 21  */
+#define FLASH_Sector_22    ((uint16_t)0x00D0) /*!< Sector Number 22  */
+#define FLASH_Sector_23    ((uint16_t)0x00D8) /*!< Sector Number 23  */
+
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_Sector_0)   || ((SECTOR) == FLASH_Sector_1)   ||\
+                                 ((SECTOR) == FLASH_Sector_2)   || ((SECTOR) == FLASH_Sector_3)   ||\
+                                 ((SECTOR) == FLASH_Sector_4)   || ((SECTOR) == FLASH_Sector_5)   ||\
+                                 ((SECTOR) == FLASH_Sector_6)   || ((SECTOR) == FLASH_Sector_7)   ||\
+                                 ((SECTOR) == FLASH_Sector_8)   || ((SECTOR) == FLASH_Sector_9)   ||\
+                                 ((SECTOR) == FLASH_Sector_10)  || ((SECTOR) == FLASH_Sector_11)  ||\
+                                 ((SECTOR) == FLASH_Sector_12)  || ((SECTOR) == FLASH_Sector_13)  ||\
+                                 ((SECTOR) == FLASH_Sector_14)  || ((SECTOR) == FLASH_Sector_15)  ||\
+                                 ((SECTOR) == FLASH_Sector_16)  || ((SECTOR) == FLASH_Sector_17)  ||\
+                                 ((SECTOR) == FLASH_Sector_18)  || ((SECTOR) == FLASH_Sector_19)  ||\
+                                 ((SECTOR) == FLASH_Sector_20)  || ((SECTOR) == FLASH_Sector_21)  ||\
+                                 ((SECTOR) == FLASH_Sector_22)  || ((SECTOR) == FLASH_Sector_23))
+
+#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F469_479xx)
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x081FFFFF)) ||\
+                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))  
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
+
+#if defined (STM32F40_41xxx) || defined(STM32F412xG)
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x080FFFFF)) ||\
+                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F))) 
+#endif /* STM32F40_41xxx || STM32F412xG */
+
+#if defined (STM32F401xx)
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF)) ||\
+                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
+#endif /* STM32F401xx */
+
+#if defined (STM32F411xE) || defined (STM32F446xx)
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0807FFFF)) ||\
+                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
+#endif /* STM32F411xE || STM32F446xx */
+
+#if defined (STM32F410xx)
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF)) ||\
+                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
+#endif /* STM32F410xx */
+
+#if defined(STM32F413_423xx)
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0817FFFF)) ||\
+                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7BDF)))
+#endif /* STM32F413_423xx */
+/**
+  * @}
+  */ 
+
+/** @defgroup Option_Bytes_Write_Protection 
+  * @{
+  */ 
+#define OB_WRP_Sector_0       ((uint32_t)0x00000001) /*!< Write protection of Sector0     */
+#define OB_WRP_Sector_1       ((uint32_t)0x00000002) /*!< Write protection of Sector1     */
+#define OB_WRP_Sector_2       ((uint32_t)0x00000004) /*!< Write protection of Sector2     */
+#define OB_WRP_Sector_3       ((uint32_t)0x00000008) /*!< Write protection of Sector3     */
+#define OB_WRP_Sector_4       ((uint32_t)0x00000010) /*!< Write protection of Sector4     */
+#define OB_WRP_Sector_5       ((uint32_t)0x00000020) /*!< Write protection of Sector5     */
+#define OB_WRP_Sector_6       ((uint32_t)0x00000040) /*!< Write protection of Sector6     */
+#define OB_WRP_Sector_7       ((uint32_t)0x00000080) /*!< Write protection of Sector7     */
+#define OB_WRP_Sector_8       ((uint32_t)0x00000100) /*!< Write protection of Sector8     */
+#define OB_WRP_Sector_9       ((uint32_t)0x00000200) /*!< Write protection of Sector9     */
+#define OB_WRP_Sector_10      ((uint32_t)0x00000400) /*!< Write protection of Sector10    */
+#define OB_WRP_Sector_11      ((uint32_t)0x00000800) /*!< Write protection of Sector11    */
+#define OB_WRP_Sector_12      ((uint32_t)0x00000001) /*!< Write protection of Sector12    */
+#define OB_WRP_Sector_13      ((uint32_t)0x00000002) /*!< Write protection of Sector13    */
+#define OB_WRP_Sector_14      ((uint32_t)0x00000004) /*!< Write protection of Sector14    */
+#define OB_WRP_Sector_15      ((uint32_t)0x00000008) /*!< Write protection of Sector15    */
+#define OB_WRP_Sector_16      ((uint32_t)0x00000010) /*!< Write protection of Sector16    */
+#define OB_WRP_Sector_17      ((uint32_t)0x00000020) /*!< Write protection of Sector17    */
+#define OB_WRP_Sector_18      ((uint32_t)0x00000040) /*!< Write protection of Sector18    */
+#define OB_WRP_Sector_19      ((uint32_t)0x00000080) /*!< Write protection of Sector19    */
+#define OB_WRP_Sector_20      ((uint32_t)0x00000100) /*!< Write protection of Sector20    */
+#define OB_WRP_Sector_21      ((uint32_t)0x00000200) /*!< Write protection of Sector21    */
+#define OB_WRP_Sector_22      ((uint32_t)0x00000400) /*!< Write protection of Sector22    */
+#define OB_WRP_Sector_23      ((uint32_t)0x00000800) /*!< Write protection of Sector23    */
+#define OB_WRP_Sector_All     ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+/**
+  * @}
+  */
+
+/** @defgroup  Selection_Protection_Mode
+  * @{
+  */
+#define OB_PcROP_Disable   ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
+#define OB_PcROP_Enable    ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i   */
+#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PcROP_Disable) || ((PCROP) == OB_PcROP_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_PC_ReadWrite_Protection 
+  * @{
+  */ 
+#define OB_PCROP_Sector_0        ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0      */
+#define OB_PCROP_Sector_1        ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1      */
+#define OB_PCROP_Sector_2        ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2      */
+#define OB_PCROP_Sector_3        ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3      */
+#define OB_PCROP_Sector_4        ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4      */
+#define OB_PCROP_Sector_5        ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5      */
+#define OB_PCROP_Sector_6        ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6      */
+#define OB_PCROP_Sector_7        ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7      */
+#define OB_PCROP_Sector_8        ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector8      */
+#define OB_PCROP_Sector_9        ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector9      */
+#define OB_PCROP_Sector_10       ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector10     */
+#define OB_PCROP_Sector_11       ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector11     */
+#define OB_PCROP_Sector_12       ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector12     */
+#define OB_PCROP_Sector_13       ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector13     */
+#define OB_PCROP_Sector_14       ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector14     */
+#define OB_PCROP_Sector_15       ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector15     */
+#define OB_PCROP_Sector_16       ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector16     */
+#define OB_PCROP_Sector_17       ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector17     */
+#define OB_PCROP_Sector_18       ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector18     */
+#define OB_PCROP_Sector_19       ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector19     */
+#define OB_PCROP_Sector_20       ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector20     */
+#define OB_PCROP_Sector_21       ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector21     */
+#define OB_PCROP_Sector_22       ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22     */
+#define OB_PCROP_Sector_23       ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23     */
+#define OB_PCROP_Sector_All      ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors  */
+
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Option_Bytes_Read_Protection 
+  * @{
+  */
+#define OB_RDP_Level_0   ((uint8_t)0xAA)
+#define OB_RDP_Level_1   ((uint8_t)0x55)
+/*#define OB_RDP_Level_2   ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 
+                                                  it's no more possible to go back to level 1 or 0 */
+#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
+                          ((LEVEL) == OB_RDP_Level_1))/*||\
+                          ((LEVEL) == OB_RDP_Level_2))*/
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Option_Bytes_IWatchdog 
+  * @{
+  */ 
+#define OB_IWDG_SW                     ((uint8_t)0x20)  /*!< Software IWDG selected */
+#define OB_IWDG_HW                     ((uint8_t)0x00)  /*!< Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Option_Bytes_nRST_STOP 
+  * @{
+  */ 
+#define OB_STOP_NoRST                  ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST                    ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FLASH_Option_Bytes_nRST_STDBY 
+  * @{
+  */ 
+#define OB_STDBY_NoRST                 ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST                   ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
+/**
+  * @}
+  */
+  
+/** @defgroup FLASH_BOR_Reset_Level 
+  * @{
+  */  
+#define OB_BOR_LEVEL3          ((uint8_t)0x00)  /*!< Supply voltage ranges from 2.70 to 3.60 V */
+#define OB_BOR_LEVEL2          ((uint8_t)0x04)  /*!< Supply voltage ranges from 2.40 to 2.70 V */
+#define OB_BOR_LEVEL1          ((uint8_t)0x08)  /*!< Supply voltage ranges from 2.10 to 2.40 V */
+#define OB_BOR_OFF             ((uint8_t)0x0C)  /*!< Supply voltage ranges from 1.62 to 2.10 V */
+#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
+                          ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
+/**
+  * @}
+  */
+  
+/** @defgroup FLASH_Dual_Boot
+  * @{
+  */
+#define OB_Dual_BootEnabled   ((uint8_t)0x10) /*!< Dual Bank Boot Enable                             */
+#define OB_Dual_BootDisabled  ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */
+#define IS_OB_BOOT(BOOT) (((BOOT) == OB_Dual_BootEnabled) || ((BOOT) == OB_Dual_BootDisabled))
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Interrupts 
+  * @{
+  */ 
+#define FLASH_IT_EOP                   ((uint32_t)0x01000000)  /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_ERR                   ((uint32_t)0x02000000)  /*!< Error Interrupt source */
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000))
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Flags 
+  * @{
+  */ 
+#define FLASH_FLAG_EOP                 ((uint32_t)0x00000001)  /*!< FLASH End of Operation flag               */
+#define FLASH_FLAG_OPERR               ((uint32_t)0x00000002)  /*!< FLASH operation Error flag                */
+#define FLASH_FLAG_WRPERR              ((uint32_t)0x00000010)  /*!< FLASH Write protected error flag          */
+#define FLASH_FLAG_PGAERR              ((uint32_t)0x00000020)  /*!< FLASH Programming Alignment error flag    */
+#define FLASH_FLAG_PGPERR              ((uint32_t)0x00000040)  /*!< FLASH Programming Parallelism error flag  */
+#define FLASH_FLAG_PGSERR              ((uint32_t)0x00000080)  /*!< FLASH Programming Sequence error flag     */
+#define FLASH_FLAG_RDERR               ((uint32_t)0x00000100)  /*!< Read Protection error flag (PCROP)        */
+#define FLASH_FLAG_BSY                 ((uint32_t)0x00010000)  /*!< FLASH Busy flag                           */ 
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFE0C) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_EOP)    || ((FLAG) == FLASH_FLAG_OPERR)  || \
+                                  ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \
+                                  ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \
+                                  ((FLAG) == FLASH_FLAG_BSY)    || ((FLAG) == FLASH_FLAG_RDERR))
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Program_Parallelism   
+  * @{
+  */
+#define FLASH_PSIZE_BYTE           ((uint32_t)0x00000000)
+#define FLASH_PSIZE_HALF_WORD      ((uint32_t)0x00000100)
+#define FLASH_PSIZE_WORD           ((uint32_t)0x00000200)
+#define FLASH_PSIZE_DOUBLE_WORD    ((uint32_t)0x00000300)
+#define CR_PSIZE_MASK              ((uint32_t)0xFFFFFCFF)
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Keys 
+  * @{
+  */ 
+#define RDP_KEY                  ((uint16_t)0x00A5)
+#define FLASH_KEY1               ((uint32_t)0x45670123)
+#define FLASH_KEY2               ((uint32_t)0xCDEF89AB)
+#define FLASH_OPT_KEY1           ((uint32_t)0x08192A3B)
+#define FLASH_OPT_KEY2           ((uint32_t)0x4C5D6E7F)
+/**
+  * @}
+  */ 
+
+/** 
+  * @brief   ACR register byte 0 (Bits[7:0]) base address  
+  */ 
+#define ACR_BYTE0_ADDRESS           ((uint32_t)0x40023C00) 
+/** 
+  * @brief   OPTCR register byte 0 (Bits[7:0]) base address  
+  */ 
+#define OPTCR_BYTE0_ADDRESS         ((uint32_t)0x40023C14)
+/** 
+  * @brief   OPTCR register byte 1 (Bits[15:8]) base address  
+  */ 
+#define OPTCR_BYTE1_ADDRESS         ((uint32_t)0x40023C15)
+/** 
+  * @brief   OPTCR register byte 2 (Bits[23:16]) base address  
+  */ 
+#define OPTCR_BYTE2_ADDRESS         ((uint32_t)0x40023C16)
+/** 
+  * @brief   OPTCR register byte 3 (Bits[31:24]) base address  
+  */ 
+#define OPTCR_BYTE3_ADDRESS         ((uint32_t)0x40023C17)
+
+/** 
+  * @brief   OPTCR1 register byte 0 (Bits[7:0]) base address  
+  */ 
+#define OPTCR1_BYTE2_ADDRESS         ((uint32_t)0x40023C1A)
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+ 
+/* FLASH Interface configuration functions ************************************/
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_PrefetchBufferCmd(FunctionalState NewState);
+void FLASH_InstructionCacheCmd(FunctionalState NewState);
+void FLASH_DataCacheCmd(FunctionalState NewState);
+void FLASH_InstructionCacheReset(void);
+void FLASH_DataCacheReset(void);
+
+/* FLASH Memory Programming functions *****************************************/   
+void         FLASH_Unlock(void);
+void         FLASH_Lock(void);
+FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange);
+FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange);
+FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange);
+FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange);
+FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);
+
+/* Option Bytes Programming functions *****************************************/ 
+void         FLASH_OB_Unlock(void);
+void         FLASH_OB_Lock(void);
+void         FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
+void         FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState);
+void         FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP);
+void         FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState);
+void         FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState);
+void         FLASH_OB_RDPConfig(uint8_t OB_RDP);
+void         FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
+void         FLASH_OB_BORConfig(uint8_t OB_BOR);
+void         FLASH_OB_BootConfig(uint8_t OB_BOOT);
+FLASH_Status FLASH_OB_Launch(void);
+uint8_t      FLASH_OB_GetUser(void);
+uint16_t     FLASH_OB_GetWRP(void);
+uint16_t     FLASH_OB_GetWRP1(void);
+uint16_t     FLASH_OB_GetPCROP(void);
+uint16_t     FLASH_OB_GetPCROP1(void);
+FlagStatus   FLASH_OB_GetRDP(void);
+uint8_t      FLASH_OB_GetBOR(void);
+
+/* Interrupts and flags management functions **********************************/
+void         FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
+FlagStatus   FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+void         FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_FLASH_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+

底盘/底盘-old/底盘/Library/stm32f4xx_flash_ramfunc.c

@@ -0,0 +1,150 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_flash_ramfunc.c
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   FLASH RAMFUNC module driver.
+  *          This file provides a FLASH firmware functions which should be 
+  *          executed from internal SRAM
+  *            + Stop/Start the flash interface while System Run
+  *            + Enable/Disable the flash sleep while System Run
+  *  
+ @verbatim    
+ ==============================================================================
+                    ##### APIs executed from Internal RAM #####
+  ==============================================================================
+  [..]
+    *** ARM Compiler ***
+    --------------------
+    [..] RAM functions are defined using the toolchain options. 
+         Functions that are be executed in RAM should reside in a separate
+         source module. Using the 'Options for File' dialog you can simply change
+         the 'Code / Const' area of a module to a memory space in physical RAM.
+         Available memory areas are declared in the 'Target' tab of the 
+         Options for Target' dialog.
+
+    *** ICCARM Compiler ***
+    -----------------------
+    [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
+
+    *** GNU Compiler ***
+    --------------------
+    [..] RAM functions are defined using a specific toolchain attribute
+         "__attribute__((section(".RamFunc")))".
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_flash_ramfunc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup FLASH RAMFUNC 
+  * @brief FLASH RAMFUNC driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup FLASH_RAMFUNC_Private_Functions
+  * @{
+  */
+
+/** @defgroup FLASH_RAMFUNC_Group1 Peripheral features functions executed from internal RAM 
+  *  @brief Peripheral Extended features functions 
+  *
+@verbatim   
+
+ ===============================================================================
+                      ##### ramfunc functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions that should be executed from RAM 
+    transfers.
+    
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Start/Stop the flash interface while System Run
+  * @note  This mode is only available for STM32F411xx devices. 
+  * @note  This mode could n't be set while executing with the flash itself. 
+  *        It should be done with specific routine executed from RAM.     
+  * @param  NewState: new state of the Smart Card mode.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+__RAM_FUNC FLASH_FlashInterfaceCmd(FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    /* Start the flash interface while System Run */
+    CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
+  }
+  else
+  {
+    /* Stop the flash interface while System Run */  
+    SET_BIT(PWR->CR, PWR_CR_FISSR);
+  }
+}
+
+/**
+  * @brief Enable/Disable the flash sleep while System Run
+  * @note  This mode is only available for STM32F411xx devices. 
+  * @note  This mode could n't be set while executing with the flash itself. 
+  *        It should be done with specific routine executed from RAM.     
+  * @param  NewState: new state of the Smart Card mode.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+__RAM_FUNC FLASH_FlashSleepModeCmd(FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    /* Enable the flash sleep while System Run */
+    SET_BIT(PWR->CR, PWR_CR_FMSSR);
+  }
+  else
+  {
+    /* Disable the flash sleep while System Run */
+    CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

底盘/底盘-old/底盘/Library/stm32f4xx_flash_ramfunc.h

@@ -0,0 +1,95 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_flash_ramfunc.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   Header file of FLASH RAMFUNC driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_FLASH_RAMFUNC_H
+#define __STM32F4xx_FLASH_RAMFUNC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH RAMFUNC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** 
+  * @brief  __RAM_FUNC definition
+  */ 
+#if defined ( __CC_ARM   )
+/* ARM Compiler
+   ------------
+   RAM functions are defined using the toolchain options. 
+   Functions that are executed in RAM should reside in a separate source module.
+   Using the 'Options for File' dialog you can simply change the 'Code / Const' 
+   area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+   dialog. 
+*/
+#define __RAM_FUNC void 
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc". 
+*/
+#define __RAM_FUNC __ramfunc void
+
+#elif defined   (  __GNUC__  )
+/* GNU Compiler
+   ------------
+  RAM functions are defined using a specific toolchain attribute 
+   "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC void  __attribute__((section(".RamFunc")))
+
+#endif
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+__RAM_FUNC FLASH_FlashInterfaceCmd(FunctionalState NewState);
+__RAM_FUNC FLASH_FlashSleepModeCmd(FunctionalState NewState);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_FLASH_RAMFUNC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+

底盘/底盘-old/底盘/Library/stm32f4xx_fmpi2c.h

@@ -0,0 +1,466 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_fmpi2c.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the I2C Fast Mode
+  *          Plus firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_FMPI2C_H
+#define __STM32F4xx_FMPI2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup FMPI2C
+  * @{
+  */
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  FMPI2C Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t FMPI2C_Timing;              /*!< Specifies the FMPI2C_TIMINGR_register value.
+                                         This parameter calculated by referring to FMPI2C initialization 
+                                         section in Reference manual*/
+
+  uint32_t FMPI2C_AnalogFilter;        /*!< Enables or disables analog noise filter.
+                                         This parameter can be a value of @ref FMPI2C_Analog_Filter */
+
+  uint32_t FMPI2C_DigitalFilter;       /*!< Configures the digital noise filter.
+                                         This parameter can be a number between 0x00 and 0x0F */
+
+  uint32_t FMPI2C_Mode;                /*!< Specifies the FMPI2C mode.
+                                         This parameter can be a value of @ref FMPI2C_mode */
+
+  uint32_t FMPI2C_OwnAddress1;         /*!< Specifies the device own address 1.
+                                         This parameter can be a 7-bit or 10-bit address */
+
+  uint32_t FMPI2C_Ack;                 /*!< Enables or disables the acknowledgement.
+                                         This parameter can be a value of @ref FMPI2C_acknowledgement */
+
+  uint32_t FMPI2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+                                         This parameter can be a value of @ref FMPI2C_acknowledged_address */
+}FMPI2C_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+
+/** @defgroup FMPI2C_Exported_Constants
+  * @{
+  */
+
+#define IS_FMPI2C_ALL_PERIPH(PERIPH)       ((PERIPH) == FMPI2C1) 
+
+/** @defgroup FMPI2C_Analog_Filter 
+  * @{
+  */
+
+#define FMPI2C_AnalogFilter_Enable         ((uint32_t)0x00000000)
+#define FMPI2C_AnalogFilter_Disable        FMPI2C_CR1_ANFOFF
+
+#define IS_FMPI2C_ANALOG_FILTER(FILTER)    (((FILTER) == FMPI2C_AnalogFilter_Enable) || \
+                                         ((FILTER) == FMPI2C_AnalogFilter_Disable))
+/**
+  * @}
+  */
+     
+/** @defgroup FMPI2C_Digital_Filter
+  * @{
+  */
+
+#define IS_FMPI2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000F)
+/**
+  * @}
+  */
+
+/** @defgroup FMPI2C_mode 
+  * @{
+  */
+
+#define FMPI2C_Mode_FMPI2C                ((uint32_t)0x00000000)
+#define FMPI2C_Mode_SMBusDevice            FMPI2C_CR1_SMBDEN
+#define FMPI2C_Mode_SMBusHost              FMPI2C_CR1_SMBHEN
+
+#define IS_FMPI2C_MODE(MODE)               (((MODE) == FMPI2C_Mode_FMPI2C) || \
+                                         ((MODE) == FMPI2C_Mode_SMBusDevice) || \
+                                         ((MODE) == FMPI2C_Mode_SMBusHost))
+/**
+  * @}
+  */
+
+/** @defgroup FMPI2C_acknowledgement
+  * @{
+  */
+
+#define FMPI2C_Ack_Enable                  ((uint32_t)0x00000000)
+#define FMPI2C_Ack_Disable                 FMPI2C_CR2_NACK
+
+#define IS_FMPI2C_ACK(ACK)                 (((ACK) == FMPI2C_Ack_Enable) || \
+                                         ((ACK) == FMPI2C_Ack_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup FMPI2C_acknowledged_address
+  * @{
+  */
+
+#define FMPI2C_AcknowledgedAddress_7bit    ((uint32_t)0x00000000)
+#define FMPI2C_AcknowledgedAddress_10bit   FMPI2C_OAR1_OA1MODE
+
+#define IS_FMPI2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == FMPI2C_AcknowledgedAddress_7bit) || \
+                                             ((ADDRESS) == FMPI2C_AcknowledgedAddress_10bit))
+/**
+  * @}
+  */ 
+
+/** @defgroup FMPI2C_own_address1
+  * @{
+  */
+
+#define IS_FMPI2C_OWN_ADDRESS1(ADDRESS1)   ((ADDRESS1) <= (uint32_t)0x000003FF)
+/**
+  * @}
+  */
+
+/** @defgroup FMPI2C_transfer_direction 
+  * @{
+  */
+
+#define FMPI2C_Direction_Transmitter       ((uint16_t)0x0000)
+#define FMPI2C_Direction_Receiver          ((uint16_t)0x0400)
+
+#define IS_FMPI2C_DIRECTION(DIRECTION)     (((DIRECTION) == FMPI2C_Direction_Transmitter) || \
+                                         ((DIRECTION) == FMPI2C_Direction_Receiver))
+/**
+  * @}
+  */
+
+/** @defgroup FMPI2C_DMA_transfer_requests 
+  * @{
+  */
+
+#define FMPI2C_DMAReq_Tx                   FMPI2C_CR1_TXDMAEN
+#define FMPI2C_DMAReq_Rx                   FMPI2C_CR1_RXDMAEN
+
+#define IS_FMPI2C_DMA_REQ(REQ)             ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup FMPI2C_slave_address
+  * @{
+  */
+
+#define IS_FMPI2C_SLAVE_ADDRESS(ADDRESS)   ((ADDRESS) <= (uint16_t)0x03FF)
+/**
+  * @}
+  */
+
+
+/** @defgroup FMPI2C_own_address2
+  * @{
+  */
+
+#define IS_FMPI2C_OWN_ADDRESS2(ADDRESS2)   ((ADDRESS2) <= (uint16_t)0x00FF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMPI2C_own_address2_mask
+  * @{
+  */
+
+#define FMPI2C_OA2_NoMask                  ((uint8_t)0x00)
+#define FMPI2C_OA2_Mask01                  ((uint8_t)0x01)
+#define FMPI2C_OA2_Mask02                  ((uint8_t)0x02)
+#define FMPI2C_OA2_Mask03                  ((uint8_t)0x03)
+#define FMPI2C_OA2_Mask04                  ((uint8_t)0x04)
+#define FMPI2C_OA2_Mask05                  ((uint8_t)0x05)
+#define FMPI2C_OA2_Mask06                  ((uint8_t)0x06)
+#define FMPI2C_OA2_Mask07                  ((uint8_t)0x07)
+
+#define IS_FMPI2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == FMPI2C_OA2_NoMask) || \
+                                         ((MASK) == FMPI2C_OA2_Mask01) || \
+                                         ((MASK) == FMPI2C_OA2_Mask02) || \
+                                         ((MASK) == FMPI2C_OA2_Mask03) || \
+                                         ((MASK) == FMPI2C_OA2_Mask04) || \
+                                         ((MASK) == FMPI2C_OA2_Mask05) || \
+                                         ((MASK) == FMPI2C_OA2_Mask06) || \
+                                         ((MASK) == FMPI2C_OA2_Mask07))  
+
+/**
+  * @}
+  */
+
+/** @defgroup FMPI2C_timeout
+  * @{
+  */
+
+#define IS_FMPI2C_TIMEOUT(TIMEOUT)   ((TIMEOUT) <= (uint16_t)0x0FFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMPI2C_registers 
+  * @{
+  */
+
+#define FMPI2C_Register_CR1                ((uint8_t)0x00)
+#define FMPI2C_Register_CR2                ((uint8_t)0x04)
+#define FMPI2C_Register_OAR1               ((uint8_t)0x08)
+#define FMPI2C_Register_OAR2               ((uint8_t)0x0C)
+#define FMPI2C_Register_TIMINGR            ((uint8_t)0x10)
+#define FMPI2C_Register_TIMEOUTR           ((uint8_t)0x14)
+#define FMPI2C_Register_ISR                ((uint8_t)0x18)
+#define FMPI2C_Register_ICR                ((uint8_t)0x1C)
+#define FMPI2C_Register_PECR               ((uint8_t)0x20)
+#define FMPI2C_Register_RXDR               ((uint8_t)0x24)
+#define FMPI2C_Register_TXDR               ((uint8_t)0x28)
+
+#define IS_FMPI2C_REGISTER(REGISTER)       (((REGISTER) == FMPI2C_Register_CR1) || \
+                                         ((REGISTER) == FMPI2C_Register_CR2) || \
+                                         ((REGISTER) == FMPI2C_Register_OAR1) || \
+                                         ((REGISTER) == FMPI2C_Register_OAR2) || \
+                                         ((REGISTER) == FMPI2C_Register_TIMINGR) || \
+                                         ((REGISTER) == FMPI2C_Register_TIMEOUTR) || \
+                                         ((REGISTER) == FMPI2C_Register_ISR) || \
+                                         ((REGISTER) == FMPI2C_Register_ICR) || \
+                                         ((REGISTER) == FMPI2C_Register_PECR) || \
+                                         ((REGISTER) == FMPI2C_Register_RXDR) || \
+                                         ((REGISTER) == FMPI2C_Register_TXDR))
+/**
+  * @}
+  */
+
+/** @defgroup FMPI2C_interrupts_definition 
+  * @{
+  */
+
+#define FMPI2C_IT_ERRI                     FMPI2C_CR1_ERRIE
+#define FMPI2C_IT_TCI                      FMPI2C_CR1_TCIE
+#define FMPI2C_IT_STOPI                    FMPI2C_CR1_STOPIE
+#define FMPI2C_IT_NACKI                    FMPI2C_CR1_NACKIE
+#define FMPI2C_IT_ADDRI                    FMPI2C_CR1_ADDRIE
+#define FMPI2C_IT_RXI                      FMPI2C_CR1_RXIE
+#define FMPI2C_IT_TXI                      FMPI2C_CR1_TXIE
+
+#define IS_FMPI2C_CONFIG_IT(IT)            ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup FMPI2C_flags_definition 
+  * @{
+  */
+
+#define  FMPI2C_FLAG_TXE                   FMPI2C_ISR_TXE
+#define  FMPI2C_FLAG_TXIS                  FMPI2C_ISR_TXIS
+#define  FMPI2C_FLAG_RXNE                  FMPI2C_ISR_RXNE
+#define  FMPI2C_FLAG_ADDR                  FMPI2C_ISR_ADDR
+#define  FMPI2C_FLAG_NACKF                 FMPI2C_ISR_NACKF
+#define  FMPI2C_FLAG_STOPF                 FMPI2C_ISR_STOPF
+#define  FMPI2C_FLAG_TC                    FMPI2C_ISR_TC
+#define  FMPI2C_FLAG_TCR                   FMPI2C_ISR_TCR
+#define  FMPI2C_FLAG_BERR                  FMPI2C_ISR_BERR
+#define  FMPI2C_FLAG_ARLO                  FMPI2C_ISR_ARLO
+#define  FMPI2C_FLAG_OVR                   FMPI2C_ISR_OVR
+#define  FMPI2C_FLAG_PECERR                FMPI2C_ISR_PECERR
+#define  FMPI2C_FLAG_TIMEOUT               FMPI2C_ISR_TIMEOUT
+#define  FMPI2C_FLAG_ALERT                 FMPI2C_ISR_ALERT
+#define  FMPI2C_FLAG_BUSY                  FMPI2C_ISR_BUSY
+
+#define IS_FMPI2C_CLEAR_FLAG(FLAG)         ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00))
+
+#define IS_FMPI2C_GET_FLAG(FLAG)           (((FLAG) == FMPI2C_FLAG_TXE) || ((FLAG) == FMPI2C_FLAG_TXIS) || \
+                                         ((FLAG) == FMPI2C_FLAG_RXNE) || ((FLAG) == FMPI2C_FLAG_ADDR) || \
+                                         ((FLAG) == FMPI2C_FLAG_NACKF) || ((FLAG) == FMPI2C_FLAG_STOPF) || \
+                                         ((FLAG) == FMPI2C_FLAG_TC) || ((FLAG) == FMPI2C_FLAG_TCR) || \
+                                         ((FLAG) == FMPI2C_FLAG_BERR) || ((FLAG) == FMPI2C_FLAG_ARLO) || \
+                                         ((FLAG) == FMPI2C_FLAG_OVR) || ((FLAG) == FMPI2C_FLAG_PECERR) || \
+                                         ((FLAG) == FMPI2C_FLAG_TIMEOUT) || ((FLAG) == FMPI2C_FLAG_ALERT) || \
+                                         ((FLAG) == FMPI2C_FLAG_BUSY))
+
+/**
+  * @}
+  */
+
+
+/** @defgroup FMPI2C_interrupts_definition 
+  * @{
+  */
+
+#define  FMPI2C_IT_TXIS                    FMPI2C_ISR_TXIS
+#define  FMPI2C_IT_RXNE                    FMPI2C_ISR_RXNE
+#define  FMPI2C_IT_ADDR                    FMPI2C_ISR_ADDR
+#define  FMPI2C_IT_NACKF                   FMPI2C_ISR_NACKF
+#define  FMPI2C_IT_STOPF                   FMPI2C_ISR_STOPF
+#define  FMPI2C_IT_TC                      FMPI2C_ISR_TC
+#define  FMPI2C_IT_TCR                     FMPI2C_ISR_TCR
+#define  FMPI2C_IT_BERR                    FMPI2C_ISR_BERR
+#define  FMPI2C_IT_ARLO                    FMPI2C_ISR_ARLO
+#define  FMPI2C_IT_OVR                     FMPI2C_ISR_OVR
+#define  FMPI2C_IT_PECERR                  FMPI2C_ISR_PECERR
+#define  FMPI2C_IT_TIMEOUT                 FMPI2C_ISR_TIMEOUT
+#define  FMPI2C_IT_ALERT                   FMPI2C_ISR_ALERT
+
+#define IS_FMPI2C_CLEAR_IT(IT)             ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00))
+                               
+#define IS_FMPI2C_GET_IT(IT)               (((IT) == FMPI2C_IT_TXIS) || ((IT) == FMPI2C_IT_RXNE) || \
+                                         ((IT) == FMPI2C_IT_ADDR) || ((IT) == FMPI2C_IT_NACKF) || \
+                                         ((IT) == FMPI2C_IT_STOPF) || ((IT) == FMPI2C_IT_TC) || \
+                                         ((IT) == FMPI2C_IT_TCR) || ((IT) == FMPI2C_IT_BERR) || \
+                                         ((IT) == FMPI2C_IT_ARLO) || ((IT) == FMPI2C_IT_OVR) || \
+                                         ((IT) == FMPI2C_IT_PECERR) || ((IT) == FMPI2C_IT_TIMEOUT) || \
+                                         ((IT) == FMPI2C_IT_ALERT))
+
+/**
+  * @}
+  */
+
+/** @defgroup FMPI2C_ReloadEndMode_definition 
+  * @{
+  */
+
+#define  FMPI2C_Reload_Mode                FMPI2C_CR2_RELOAD
+#define  FMPI2C_AutoEnd_Mode               FMPI2C_CR2_AUTOEND
+#define  FMPI2C_SoftEnd_Mode               ((uint32_t)0x00000000)
+
+                              
+#define IS_RELOAD_END_MODE(MODE)        (((MODE) == FMPI2C_Reload_Mode) || \
+                                         ((MODE) == FMPI2C_AutoEnd_Mode) || \
+                                         ((MODE) == FMPI2C_SoftEnd_Mode))
+                               
+
+/**
+  * @}
+  */
+
+/** @defgroup FMPI2C_StartStopMode_definition 
+  * @{
+  */
+
+#define  FMPI2C_No_StartStop                 ((uint32_t)0x00000000)
+#define  FMPI2C_Generate_Stop                FMPI2C_CR2_STOP
+#define  FMPI2C_Generate_Start_Read          (uint32_t)(FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN)
+#define  FMPI2C_Generate_Start_Write         FMPI2C_CR2_START
+
+                              
+#define IS_START_STOP_MODE(MODE)        (((MODE) == FMPI2C_Generate_Stop) || \
+                                         ((MODE) == FMPI2C_Generate_Start_Read) || \
+                                         ((MODE) == FMPI2C_Generate_Start_Write) || \
+                                         ((MODE) == FMPI2C_No_StartStop))
+                               
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+
+/* Initialization and Configuration functions *********************************/
+void FMPI2C_DeInit(FMPI2C_TypeDef* FMPI2Cx);
+void FMPI2C_Init(FMPI2C_TypeDef* FMPI2Cx, FMPI2C_InitTypeDef* FMPI2C_InitStruct);
+void FMPI2C_StructInit(FMPI2C_InitTypeDef* FMPI2C_InitStruct);
+void FMPI2C_Cmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
+void FMPI2C_SoftwareResetCmd(FMPI2C_TypeDef* FMPI2Cx);
+void FMPI2C_ITConfig(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_IT, FunctionalState NewState);
+void FMPI2C_StretchClockCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
+void FMPI2C_DualAddressCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
+void FMPI2C_OwnAddress2Config(FMPI2C_TypeDef* FMPI2Cx, uint16_t Address, uint8_t Mask);
+void FMPI2C_GeneralCallCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
+void FMPI2C_SlaveByteControlCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
+void FMPI2C_SlaveAddressConfig(FMPI2C_TypeDef* FMPI2Cx, uint16_t Address);
+void FMPI2C_10BitAddressingModeCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
+
+/* Communications handling functions ******************************************/
+void FMPI2C_AutoEndCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
+void FMPI2C_ReloadCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
+void FMPI2C_NumberOfBytesConfig(FMPI2C_TypeDef* FMPI2Cx, uint8_t Number_Bytes);
+void FMPI2C_MasterRequestConfig(FMPI2C_TypeDef* FMPI2Cx, uint16_t FMPI2C_Direction);
+void FMPI2C_GenerateSTART(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
+void FMPI2C_GenerateSTOP(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
+void FMPI2C_10BitAddressHeaderCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
+void FMPI2C_AcknowledgeConfig(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
+uint8_t FMPI2C_GetAddressMatched(FMPI2C_TypeDef* FMPI2Cx);
+uint16_t FMPI2C_GetTransferDirection(FMPI2C_TypeDef* FMPI2Cx);
+void FMPI2C_TransferHandling(FMPI2C_TypeDef* FMPI2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode);
+
+/*  SMBUS management functions ************************************************/
+void FMPI2C_SMBusAlertCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
+void FMPI2C_ClockTimeoutCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
+void FMPI2C_ExtendedClockTimeoutCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
+void FMPI2C_IdleClockTimeoutCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
+void FMPI2C_TimeoutAConfig(FMPI2C_TypeDef* FMPI2Cx, uint16_t Timeout);
+void FMPI2C_TimeoutBConfig(FMPI2C_TypeDef* FMPI2Cx, uint16_t Timeout);
+void FMPI2C_CalculatePEC(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
+void FMPI2C_PECRequestCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
+uint8_t FMPI2C_GetPEC(FMPI2C_TypeDef* FMPI2Cx);
+
+/* FMPI2C registers management functions *****************************************/
+uint32_t FMPI2C_ReadRegister(FMPI2C_TypeDef* FMPI2Cx, uint8_t FMPI2C_Register);
+
+/* Data transfers management functions ****************************************/
+void FMPI2C_SendData(FMPI2C_TypeDef* FMPI2Cx, uint8_t Data);
+uint8_t FMPI2C_ReceiveData(FMPI2C_TypeDef* FMPI2Cx);
+
+/* DMA transfers management functions *****************************************/
+void FMPI2C_DMACmd(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_DMAReq, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus FMPI2C_GetFlagStatus(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_FLAG);
+void FMPI2C_ClearFlag(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_FLAG);
+ITStatus FMPI2C_GetITStatus(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_IT);
+void FMPI2C_ClearITPendingBit(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_IT);
+
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_FMPI2C_H */
+

底盘/底盘-old/底盘/Library/stm32f4xx_fsmc.h

@@ -0,0 +1,667 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_fsmc.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the FSMC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_FSMC_H
+#define __STM32F4xx_FSMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup FSMC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  Timing parameters For NOR/SRAM Banks  
+  */
+typedef struct
+{
+  uint32_t FSMC_AddressSetupTime;       /*!< Defines the number of HCLK cycles to configure
+                                             the duration of the address setup time. 
+                                             This parameter can be a value between 0 and 0xF.
+                                             @note This parameter is not used with synchronous NOR Flash memories. */
+
+  uint32_t FSMC_AddressHoldTime;        /*!< Defines the number of HCLK cycles to configure
+                                             the duration of the address hold time.
+                                             This parameter can be a value between 0 and 0xF. 
+                                             @note This parameter is not used with synchronous NOR Flash memories.*/
+
+  uint32_t FSMC_DataSetupTime;          /*!< Defines the number of HCLK cycles to configure
+                                             the duration of the data setup time.
+                                             This parameter can be a value between 0 and 0xFF.
+                                             @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
+
+  uint32_t FSMC_BusTurnAroundDuration;  /*!< Defines the number of HCLK cycles to configure
+                                             the duration of the bus turnaround.
+                                             This parameter can be a value between 0 and 0xF.
+                                             @note This parameter is only used for multiplexed NOR Flash memories. */
+
+  uint32_t FSMC_CLKDivision;            /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+                                             This parameter can be a value between 1 and 0xF.
+                                             @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
+
+  uint32_t FSMC_DataLatency;            /*!< Defines the number of memory clock cycles to issue
+                                             to the memory before getting the first data.
+                                             The parameter value depends on the memory type as shown below:
+                                              - It must be set to 0 in case of a CRAM
+                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
+                                              - It may assume a value between 0 and 0xF in NOR Flash memories
+                                                with synchronous burst mode enable */
+
+  uint32_t FSMC_AccessMode;             /*!< Specifies the asynchronous access mode. 
+                                             This parameter can be a value of @ref FSMC_Access_Mode */
+}FSMC_NORSRAMTimingInitTypeDef;
+
+/** 
+  * @brief  FSMC NOR/SRAM Init structure definition
+  */
+typedef struct
+{
+  uint32_t FSMC_Bank;                /*!< Specifies the NOR/SRAM memory bank that will be used.
+                                          This parameter can be a value of @ref FSMC_NORSRAM_Bank */
+
+  uint32_t FSMC_DataAddressMux;      /*!< Specifies whether the address and data values are
+                                          multiplexed on the data bus or not. 
+                                          This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
+
+  uint32_t FSMC_MemoryType;          /*!< Specifies the type of external memory attached to
+                                          the corresponding memory bank.
+                                          This parameter can be a value of @ref FSMC_Memory_Type */
+
+  uint32_t FSMC_MemoryDataWidth;     /*!< Specifies the external memory device width.
+                                          This parameter can be a value of @ref FSMC_Data_Width */
+
+  uint32_t FSMC_BurstAccessMode;     /*!< Enables or disables the burst access mode for Flash memory,
+                                          valid only with synchronous burst Flash memories.
+                                          This parameter can be a value of @ref FSMC_Burst_Access_Mode */
+
+  uint32_t FSMC_AsynchronousWait;     /*!< Enables or disables wait signal during asynchronous transfers,
+                                          valid only with asynchronous Flash memories.
+                                          This parameter can be a value of @ref FSMC_AsynchronousWait */                                          
+
+  uint32_t FSMC_WaitSignalPolarity;  /*!< Specifies the wait signal polarity, valid only when accessing
+                                          the Flash memory in burst mode.
+                                          This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
+
+  uint32_t FSMC_WrapMode;            /*!< Enables or disables the Wrapped burst access mode for Flash
+                                          memory, valid only when accessing Flash memories in burst mode.
+                                          This parameter can be a value of @ref FSMC_Wrap_Mode */
+
+  uint32_t FSMC_WaitSignalActive;    /*!< Specifies if the wait signal is asserted by the memory one
+                                          clock cycle before the wait state or during the wait state,
+                                          valid only when accessing memories in burst mode. 
+                                          This parameter can be a value of @ref FSMC_Wait_Timing */
+
+  uint32_t FSMC_WriteOperation;      /*!< Enables or disables the write operation in the selected bank by the FSMC. 
+                                          This parameter can be a value of @ref FSMC_Write_Operation */
+
+  uint32_t FSMC_WaitSignal;          /*!< Enables or disables the wait state insertion via wait
+                                          signal, valid for Flash memory access in burst mode. 
+                                          This parameter can be a value of @ref FSMC_Wait_Signal */
+
+  uint32_t FSMC_ExtendedMode;        /*!< Enables or disables the extended mode.
+                                          This parameter can be a value of @ref FSMC_Extended_Mode */
+
+  uint32_t FSMC_WriteBurst;          /*!< Enables or disables the write burst operation.
+                                          This parameter can be a value of @ref FSMC_Write_Burst */ 
+
+  FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the  Extended Mode is not used*/  
+
+  FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;     /*!< Timing Parameters for write access if the  Extended Mode is used*/      
+}FSMC_NORSRAMInitTypeDef;
+
+/** 
+  * @brief  Timing parameters For FSMC NAND and PCCARD Banks
+  */
+typedef struct
+{
+  uint32_t FSMC_SetupTime;      /*!< Defines the number of HCLK cycles to setup address before
+                                     the command assertion for NAND Flash read or write access
+                                     to common/Attribute or I/O memory space (depending on
+                                     the memory space timing to be configured).
+                                     This parameter can be a value between 0 and 0xFF.*/
+
+  uint32_t FSMC_WaitSetupTime;  /*!< Defines the minimum number of HCLK cycles to assert the
+                                     command for NAND Flash read or write access to
+                                     common/Attribute or I/O memory space (depending on the
+                                     memory space timing to be configured). 
+                                     This parameter can be a number between 0x00 and 0xFF */
+
+  uint32_t FSMC_HoldSetupTime;  /*!< Defines the number of HCLK clock cycles to hold address
+                                     (and data for write access) after the command de-assertion
+                                     for NAND Flash read or write access to common/Attribute
+                                     or I/O memory space (depending on the memory space timing
+                                     to be configured).
+                                     This parameter can be a number between 0x00 and 0xFF */
+
+  uint32_t FSMC_HiZSetupTime;   /*!< Defines the number of HCLK clock cycles during which the
+                                     data bus is kept in HiZ after the start of a NAND Flash
+                                     write access to common/Attribute or I/O memory space (depending
+                                     on the memory space timing to be configured).
+                                     This parameter can be a number between 0x00 and 0xFF */
+}FSMC_NAND_PCCARDTimingInitTypeDef;
+
+/** 
+  * @brief  FSMC NAND Init structure definition
+  */
+typedef struct
+{
+  uint32_t FSMC_Bank;              /*!< Specifies the NAND memory bank that will be used.
+                                      This parameter can be a value of @ref FSMC_NAND_Bank */
+
+  uint32_t FSMC_Waitfeature;      /*!< Enables or disables the Wait feature for the NAND Memory Bank.
+                                       This parameter can be any value of @ref FSMC_Wait_feature */
+
+  uint32_t FSMC_MemoryDataWidth;  /*!< Specifies the external memory device width.
+                                       This parameter can be any value of @ref FSMC_Data_Width */
+
+  uint32_t FSMC_ECC;              /*!< Enables or disables the ECC computation.
+                                       This parameter can be any value of @ref FSMC_ECC */
+
+  uint32_t FSMC_ECCPageSize;      /*!< Defines the page size for the extended ECC.
+                                       This parameter can be any value of @ref FSMC_ECC_Page_Size */
+
+  uint32_t FSMC_TCLRSetupTime;    /*!< Defines the number of HCLK cycles to configure the
+                                       delay between CLE low and RE low.
+                                       This parameter can be a value between 0 and 0xFF. */
+
+  uint32_t FSMC_TARSetupTime;     /*!< Defines the number of HCLK cycles to configure the
+                                       delay between ALE low and RE low.
+                                       This parameter can be a number between 0x0 and 0xFF */ 
+
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;   /*!< FSMC Common Space Timing */ 
+
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
+}FSMC_NANDInitTypeDef;
+
+/** 
+  * @brief  FSMC PCCARD Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t FSMC_Waitfeature;    /*!< Enables or disables the Wait feature for the Memory Bank.
+                                    This parameter can be any value of @ref FSMC_Wait_feature */
+
+  uint32_t FSMC_TCLRSetupTime;  /*!< Defines the number of HCLK cycles to configure the
+                                     delay between CLE low and RE low.
+                                     This parameter can be a value between 0 and 0xFF. */
+
+  uint32_t FSMC_TARSetupTime;   /*!< Defines the number of HCLK cycles to configure the
+                                     delay between ALE low and RE low.
+                                     This parameter can be a number between 0x0 and 0xFF */ 
+
+  
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
+
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;  /*!< FSMC Attribute Space Timing */ 
+  
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */  
+}FSMC_PCCARDInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FSMC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup FSMC_NORSRAM_Bank 
+  * @{
+  */
+#define FSMC_Bank1_NORSRAM1                      ((uint32_t)0x00000000)
+#define FSMC_Bank1_NORSRAM2                      ((uint32_t)0x00000002)
+#define FSMC_Bank1_NORSRAM3                      ((uint32_t)0x00000004)
+#define FSMC_Bank1_NORSRAM4                      ((uint32_t)0x00000006)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_NAND_Bank 
+  * @{
+  */  
+#define FSMC_Bank2_NAND                          ((uint32_t)0x00000010)
+#define FSMC_Bank3_NAND                          ((uint32_t)0x00000100)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_PCCARD_Bank 
+  * @{
+  */    
+#define FSMC_Bank4_PCCARD                        ((uint32_t)0x00001000)
+/**
+  * @}
+  */
+
+#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
+                                    ((BANK) == FSMC_Bank1_NORSRAM2) || \
+                                    ((BANK) == FSMC_Bank1_NORSRAM3) || \
+                                    ((BANK) == FSMC_Bank1_NORSRAM4))
+
+#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+                                 ((BANK) == FSMC_Bank3_NAND))
+
+#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+                                    ((BANK) == FSMC_Bank3_NAND) || \
+                                    ((BANK) == FSMC_Bank4_PCCARD))
+
+#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+                               ((BANK) == FSMC_Bank3_NAND) || \
+                               ((BANK) == FSMC_Bank4_PCCARD))
+
+/** @defgroup FSMC_NOR_SRAM_Controller 
+  * @{
+  */
+
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing 
+  * @{
+  */
+
+#define FSMC_DataAddressMux_Disable                ((uint32_t)0x00000000)
+#define FSMC_DataAddressMux_Enable                 ((uint32_t)0x00000002)
+#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
+                          ((MUX) == FSMC_DataAddressMux_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Memory_Type 
+  * @{
+  */
+
+#define FSMC_MemoryType_SRAM                     ((uint32_t)0x00000000)
+#define FSMC_MemoryType_PSRAM                    ((uint32_t)0x00000004)
+#define FSMC_MemoryType_NOR                      ((uint32_t)0x00000008)
+#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
+                                ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
+                                ((MEMORY) == FSMC_MemoryType_NOR))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Width 
+  * @{
+  */
+
+#define FSMC_MemoryDataWidth_8b                  ((uint32_t)0x00000000)
+#define FSMC_MemoryDataWidth_16b                 ((uint32_t)0x00000010)
+#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
+                                     ((WIDTH) == FSMC_MemoryDataWidth_16b))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Burst_Access_Mode 
+  * @{
+  */
+
+#define FSMC_BurstAccessMode_Disable             ((uint32_t)0x00000000) 
+#define FSMC_BurstAccessMode_Enable              ((uint32_t)0x00000100)
+#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
+                                  ((STATE) == FSMC_BurstAccessMode_Enable))
+/**
+  * @}
+  */
+    
+/** @defgroup FSMC_AsynchronousWait 
+  * @{
+  */
+#define FSMC_AsynchronousWait_Disable            ((uint32_t)0x00000000)
+#define FSMC_AsynchronousWait_Enable             ((uint32_t)0x00008000)
+#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
+                                 ((STATE) == FSMC_AsynchronousWait_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Signal_Polarity 
+  * @{
+  */
+#define FSMC_WaitSignalPolarity_Low              ((uint32_t)0x00000000)
+#define FSMC_WaitSignalPolarity_High             ((uint32_t)0x00000200)
+#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
+                                         ((POLARITY) == FSMC_WaitSignalPolarity_High))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wrap_Mode 
+  * @{
+  */
+#define FSMC_WrapMode_Disable                    ((uint32_t)0x00000000)
+#define FSMC_WrapMode_Enable                     ((uint32_t)0x00000400) 
+#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
+                                 ((MODE) == FSMC_WrapMode_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Timing 
+  * @{
+  */
+#define FSMC_WaitSignalActive_BeforeWaitState    ((uint32_t)0x00000000)
+#define FSMC_WaitSignalActive_DuringWaitState    ((uint32_t)0x00000800) 
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
+                                            ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Write_Operation 
+  * @{
+  */
+#define FSMC_WriteOperation_Disable                     ((uint32_t)0x00000000)
+#define FSMC_WriteOperation_Enable                      ((uint32_t)0x00001000)
+#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
+                                            ((OPERATION) == FSMC_WriteOperation_Enable))                         
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Signal 
+  * @{
+  */
+#define FSMC_WaitSignal_Disable                  ((uint32_t)0x00000000)
+#define FSMC_WaitSignal_Enable                   ((uint32_t)0x00002000) 
+#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
+                                      ((SIGNAL) == FSMC_WaitSignal_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Extended_Mode 
+  * @{
+  */
+#define FSMC_ExtendedMode_Disable                ((uint32_t)0x00000000)
+#define FSMC_ExtendedMode_Enable                 ((uint32_t)0x00004000)
+
+#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
+                                     ((MODE) == FSMC_ExtendedMode_Enable)) 
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Write_Burst 
+  * @{
+  */
+
+#define FSMC_WriteBurst_Disable                  ((uint32_t)0x00000000)
+#define FSMC_WriteBurst_Enable                   ((uint32_t)0x00080000) 
+#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
+                                    ((BURST) == FSMC_WriteBurst_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Address_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Address_Hold_Time 
+  * @{
+  */
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Bus_Turn_around_Duration 
+  * @{
+  */
+#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_CLK_Division 
+  * @{
+  */
+#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Latency 
+  * @{
+  */
+#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Access_Mode 
+  * @{
+  */
+#define FSMC_AccessMode_A                        ((uint32_t)0x00000000)
+#define FSMC_AccessMode_B                        ((uint32_t)0x10000000) 
+#define FSMC_AccessMode_C                        ((uint32_t)0x20000000)
+#define FSMC_AccessMode_D                        ((uint32_t)0x30000000)
+#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
+                                   ((MODE) == FSMC_AccessMode_B) || \
+                                   ((MODE) == FSMC_AccessMode_C) || \
+                                   ((MODE) == FSMC_AccessMode_D))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/** @defgroup FSMC_NAND_PCCARD_Controller 
+  * @{
+  */
+
+/** @defgroup FSMC_Wait_feature 
+  * @{
+  */
+#define FSMC_Waitfeature_Disable                 ((uint32_t)0x00000000)
+#define FSMC_Waitfeature_Enable                  ((uint32_t)0x00000002)
+#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
+                                       ((FEATURE) == FSMC_Waitfeature_Enable))
+/**
+  * @}
+  */
+
+
+/** @defgroup FSMC_ECC 
+  * @{
+  */
+#define FSMC_ECC_Disable                         ((uint32_t)0x00000000)
+#define FSMC_ECC_Enable                          ((uint32_t)0x00000040)
+#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
+                                  ((STATE) == FSMC_ECC_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_ECC_Page_Size 
+  * @{
+  */
+#define FSMC_ECCPageSize_256Bytes                ((uint32_t)0x00000000)
+#define FSMC_ECCPageSize_512Bytes                ((uint32_t)0x00020000)
+#define FSMC_ECCPageSize_1024Bytes               ((uint32_t)0x00040000)
+#define FSMC_ECCPageSize_2048Bytes               ((uint32_t)0x00060000)
+#define FSMC_ECCPageSize_4096Bytes               ((uint32_t)0x00080000)
+#define FSMC_ECCPageSize_8192Bytes               ((uint32_t)0x000A0000)
+#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_8192Bytes))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_TCLR_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_TAR_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Hold_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_HiZ_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Interrupt_sources 
+  * @{
+  */
+#define FSMC_IT_RisingEdge                       ((uint32_t)0x00000008)
+#define FSMC_IT_Level                            ((uint32_t)0x00000010)
+#define FSMC_IT_FallingEdge                      ((uint32_t)0x00000020)
+#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
+#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
+                            ((IT) == FSMC_IT_Level) || \
+                            ((IT) == FSMC_IT_FallingEdge)) 
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Flags 
+  * @{
+  */
+#define FSMC_FLAG_RisingEdge                     ((uint32_t)0x00000001)
+#define FSMC_FLAG_Level                          ((uint32_t)0x00000002)
+#define FSMC_FLAG_FallingEdge                    ((uint32_t)0x00000004)
+#define FSMC_FLAG_FEMPT                          ((uint32_t)0x00000040)
+#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
+                                ((FLAG) == FSMC_FLAG_Level) || \
+                                ((FLAG) == FSMC_FLAG_FallingEdge) || \
+                                ((FLAG) == FSMC_FLAG_FEMPT))
+
+#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/* NOR/SRAM Controller functions **********************************************/
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+
+/* NAND Controller functions **************************************************/
+void FSMC_NANDDeInit(uint32_t FSMC_Bank);
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
+
+/* PCCARD Controller functions ************************************************/
+void FSMC_PCCARDDeInit(void);
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
+void FSMC_PCCARDCmd(FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_FSMC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+

底盘/底盘-old/底盘/Library/stm32f4xx_gpio.c

@@ -0,0 +1,603 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_gpio.c
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the GPIO peripheral:           
+  *           + Initialization and Configuration
+  *           + GPIO Read and Write
+  *           + GPIO Alternate functions configuration
+  * 
+@verbatim  
+ ===============================================================================
+                      ##### How to use this driver #####
+ ===============================================================================       
+ [..]             
+   (#) Enable the GPIO AHB clock using the following function
+       RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+               
+   (#) Configure the GPIO pin(s) using GPIO_Init()
+       Four possible configuration are available for each pin:
+       (++) Input: Floating, Pull-up, Pull-down.
+       (++) Output: Push-Pull (Pull-up, Pull-down or no Pull)
+            Open Drain (Pull-up, Pull-down or no Pull). In output mode, the speed 
+            is configurable: 2 MHz, 25 MHz, 50 MHz or 100 MHz.
+       (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) Open 
+            Drain (Pull-up, Pull-down or no Pull).
+       (++) Analog: required mode when a pin is to be used as ADC channel or DAC 
+            output.
+   
+   (#) Peripherals alternate function:
+       (++) For ADC and DAC, configure the desired pin in analog mode using 
+            GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN;
+            (+++) For other peripherals (TIM, USART...):
+            (+++) Connect the pin to the desired peripherals' Alternate 
+                     Function (AF) using GPIO_PinAFConfig() function
+            (+++) Configure the desired pin in alternate function mode using
+                     GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+            (+++) Select the type, pull-up/pull-down and output speed via 
+                     GPIO_PuPd, GPIO_OType and GPIO_Speed members
+            (+++) Call GPIO_Init() function
+          
+   (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
+            
+   (#) To set/reset the level of a pin configured in output mode use 
+       GPIO_SetBits()/GPIO_ResetBits()
+                 
+   (#) During and just after reset, the alternate functions are not 
+       active and the GPIO pins are configured in input floating mode (except JTAG
+       pins).
+  
+   (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose 
+       (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has 
+       priority over the GPIO function.
+  
+   (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as 
+       general purpose PH0 and PH1, respectively, when the HSE oscillator is off. 
+       The HSE has priority over the GPIO function.
+               
+@endverbatim        
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_gpio.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup GPIO 
+  * @brief GPIO driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup GPIO_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup GPIO_Group1 Initialization and Configuration
+ *  @brief   Initialization and Configuration
+ *
+@verbatim   
+ ===============================================================================
+                 ##### Initialization and Configuration #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
+  * @note   By default, The GPIO pins are configured in input floating mode (except JTAG pins).
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.  
+  * @retval None
+  */
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  if (GPIOx == GPIOA)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE);
+  }
+  else if (GPIOx == GPIOB)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE);
+  }
+  else if (GPIOx == GPIOC)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE);
+  }
+  else if (GPIOx == GPIOD)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE);
+  }
+  else if (GPIOx == GPIOE)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE);
+  }
+  else if (GPIOx == GPIOF)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE);
+  }
+  else if (GPIOx == GPIOG)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE);
+  }
+  else if (GPIOx == GPIOH)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE);
+  }
+
+  else if (GPIOx == GPIOI)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE);
+  }
+  else if (GPIOx == GPIOJ)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, DISABLE);
+  }
+  else
+  {
+    if (GPIOx == GPIOK)
+    {
+      RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, ENABLE);
+      RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.   
+  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+  uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
+  assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+  assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
+
+  /* ------------------------- Configure the port pins ---------------- */
+  /*-- GPIO Mode Configuration --*/
+  for (pinpos = 0x00; pinpos < 0x10; pinpos++)
+  {
+    pos = ((uint32_t)0x01) << pinpos;
+    /* Get the port pins position */
+    currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+
+    if (currentpin == pos)
+    {
+      GPIOx->MODER  &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
+      GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
+
+      if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
+      {
+        /* Check Speed mode parameters */
+        assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
+
+        /* Speed mode configuration */
+        GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
+        GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
+
+        /* Check Output mode parameters */
+        assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
+
+        /* Output mode configuration*/
+        GPIOx->OTYPER  &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;
+        GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
+      }
+
+      /* Pull-up Pull down resistor configuration*/
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
+      GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
+    }
+  }
+}
+
+/**
+  * @brief  Fills each GPIO_InitStruct member with its default value.
+  * @param  GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
+{
+  /* Reset GPIO init structure parameters values */
+  GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
+  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
+  GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
+}
+
+/**
+  * @brief  Locks GPIO Pins configuration registers.
+  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+  * @note   The configuration of the locked GPIO pins can no longer be modified
+  *         until the next reset.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. 
+  * @param  GPIO_Pin: specifies the port bit to be locked.
+  *          This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  __IO uint32_t tmp = 0x00010000;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  tmp |= GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKK bit */
+  GPIOx->LCKR =  GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LCKR = tmp;
+  /* Read LCKK bit*/
+  tmp = GPIOx->LCKR;
+  /* Read LCKK bit*/
+  tmp = GPIOx->LCKR;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Group2 GPIO Read and Write
+ *  @brief   GPIO Read and Write
+ *
+@verbatim   
+ ===============================================================================
+                         ##### GPIO Read and Write #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads the specified input port pin.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. 
+  * @param  GPIO_Pin: specifies the port bit to read.
+  *         This parameter can be GPIO_Pin_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Reads the specified GPIO input data port.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. 
+  * @retval GPIO input data port value.
+  */
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  return ((uint16_t)GPIOx->IDR);
+}
+
+/**
+  * @brief  Reads the specified output data port bit.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. 
+  * @param  GPIO_Pin: specifies the port bit to read.
+  *          This parameter can be GPIO_Pin_x where x can be (0..15).
+  * @retval The output port pin value.
+  */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+  if (((GPIOx->ODR) & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Reads the specified GPIO output data port.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. 
+  * @retval GPIO output data port value.
+  */
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  return ((uint16_t)GPIOx->ODR);
+}
+
+/**
+  * @brief  Sets the selected data port bits.
+  * @note   This functions uses GPIOx_BSRR register to allow atomic read/modify 
+  *         accesses. In this way, there is no risk of an IRQ occurring between
+  *         the read and the modify access.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. 
+  * @param  GPIO_Pin: specifies the port bits to be written.
+  *          This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  GPIOx->BSRR = GPIO_Pin;
+}
+
+/**
+  * @brief  Clears the selected data port bits.
+  * @note   This functions uses GPIOx_BSRR register to allow atomic read/modify 
+  *         accesses. In this way, there is no risk of an IRQ occurring between
+  *         the read and the modify access.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. 
+  * @param  GPIO_Pin: specifies the port bits to be written.
+  *          This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
+}
+
+/**
+  * @brief  Sets or clears the selected data port bit.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. 
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *          This parameter can be one of GPIO_Pin_x where x can be (0..15).
+  * @param  BitVal: specifies the value to be written to the selected bit.
+  *          This parameter can be one of the BitAction enum values:
+  *            @arg Bit_RESET: to clear the port pin
+  *            @arg Bit_SET: to set the port pin
+  * @retval None
+  */
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_BIT_ACTION(BitVal));
+
+  if (BitVal != Bit_RESET)
+  {
+    GPIOx->BSRR = GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
+  }
+}
+
+/**
+  * @brief  Writes data to the specified GPIO data port.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. 
+  * @param  PortVal: specifies the value to be written to the port output data register.
+  * @retval None
+  */
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  GPIOx->ODR = PortVal;
+}
+
+/**
+  * @brief  Toggles the specified GPIO pins..
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. 
+  * @param  GPIO_Pin: Specifies the pins to be toggled.
+  * @retval None
+  */
+void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  GPIOx->ODR ^= GPIO_Pin;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function
+ *  @brief   GPIO Alternate functions configuration function
+ *
+@verbatim   
+ ===============================================================================
+           ##### GPIO Alternate functions configuration function #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Changes the mapping of the specified pin.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. 
+  * @param  GPIO_PinSource: specifies the pin for the Alternate function.
+  *         This parameter can be GPIO_PinSourcex where x can be (0..15).
+  * @param  GPIO_AFSelection: selects the pin to used as Alternate function.
+  *          This parameter can be one of the following values:
+  *            @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset) 
+  *            @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset) 
+  *            @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset) 
+  *            @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset) 
+  *            @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
+  *            @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1
+  *            @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1
+  *            @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2
+  *            @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2
+  *            @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2
+  *            @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3
+  *            @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3
+  *            @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3
+  *            @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3
+  *            @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4
+  *            @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4
+  *            @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4
+  *            @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5
+  *            @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
+  *            @arg GPIO_AF_SPI4: Connect SPI4 pins to AF5 
+  *            @arg GPIO_AF_SPI5: Connect SPI5 pins to AF5 
+  *            @arg GPIO_AF_SPI6: Connect SPI6 pins to AF5
+  *            @arg GPIO_AF_SAI1: Connect SAI1 pins to AF6 for STM32F42xxx/43xxx devices.       
+  *            @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
+  *            @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7
+  *            @arg GPIO_AF_USART1: Connect USART1 pins to AF7
+  *            @arg GPIO_AF_USART2: Connect USART2 pins to AF7
+  *            @arg GPIO_AF_USART3: Connect USART3 pins to AF7
+  *            @arg GPIO_AF_UART4: Connect UART4 pins to AF8
+  *            @arg GPIO_AF_UART5: Connect UART5 pins to AF8
+  *            @arg GPIO_AF_USART6: Connect USART6 pins to AF8
+  *            @arg GPIO_AF_UART7: Connect UART7 pins to AF8
+  *            @arg GPIO_AF_UART8: Connect UART8 pins to AF8
+  *            @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9
+  *            @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9
+  *            @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9
+  *            @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9
+  *            @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9
+  *            @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10
+  *            @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10
+  *            @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11
+  *            @arg GPIO_AF_FSMC: Connect FSMC pins to AF12 
+  *            @arg GPIO_AF_FMC: Connect FMC pins to AF12 for STM32F42xxx/43xxx devices.   
+  *            @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12
+  *            @arg GPIO_AF_SDIO: Connect SDIO pins to AF12
+  *            @arg GPIO_AF_DCMI: Connect DCMI pins to AF13
+  *            @arg GPIO_AF_LTDC: Connect LTDC pins to AF14 for STM32F429xx/439xx devices. 
+  *            @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15
+  * @retval None
+  */
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
+{
+  uint32_t temp = 0x00;
+  uint32_t temp_2 = 0x00;
+  
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+  assert_param(IS_GPIO_AF(GPIO_AF));
+  
+  temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
+  GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
+  temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
+  GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+

底盘/底盘-old/底盘/Library/stm32f4xx_gpio.h

@@ -0,0 +1,584 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_gpio.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the GPIO firmware
+  *          library.  
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_GPIO_H
+#define __STM32F4xx_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+                                    ((PERIPH) == GPIOB) || \
+                                    ((PERIPH) == GPIOC) || \
+                                    ((PERIPH) == GPIOD) || \
+                                    ((PERIPH) == GPIOE) || \
+                                    ((PERIPH) == GPIOF) || \
+                                    ((PERIPH) == GPIOG) || \
+                                    ((PERIPH) == GPIOH) || \
+                                    ((PERIPH) == GPIOI) || \
+                                    ((PERIPH) == GPIOJ) || \
+                                    ((PERIPH) == GPIOK))
+
+/** 
+  * @brief  GPIO Configuration Mode enumeration 
+  */   
+typedef enum
+{ 
+  GPIO_Mode_IN   = 0x00, /*!< GPIO Input Mode */
+  GPIO_Mode_OUT  = 0x01, /*!< GPIO Output Mode */
+  GPIO_Mode_AF   = 0x02, /*!< GPIO Alternate function Mode */
+  GPIO_Mode_AN   = 0x03  /*!< GPIO Analog Mode */
+}GPIOMode_TypeDef;
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)  || ((MODE) == GPIO_Mode_OUT) || \
+                            ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
+
+/** 
+  * @brief  GPIO Output type enumeration 
+  */  
+typedef enum
+{ 
+  GPIO_OType_PP = 0x00,
+  GPIO_OType_OD = 0x01
+}GPIOOType_TypeDef;
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
+
+
+/** 
+  * @brief  GPIO Output Maximum frequency enumeration 
+  */  
+typedef enum
+{ 
+  GPIO_Low_Speed     = 0x00, /*!< Low speed    */
+  GPIO_Medium_Speed  = 0x01, /*!< Medium speed */
+  GPIO_Fast_Speed    = 0x02, /*!< Fast speed   */
+  GPIO_High_Speed    = 0x03  /*!< High speed   */
+}GPIOSpeed_TypeDef;
+
+/* Add legacy definition */
+#define  GPIO_Speed_2MHz    GPIO_Low_Speed    
+#define  GPIO_Speed_25MHz   GPIO_Medium_Speed 
+#define  GPIO_Speed_50MHz   GPIO_Fast_Speed 
+#define  GPIO_Speed_100MHz  GPIO_High_Speed  
+  
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) || \
+                              ((SPEED) == GPIO_Fast_Speed)||  ((SPEED) == GPIO_High_Speed)) 
+
+/** 
+  * @brief  GPIO Configuration PullUp PullDown enumeration 
+  */ 
+typedef enum
+{ 
+  GPIO_PuPd_NOPULL = 0x00,
+  GPIO_PuPd_UP     = 0x01,
+  GPIO_PuPd_DOWN   = 0x02
+}GPIOPuPd_TypeDef;
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
+                            ((PUPD) == GPIO_PuPd_DOWN))
+
+/** 
+  * @brief  GPIO Bit SET and Bit RESET enumeration 
+  */ 
+typedef enum
+{ 
+  Bit_RESET = 0,
+  Bit_SET
+}BitAction;
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+
+
+/** 
+  * @brief   GPIO Init structure definition  
+  */ 
+typedef struct
+{
+  uint32_t GPIO_Pin;              /*!< Specifies the GPIO pins to be configured.
+                                       This parameter can be any value of @ref GPIO_pins_define */
+
+  GPIOMode_TypeDef GPIO_Mode;     /*!< Specifies the operating mode for the selected pins.
+                                       This parameter can be a value of @ref GPIOMode_TypeDef */
+
+  GPIOSpeed_TypeDef GPIO_Speed;   /*!< Specifies the speed for the selected pins.
+                                       This parameter can be a value of @ref GPIOSpeed_TypeDef */
+
+  GPIOOType_TypeDef GPIO_OType;   /*!< Specifies the operating output type for the selected pins.
+                                       This parameter can be a value of @ref GPIOOType_TypeDef */
+
+  GPIOPuPd_TypeDef GPIO_PuPd;     /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+                                       This parameter can be a value of @ref GPIOPuPd_TypeDef */
+}GPIO_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup GPIO_pins_define 
+  * @{
+  */ 
+#define GPIO_Pin_0                 ((uint16_t)0x0001)  /* Pin 0 selected */
+#define GPIO_Pin_1                 ((uint16_t)0x0002)  /* Pin 1 selected */
+#define GPIO_Pin_2                 ((uint16_t)0x0004)  /* Pin 2 selected */
+#define GPIO_Pin_3                 ((uint16_t)0x0008)  /* Pin 3 selected */
+#define GPIO_Pin_4                 ((uint16_t)0x0010)  /* Pin 4 selected */
+#define GPIO_Pin_5                 ((uint16_t)0x0020)  /* Pin 5 selected */
+#define GPIO_Pin_6                 ((uint16_t)0x0040)  /* Pin 6 selected */
+#define GPIO_Pin_7                 ((uint16_t)0x0080)  /* Pin 7 selected */
+#define GPIO_Pin_8                 ((uint16_t)0x0100)  /* Pin 8 selected */
+#define GPIO_Pin_9                 ((uint16_t)0x0200)  /* Pin 9 selected */
+#define GPIO_Pin_10                ((uint16_t)0x0400)  /* Pin 10 selected */
+#define GPIO_Pin_11                ((uint16_t)0x0800)  /* Pin 11 selected */
+#define GPIO_Pin_12                ((uint16_t)0x1000)  /* Pin 12 selected */
+#define GPIO_Pin_13                ((uint16_t)0x2000)  /* Pin 13 selected */
+#define GPIO_Pin_14                ((uint16_t)0x4000)  /* Pin 14 selected */
+#define GPIO_Pin_15                ((uint16_t)0x8000)  /* Pin 15 selected */
+#define GPIO_Pin_All               ((uint16_t)0xFFFF)  /* All pins selected */
+
+#define GPIO_PIN_MASK              ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
+#define IS_GPIO_PIN(PIN)           (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
+                              ((PIN) == GPIO_Pin_1) || \
+                              ((PIN) == GPIO_Pin_2) || \
+                              ((PIN) == GPIO_Pin_3) || \
+                              ((PIN) == GPIO_Pin_4) || \
+                              ((PIN) == GPIO_Pin_5) || \
+                              ((PIN) == GPIO_Pin_6) || \
+                              ((PIN) == GPIO_Pin_7) || \
+                              ((PIN) == GPIO_Pin_8) || \
+                              ((PIN) == GPIO_Pin_9) || \
+                              ((PIN) == GPIO_Pin_10) || \
+                              ((PIN) == GPIO_Pin_11) || \
+                              ((PIN) == GPIO_Pin_12) || \
+                              ((PIN) == GPIO_Pin_13) || \
+                              ((PIN) == GPIO_Pin_14) || \
+                              ((PIN) == GPIO_Pin_15))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup GPIO_Pin_sources 
+  * @{
+  */ 
+#define GPIO_PinSource0            ((uint8_t)0x00)
+#define GPIO_PinSource1            ((uint8_t)0x01)
+#define GPIO_PinSource2            ((uint8_t)0x02)
+#define GPIO_PinSource3            ((uint8_t)0x03)
+#define GPIO_PinSource4            ((uint8_t)0x04)
+#define GPIO_PinSource5            ((uint8_t)0x05)
+#define GPIO_PinSource6            ((uint8_t)0x06)
+#define GPIO_PinSource7            ((uint8_t)0x07)
+#define GPIO_PinSource8            ((uint8_t)0x08)
+#define GPIO_PinSource9            ((uint8_t)0x09)
+#define GPIO_PinSource10           ((uint8_t)0x0A)
+#define GPIO_PinSource11           ((uint8_t)0x0B)
+#define GPIO_PinSource12           ((uint8_t)0x0C)
+#define GPIO_PinSource13           ((uint8_t)0x0D)
+#define GPIO_PinSource14           ((uint8_t)0x0E)
+#define GPIO_PinSource15           ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
+                                       ((PINSOURCE) == GPIO_PinSource1) || \
+                                       ((PINSOURCE) == GPIO_PinSource2) || \
+                                       ((PINSOURCE) == GPIO_PinSource3) || \
+                                       ((PINSOURCE) == GPIO_PinSource4) || \
+                                       ((PINSOURCE) == GPIO_PinSource5) || \
+                                       ((PINSOURCE) == GPIO_PinSource6) || \
+                                       ((PINSOURCE) == GPIO_PinSource7) || \
+                                       ((PINSOURCE) == GPIO_PinSource8) || \
+                                       ((PINSOURCE) == GPIO_PinSource9) || \
+                                       ((PINSOURCE) == GPIO_PinSource10) || \
+                                       ((PINSOURCE) == GPIO_PinSource11) || \
+                                       ((PINSOURCE) == GPIO_PinSource12) || \
+                                       ((PINSOURCE) == GPIO_PinSource13) || \
+                                       ((PINSOURCE) == GPIO_PinSource14) || \
+                                       ((PINSOURCE) == GPIO_PinSource15))
+/**
+  * @}
+  */ 
+
+/** @defgroup GPIO_Alternat_function_selection_define 
+  * @{
+  */ 
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping */
+#if defined(STM32F446xx)
+#define GPIO_AF0_TIM2         ((uint8_t)0x00)  /* TIM2 Alternate Function mapping */
+#endif /* STM32F446xx */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+#define GPIO_AF_LPTIM         ((uint8_t)0x01)  /* LPTIM Alternate Function mapping */
+#endif /* STM32F410xx || STM32F413_423xx */
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping */
+#define GPIO_AF_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping */
+#define GPIO_AF_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+#if defined(STM32F446xx)
+#define GPIO_AF3_CEC          ((uint8_t)0x03)  /* CEC Alternate Function mapping */
+#endif /* STM32F446xx */
+#if defined(STM32F413_423xx)
+#define GPIO_AF3_DFSDM2       ((uint8_t)0x03)  /* DFSDM2 Alternate Function mapping */
+#endif /* STM32F413_423xx */
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+#if defined(STM32F446xx)
+#define GPIO_AF4_CEC          ((uint8_t)0x04)  /* CEC Alternate Function mapping */
+#endif /* STM32F446xx */
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+#define GPIO_AF_FMPI2C        ((uint8_t)0x04)  /* FMPI2C Alternate Function mapping */
+#endif /* STM32F410xx || STM32F446xx */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3         ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping (Only for STM32F411xE and STM32F413_423xx Devices) */
+#define GPIO_AF_SPI4          ((uint8_t)0x05)  /* SPI4/I2S4 Alternate Function mapping */
+#define GPIO_AF_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping      */
+#define GPIO_AF_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping      */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_SPI1         ((uint8_t)0x06)  /* SPI1 Alternate Function mapping (Only for STM32F410xx Devices) */
+#define GPIO_AF6_SPI2         ((uint8_t)0x06)  /* SPI2 Alternate Function mapping (Only for STM32F410xx/STM32F411xE Devices) */
+#define GPIO_AF6_SPI4         ((uint8_t)0x06)  /* SPI4 Alternate Function mapping (Only for STM32F411xE Devices) */
+#define GPIO_AF6_SPI5         ((uint8_t)0x06)  /* SPI5 Alternate Function mapping (Only for STM32F410xx/STM32F411xE Devices) */
+#define GPIO_AF_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping      */
+#define GPIO_AF_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping (only for STM32F412xG and STM32F413_423xx Devices) */
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+#define GPIO_AF6_DFSDM1       ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping */
+#endif /* STM32F412xG || STM32F413_423xx */
+#if defined(STM32F413_423xx)
+#define GPIO_AF6_DFSDM2       ((uint8_t)0x06)  /* DFSDM2 Alternate Function mapping */
+#endif /* STM32F413_423xx */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF_USART1         ((uint8_t)0x07)  /* USART1 Alternate Function mapping  */
+#define GPIO_AF_USART2         ((uint8_t)0x07)  /* USART2 Alternate Function mapping  */
+#define GPIO_AF_USART3         ((uint8_t)0x07)  /* USART3 Alternate Function mapping  */
+#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3/I2S3ext Alternate Function mapping */
+#if defined(STM32F413_423xx)
+#define GPIO_AF7_DFSDM2        ((uint8_t)0x07)  /* DFSDM2 Alternate Function mapping     */
+#define GPIO_AF7_SAI1          ((uint8_t)0x07)  /* SAI1 Alternate Function mapping       */
+#endif /* STM32F413_423xx */
+
+/** 
+  * @brief   AF 7 selection Legacy 
+  */ 
+#define GPIO_AF_I2S3ext   GPIO_AF7_SPI3
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+#define GPIO_AF_UART7         ((uint8_t)0x08)  /* UART7 Alternate Function mapping  */
+#define GPIO_AF_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+#define GPIO_AF8_USART3        ((uint8_t)0x08)  /* USART3 Alternate Function mapping */
+#define GPIO_AF8_DFSDM1        ((uint8_t)0x08)  /* DFSDM Alternate Function mapping  */
+#define GPIO_AF8_CAN1          ((uint8_t)0x08)  /* CAN1 Alternate Function mapping   */
+#endif /* STM32F412xG || STM32F413_423xx */
+#if defined(STM32F446xx)
+#define GPIO_AF8_SAI2          ((uint8_t)0x08)  /* SAI2 Alternate Function mapping */
+#define GPIO_AF_SPDIF         ((uint8_t)0x08)   /* SPDIF Alternate Function mapping */
+#endif /* STM32F446xx */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
+#define GPIO_AF_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */
+#define GPIO_AF_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */
+#define GPIO_AF_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */
+#define GPIO_AF_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_I2C2         ((uint8_t)0x09)  /* I2C2 Alternate Function mapping (Only for STM32F401xx/STM32F410xx/STM32F411xE/STM32F412xG/STM32F413_423xx Devices) */
+#define GPIO_AF9_I2C3         ((uint8_t)0x09)  /* I2C3 Alternate Function mapping (Only for STM32F401xx/STM32F411xE/STM32F412xG and STM32F413_423xx Devices) */
+#if defined(STM32F446xx)
+#define GPIO_AF9_SAI2         ((uint8_t)0x09)  /* SAI2 Alternate Function mapping */
+#endif /* STM32F446xx */
+#define GPIO_AF9_LTDC         ((uint8_t)0x09)  /* LTDC Alternate Function mapping */
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+#define GPIO_AF9_QUADSPI      ((uint8_t)0x09)  /* QuadSPI Alternate Function mapping */
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+#define GPIO_AF9_FMPI2C       ((uint8_t)0x09)  /* FMPI2C Alternate Function mapping (Only for STM32F410xx Devices) */
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF_OTG_FS         ((uint8_t)0xA)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF_OTG_HS         ((uint8_t)0xA)  /* OTG_HS Alternate Function mapping */
+#if defined(STM32F446xx)
+#define GPIO_AF10_SAI2         ((uint8_t)0x0A)  /* SAI2 Alternate Function mapping */
+#endif /* STM32F446xx */
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* QuadSPI Alternate Function mapping */
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+#define GPIO_AF10_FMC           ((uint8_t)0xA)  /* FMC Alternate Function mapping    */
+#define GPIO_AF10_DFSDM1         ((uint8_t)0xA) /* DFSDM Alternate Function mapping  */
+#endif /* STM32F412xG || STM32F413_423xx */
+#if defined(STM32F413_423xx)
+#define GPIO_AF10_DFSDM2        ((uint8_t)0x0A)  /* DFSDM2 Alternate Function mapping */
+#define GPIO_AF10_SAI1          ((uint8_t)0x0A)  /* SAI1 Alternate Function mapping   */
+#endif /* STM32F413_423xx */
+/** 
+  * @brief   AF 11 selection  
+  */ 
+#define GPIO_AF_ETH             ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
+#if defined(STM32F413_423xx)
+#define GPIO_AF11_UART4         ((uint8_t)0x0B)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF11_UART5         ((uint8_t)0x0B)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF11_UART9         ((uint8_t)0x0B)  /* UART9 Alternate Function mapping  */
+#define GPIO_AF11_UART10        ((uint8_t)0x0B)  /* UART10 Alternate Function mapping */
+#define GPIO_AF11_CAN3          ((uint8_t)0x0B)  /* CAN3 Alternate Function mapping   */
+#endif /* STM32F413_423xx */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+#define GPIO_AF_FSMC             ((uint8_t)0xC)  /* FSMC Alternate Function mapping                     */
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+#define GPIO_AF_FMC              ((uint8_t)0xC)  /* FMC Alternate Function mapping                      */
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
+
+#define GPIO_AF_OTG_HS_FS        ((uint8_t)0xC)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF_SDIO             ((uint8_t)0xC)  /* SDIO Alternate Function mapping                     */
+
+/** 
+  * @brief   AF 13 selection  
+  */ 
+#define GPIO_AF_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
+#if defined(STM32F469_479xx)
+#define GPIO_AF_DSI           ((uint8_t)0x0D)  /* DSI Alternate Function mapping */
+#endif /* STM32F469_479xx */
+/** 
+  * @brief   AF 14 selection  
+  */
+#define GPIO_AF_LTDC          ((uint8_t)0x0E)  /* LCD-TFT Alternate Function mapping */
+#if defined(STM32F413_423xx)
+#define GPIO_AF14_RNG         ((uint8_t)0x0E)  /* RNG Alternate Function mapping  */
+#endif /* STM32F413_423xx */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#if defined(STM32F40_41xxx)
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_RTC_50Hz)  || ((AF) == GPIO_AF_TIM14)     || \
+                          ((AF) == GPIO_AF_MCO)       || ((AF) == GPIO_AF_TAMPER)    || \
+                          ((AF) == GPIO_AF_SWJ)       || ((AF) == GPIO_AF_TRACE)     || \
+                          ((AF) == GPIO_AF_TIM1)      || ((AF) == GPIO_AF_TIM2)      || \
+                          ((AF) == GPIO_AF_TIM3)      || ((AF) == GPIO_AF_TIM4)      || \
+                          ((AF) == GPIO_AF_TIM5)      || ((AF) == GPIO_AF_TIM8)      || \
+                          ((AF) == GPIO_AF_I2C1)      || ((AF) == GPIO_AF_I2C2)      || \
+                          ((AF) == GPIO_AF_I2C3)      || ((AF) == GPIO_AF_SPI1)      || \
+                          ((AF) == GPIO_AF_SPI2)      || ((AF) == GPIO_AF_TIM13)     || \
+                          ((AF) == GPIO_AF_SPI3)      || ((AF) == GPIO_AF_TIM14)     || \
+                          ((AF) == GPIO_AF_USART1)    || ((AF) == GPIO_AF_USART2)    || \
+                          ((AF) == GPIO_AF_USART3)    || ((AF) == GPIO_AF_UART4)     || \
+                          ((AF) == GPIO_AF_UART5)     || ((AF) == GPIO_AF_USART6)    || \
+                          ((AF) == GPIO_AF_CAN1)      || ((AF) == GPIO_AF_CAN2)      || \
+                          ((AF) == GPIO_AF_OTG_FS)    || ((AF) == GPIO_AF_OTG_HS)    || \
+                          ((AF) == GPIO_AF_ETH)       || ((AF) == GPIO_AF_OTG_HS_FS) || \
+                          ((AF) == GPIO_AF_SDIO)      || ((AF) == GPIO_AF_DCMI)      || \
+                          ((AF) == GPIO_AF_EVENTOUT)  || ((AF) == GPIO_AF_FSMC))
+#endif /* STM32F40_41xxx */
+
+#if defined(STM32F401xx)
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_RTC_50Hz)  || ((AF) == GPIO_AF_TIM14)     || \
+                          ((AF) == GPIO_AF_MCO)       || ((AF) == GPIO_AF_TAMPER)    || \
+                          ((AF) == GPIO_AF_SWJ)       || ((AF) == GPIO_AF_TRACE)     || \
+                          ((AF) == GPIO_AF_TIM1)      || ((AF) == GPIO_AF_TIM2)      || \
+                          ((AF) == GPIO_AF_TIM3)      || ((AF) == GPIO_AF_TIM4)      || \
+                          ((AF) == GPIO_AF_TIM5)      || ((AF) == GPIO_AF_TIM8)      || \
+                          ((AF) == GPIO_AF_I2C1)      || ((AF) == GPIO_AF_I2C2)      || \
+                          ((AF) == GPIO_AF_I2C3)      || ((AF) == GPIO_AF_SPI1)      || \
+                          ((AF) == GPIO_AF_SPI2)      || ((AF) == GPIO_AF_TIM13)     || \
+                          ((AF) == GPIO_AF_SPI3)      || ((AF) == GPIO_AF_TIM14)     || \
+                          ((AF) == GPIO_AF_USART1)    || ((AF) == GPIO_AF_USART2)    || \
+                          ((AF) == GPIO_AF_SDIO)      || ((AF) == GPIO_AF_USART6)    || \
+                          ((AF) == GPIO_AF_OTG_FS)    || ((AF) == GPIO_AF_OTG_HS)    || \
+                          ((AF) == GPIO_AF_EVENTOUT)  || ((AF) == GPIO_AF_SPI4))
+#endif /* STM32F401xx */
+
+#if defined(STM32F411xE)
+#define IS_GPIO_AF(AF)   (((AF) < 16) && ((AF) != 11) && ((AF) != 13) && ((AF) != 14))
+#endif /* STM32F411xE */
+
+#if defined(STM32F410xx)
+#define IS_GPIO_AF(AF)   (((AF) < 10) || ((AF) == 15))
+#endif /* STM32F410xx */
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx)
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_RTC_50Hz)  || ((AF) == GPIO_AF_TIM14)     || \
+                          ((AF) == GPIO_AF_MCO)       || ((AF) == GPIO_AF_TAMPER)    || \
+                          ((AF) == GPIO_AF_SWJ)       || ((AF) == GPIO_AF_TRACE)     || \
+                          ((AF) == GPIO_AF_TIM1)      || ((AF) == GPIO_AF_TIM2)      || \
+                          ((AF) == GPIO_AF_TIM3)      || ((AF) == GPIO_AF_TIM4)      || \
+                          ((AF) == GPIO_AF_TIM5)      || ((AF) == GPIO_AF_TIM8)      || \
+                          ((AF) == GPIO_AF_I2C1)      || ((AF) == GPIO_AF_I2C2)      || \
+                          ((AF) == GPIO_AF_I2C3)      || ((AF) == GPIO_AF_SPI1)      || \
+                          ((AF) == GPIO_AF_SPI2)      || ((AF) == GPIO_AF_TIM13)     || \
+                          ((AF) == GPIO_AF_SPI3)      || ((AF) == GPIO_AF_TIM14)     || \
+                          ((AF) == GPIO_AF_USART1)    || ((AF) == GPIO_AF_USART2)    || \
+                          ((AF) == GPIO_AF_USART3)    || ((AF) == GPIO_AF_UART4)     || \
+                          ((AF) == GPIO_AF_UART5)     || ((AF) == GPIO_AF_USART6)    || \
+                          ((AF) == GPIO_AF_CAN1)      || ((AF) == GPIO_AF_CAN2)      || \
+                          ((AF) == GPIO_AF_OTG_FS)    || ((AF) == GPIO_AF_OTG_HS)    || \
+                          ((AF) == GPIO_AF_ETH)       || ((AF) == GPIO_AF_OTG_HS_FS) || \
+                          ((AF) == GPIO_AF_SDIO)      || ((AF) == GPIO_AF_DCMI)      || \
+                          ((AF) == GPIO_AF_EVENTOUT)  || ((AF) == GPIO_AF_SPI4)      || \
+                          ((AF) == GPIO_AF_SPI5)      || ((AF) == GPIO_AF_SPI6)      || \
+                          ((AF) == GPIO_AF_UART7)     || ((AF) == GPIO_AF_UART8)     || \
+                          ((AF) == GPIO_AF_FMC)       ||  ((AF) == GPIO_AF_SAI1)     || \
+                          ((AF) == GPIO_AF_LTDC))
+#endif /* STM32F427_437xx ||  STM32F429_439xx */
+
+#if defined(STM32F412xG)
+#define IS_GPIO_AF(AF)   (((AF) < 16) && ((AF) != 11) && ((AF) != 14))
+#endif /* STM32F412xG */
+
+#if defined(STM32F413_423xx)
+#define IS_GPIO_AF(AF)   (((AF) < 16) && ((AF) != 13))
+#endif /* STM32F413_423xx */
+
+#if defined(STM32F446xx)
+#define IS_GPIO_AF(AF)   (((AF) < 16) && ((AF) != 11) && ((AF) != 14))
+#endif /* STM32F446xx */
+
+#if defined(STM32F469_479xx)
+#define IS_GPIO_AF(AF)   ((AF) < 16)
+#endif /* STM32F469_479xx */
+
+/**
+  * @}
+  */ 
+
+/** @defgroup GPIO_Legacy 
+  * @{
+  */
+    
+#define GPIO_Mode_AIN           GPIO_Mode_AN
+
+#define GPIO_AF_OTG1_FS         GPIO_AF_OTG_FS
+#define GPIO_AF_OTG2_HS         GPIO_AF_OTG_HS
+#define GPIO_AF_OTG2_FS         GPIO_AF_OTG_HS_FS
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/*  Function used to set the GPIO configuration to the default reset state ****/
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+
+/* Initialization and Configuration functions *********************************/
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
+/* GPIO Read and Write functions **********************************************/
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
+/* GPIO Alternate functions configuration function ****************************/
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_GPIO_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+

底盘/底盘-old/底盘/Library/stm32f4xx_hash.c

@@ -0,0 +1,718 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hash.c
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the HASH / HMAC Processor (HASH) peripheral:           
+  *           - Initialization and Configuration functions
+  *           - Message Digest generation functions
+  *           - context swapping functions   
+  *           - DMA interface function       
+  *           - Interrupts and flags management       
+  *         
+@verbatim
+ ===================================================================      
+                 ##### How to use this driver #####
+ ===================================================================
+            
+ *** HASH operation : *** 
+ ========================                 
+ [..]
+   (#) Enable the HASH controller clock using 
+       RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function.
+             
+   (#) Initialize the HASH using HASH_Init() function. 
+                 
+   (#) Reset the HASH processor core, so that the HASH will be ready 
+       to compute he message digest of a new message by using HASH_Reset() function.
+  
+   (#) Enable the HASH controller using the HASH_Cmd() function. 
+                  
+   (#) if using DMA for Data input transfer, Activate the DMA Request 
+       using HASH_DMACmd() function 
+                      
+   (#) if DMA is not used for data transfer, use HASH_DataIn() function 
+       to enter data to IN FIFO.
+               
+            
+   (#) Configure the Number of valid bits in last word of the message 
+       using HASH_SetLastWordValidBitsNbr() function.
+               
+   (#) if the message length is not an exact multiple of 512 bits, 
+       then the function HASH_StartDigest() must be called to launch the computation
+       of the final digest.     
+               
+   (#) Once computed, the digest can be read using HASH_GetDigest() function.         
+                     
+   (#) To control HASH events you can use one of the following wo methods:
+       (++) Check on HASH flags using the HASH_GetFlagStatus() function.  
+       (++) Use HASH interrupts through the function HASH_ITConfig() at 
+            initialization phase and HASH_GetITStatus() function into 
+            interrupt routines in hashing phase.
+            After checking on a flag you should clear it using HASH_ClearFlag()
+            function. And after checking on an interrupt event you should 
+            clear it using HASH_ClearITPendingBit() function.     
+                       
+   (#) Save and restore hash processor context using 
+       HASH_SaveContext() and HASH_RestoreContext() functions.     
+                
+  
+              
+ *** HMAC operation : *** 
+ ========================
+ [..] The HMAC algorithm is used for message authentication, by 
+      irreversibly binding the message being processed to a key chosen 
+      by the user. 
+      For HMAC specifications, refer to "HMAC: keyed-hashing for message 
+      authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997"
+            
+ [..] Basically, the HMAC algorithm consists of two nested hash operations:
+      HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)]
+      where:
+      (+) "pad" is a sequence of zeroes needed to extend the key to the 
+          length of the underlying hash function data block (that is 
+          512 bits for both the SHA-1 and MD5 hash algorithms)
+      (+) "|"   represents the concatenation operator 
+            
+           
+ [..]To compute the HMAC, four different phases are required:                  
+   (#) Initialize the HASH using HASH_Init() function to do HMAC 
+       operation. 
+                  
+   (#) The key (to be used for the inner hash function) is then given to the core. 
+       This operation follows the same mechanism as the one used to send the 
+       message in the hash operation (that is, by HASH_DataIn() function and, 
+       finally, HASH_StartDigest() function.
+            
+   (#) Once the last word has been entered and computation has started, 
+       the hash processor elaborates the key. It is then ready to accept the message
+       text using the same mechanism as the one used to send the message in the
+       hash operation.
+         
+   (#) After the first hash round, the hash processor returns "ready" to indicate 
+       that it is ready to receive the key to be used for the outer hash function 
+       (normally, this key is the same as the one used for the inner hash function). 
+       When the last word of the key is entered and computation starts, the HMAC 
+       result is made available using HASH_GetDigest() function.
+
+@endverbatim
+  *         
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hash.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup HASH 
+  * @brief HASH driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/ 
+
+/** @defgroup HASH_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup HASH_Group1 Initialization and Configuration functions
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and Configuration functions #####
+ ===============================================================================  
+ [..] This section provides functions allowing to 
+   (+) Initialize the HASH peripheral
+   (+) Configure the HASH Processor 
+   (+) MD5/SHA1, 
+   (+) HASH/HMAC, 
+   (+) datatype 
+   (+) HMAC Key (if mode = HMAC)
+   (+) Reset the HASH Processor 
+   
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  De-initializes the HASH peripheral registers to their default reset values
+  * @param  None
+  * @retval None
+  */
+void HASH_DeInit(void)
+{
+  /* Enable HASH reset state */
+  RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, ENABLE);
+  /* Release HASH from reset state */
+  RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, DISABLE);
+}
+
+/**
+  * @brief  Initializes the HASH peripheral according to the specified parameters
+  *         in the HASH_InitStruct structure.
+  * @note   the hash processor is reset when calling this function so that the
+  *         HASH will be ready to compute the message digest of a new message.
+  *         There is no need to call HASH_Reset() function.           
+  * @param  HASH_InitStruct: pointer to a HASH_InitTypeDef structure that contains
+  *         the configuration information for the HASH peripheral.
+  * @note   The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only 
+  *          if the algorithm mode is HMAC.       
+  * @retval None
+  */
+void HASH_Init(HASH_InitTypeDef* HASH_InitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_HASH_ALGOSELECTION(HASH_InitStruct->HASH_AlgoSelection));
+  assert_param(IS_HASH_DATATYPE(HASH_InitStruct->HASH_DataType));
+  assert_param(IS_HASH_ALGOMODE(HASH_InitStruct->HASH_AlgoMode));
+  
+  /* Configure the Algorithm used, algorithm mode and the datatype */
+  HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE);
+  HASH->CR |= (HASH_InitStruct->HASH_AlgoSelection | \
+               HASH_InitStruct->HASH_DataType | \
+               HASH_InitStruct->HASH_AlgoMode);
+  
+  /* if algorithm mode is HMAC, set the Key */  
+  if(HASH_InitStruct->HASH_AlgoMode == HASH_AlgoMode_HMAC) 
+  {
+    assert_param(IS_HASH_HMAC_KEYTYPE(HASH_InitStruct->HASH_HMACKeyType));
+    HASH->CR &= ~HASH_CR_LKEY;
+    HASH->CR |= HASH_InitStruct->HASH_HMACKeyType;
+  }
+
+  /* Reset the HASH processor core, so that the HASH will be ready to compute 
+     the message digest of a new message */
+  HASH->CR |= HASH_CR_INIT;  
+}
+
+/**
+  * @brief  Fills each HASH_InitStruct member with its default value.
+  * @param  HASH_InitStruct : pointer to a HASH_InitTypeDef structure which will
+  *          be initialized.  
+  *  @note  The default values set are : Processor mode is HASH, Algorithm selected is SHA1,
+  *          Data type selected is 32b and HMAC Key Type is short key.  
+  * @retval None
+  */
+void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct)
+{
+  /* Initialize the HASH_AlgoSelection member */
+  HASH_InitStruct->HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
+
+  /* Initialize the HASH_AlgoMode member */
+  HASH_InitStruct->HASH_AlgoMode = HASH_AlgoMode_HASH;
+
+  /* Initialize the HASH_DataType member */
+  HASH_InitStruct->HASH_DataType = HASH_DataType_32b;
+
+  /* Initialize the HASH_HMACKeyType member */
+  HASH_InitStruct->HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
+}
+
+/**
+  * @brief  Resets the HASH processor core, so that the HASH will be ready
+  *         to compute the message digest of a new message.
+  * @note   Calling this function will clear the HASH_SR_DCIS (Digest calculation 
+  *         completion interrupt status) bit corresponding to HASH_IT_DCI 
+  *         interrupt and HASH_FLAG_DCIS flag. 
+  * @param  None
+  * @retval None
+  */
+void HASH_Reset(void)
+{
+  /* Reset the HASH processor core */
+  HASH->CR |= HASH_CR_INIT;
+}
+/**
+  * @}
+  */
+ 
+/** @defgroup HASH_Group2 Message Digest generation functions
+ *  @brief    Message Digest generation functions
+ *
+@verbatim    
+ ===============================================================================
+                  ##### Message Digest generation functions #####
+ ===============================================================================  
+ [..] This section provides functions allowing the generation of message digest: 
+   (+) Push data in the IN FIFO : using HASH_DataIn()
+   (+) Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr()  
+   (+) set the last word valid bits number using HASH_SetLastWordValidBitsNbr() 
+   (+) start digest calculation : using HASH_StartDigest()
+   (+) Get the Digest message : using HASH_GetDigest()
+ 
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Configure the Number of valid bits in last word of the message
+  * @param  ValidNumber: Number of valid bits in last word of the message.
+  *           This parameter must be a number between 0 and 0x1F.
+  *             - 0x00: All 32 bits of the last data written are valid
+  *             - 0x01: Only bit [0] of the last data written is valid
+  *             - 0x02: Only bits[1:0] of the last data written are valid
+  *             - 0x03: Only bits[2:0] of the last data written are valid
+  *             - ...
+  *             - 0x1F: Only bits[30:0] of the last data written are valid    
+  * @note   The Number of valid bits must be set before to start the message 
+  *         digest competition (in Hash and HMAC) and key treatment(in HMAC).    
+  * @retval None
+  */
+void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber)
+{
+  /* Check the parameters */
+  assert_param(IS_HASH_VALIDBITSNUMBER(ValidNumber));
+  
+  /* Configure the Number of valid bits in last word of the message */
+  HASH->STR &= ~(HASH_STR_NBW);
+  HASH->STR |= ValidNumber;
+}
+
+/**
+  * @brief  Writes data in the Data Input FIFO
+  * @param  Data: new data of the message to be processed.
+  * @retval None
+  */
+void HASH_DataIn(uint32_t Data)
+{
+  /* Write in the DIN register a new data */
+  HASH->DIN = Data;
+}
+
+/**
+  * @brief  Returns the number of words already pushed into the IN FIFO.
+  * @param  None
+  * @retval The value of words already pushed into the IN FIFO.
+  */
+uint8_t HASH_GetInFIFOWordsNbr(void)
+{
+  /* Return the value of NBW bits */
+  return ((HASH->CR & HASH_CR_NBW) >> 8);
+}
+
+/**
+  * @brief  Provides the message digest result.
+  * @note   In MD5 mode, Data[7] to Data[4] filed of HASH_MsgDigest structure is not used
+  *         and is read as zero.
+  *         In SHA-1 mode, Data[7] to Data[5] filed of HASH_MsgDigest structure is not used
+  *         and is read as zero.    
+  *         In SHA-224 mode, Data[7] filed of HASH_MsgDigest structure is not used
+  *         and is read as zero.  
+  * @param  HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will 
+  *         hold the message digest result 
+  * @retval None
+  */
+void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest)
+{
+  /* Get the data field */
+  HASH_MessageDigest->Data[0] = HASH->HR[0];
+  HASH_MessageDigest->Data[1] = HASH->HR[1];
+  HASH_MessageDigest->Data[2] = HASH->HR[2];
+  HASH_MessageDigest->Data[3] = HASH->HR[3];
+  HASH_MessageDigest->Data[4] = HASH->HR[4];
+  HASH_MessageDigest->Data[5] = HASH_DIGEST->HR[5];
+  HASH_MessageDigest->Data[6] = HASH_DIGEST->HR[6];
+  HASH_MessageDigest->Data[7] = HASH_DIGEST->HR[7];
+}
+
+/**
+  * @brief  Starts the message padding and calculation of the final message     
+  * @param  None
+  * @retval None
+  */
+void HASH_StartDigest(void)
+{
+  /* Start the Digest calculation */
+  HASH->STR |= HASH_STR_DCAL;
+}
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Group3 Context swapping functions
+ *  @brief   Context swapping functions
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Context swapping functions #####
+ ===============================================================================  
+ 
+ [..] This section provides functions allowing to save and store HASH Context
+  
+ [..] It is possible to interrupt a HASH/HMAC process to perform another processing 
+      with a higher priority, and to complete the interrupted process later on, when 
+      the higher priority task is complete. To do so, the context of the interrupted 
+      task must be saved from the HASH registers to memory, and then be restored 
+      from memory to the HASH registers.
+  
+   (#) To save the current context, use HASH_SaveContext() function
+   (#) To restore the saved context, use HASH_RestoreContext() function 
+  
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Save the Hash peripheral Context. 
+  * @note   The context can be saved only when no block is currently being 
+  *         processed. So user must wait for DINIS = 1 (the last block has been 
+  *         processed and the input FIFO is empty) or NBW != 0 (the FIFO is not 
+  *         full and no processing is ongoing).   
+  * @param  HASH_ContextSave: pointer to a HASH_Context structure that contains
+  *         the repository for current context.
+  * @retval None
+  */
+void HASH_SaveContext(HASH_Context* HASH_ContextSave)
+{
+  uint8_t i = 0;
+  
+  /* save context registers */
+  HASH_ContextSave->HASH_IMR = HASH->IMR;  
+  HASH_ContextSave->HASH_STR = HASH->STR;      
+  HASH_ContextSave->HASH_CR  = HASH->CR;     
+  for(i=0; i<=53;i++)
+  {
+     HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i];
+  }   
+}
+
+/**
+  * @brief  Restore the Hash peripheral Context.  
+  * @note   After calling this function, user can restart the processing from the
+  *         point where it has been interrupted.  
+  * @param  HASH_ContextRestore: pointer to a HASH_Context structure that contains
+  *         the repository for saved context.
+  * @retval None
+  */
+void HASH_RestoreContext(HASH_Context* HASH_ContextRestore)  
+{
+  uint8_t i = 0;
+  
+  /* restore context registers */
+  HASH->IMR = HASH_ContextRestore->HASH_IMR;   
+  HASH->STR = HASH_ContextRestore->HASH_STR;     
+  HASH->CR = HASH_ContextRestore->HASH_CR;
+  
+  /* Initialize the hash processor */
+  HASH->CR |= HASH_CR_INIT; 
+  
+   /* continue restoring context registers */     
+  for(i=0; i<=53;i++)
+  {
+     HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i];
+  }   
+}
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Group4 HASH's DMA interface Configuration function
+ *  @brief   HASH's DMA interface Configuration function 
+ *
+@verbatim   
+ ===============================================================================
+               ##### HASH's DMA interface Configuration function #####
+ ===============================================================================  
+
+ [..] This section provides functions allowing to configure the DMA interface for 
+      HASH/ HMAC data input transfer.
+   
+ [..] When the DMA mode is enabled (using the HASH_DMACmd() function), data can be 
+      sent to the IN FIFO using the DMA peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables auto-start message padding and
+  *         calculation of the final message digest at the end of DMA transfer.
+  * @param  NewState: new state of the selected HASH DMA transfer request.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void HASH_AutoStartDigest(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the auto start of the final message digest at the end of DMA transfer */
+    HASH->CR &= ~HASH_CR_MDMAT;
+  }
+  else
+  {
+    /* Disable the auto start of the final message digest at the end of DMA transfer */
+    HASH->CR |= HASH_CR_MDMAT;
+  }
+}
+  
+/**
+  * @brief  Enables or disables the HASH DMA interface.
+  * @note   The DMA is disabled by hardware after the end of transfer.
+  * @param  NewState: new state of the selected HASH DMA transfer request.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void HASH_DMACmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the HASH DMA request */
+    HASH->CR |= HASH_CR_DMAE;
+  }
+  else
+  {
+    /* Disable the HASH DMA request */
+    HASH->CR &= ~HASH_CR_DMAE;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Group5 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+               ##### Interrupts and flags management functions #####
+ ===============================================================================  
+
+ [..] This section provides functions allowing to configure the HASH Interrupts and 
+      to get the status and clear flags and Interrupts pending bits.
+  
+ [..] The HASH provides 2 Interrupts sources and 5 Flags:
+  
+ *** Flags : ***
+ =============== 
+ [..]
+   (#) HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO 
+      which means that a  new block (512 bit) can be entered into the input buffer.
+                          
+   (#) HASH_FLAG_DCIS :  set when Digest calculation is complete
+      
+   (#) HASH_FLAG_DMAS :  set when HASH's DMA interface is enabled (DMAE=1) or 
+       a transfer is ongoing. This Flag is cleared only by hardware.
+                           
+   (#) HASH_FLAG_BUSY :  set when The hash core is processing a block of data
+       This Flag is cleared only by hardware. 
+                           
+   (#) HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that 
+       the Data IN FIFO contains at least one word of data. This Flag is cleared 
+       only by hardware.
+     
+ *** Interrupts : ***
+ ====================
+ [..]   
+   (#) HASH_IT_DINI  : if enabled, this interrupt source is pending when 16 
+       locations are free in the Data IN FIFO  which means that a new block (512 bit)
+       can be entered into the input buffer. This interrupt source is cleared using 
+       HASH_ClearITPendingBit(HASH_IT_DINI) function.
+   
+   (#) HASH_IT_DCI   : if enabled, this interrupt source is pending when Digest 
+       calculation is complete. This interrupt source is cleared using 
+       HASH_ClearITPendingBit(HASH_IT_DCI) function.
+
+ *** Managing the HASH controller events : ***
+ =============================================
+ [..] The user should identify which mode will be used in his application to manage 
+      the HASH controller events: Polling mode or Interrupt mode.
+  
+   (#) In the Polling Mode it is advised to use the following functions:
+       (++) HASH_GetFlagStatus() : to check if flags events occur. 
+       (++) HASH_ClearFlag()     : to clear the flags events.
+    
+   (#)  In the Interrupt Mode it is advised to use the following functions:
+       (++) HASH_ITConfig()       : to enable or disable the interrupt source.
+       (++) HASH_GetITStatus()    : to check if Interrupt occurs.
+       (++) HASH_ClearITPendingBit() : to clear the Interrupt pending Bit 
+            (corresponding Flag). 
+
+@endverbatim
+  * @{
+  */ 
+  
+/**
+  * @brief  Enables or disables the specified HASH interrupts.
+  * @param  HASH_IT: specifies the HASH interrupt source to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg HASH_IT_DINI: Data Input interrupt
+  *            @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
+  * @param  NewState: new state of the specified HASH interrupt.
+  *           This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_HASH_IT(HASH_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected HASH interrupt */
+    HASH->IMR |= HASH_IT;
+  }
+  else
+  {
+    /* Disable the selected HASH interrupt */
+    HASH->IMR &= (uint32_t)(~HASH_IT);
+  }
+}
+
+/**
+  * @brief  Checks whether the specified HASH flag is set or not.
+  * @param  HASH_FLAG: specifies the HASH flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg HASH_FLAG_DINIS: Data input interrupt status flag
+  *            @arg HASH_FLAG_DCIS: Digest calculation completion interrupt status flag
+  *            @arg HASH_FLAG_BUSY: Busy flag
+  *            @arg HASH_FLAG_DMAS: DMAS Status flag
+  *            @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag
+  * @retval The new state of HASH_FLAG (SET or RESET)
+  */
+FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tempreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_HASH_GET_FLAG(HASH_FLAG));
+
+  /* check if the FLAG is in CR register */
+  if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint32_t)RESET ) 
+  {
+    tempreg = HASH->CR;
+  }
+  else /* The FLAG is in SR register */
+  {
+    tempreg = HASH->SR;
+  }
+
+  /* Check the status of the specified HASH flag */
+  if ((tempreg & HASH_FLAG) != (uint32_t)RESET)
+  {
+    /* HASH is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* HASH_FLAG is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the HASH_FLAG status */
+  return  bitstatus;
+}
+/**
+  * @brief  Clears the HASH flags.
+  * @param  HASH_FLAG: specifies the flag to clear. 
+  *          This parameter can be any combination of the following values:
+  *            @arg HASH_FLAG_DINIS: Data Input Flag
+  *            @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag                       
+  * @retval None
+  */
+void HASH_ClearFlag(uint32_t HASH_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG));
+  
+  /* Clear the selected HASH flags */
+  HASH->SR = ~(uint32_t)HASH_FLAG;
+}
+/**
+  * @brief  Checks whether the specified HASH interrupt has occurred or not.
+  * @param  HASH_IT: specifies the HASH interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg HASH_IT_DINI: Data Input interrupt
+  *            @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
+  * @retval The new state of HASH_IT (SET or RESET).
+  */
+ITStatus HASH_GetITStatus(uint32_t HASH_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_HASH_GET_IT(HASH_IT));  
+
+
+  /* Check the status of the specified HASH interrupt */
+  tmpreg =  HASH->SR;
+
+  if (((HASH->IMR & tmpreg) & HASH_IT) != RESET)
+  {
+    /* HASH_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* HASH_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the HASH_IT status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the HASH interrupt pending bit(s).
+  * @param  HASH_IT: specifies the HASH interrupt pending bit(s) to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg HASH_IT_DINI: Data Input interrupt
+  *            @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
+  * @retval None
+  */
+void HASH_ClearITPendingBit(uint32_t HASH_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_HASH_IT(HASH_IT));
+
+  /* Clear the selected HASH interrupt pending bit */
+  HASH->SR = (uint32_t)(~HASH_IT);
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+

底盘/底盘-old/底盘/Library/stm32f4xx_hash.h

@@ -0,0 +1,249 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hash.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the HASH 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HASH_H
+#define __STM32F4xx_HASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup HASH
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief   HASH Init structure definition
+  */ 
+typedef struct
+{
+  uint32_t HASH_AlgoSelection; /*!< SHA-1, SHA-224, SHA-256 or MD5. This parameter
+                                    can be a value of @ref HASH_Algo_Selection */
+  uint32_t HASH_AlgoMode;      /*!< HASH or HMAC. This parameter can be a value 
+                                    of @ref HASH_processor_Algorithm_Mode */
+  uint32_t HASH_DataType;      /*!< 32-bit data, 16-bit data, 8-bit data or 
+                                    bit string. This parameter can be a value of
+                                    @ref HASH_Data_Type */
+  uint32_t HASH_HMACKeyType;   /*!< HMAC Short key or HMAC Long Key. This parameter
+                                    can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */
+}HASH_InitTypeDef;
+
+/** 
+  * @brief  HASH message digest result structure definition  
+  */ 
+typedef struct
+{
+  uint32_t Data[8];      /*!< Message digest result : 8x 32bit wors for SHA-256,
+                                                      7x 32bit wors for SHA-224,
+                                                      5x 32bit words for SHA-1 or
+                                                      4x 32bit words for MD5  */
+} HASH_MsgDigest; 
+
+/** 
+  * @brief  HASH context swapping structure definition  
+  */ 
+typedef struct
+{
+  uint32_t HASH_IMR; 
+  uint32_t HASH_STR;      
+  uint32_t HASH_CR;     
+  uint32_t HASH_CSR[54];       
+}HASH_Context;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HASH_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup HASH_Algo_Selection 
+  * @{
+  */ 
+#define HASH_AlgoSelection_SHA1      ((uint32_t)0x0000) /*!< HASH function is SHA1   */
+#define HASH_AlgoSelection_SHA224    HASH_CR_ALGO_1     /*!< HASH function is SHA224 */
+#define HASH_AlgoSelection_SHA256    HASH_CR_ALGO       /*!< HASH function is SHA256 */
+#define HASH_AlgoSelection_MD5       HASH_CR_ALGO_0     /*!< HASH function is MD5    */
+
+#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \
+                                              ((ALGOSELECTION) == HASH_AlgoSelection_SHA224) || \
+                                              ((ALGOSELECTION) == HASH_AlgoSelection_SHA256) || \
+                                              ((ALGOSELECTION) == HASH_AlgoSelection_MD5))
+/**
+  * @}
+  */
+
+/** @defgroup HASH_processor_Algorithm_Mode 
+  * @{
+  */ 
+#define HASH_AlgoMode_HASH         ((uint32_t)0x00000000) /*!< Algorithm is HASH */ 
+#define HASH_AlgoMode_HMAC         HASH_CR_MODE           /*!< Algorithm is HMAC */
+
+#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \
+                                    ((ALGOMODE) == HASH_AlgoMode_HMAC))
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Data_Type  
+  * @{
+  */  
+#define HASH_DataType_32b          ((uint32_t)0x0000) /*!< 32-bit data. No swapping                     */
+#define HASH_DataType_16b          HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped       */
+#define HASH_DataType_8b           HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped            */
+#define HASH_DataType_1b           HASH_CR_DATATYPE   /*!< 1-bit data. In the word all bits are swapped */
+
+#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \
+                                    ((DATATYPE) == HASH_DataType_16b)|| \
+                                    ((DATATYPE) == HASH_DataType_8b) || \
+                                    ((DATATYPE) == HASH_DataType_1b))
+/**
+  * @}
+  */
+
+/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode  
+  * @{
+  */ 
+#define HASH_HMACKeyType_ShortKey      ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */
+#define HASH_HMACKeyType_LongKey       HASH_CR_LKEY           /*!< HMAC Key is > 64 bytes  */
+
+#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \
+                                       ((KEYTYPE) == HASH_HMACKeyType_LongKey))
+/**
+  * @}
+  */
+
+/** @defgroup Number_of_valid_bits_in_last_word_of_the_message   
+  * @{
+  */  
+#define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F)
+
+/**
+  * @}
+  */
+
+/** @defgroup HASH_interrupts_definition   
+  * @{
+  */  
+#define HASH_IT_DINI               HASH_IMR_DINIM  /*!< A new block can be entered into the input buffer (DIN) */
+#define HASH_IT_DCI                HASH_IMR_DCIM   /*!< Digest calculation complete                            */
+
+#define IS_HASH_IT(IT) ((((IT) & (uint32_t)0xFFFFFFFC) == 0x00000000) && ((IT) != 0x00000000))
+#define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI))
+				   
+/**
+  * @}
+  */
+
+/** @defgroup HASH_flags_definition   
+  * @{
+  */  
+#define HASH_FLAG_DINIS            HASH_SR_DINIS  /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
+#define HASH_FLAG_DCIS             HASH_SR_DCIS   /*!< Digest calculation complete                                                         */
+#define HASH_FLAG_DMAS             HASH_SR_DMAS   /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing                          */
+#define HASH_FLAG_BUSY             HASH_SR_BUSY   /*!< The hash core is Busy : processing a block of data                                  */
+#define HASH_FLAG_DINNE            HASH_CR_DINNE  /*!< DIN not empty : The input buffer contains at least one word of data                 */
+
+#define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \
+                                ((FLAG) == HASH_FLAG_DCIS)  || \
+                                ((FLAG) == HASH_FLAG_DMAS)  || \
+                                ((FLAG) == HASH_FLAG_BUSY)  || \
+                                ((FLAG) == HASH_FLAG_DINNE)) 
+
+#define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \
+                                 ((FLAG) == HASH_FLAG_DCIS))                                 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+  
+/*  Function used to set the HASH configuration to the default reset state ****/
+void HASH_DeInit(void);
+
+/* HASH Configuration function ************************************************/
+void HASH_Init(HASH_InitTypeDef* HASH_InitStruct);
+void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct);
+void HASH_Reset(void);
+
+/* HASH Message Digest generation functions ***********************************/
+void HASH_DataIn(uint32_t Data);
+uint8_t HASH_GetInFIFOWordsNbr(void);
+void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber);
+void HASH_StartDigest(void);
+void HASH_AutoStartDigest(FunctionalState NewState);
+void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest);
+
+/* HASH Context swapping functions ********************************************/
+void HASH_SaveContext(HASH_Context* HASH_ContextSave);
+void HASH_RestoreContext(HASH_Context* HASH_ContextRestore);
+
+/* HASH DMA interface function ************************************************/
+void HASH_DMACmd(FunctionalState NewState);
+
+/* HASH Interrupts and flags management functions *****************************/
+void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState);
+FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG);
+void HASH_ClearFlag(uint32_t HASH_FLAG);
+ITStatus HASH_GetITStatus(uint32_t HASH_IT);
+void HASH_ClearITPendingBit(uint32_t HASH_IT);
+
+/* High Level SHA1 functions **************************************************/
+ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]);
+ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen,
+                      uint8_t *Input, uint32_t Ilen,
+                      uint8_t Output[20]);
+
+/* High Level MD5 functions ***************************************************/
+ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]);
+ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen,
+                     uint8_t *Input, uint32_t Ilen,
+                     uint8_t Output[16]);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_HASH_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+

底盘/底盘-old/底盘/Library/stm32f4xx_hash_md5.c

@@ -0,0 +1,312 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hash_md5.c
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file provides high level functions to compute the HASH MD5 and
+  *          HMAC MD5 Digest of an input message.
+  *          It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH
+  *          peripheral.
+  *
+@verbatim
+ ===================================================================
+                  ##### How to use this driver #####
+ ===================================================================
+ [..]
+   (#) Enable The HASH controller clock using 
+       RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function.
+  
+   (#) Calculate the HASH MD5 Digest using HASH_MD5() function.
+  
+   (#) Calculate the HMAC MD5 Digest using HMAC_MD5() function.
+  
+@endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hash.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup HASH 
+  * @brief HASH driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define MD5BUSY_TIMEOUT    ((uint32_t) 0x00010000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HASH_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup HASH_Group7 High Level MD5 functions
+ *  @brief   High Level MD5 Hash and HMAC functions 
+ *
+@verbatim   
+ ===============================================================================
+              ##### High Level MD5 Hash and HMAC functions #####
+ ===============================================================================
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Compute the HASH MD5 digest.
+  * @param  Input: pointer to the Input buffer to be treated.
+  * @param  Ilen: length of the Input buffer.
+  * @param  Output: the returned digest
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: digest computation done
+  *          - ERROR: digest computation failed
+  */
+ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16])
+{
+  HASH_InitTypeDef MD5_HASH_InitStructure;
+  HASH_MsgDigest MD5_MessageDigest;
+  __IO uint16_t nbvalidbitsdata = 0;
+  uint32_t i = 0;
+  __IO uint32_t counter = 0;
+  uint32_t busystatus = 0;
+  ErrorStatus status = SUCCESS;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+
+
+  /* Number of valid bits in last word of the Input data */
+  nbvalidbitsdata = 8 * (Ilen % 4);
+
+  /* HASH peripheral initialization */
+  HASH_DeInit();
+
+  /* HASH Configuration */
+  MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5;
+  MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH;
+  MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
+  HASH_Init(&MD5_HASH_InitStructure);
+
+  /* Configure the number of valid bits in last word of the data */
+  HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
+
+  /* Write the Input block in the IN FIFO */
+  for(i=0; i<Ilen; i+=4)
+  {
+    HASH_DataIn(*(uint32_t*)inputaddr);
+    inputaddr+=4;
+  }
+
+  /* Start the HASH processor */
+  HASH_StartDigest();
+
+  /* wait until the Busy flag is RESET */
+  do
+  {
+    busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
+    counter++;
+  }while ((counter != MD5BUSY_TIMEOUT) && (busystatus != RESET));
+
+  if (busystatus != RESET)
+  {
+     status = ERROR;
+  }
+  else
+  {
+    /* Read the message digest */
+    HASH_GetDigest(&MD5_MessageDigest);
+    *(uint32_t*)(outputaddr)  = __REV(MD5_MessageDigest.Data[0]);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr)  = __REV(MD5_MessageDigest.Data[1]);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr)  = __REV(MD5_MessageDigest.Data[2]);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr)  = __REV(MD5_MessageDigest.Data[3]);
+  }
+  return status; 
+}
+
+/**
+  * @brief  Compute the HMAC MD5 digest.
+  * @param  Key: pointer to the Key used for HMAC.
+  * @param  Keylen: length of the Key used for HMAC.
+  * @param  Input: pointer to the Input buffer to be treated.
+  * @param  Ilen: length of the Input buffer.
+  * @param  Output: the returned digest  
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: digest computation done
+  *          - ERROR: digest computation failed
+  */
+ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen, uint8_t *Input, 
+                     uint32_t Ilen, uint8_t Output[16])
+{
+  HASH_InitTypeDef MD5_HASH_InitStructure;
+  HASH_MsgDigest MD5_MessageDigest;
+  __IO uint16_t nbvalidbitsdata = 0;
+  __IO uint16_t nbvalidbitskey = 0;
+  uint32_t i = 0;
+  __IO uint32_t counter = 0;
+  uint32_t busystatus = 0;
+  ErrorStatus status = SUCCESS;
+  uint32_t keyaddr    = (uint32_t)Key;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+
+  /* Number of valid bits in last word of the Input data */
+  nbvalidbitsdata = 8 * (Ilen % 4);
+
+  /* Number of valid bits in last word of the Key */
+  nbvalidbitskey = 8 * (Keylen % 4);
+   
+  /* HASH peripheral initialization */
+  HASH_DeInit();
+
+  /* HASH Configuration */
+  MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5;
+  MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HMAC;
+  MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
+  if(Keylen > 64)
+  {
+    /* HMAC long Key */
+    MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey;
+  }
+  else
+  {
+    /* HMAC short Key */
+    MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
+  }
+  HASH_Init(&MD5_HASH_InitStructure);
+
+  /* Configure the number of valid bits in last word of the Key */
+  HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
+
+  /* Write the Key */
+  for(i=0; i<Keylen; i+=4)
+  {
+    HASH_DataIn(*(uint32_t*)keyaddr);
+    keyaddr+=4;
+  }
+  
+  /* Start the HASH processor */
+  HASH_StartDigest();
+
+  /* wait until the Busy flag is RESET */
+  do
+  {
+    busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
+    counter++;
+  }while ((counter != MD5BUSY_TIMEOUT) && (busystatus != RESET));
+
+  if (busystatus != RESET)
+  {
+     status = ERROR;
+  }
+  else
+  {
+    /* Configure the number of valid bits in last word of the Input data */
+    HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
+
+    /* Write the Input block in the IN FIFO */
+    for(i=0; i<Ilen; i+=4)
+    {
+      HASH_DataIn(*(uint32_t*)inputaddr);
+      inputaddr+=4;
+    }
+
+    /* Start the HASH processor */
+    HASH_StartDigest();
+
+    /* wait until the Busy flag is RESET */
+    counter =0;
+    do
+    {
+       busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
+       counter++;
+    }while ((counter != MD5BUSY_TIMEOUT) && (busystatus != RESET));
+
+    if (busystatus != RESET)
+    {
+      status = ERROR;
+    }
+    else
+    {  
+      /* Configure the number of valid bits in last word of the Key */
+      HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
+
+      /* Write the Key */
+      keyaddr = (uint32_t)Key;
+      for(i=0; i<Keylen; i+=4)
+      {
+        HASH_DataIn(*(uint32_t*)keyaddr);
+        keyaddr+=4;
+      }
+  
+       /* Start the HASH processor */
+       HASH_StartDigest();
+
+       /* wait until the Busy flag is RESET */
+       counter =0;
+       do
+       {
+          busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
+          counter++;
+      }while ((counter != MD5BUSY_TIMEOUT) && (busystatus != RESET));
+
+      if (busystatus != RESET)
+      {
+         status = ERROR;
+      }
+      else
+      {
+         /* Read the message digest */
+         HASH_GetDigest(&MD5_MessageDigest);
+         *(uint32_t*)(outputaddr)  = __REV(MD5_MessageDigest.Data[0]);
+         outputaddr+=4;
+         *(uint32_t*)(outputaddr)  = __REV(MD5_MessageDigest.Data[1]);
+         outputaddr+=4;
+         *(uint32_t*)(outputaddr)  = __REV(MD5_MessageDigest.Data[2]);
+         outputaddr+=4;
+         *(uint32_t*)(outputaddr)  = __REV(MD5_MessageDigest.Data[3]);
+      }
+    }
+  }
+  return status;  
+}
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+

底盘/底盘-old/底盘/Library/stm32f4xx_hash_sha1.c

@@ -0,0 +1,315 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hash_sha1.c
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file provides high level functions to compute the HASH SHA1 and
+  *          HMAC SHA1 Digest of an input message.
+  *          It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH
+  *          peripheral.
+  *
+@verbatim
+ ===================================================================
+                 ##### How to use this driver #####
+ ===================================================================
+ [..]
+   (#) Enable The HASH controller clock using 
+       RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function.
+  
+   (#) Calculate the HASH SHA1 Digest using HASH_SHA1() function.
+  
+   (#) Calculate the HMAC SHA1 Digest using HMAC_SHA1() function.
+  
+@endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hash.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup HASH 
+  * @brief HASH driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define SHA1BUSY_TIMEOUT    ((uint32_t) 0x00010000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HASH_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup HASH_Group6 High Level SHA1 functions
+ *  @brief   High Level SHA1 Hash and HMAC functions 
+ *
+@verbatim   
+ ===============================================================================
+               ##### High Level SHA1 Hash and HMAC functions #####
+ ===============================================================================
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Compute the HASH SHA1 digest.
+  * @param  Input: pointer to the Input buffer to be treated.
+  * @param  Ilen: length of the Input buffer.
+  * @param  Output: the returned digest
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: digest computation done
+  *          - ERROR: digest computation failed
+  */
+ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20])
+{
+  HASH_InitTypeDef SHA1_HASH_InitStructure;
+  HASH_MsgDigest SHA1_MessageDigest;
+  __IO uint16_t nbvalidbitsdata = 0;
+  uint32_t i = 0;
+  __IO uint32_t counter = 0;
+  uint32_t busystatus = 0;
+  ErrorStatus status = SUCCESS;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+
+  /* Number of valid bits in last word of the Input data */
+  nbvalidbitsdata = 8 * (Ilen % 4);
+
+  /* HASH peripheral initialization */
+  HASH_DeInit();
+
+  /* HASH Configuration */
+  SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
+  SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH;
+  SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
+  HASH_Init(&SHA1_HASH_InitStructure);
+
+  /* Configure the number of valid bits in last word of the data */
+  HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
+
+  /* Write the Input block in the IN FIFO */
+  for(i=0; i<Ilen; i+=4)
+  {
+    HASH_DataIn(*(uint32_t*)inputaddr);
+    inputaddr+=4;
+  }
+
+  /* Start the HASH processor */
+  HASH_StartDigest();
+
+  /* wait until the Busy flag is RESET */
+  do
+  {
+    busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
+    counter++;
+  }while ((counter != SHA1BUSY_TIMEOUT) && (busystatus != RESET));
+
+  if (busystatus != RESET)
+  {
+     status = ERROR;
+  }
+  else
+  {
+    /* Read the message digest */
+    HASH_GetDigest(&SHA1_MessageDigest);
+    *(uint32_t*)(outputaddr)  = __REV(SHA1_MessageDigest.Data[0]);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr)  = __REV(SHA1_MessageDigest.Data[1]);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr)  = __REV(SHA1_MessageDigest.Data[2]);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr)  = __REV(SHA1_MessageDigest.Data[3]);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr)  = __REV(SHA1_MessageDigest.Data[4]);
+  }
+  return status;
+}
+
+/**
+  * @brief  Compute the HMAC SHA1 digest.
+  * @param  Key: pointer to the Key used for HMAC.
+  * @param  Keylen: length of the Key used for HMAC.  
+  * @param  Input: pointer to the Input buffer to be treated.
+  * @param  Ilen: length of the Input buffer.
+  * @param  Output: the returned digest
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: digest computation done
+  *          - ERROR: digest computation failed
+  */
+ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen, uint8_t *Input,
+                      uint32_t Ilen, uint8_t Output[20])
+{
+  HASH_InitTypeDef SHA1_HASH_InitStructure;
+  HASH_MsgDigest SHA1_MessageDigest;
+  __IO uint16_t nbvalidbitsdata = 0;
+  __IO uint16_t nbvalidbitskey = 0;
+  uint32_t i = 0;
+  __IO uint32_t counter = 0;
+  uint32_t busystatus = 0;
+  ErrorStatus status = SUCCESS;
+  uint32_t keyaddr    = (uint32_t)Key;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+
+  /* Number of valid bits in last word of the Input data */
+  nbvalidbitsdata = 8 * (Ilen % 4);
+
+  /* Number of valid bits in last word of the Key */
+  nbvalidbitskey = 8 * (Keylen % 4);
+
+  /* HASH peripheral initialization */
+  HASH_DeInit();
+
+  /* HASH Configuration */
+  SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
+  SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HMAC;
+  SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
+  if(Keylen > 64)
+  {
+    /* HMAC long Key */
+    SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey;
+  }
+  else
+  {
+    /* HMAC short Key */
+    SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
+  }
+  HASH_Init(&SHA1_HASH_InitStructure);
+
+  /* Configure the number of valid bits in last word of the Key */
+  HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
+
+  /* Write the Key */
+  for(i=0; i<Keylen; i+=4)
+  {
+    HASH_DataIn(*(uint32_t*)keyaddr);
+    keyaddr+=4;
+  }
+
+  /* Start the HASH processor */
+  HASH_StartDigest();
+
+  /* wait until the Busy flag is RESET */
+  do
+  {
+    busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
+    counter++;
+  }while ((counter != SHA1BUSY_TIMEOUT) && (busystatus != RESET));
+
+  if (busystatus != RESET)
+  {
+     status = ERROR;
+  }
+  else
+  {
+    /* Configure the number of valid bits in last word of the Input data */
+    HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
+
+    /* Write the Input block in the IN FIFO */
+    for(i=0; i<Ilen; i+=4)
+    {
+      HASH_DataIn(*(uint32_t*)inputaddr);
+      inputaddr+=4;
+    }
+
+    /* Start the HASH processor */
+    HASH_StartDigest();
+
+
+    /* wait until the Busy flag is RESET */
+    counter =0;
+    do
+    {
+      busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
+      counter++;
+    }while ((counter != SHA1BUSY_TIMEOUT) && (busystatus != RESET));
+
+    if (busystatus != RESET)
+    {
+      status = ERROR;
+    }
+    else
+    {  
+      /* Configure the number of valid bits in last word of the Key */
+      HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
+
+      /* Write the Key */
+      keyaddr = (uint32_t)Key;
+      for(i=0; i<Keylen; i+=4)
+      {
+        HASH_DataIn(*(uint32_t*)keyaddr);
+        keyaddr+=4;
+      }
+
+      /* Start the HASH processor */
+      HASH_StartDigest();
+
+      /* wait until the Busy flag is RESET */
+      counter =0;
+      do
+      {
+        busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
+        counter++;
+      }while ((counter != SHA1BUSY_TIMEOUT) && (busystatus != RESET));
+
+      if (busystatus != RESET)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        /* Read the message digest */
+        HASH_GetDigest(&SHA1_MessageDigest);
+        *(uint32_t*)(outputaddr)  = __REV(SHA1_MessageDigest.Data[0]);
+        outputaddr+=4;
+        *(uint32_t*)(outputaddr)  = __REV(SHA1_MessageDigest.Data[1]);
+        outputaddr+=4;
+        *(uint32_t*)(outputaddr)  = __REV(SHA1_MessageDigest.Data[2]);
+        outputaddr+=4;
+        *(uint32_t*)(outputaddr)  = __REV(SHA1_MessageDigest.Data[3]);
+        outputaddr+=4;
+        *(uint32_t*)(outputaddr)  = __REV(SHA1_MessageDigest.Data[4]);
+      }
+    }  
+  }
+  return status;  
+}
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+

底盘/底盘-old/底盘/Library/stm32f4xx_i2c.h

@@ -0,0 +1,701 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_i2c.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the I2C firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_I2C_H
+#define __STM32F4xx_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  I2C Init structure definition  
+  */
+
+typedef struct
+{
+  uint32_t I2C_ClockSpeed;          /*!< Specifies the clock frequency.
+                                         This parameter must be set to a value lower than 400kHz */
+
+  uint16_t I2C_Mode;                /*!< Specifies the I2C mode.
+                                         This parameter can be a value of @ref I2C_mode */
+
+  uint16_t I2C_DutyCycle;           /*!< Specifies the I2C fast mode duty cycle.
+                                         This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+  uint16_t I2C_OwnAddress1;         /*!< Specifies the first device own address.
+                                         This parameter can be a 7-bit or 10-bit address. */
+
+  uint16_t I2C_Ack;                 /*!< Enables or disables the acknowledgement.
+                                         This parameter can be a value of @ref I2C_acknowledgement */
+
+  uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+                                         This parameter can be a value of @ref I2C_acknowledged_address */
+}I2C_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+
+/** @defgroup I2C_Exported_Constants
+  * @{
+  */
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
+                                   ((PERIPH) == I2C2) || \
+                                   ((PERIPH) == I2C3))
+/** @defgroup I2C_Digital_Filter
+  * @{
+  */
+
+#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000F)
+/**
+  * @}
+  */
+
+
+/** @defgroup I2C_mode 
+  * @{
+  */
+
+#define I2C_Mode_I2C                    ((uint16_t)0x0000)
+#define I2C_Mode_SMBusDevice            ((uint16_t)0x0002)  
+#define I2C_Mode_SMBusHost              ((uint16_t)0x000A)
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
+                           ((MODE) == I2C_Mode_SMBusDevice) || \
+                           ((MODE) == I2C_Mode_SMBusHost))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_duty_cycle_in_fast_mode 
+  * @{
+  */
+
+#define I2C_DutyCycle_16_9              ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_DutyCycle_2                 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
+                                  ((CYCLE) == I2C_DutyCycle_2))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_acknowledgement
+  * @{
+  */
+
+#define I2C_Ack_Enable                  ((uint16_t)0x0400)
+#define I2C_Ack_Disable                 ((uint16_t)0x0000)
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
+                                 ((STATE) == I2C_Ack_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_transfer_direction 
+  * @{
+  */
+
+#define  I2C_Direction_Transmitter      ((uint8_t)0x00)
+#define  I2C_Direction_Receiver         ((uint8_t)0x01)
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
+                                     ((DIRECTION) == I2C_Direction_Receiver))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_acknowledged_address 
+  * @{
+  */
+
+#define I2C_AcknowledgedAddress_7bit    ((uint16_t)0x4000)
+#define I2C_AcknowledgedAddress_10bit   ((uint16_t)0xC000)
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
+                                             ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_registers 
+  * @{
+  */
+
+#define I2C_Register_CR1                ((uint8_t)0x00)
+#define I2C_Register_CR2                ((uint8_t)0x04)
+#define I2C_Register_OAR1               ((uint8_t)0x08)
+#define I2C_Register_OAR2               ((uint8_t)0x0C)
+#define I2C_Register_DR                 ((uint8_t)0x10)
+#define I2C_Register_SR1                ((uint8_t)0x14)
+#define I2C_Register_SR2                ((uint8_t)0x18)
+#define I2C_Register_CCR                ((uint8_t)0x1C)
+#define I2C_Register_TRISE              ((uint8_t)0x20)
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
+                                   ((REGISTER) == I2C_Register_CR2) || \
+                                   ((REGISTER) == I2C_Register_OAR1) || \
+                                   ((REGISTER) == I2C_Register_OAR2) || \
+                                   ((REGISTER) == I2C_Register_DR) || \
+                                   ((REGISTER) == I2C_Register_SR1) || \
+                                   ((REGISTER) == I2C_Register_SR2) || \
+                                   ((REGISTER) == I2C_Register_CCR) || \
+                                   ((REGISTER) == I2C_Register_TRISE))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_NACK_position 
+  * @{
+  */
+
+#define I2C_NACKPosition_Next           ((uint16_t)0x0800)
+#define I2C_NACKPosition_Current        ((uint16_t)0xF7FF)
+#define IS_I2C_NACK_POSITION(POSITION)  (((POSITION) == I2C_NACKPosition_Next) || \
+                                         ((POSITION) == I2C_NACKPosition_Current))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_SMBus_alert_pin_level 
+  * @{
+  */
+
+#define I2C_SMBusAlert_Low              ((uint16_t)0x2000)
+#define I2C_SMBusAlert_High             ((uint16_t)0xDFFF)
+#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
+                                   ((ALERT) == I2C_SMBusAlert_High))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_PEC_position 
+  * @{
+  */
+
+#define I2C_PECPosition_Next            ((uint16_t)0x0800)
+#define I2C_PECPosition_Current         ((uint16_t)0xF7FF)
+#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
+                                       ((POSITION) == I2C_PECPosition_Current))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_interrupts_definition 
+  * @{
+  */
+
+#define I2C_IT_BUF                      ((uint16_t)0x0400)
+#define I2C_IT_EVT                      ((uint16_t)0x0200)
+#define I2C_IT_ERR                      ((uint16_t)0x0100)
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_interrupts_definition 
+  * @{
+  */
+
+#define I2C_IT_SMBALERT                 ((uint32_t)0x01008000)
+#define I2C_IT_TIMEOUT                  ((uint32_t)0x01004000)
+#define I2C_IT_PECERR                   ((uint32_t)0x01001000)
+#define I2C_IT_OVR                      ((uint32_t)0x01000800)
+#define I2C_IT_AF                       ((uint32_t)0x01000400)
+#define I2C_IT_ARLO                     ((uint32_t)0x01000200)
+#define I2C_IT_BERR                     ((uint32_t)0x01000100)
+#define I2C_IT_TXE                      ((uint32_t)0x06000080)
+#define I2C_IT_RXNE                     ((uint32_t)0x06000040)
+#define I2C_IT_STOPF                    ((uint32_t)0x02000010)
+#define I2C_IT_ADD10                    ((uint32_t)0x02000008)
+#define I2C_IT_BTF                      ((uint32_t)0x02000004)
+#define I2C_IT_ADDR                     ((uint32_t)0x02000002)
+#define I2C_IT_SB                       ((uint32_t)0x02000001)
+
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
+
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
+                           ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
+                           ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
+                           ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
+                           ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
+                           ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
+                           ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_flags_definition 
+  * @{
+  */
+
+/** 
+  * @brief  SR2 register flags  
+  */
+
+#define I2C_FLAG_DUALF                  ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHOST                ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00200000)
+#define I2C_FLAG_GENCALL                ((uint32_t)0x00100000)
+#define I2C_FLAG_TRA                    ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSY                   ((uint32_t)0x00020000)
+#define I2C_FLAG_MSL                    ((uint32_t)0x00010000)
+
+/** 
+  * @brief  SR1 register flags  
+  */
+
+#define I2C_FLAG_SMBALERT               ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMEOUT                ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR                 ((uint32_t)0x10001000)
+#define I2C_FLAG_OVR                    ((uint32_t)0x10000800)
+#define I2C_FLAG_AF                     ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLO                   ((uint32_t)0x10000200)
+#define I2C_FLAG_BERR                   ((uint32_t)0x10000100)
+#define I2C_FLAG_TXE                    ((uint32_t)0x10000080)
+#define I2C_FLAG_RXNE                   ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF                  ((uint32_t)0x10000010)
+#define I2C_FLAG_ADD10                  ((uint32_t)0x10000008)
+#define I2C_FLAG_BTF                    ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDR                   ((uint32_t)0x10000002)
+#define I2C_FLAG_SB                     ((uint32_t)0x10000001)
+
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
+                               ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
+                               ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
+                               ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
+                               ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
+                               ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
+                               ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
+                               ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
+                               ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
+                               ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
+                               ((FLAG) == I2C_FLAG_SB))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Events 
+  * @{
+  */
+
+/**
+ ===============================================================================
+               I2C Master Events (Events grouped in order of communication)
+ ===============================================================================
+ */
+
+/** 
+  * @brief  Communication start
+  * 
+  * After sending the START condition (I2C_GenerateSTART() function) the master 
+  * has to wait for this event. It means that the Start condition has been correctly 
+  * released on the I2C bus (the bus is free, no other devices is communicating).
+  * 
+  */
+/* --EV5 */
+#define  I2C_EVENT_MASTER_MODE_SELECT                      ((uint32_t)0x00030001)  /* BUSY, MSL and SB flag */
+
+/** 
+  * @brief  Address Acknowledge
+  * 
+  * After checking on EV5 (start condition correctly released on the bus), the 
+  * master sends the address of the slave(s) with which it will communicate 
+  * (I2C_Send7bitAddress() function, it also determines the direction of the communication: 
+  * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges 
+  * his address. If an acknowledge is sent on the bus, one of the following events will 
+  * be set:
+  * 
+  *  1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED 
+  *     event is set.
+  *  
+  *  2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED 
+  *     is set
+  *  
+  *  3) In case of 10-Bit addressing mode, the master (just after generating the START 
+  *  and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() 
+  *  function). Then master should wait on EV9. It means that the 10-bit addressing 
+  *  header has been correctly sent on the bus. Then master should send the second part of 
+  *  the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master 
+  *  should wait for event EV6. 
+  *     
+  */
+
+/* --EV6 */
+#define  I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED        ((uint32_t)0x00070082)  /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define  I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED           ((uint32_t)0x00030002)  /* BUSY, MSL and ADDR flags */
+/* --EV9 */
+#define  I2C_EVENT_MASTER_MODE_ADDRESS10                   ((uint32_t)0x00030008)  /* BUSY, MSL and ADD10 flags */
+
+/** 
+  * @brief Communication events
+  * 
+  * If a communication is established (START condition generated and slave address 
+  * acknowledged) then the master has to check on one of the following events for 
+  * communication procedures:
+  *  
+  * 1) Master Receiver mode: The master has to wait on the event EV7 then to read 
+  *    the data received from the slave (I2C_ReceiveData() function).
+  * 
+  * 2) Master Transmitter mode: The master has to send data (I2C_SendData() 
+  *    function) then to wait on event EV8 or EV8_2.
+  *    These two events are similar: 
+  *     - EV8 means that the data has been written in the data register and is 
+  *       being shifted out.
+  *     - EV8_2 means that the data has been physically shifted out and output 
+  *       on the bus.
+  *     In most cases, using EV8 is sufficient for the application.
+  *     Using EV8_2 leads to a slower communication but ensure more reliable test.
+  *     EV8_2 is also more suitable than EV8 for testing on the last data transmission 
+  *     (before Stop condition generation).
+  *     
+  *  @note In case the  user software does not guarantee that this event EV7 is 
+  *        managed before the current byte end of transfer, then user may check on EV7 
+  *        and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
+  *        In this case the communication may be slower.
+  * 
+  */
+
+/* Master RECEIVER mode -----------------------------*/ 
+/* --EV7 */
+#define  I2C_EVENT_MASTER_BYTE_RECEIVED                    ((uint32_t)0x00030040)  /* BUSY, MSL and RXNE flags */
+
+/* Master TRANSMITTER mode --------------------------*/
+/* --EV8 */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING                 ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
+/* --EV8_2 */
+#define  I2C_EVENT_MASTER_BYTE_TRANSMITTED                 ((uint32_t)0x00070084)  /* TRA, BUSY, MSL, TXE and BTF flags */
+
+
+/**
+ ===============================================================================
+               I2C Slave Events (Events grouped in order of communication)
+ ===============================================================================
+ */
+
+
+/** 
+  * @brief  Communication start events
+  * 
+  * Wait on one of these events at the start of the communication. It means that 
+  * the I2C peripheral detected a Start condition on the bus (generated by master 
+  * device) followed by the peripheral address. The peripheral generates an ACK 
+  * condition on the bus (if the acknowledge feature is enabled through function 
+  * I2C_AcknowledgeConfig()) and the events listed above are set :
+  *  
+  * 1) In normal case (only one address managed by the slave), when the address 
+  *   sent by the master matches the own address of the peripheral (configured by 
+  *   I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set 
+  *   (where XXX could be TRANSMITTER or RECEIVER).
+  *    
+  * 2) In case the address sent by the master matches the second address of the 
+  *   peripheral (configured by the function I2C_OwnAddress2Config() and enabled 
+  *   by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED 
+  *   (where XXX could be TRANSMITTER or RECEIVER) are set.
+  *   
+  * 3) In case the address sent by the master is General Call (address 0x00) and 
+  *   if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) 
+  *   the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.   
+  * 
+  */
+
+/* --EV1  (all the events below are variants of EV1) */   
+/* 1) Case of One Single Address managed by the slave */
+#define  I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED          ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+#define  I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED       ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+
+/* 2) Case of Dual address managed by the slave */
+#define  I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED    ((uint32_t)0x00820000)  /* DUALF and BUSY flags */
+#define  I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)  /* DUALF, TRA, BUSY and TXE flags */
+
+/* 3) Case of General Call enabled for the slave */
+#define  I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED        ((uint32_t)0x00120000)  /* GENCALL and BUSY flags */
+
+/** 
+  * @brief  Communication events
+  * 
+  * Wait on one of these events when EV1 has already been checked and: 
+  * 
+  * - Slave RECEIVER mode:
+  *     - EV2: When the application is expecting a data byte to be received. 
+  *     - EV4: When the application is expecting the end of the communication: master 
+  *       sends a stop condition and data transmission is stopped.
+  *    
+  * - Slave Transmitter mode:
+  *    - EV3: When a byte has been transmitted by the slave and the application is expecting 
+  *      the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
+  *      I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be 
+  *      used when the user software doesn't guarantee the EV3 is managed before the
+  *      current byte end of transfer.
+  *    - EV3_2: When the master sends a NACK in order to tell slave that data transmission 
+  *      shall end (before sending the STOP condition). In this case slave has to stop sending 
+  *      data bytes and expect a Stop condition on the bus.
+  *      
+  *  @note In case the  user software does not guarantee that the event EV2 is 
+  *        managed before the current byte end of transfer, then user may check on EV2 
+  *        and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
+  *        In this case the communication may be slower.
+  *
+  */
+
+/* Slave RECEIVER mode --------------------------*/ 
+/* --EV2 */
+#define  I2C_EVENT_SLAVE_BYTE_RECEIVED                     ((uint32_t)0x00020040)  /* BUSY and RXNE flags */
+/* --EV4  */
+#define  I2C_EVENT_SLAVE_STOP_DETECTED                     ((uint32_t)0x00000010)  /* STOPF flag */
+
+/* Slave TRANSMITTER mode -----------------------*/
+/* --EV3 */
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTED                  ((uint32_t)0x00060084)  /* TRA, BUSY, TXE and BTF flags */
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTING                 ((uint32_t)0x00060080)  /* TRA, BUSY and TXE flags */
+/* --EV3_2 */
+#define  I2C_EVENT_SLAVE_ACK_FAILURE                       ((uint32_t)0x00000400)  /* AF flag */
+
+/*
+ ===============================================================================
+                          End of Events Description
+ ===============================================================================
+ */
+
+#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
+                             ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
+                             ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_own_address1 
+  * @{
+  */
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_clock_speed 
+  * @{
+  */
+
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/*  Function used to set the I2C configuration to the default reset state *****/
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+
+/* Initialization and Configuration functions *********************************/
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter);
+void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
+/* Data transfers functions ***************************************************/ 
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+
+/* PEC management functions ***************************************************/ 
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
+
+/* DMA transfers management functions *****************************************/
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
+/* Interrupts, events and flags management functions **************************/
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
+
+/* 
+ ===============================================================================
+                          I2C State Monitoring Functions
+ ===============================================================================
+  This I2C driver provides three different ways for I2C state monitoring
+  depending on the application requirements and constraints:
+         
+   
+     1. Basic state monitoring (Using I2C_CheckEvent() function)
+     -----------------------------------------------------------
+        It compares the status registers (SR1 and SR2) content to a given event
+        (can be the combination of one or more flags).
+        It returns SUCCESS if the current status includes the given flags 
+        and returns ERROR if one or more flags are missing in the current status.
+
+          - When to use
+             - This function is suitable for most applications as well as for startup 
+               activity since the events are fully described in the product reference 
+               manual (RM0090).
+             - It is also suitable for users who need to define their own events.
+
+          - Limitations
+             - If an error occurs (ie. error flags are set besides to the monitored 
+               flags), the I2C_CheckEvent() function may return SUCCESS despite 
+               the communication hold or corrupted real state. 
+               In this case, it is advised to use error interrupts to monitor 
+               the error events and handle them in the interrupt IRQ handler.
+         
+     Note 
+         For error management, it is advised to use the following functions:
+           - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
+           - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+             Where x is the peripheral instance (I2C1, I2C2 ...)
+           - I2C_GetFlagStatus() or I2C_GetITStatus()  to be called into the 
+             I2Cx_ER_IRQHandler() function in order to determine which error occurred.
+           - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() 
+             and/or I2C_GenerateStop() in order to clear the error flag and source 
+             and return to correct  communication status.
+             
+ 
+     2. Advanced state monitoring (Using the function I2C_GetLastEvent())
+     -------------------------------------------------------------------- 
+        Using the function I2C_GetLastEvent() which returns the image of both status 
+        registers in a single word (uint32_t) (Status Register 2 value is shifted left 
+        by 16 bits and concatenated to Status Register 1).
+
+          - When to use
+             - This function is suitable for the same applications above but it 
+               allows to overcome the mentioned limitation of I2C_GetFlagStatus() 
+               function.
+             - The returned value could be compared to events already defined in 
+               this file or to custom values defined by user.
+               This function is suitable when multiple flags are monitored at the 
+               same time.
+             - At the opposite of I2C_CheckEvent() function, this function allows 
+               user to choose when an event is accepted (when all events flags are 
+               set and no other flags are set or just when the needed flags are set 
+               like I2C_CheckEvent() function.
+
+          - Limitations
+             - User may need to define his own events.
+             - Same remark concerning the error management is applicable for this 
+               function if user decides to check only regular communication flags 
+               (and ignores error flags).
+      
+ 
+     3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
+     -----------------------------------------------------------------------
+     
+      Using the function I2C_GetFlagStatus() which simply returns the status of 
+      one single flag (ie. I2C_FLAG_RXNE ...). 
+
+          - When to use
+             - This function could be used for specific applications or in debug 
+               phase.
+             - It is suitable when only one flag checking is needed (most I2C 
+               events are monitored through multiple flags).
+          - Limitations: 
+             - When calling this function, the Status register is accessed. 
+               Some flags are cleared when the status register is accessed. 
+               So checking the status of one Flag, may clear other ones.
+             - Function may need to be called twice or more in order to monitor 
+               one single event.           
+ */
+
+/*
+ ===============================================================================
+                          1. Basic state monitoring
+ ===============================================================================
+ */
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
+/*
+ ===============================================================================
+                          2. Advanced state monitoring
+ ===============================================================================
+ */
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
+/*
+ ===============================================================================
+                          3. Flag-based state monitoring
+ ===============================================================================
+ */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+
+
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_I2C_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+

底盘/底盘-old/底盘/Library/stm32f4xx_iwdg.c

@@ -0,0 +1,258 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_iwdg.c
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Independent watchdog (IWDG) peripheral:           
+  *           + Prescaler and Counter configuration
+  *           + IWDG activation
+  *           + Flag management
+  *
+    @verbatim    
+ ===============================================================================
+                          ##### IWDG features #####
+ ===============================================================================
+    [..]  
+      The IWDG can be started by either software or hardware (configurable
+      through option byte).
+              
+      The IWDG is clocked by its own dedicated low-speed clock (LSI) and
+      thus stays active even if the main clock fails.
+      Once the IWDG is started, the LSI is forced ON and cannot be disabled
+      (LSI cannot be disabled too), and the counter starts counting down from 
+      the reset value of 0xFFF. When it reaches the end of count value (0x000)
+      a system reset is generated.
+      The IWDG counter should be reloaded at regular intervals to prevent
+      an MCU reset.
+                             
+      The IWDG is implemented in the VDD voltage domain that is still functional
+      in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).          
+              
+      IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
+      reset occurs.
+              
+      Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
+      The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx
+      devices provide the capability to measure the LSI frequency (LSI clock
+      connected internally to TIM5 CH4 input capture). The measured value
+      can be used to have an IWDG timeout with an acceptable accuracy. 
+      For more information, please refer to the STM32F4xx Reference manual
+            
+                     ##### How to use this driver #####
+ ===============================================================================
+    [..]
+      (#) Enable write access to IWDG_PR and IWDG_RLR registers using
+          IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function
+                 
+      (#) Configure the IWDG prescaler using IWDG_SetPrescaler() function
+              
+      (#) Configure the IWDG counter value using IWDG_SetReload() function.
+          This value will be loaded in the IWDG counter each time the counter
+          is reloaded, then the IWDG will start counting down from this value.
+              
+      (#) Start the IWDG using IWDG_Enable() function, when the IWDG is used
+          in software mode (no need to enable the LSI, it will be enabled
+          by hardware)
+               
+      (#) Then the application program must reload the IWDG counter at regular
+          intervals during normal operation to prevent an MCU reset, using
+          IWDG_ReloadCounter() function.      
+            
+    @endverbatim    
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_iwdg.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup IWDG 
+  * @brief IWDG driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* KR register bit mask */
+#define KR_KEY_RELOAD    ((uint16_t)0xAAAA)
+#define KR_KEY_ENABLE    ((uint16_t)0xCCCC)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup IWDG_Private_Functions
+  * @{
+  */
+
+/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
+ *  @brief   Prescaler and Counter configuration functions
+ *
+@verbatim   
+ ===============================================================================
+              ##### Prescaler and Counter configuration functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables write access to IWDG_PR and IWDG_RLR registers.
+  * @param  IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
+  *          This parameter can be one of the following values:
+  *            @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
+  *            @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
+  * @retval None
+  */
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
+  IWDG->KR = IWDG_WriteAccess;
+}
+
+/**
+  * @brief  Sets IWDG Prescaler value.
+  * @param  IWDG_Prescaler: specifies the IWDG Prescaler value.
+  *          This parameter can be one of the following values:
+  *            @arg IWDG_Prescaler_4: IWDG prescaler set to 4
+  *            @arg IWDG_Prescaler_8: IWDG prescaler set to 8
+  *            @arg IWDG_Prescaler_16: IWDG prescaler set to 16
+  *            @arg IWDG_Prescaler_32: IWDG prescaler set to 32
+  *            @arg IWDG_Prescaler_64: IWDG prescaler set to 64
+  *            @arg IWDG_Prescaler_128: IWDG prescaler set to 128
+  *            @arg IWDG_Prescaler_256: IWDG prescaler set to 256
+  * @retval None
+  */
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
+  IWDG->PR = IWDG_Prescaler;
+}
+
+/**
+  * @brief  Sets IWDG Reload value.
+  * @param  Reload: specifies the IWDG Reload value.
+  *          This parameter must be a number between 0 and 0x0FFF.
+  * @retval None
+  */
+void IWDG_SetReload(uint16_t Reload)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_RELOAD(Reload));
+  IWDG->RLR = Reload;
+}
+
+/**
+  * @brief  Reloads IWDG counter with value defined in the reload register
+  *         (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  None
+  * @retval None
+  */
+void IWDG_ReloadCounter(void)
+{
+  IWDG->KR = KR_KEY_RELOAD;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Group2 IWDG activation function
+ *  @brief   IWDG activation function 
+ *
+@verbatim   
+ ===============================================================================
+                    ##### IWDG activation function #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  None
+  * @retval None
+  */
+void IWDG_Enable(void)
+{
+  IWDG->KR = KR_KEY_ENABLE;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Group3 Flag management function 
+ *  @brief  Flag management function  
+ *
+@verbatim   
+ ===============================================================================
+                    ##### Flag management function #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified IWDG flag is set or not.
+  * @param  IWDG_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg IWDG_FLAG_PVU: Prescaler Value Update on going
+  *            @arg IWDG_FLAG_RVU: Reload Value Update on going
+  * @retval The new state of IWDG_FLAG (SET or RESET).
+  */
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_IWDG_FLAG(IWDG_FLAG));
+  if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

底盘/底盘-old/底盘/Library/stm32f4xx_iwdg.h

@@ -0,0 +1,123 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_iwdg.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the IWDG 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_IWDG_H
+#define __STM32F4xx_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup IWDG
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup IWDG_Exported_Constants
+  * @{
+  */
+  
+/** @defgroup IWDG_WriteAccess
+  * @{
+  */
+#define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
+                                      ((ACCESS) == IWDG_WriteAccess_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_prescaler 
+  * @{
+  */
+#define IWDG_Prescaler_4            ((uint8_t)0x00)
+#define IWDG_Prescaler_8            ((uint8_t)0x01)
+#define IWDG_Prescaler_16           ((uint8_t)0x02)
+#define IWDG_Prescaler_32           ((uint8_t)0x03)
+#define IWDG_Prescaler_64           ((uint8_t)0x04)
+#define IWDG_Prescaler_128          ((uint8_t)0x05)
+#define IWDG_Prescaler_256          ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4)  || \
+                                      ((PRESCALER) == IWDG_Prescaler_8)  || \
+                                      ((PRESCALER) == IWDG_Prescaler_16) || \
+                                      ((PRESCALER) == IWDG_Prescaler_32) || \
+                                      ((PRESCALER) == IWDG_Prescaler_64) || \
+                                      ((PRESCALER) == IWDG_Prescaler_128)|| \
+                                      ((PRESCALER) == IWDG_Prescaler_256))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Flag 
+  * @{
+  */
+#define IWDG_FLAG_PVU               ((uint16_t)0x0001)
+#define IWDG_FLAG_RVU               ((uint16_t)0x0002)
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Prescaler and Counter configuration functions ******************************/
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+
+/* IWDG activation function ***************************************************/
+void IWDG_Enable(void);
+
+/* Flag management function ***************************************************/
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_IWDG_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

底盘/底盘-old/底盘/Library/stm32f4xx_lptim.c

@@ -0,0 +1,943 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_lptim.c
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file provides firmware functions to manage the following
+  *          functionalities of the Low Power Timer (LPT) peripheral:
+  *           + Initialization functions.
+  *           + Configuration functions.
+  *           + Interrupts and flags management functions.
+  *
+  *  @verbatim
+  *
+================================================================================
+                   ##### How to use this driver #####
+================================================================================
+
+           Basic configuration:
+           --------------------
+           - Configure the clock source, the prescaler, the waveform shape and
+             the output polarity by filling the "LPTIM_InitTypeDef" structure and
+             calling LPTIM_Init.
+           - If the ULPTIM source is selected as clock source, configure the digital
+             Glitch filter by setting the number of consecutive samples
+             to be detected by using LPTIM_ConfigClockGlitchFilter.
+           - To select a software start use LPTIM_SelectSoftwareStart.
+           - To select an external trigger for the start of the counter, configure
+             the source and its active edge polarity by calling
+             LPTIM_ConfigExternalTrigger. Configure the Digital Glitch filter for
+             the external triggers by setting the number of consecutive samples
+             to be detected by using LPTIM_ConfigTriggerGlitchFilter.
+           - Select the operating mode of the peripheral by using
+             LPTIM_SelectOperatingMode, 2 modes can be selected:
+               + Continuous mode: the timer is free running, the timer is started
+                 from a trigger event and never stops until the timer is disabled
+               + One shot mode: the timer is started from a trigger event and
+                 stops when reaching the auto-reload value.
+           - Use LPTIM_SetAutoreloadValue to set the auto-reload value and
+             LPTIM_SetCompareValue to set the compare value.
+           - Configure the preload mode by using LPTIM_ConfigUpdate function. 2 modes
+             are available:
+               + The Autoreload and compare registers are updated immediately after
+                 APB write.
+               + The Autoreload and compare registers are updated at the end of
+                 counter period.
+            - Enable the peripheral by calling LPTIM_Cmd.
+
+           Encoder mode:
+           -------------
+           - To select the encoder feature, use the function: LPTIM_SelectEncoderMode.
+           - To select on which edge (Rising edge, falling edge or both edges)
+             the counter is incremented, use LPTIM_SelectClockPolarity.
+
+           Counter mode:
+           -------------
+           - Use LPTIM_SelectCounterMode to select the counting mode. In this mode
+             the counter is incremented on each valid event on ULPTIM.
+
+           Timeout function:
+           -----------------
+           In this case, the trigger will reset the timer. The first trigger event
+           will start the timer, any successive trigger event will reset the counter
+           and the timer restarts.
+           - To active this feature use LPTIM_TimoutCmd.
+
+           Interrupt configuration:
+           ------------------------
+           - Use LPTIM_ITConfig to configure an interruption.
+           - Call LPTIM_GetFlagStatus to get a flag status.
+           - Call LPTIM_GetITStatus to get an interrupt status.
+           - Use LPTIM_ClearFlag to clear a flag.
+  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_lptim.h"
+
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup LPTIM
+  * @brief LPTIM driver modules
+  * @{
+  */
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+/* External variables --------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+
+#define CFGR_INIT_CLEAR_MASK                 ((uint32_t) 0xFFCFF1FE)
+#define CFGR_TRIG_AND_POL_CLEAR_MASK         ((uint32_t) 0xFFF91FFF)
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup LPTIM_Private_Functions
+  * @{
+  */
+
+/** @defgroup LPTIM_Group1 Initialization functions
+  *  @brief   Initialization functions
+  *
+@verbatim
+ ===============================================================================
+                             Initialization functions
+ ===============================================================================
+  This section provides functions allowing to:
+   - Deinitialize  the LPTimer
+   - Initialize the Clock source, the Prescaler, the Ouput Waveform shape and Polarity
+   - Initialize the member of LPTIM_InitStruct structer with default value
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the LPTIMx peripheral registers to their default reset values.
+  * @param  LPTIMx: where x can be 1.
+  * @retval None
+  *
+  */
+void LPTIM_DeInit(LPTIM_TypeDef* LPTIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  
+  /* Deinitializes the LPTIM1 peripheral */
+  if(LPTIMx == LPTIM1)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_LPTIM1, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_LPTIM1, DISABLE);
+  }
+}
+
+/**
+  * @brief  Initializes the LPTIMx peripheral according to the specified parameters
+  *         in the LPTIM_InitStruct.
+  * @param  LPTIMx: where x can be 1.
+  * @param  LPTIM_InitStruct: pointer to an LPTIM_InitTypeDef structure that contains
+  *         the configuration information for the specified LPTIM peripheral.
+  * @retval None
+  *
+  * @note   It is mandatory to disable the peripheral to use this function.
+  */
+void LPTIM_Init(LPTIM_TypeDef* LPTIMx, LPTIM_InitTypeDef* LPTIM_InitStruct)
+{
+  uint32_t tmpreg1 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->LPTIM_ClockSource));
+  assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->LPTIM_Prescaler));
+  assert_param(IS_LPTIM_WAVEFORM(LPTIM_InitStruct->LPTIM_Waveform));
+  assert_param(IS_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->LPTIM_OutputPolarity));
+  
+  /* Get the LPTIMx CFGR value */
+  tmpreg1 = LPTIMx->CFGR;
+  
+  /* Clear CKSEL, PRESC, WAVE and WAVEPOL bits */
+  tmpreg1 &= CFGR_INIT_CLEAR_MASK;
+  
+  /* Set or Reset CKSEL bit according to LPTIM_ClockSource value */
+  /* Set or Reset PRESC bits according to LPTIM_Prescaler value */
+  /* Set or Reset WAVE bit according to LPTIM_Waveform value */
+  /* Set or Reset WAVEPOL bit according to LPTIM_OutputPolarity value */
+  tmpreg1 |= (LPTIM_InitStruct->LPTIM_ClockSource | LPTIM_InitStruct->LPTIM_Prescaler
+              |LPTIM_InitStruct->LPTIM_Waveform | LPTIM_InitStruct->LPTIM_OutputPolarity);
+  
+  /* Write to LPTIMx CFGR */
+  LPTIMx->CFGR = tmpreg1;
+}
+
+/**
+  * @brief  Fills each LPTIM_InitStruct member with its default value.
+  * @param  LPTIM_InitStruct : pointer to a LPTIM_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void LPTIM_StructInit(LPTIM_InitTypeDef* LPTIM_InitStruct)
+{
+  /* APB Clock/Low Power oscillators is selected as default Clock source*/
+  LPTIM_InitStruct->LPTIM_ClockSource = LPTIM_ClockSource_APBClock_LPosc;
+  
+  /* High Polarity is selected as default polarity */
+  LPTIM_InitStruct->LPTIM_OutputPolarity = LPTIM_OutputPolarity_High;
+  
+  /* DIV=1 is selected as default prescaler */
+  LPTIM_InitStruct->LPTIM_Prescaler = LPTIM_Prescaler_DIV1;
+  
+  /* PWM/One pulse mode is selected as default Waveform shape */
+  LPTIM_InitStruct->LPTIM_Waveform = LPTIM_Waveform_PWM_OnePulse;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Group2 Configuration functions
+  *  @brief   Configuration functions
+  *
+@verbatim
+ ===============================================================================
+                       Configuration functions
+ ===============================================================================
+    This section provides functions allowing to configure the Low Power Timer:
+    - Select the Clock source.
+    - Configure the Glitch filter for the external clock and the external clock.
+    - Configure the prescaler of the counter.
+    - Select the Trigger source of the counter.
+    - Configure the operating mode (Single or Continuous mode).
+    - Select the Waveform shape (PWM/One Pulse or Set once) and polarity.
+    - Enable or disable the Encoder mode and the Timeout function.
+    - Write on the Autoreload and the Compare registers and configure the
+      preload mode.
+    - Get the Counter value.
+    - Enable or disable the peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified LPTIM peripheral.
+  * @param  LPTIMx: where x can be 1.
+  * @param  NewState: new state of the LPTIMx peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void LPTIM_Cmd(LPTIM_TypeDef* LPTIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if(NewState != DISABLE)
+  {
+    /* Set the ENABLE bit */
+    LPTIMx->CR |= LPTIM_CR_ENABLE;
+  }
+  else
+  {
+    /* Reset the ENABLE bit */
+    LPTIMx->CR &= ~(LPTIM_CR_ENABLE);
+  }
+}
+
+/**
+  * @brief  Selects the Clock source of the LPTIM counter.
+  * @param  LPTIMx: where x can be 1.
+  * @param  LPTIM_ClockSource: the selected clock source.
+  *         This parameter can be:
+  *         @arg LPTIM_ClockSource_APBClock_LPosc : APB clock/LP oscillators selected
+  *         @arg LPTIM_ClockSource_ULPTIM: ULPTIM (external input) selected
+  * @retval None
+  *
+  * @note   It is mandatory to disable the peripheral to use this function.
+  */
+void LPTIM_SelectClockSource(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_ClockSource)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_ClockSource));
+  
+  /* Clear the CKSEL bit */
+  LPTIMx->CFGR &= ~(LPTIM_CFGR_CKSEL);
+  
+  /* Set or Reset the CKSEL bit */
+  LPTIMx->CFGR |= LPTIM_ClockSource;
+}
+
+/**
+  * @brief  Configures the polarity of the edge to be used to count
+  *         if the ULPTIM input is selected.
+  * @param  LPTIMx: where x can be 1.
+  * @param  LPTIM_ClockPolarity: the selected clock polarity.
+  * This parameter can be:
+  *     @arg LPTIM_ClockPolarity_RisingEdge : Counter Clock = LPTIM Clock / 1
+  *     @arg LPTIM_ClockPolarity_FallingEdge : Counter Clock = LPTIM Clock / 2
+  *     @arg LPTIM_ClockPolarity_BothEdges : Counter Clock = LPTIM Clock / 4
+  * @retval None
+  *
+  * @note   It is mandatory to disable the peripheral to use this function.
+  */
+void LPTIM_SelectULPTIMClockPolarity(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_ClockPolarity)
+{
+  uint32_t tmpreg1 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  assert_param(IS_LPTIM_CLOCK_POLARITY(LPTIM_ClockPolarity));
+  
+  /* Get the LPTIMx CFGR value */
+  tmpreg1 = LPTIMx->CFGR;
+  
+  /* Clear the CKPOL bits */
+  tmpreg1 &= ~(LPTIM_CFGR_CKPOL);
+  
+  /* Set or Reset the PRESC bits */
+  tmpreg1 |= LPTIM_ClockPolarity;
+  
+  /* Write to LPTIMx CFGR */
+  LPTIMx->CFGR = tmpreg1;
+}
+
+/**
+  * @brief  Configures the Clock Prescaler.
+  * @param  LPTIMx: where x can be 1.
+  * @param  LPTIM_Prescaler: the selected clock prescaler.
+  * This parameter can be:
+  *     @arg LPTIM_Prescaler_DIV1 : Counter Clock = LPTIM Clock / 1
+  *     @arg LPTIM_Prescaler_DIV2 : Counter Clock = LPTIM Clock / 2
+  *     @arg LPTIM_Prescaler_DIV4 : Counter Clock = LPTIM Clock / 4
+  *     @arg LPTIM_Prescaler_DIV8 : Counter Clock = LPTIM Clock / 8
+  *     @arg LPTIM_Prescaler_DIV16 : Counter Clock = LPTIM Clock / 16
+  *     @arg LPTIM_Prescaler_DIV32 : Counter Clock = LPTIM Clock / 32
+  *     @arg LPTIM_Prescaler_DIV64 : Counter Clock = LPTIM Clock / 64
+  *     @arg LPTIM_Prescaler_DIV128 : Counter Clock = LPTIM Clock / 128
+  * @retval None
+  *
+  * @note   It is mandatory to disable the peripheral to use this function.
+  */
+void LPTIM_ConfigPrescaler(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Prescaler)
+{
+  uint32_t tmpreg1 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_Prescaler));
+  
+  /* Get the LPTIMx CFGR value */
+  tmpreg1 = LPTIMx->CFGR;
+  
+  /* Clear the PRESC bits */
+  tmpreg1 &= ~(LPTIM_CFGR_PRESC);
+  
+  /* Set or Reset the PRESC bits */
+  tmpreg1 |= LPTIM_Prescaler;
+  
+  /* Write to LPTIMx CFGR */
+  LPTIMx->CFGR = tmpreg1;
+}
+
+/**
+  * @brief  Selects the trigger source for the counter and its polarity.
+  * @param  LPTIMx: where x can be 1.
+  * @param  LPTIM_ExtTRGSource: the selected external trigger.
+  * This parameter can be:
+  *     @arg LPTIM_ExtTRGSource_Trig0 : ext_trig0
+  *     @arg LPTIM_ExtTRGSource_Trig1 : ext_trig1
+  *     @arg LPTIM_ExtTRGSource_Trig2 : ext_trig2
+  *     @arg LPTIM_ExtTRGSource_Trig3 : ext_trig3
+  *     @arg LPTIM_ExtTRGSource_Trig4 : ext_trig4
+  *     @arg LPTIM_ExtTRGSource_Trig5 : ext_trig5
+  *     @arg LPTIM_ExtTRGSource_Trig6 : ext_trig6
+  *     @arg LPTIM_ExtTRGSource_Trig7 : ext_trig7
+  * @param  LPTIM_ExtTRGPolarity: the selected external trigger.
+  * This parameter can be:
+  *     @arg LPTIM_ExtTRGPolarity_RisingEdge : Rising edge polarity selected
+  *     @arg LPTIM_ExtTRGPolarity_FallingEdge : Falling edge polarity selected
+  *     @arg LPTIM_ExtTRGPolarity_BothEdges : Both edges polarity selected
+  * @retval None
+  *
+  * @note   It is mandatory to disable the peripheral to use this function.
+  */
+void LPTIM_ConfigExternalTrigger(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_ExtTRGSource, uint32_t LPTIM_ExtTRGPolarity)
+{
+  uint32_t tmpreg1 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  assert_param(IS_LPTIM_EXT_TRG_SOURCE(LPTIM_ExtTRGSource));
+  assert_param(IS_LPTIM_EXT_TRG_POLARITY(LPTIM_ExtTRGPolarity));
+  
+  /* Get the LPTIMx CFGR value */
+  tmpreg1 = LPTIMx->CFGR;
+  
+  /* Clear the TRIGEN and TRIGSEL bits */
+  tmpreg1 &= CFGR_TRIG_AND_POL_CLEAR_MASK;
+  
+  /* Set or Reset the TRIGEN and TRIGSEL bits */
+  tmpreg1 |= (LPTIM_ExtTRGSource | LPTIM_ExtTRGPolarity);
+  
+  /* Write to LPTIMx CFGR */
+  LPTIMx->CFGR = tmpreg1;
+}
+
+/**
+  * @brief  Selects a software start of the counter.
+  * @param  LPTIMx: where x can be 1.
+  * @retval None
+  *
+  * @note   It is mandatory to disable the peripheral to use this function.
+  */
+void LPTIM_SelectSoftwareStart(LPTIM_TypeDef* LPTIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  
+  /* Reset the TRIGEN bits to allow a software start */
+  LPTIMx->CFGR &= ~(LPTIM_CFGR_TRIGEN);
+}
+
+/**
+  * @brief  Configures the digital filter for trigger by determining the number of consecutive
+  *         samples at the specified level to detect a correct transition.
+  * @param  LPTIMx: where x can be 1.
+  * @param  LPTIM_TrigSampleTime: the number of samples to detect a valid transition.
+  * This parameter can be:
+  *     @arg LPTIM_TrigSampleTime_DirectTransistion : Event is detected on input transitions
+  *     @arg LPTIM_TrigSampleTime_2Transistions : Event is detected after 2 consecutive samples at the active level
+  *     @arg LPTIM_TrigSampleTime_4Transistions : Event is detected after 4 consecutive samples at the active level
+  *     @arg LPTIM_TrigSampleTime_8Transistions : Event is detected after 8 consecutive samples at the active level
+  * @retval None
+  *
+  * @note   It is mandatory to disable the peripheral to use this function.
+  * @note   An auxiliary clock must be present to use this feature.
+  */
+void LPTIM_ConfigTriggerGlitchFilter(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_TrigSampleTime)
+{
+  uint32_t tmpreg1 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(LPTIM_TrigSampleTime));
+  
+  /* Get the LPTIMx CFGR value */
+  tmpreg1 = LPTIMx->CFGR;
+  
+  /* Clear the TRGFLT bits */
+  tmpreg1 &= ~(LPTIM_CFGR_TRGFLT);
+  
+  /* Set or Reset the TRGFLT bits according to LPTIM_TrigSampleTime */
+  tmpreg1 |= (LPTIM_TrigSampleTime);
+  
+  /* Write to LPTIMx CFGR */
+  LPTIMx->CFGR = tmpreg1;
+}
+
+/**
+  * @brief  Configures the digital filter for  the external clock by determining the number
+            of consecutive samples at the specified level to detect a correct transition.
+  * @param  LPTIMx: where x can be 1.
+  * @param  LPTIM_ClockSampleTime: the number of samples to detect a valid transition.
+  * This parameter can be:
+  *     @arg LPTIM_ClockSampleTime_DirectTransistion : Event is detected on input transitions
+  *     @arg LPTIM_ClockSampleTime_2Transistions : Event is detected after 2 consecutive samples at the active level
+  *     @arg LPTIM_ClockSampleTime_4Transistions : Event is detected after 4 consecutive samples at the active level
+  *     @arg LPTIM_ClockSampleTime_8Transistions : Event is detected after 8 consecutive samples at the active level
+  * @retval None
+  *
+  * @note   It is mandatory to disable the peripheral to use this function.
+  * @note   An auxiliary clock must be present to use this feature.
+  */
+void LPTIM_ConfigClockGlitchFilter(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_ClockSampleTime)
+{
+  uint32_t tmpreg1 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(LPTIM_ClockSampleTime));
+  
+  /* Get the LPTIMx CFGR value */
+  tmpreg1 = LPTIMx->CFGR;
+  
+  /* Clear the CKFLT bits */
+  tmpreg1 &= ~(LPTIM_CFGR_CKFLT);
+  
+  /* Set or Reset the CKFLT bits according to LPTIM_ClockSampleTime */
+  tmpreg1 |= LPTIM_ClockSampleTime;
+  
+  /* Write to LPTIMx CFGR */
+  LPTIMx->CFGR = tmpreg1;
+}
+
+/**
+  * @brief  Selects an operating mode.
+  * @param  LPTIMx: where x can be 1.
+  * @param  LPTIM_Mode: the selected mode.
+  * This parameter can be:
+  *     @arg LPTIM_Mode_Continuous : Timer starts in Continuous mode
+  *     @arg LPTIM_Mode_Single : Timer will starts in Single mode
+  * @retval None
+  */
+void LPTIM_SelectOperatingMode(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Mode)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  assert_param(IS_LPTIM_MODE(LPTIM_Mode));
+  
+  
+  if(LPTIM_Mode == LPTIM_Mode_Continuous)
+  {
+    /* Set the CNTSTRT to select the continuous start*/
+    LPTIMx->CR |= LPTIM_Mode_Continuous;
+  }
+  else /*LPTIM_Mode_Single */
+  {
+    /* Set the SNGSTRT to select the continuous start*/
+    LPTIMx->CR |= LPTIM_Mode_Single;
+  }
+}
+
+/**
+  * @brief  Enables or disables the Timeout function.
+  * @param  LPTIMx: where x can be 1.
+  * @param  NewState: new state of the Timeout function.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  *
+  * @note   It is mandatory to disable the peripheral to use this function.
+  */
+void LPTIM_TimoutCmd(LPTIM_TypeDef* LPTIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if(NewState != DISABLE)
+  {
+    /* Set the TIMOUT bit */
+    LPTIMx->CFGR |= LPTIM_CFGR_TIMOUT;
+  }
+  else
+  {
+    /* Reset the TIMOUT bit */
+    LPTIMx->CFGR &= ~(LPTIM_CFGR_TIMOUT);
+  }
+}
+
+/**
+  * @brief  Configures the Waveform shape.
+  * @param  LPTIMx: where x can be 1.
+  * @param  LPTIM_Waveform: the selected waveform shape.
+  * This parameter can be:
+  *     @arg LPTIM_Waveform_PWM_OnePulse : PWM/One Pulse is selected
+  *     @arg LPTIM_Waveform_SetOnce : Set once is selected
+  * @retval None
+  *
+  * @note   It is mandatory to disable the peripheral to use this function.
+  */
+void LPTIM_ConfigWaveform(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Waveform)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  assert_param(IS_LPTIM_WAVEFORM(LPTIM_Waveform));
+  
+  /* Clear the WAVE bit */
+  LPTIMx->CFGR &= ~(LPTIM_CFGR_CKFLT);
+  
+  /* Set or Reset the WAVE bit according to LPTIM_Waveform */
+  LPTIMx->CFGR |= (LPTIM_Waveform);
+}
+
+/**
+  * @brief  Configures the Autoreload and Compare registers update mode.
+  * @param  LPTIMx: where x can be 1.
+  * @param  LPTIM_Update: The selected update mode.
+  * This parameter can be:
+  *     @arg LPTIM_Update_Immediate : Registers updated after APB write
+  *     @arg LPTIM_Update_EndOfPeriod : Registers updated at the end of current timer preload
+  * @retval None
+  *
+  * @note   It is mandatory to disable the peripheral to use this function.
+  */
+void LPTIM_ConfigUpdate(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Update)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  assert_param(IS_LPTIM_UPDATE(LPTIM_Update));
+  
+  /* Clear the PRELOAD bit */
+  LPTIMx->CFGR &= ~(LPTIM_CFGR_PRELOAD);
+  
+  /* Set or Reset the PRELOAD bit according to LPTIM_Update */
+  LPTIMx->CFGR |= (LPTIM_Update);
+}
+
+/**
+  * @brief  Writes the passed parameter in the Autoreload register.
+  * @param  LPTIMx: where x can be 1.
+  * @param  LPTIM_Autoreload: The Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF
+  * @retval None
+  */
+void LPTIM_SetAutoreloadValue(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Autoreload)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  assert_param(IS_LPTIM_AUTORELOAD(LPTIM_Autoreload));
+  
+  /* Write LPTIM_Autoreload in Autoreload register */
+  LPTIMx->ARR = LPTIM_Autoreload;
+}
+
+/**
+  * @brief  Writes the passed parameter in the Compare register.
+  * @param  LPTIMx: where x can be 1.
+  * @param  LPTIM_Compare: The Compare value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF
+  * @retval None
+  */
+void LPTIM_SetCompareValue(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Compare)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  assert_param(IS_LPTIM_COMPARE(LPTIM_Compare));
+  
+  /* Write LPTIM_Compare in Compare register */
+  LPTIMx->CMP = LPTIM_Compare;
+}
+
+/**
+  * @brief  Enables or disables the Counter mode. When the Counter mode is enabled,
+  *         the counter is incremented each valid event on ULPTIM
+  * @param  LPTIMx: where x can be 1.
+  * @param  NewState: new state of the Counter mode.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  *
+  * @note   It is mandatory to disable the peripheral to use this function.
+  */
+void LPTIM_SelectCounterMode(LPTIM_TypeDef* LPTIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if(NewState != DISABLE)
+  {
+    /* Set the COUNTMODE bit */
+    LPTIMx->CFGR |= LPTIM_CFGR_COUNTMODE;
+  }
+  else
+  {
+    /* Reset the COUNTMODE bit */
+    LPTIMx->CFGR &= ~(LPTIM_CFGR_COUNTMODE);
+  }
+}
+
+/**
+  * @brief  Enables or disables the Encoder mode.
+  * @param  LPTIMx: where x can be 1.
+  * @param  NewState: New state of the encoder mode.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  *
+  * @note   It is mandatory to disable the peripheral to use this function.
+  */
+void LPTIM_SelectEncoderMode(LPTIM_TypeDef* LPTIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if(NewState != DISABLE)
+  {
+    /* Set the ENC bit */
+    LPTIMx->CFGR |= LPTIM_CFGR_ENC;
+  }
+  else
+  {
+    /* Reset the ENC bit */
+    LPTIMx->CFGR &= ~(LPTIM_CFGR_ENC);
+  }
+}
+
+/**
+  * @brief  Gets the LPTIMx counter value.
+  * @param  LPTIMx: where x can be 1.
+  * @retval Counter Register value
+  */
+uint32_t LPTIM_GetCounterValue(LPTIM_TypeDef* LPTIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  
+  /* Get the Counter Register value */
+  return LPTIMx->CNT;
+}
+
+/**
+  * @brief  Gets the LPTIMx Autoreload value.
+  * @param  LPTIMx: where x can be 1.
+  * @retval Counter Register value
+  */
+uint32_t LPTIM_GetAutoreloadValue(LPTIM_TypeDef* LPTIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  
+  /* Get the Counter Register value */
+  return LPTIMx->ARR;
+}
+
+/**
+  * @brief  Gets the LPTIMx Compare value.
+  * @param  LPTIMx: where x can be 1.
+  * @retval Counter Register value
+  */
+uint32_t LPTIM_GetCompareValue(LPTIM_TypeDef* LPTIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  
+  /* Get the Counter Register value */
+  return LPTIMx->CMP;
+}
+
+/**
+  * @brief  LPTIM Input 1 Remap.
+  * @param  LPTIMx: where x can be 1.
+  * @param  LPTIM_OPTR :
+  * This Parameter can be :
+  *    @arg LPTIM_OP_PAD_AF  : Port B5 on AF1 or Port C0 on AF1 for input timer
+  *    @arg LPTIM_OP_PAD_PA4 : Input remapped to Port A4
+  *    @arg RCC_LPTIM1CLKSOURCE_LSI : Input remapped to Port B9
+  *    @arg LPTIM_OP_TIM_DAC : Input coming from timer 6 output (for encoder mode)
+  * @retval Counter Register value
+  */
+void LPTIM_RemapConfig(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_OPTR)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  
+  /* Get the Counter Register value */
+  LPTIMx->OR = LPTIM_OPTR;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Group3 Interrupts and flags management functions
+  *  @brief    Interrupts and flags management functions
+  *
+@verbatim
+ ===============================================================================
+                  Interrupts and flags management functions
+ ===============================================================================
+  This section provides functions allowing to configure the LPTIM Interrupts, get
+  the status and clear flags bits.
+
+  The LPTIM provides 7 Flags and Interrupts sources (2 flags and Interrupt sources
+  are available only on LPTIM peripherals equipped with encoder mode interface)
+
+  Flags and Interrupts sources:
+  =============================
+  1. Compare match.
+  2. Auto-reload match.
+  3. External trigger event.
+  4. Autoreloaded register write completed.
+  5. Compare register write completed.
+  6. Direction change: from up to down [Available only for LPTIM peripheral with
+     encoder mode module]
+  7. Direction change: from down to up [Available only for LPTIM peripheral with
+     encoder mode module]
+
+  - To enable a specific interrupt source, use "LPTIM_ITConfig" function.
+  - To check if an interrupt was occurred, call "LPTIM_GetITStatus" function and read
+    the returned value.
+  - To get a flag status, call the "LPTIM_GetFlagStatus" function and read the returned
+    value.
+  - To clear a flag or an interrupt, use LPTIM_ClearFlag function with the
+    corresponding flag (interrupt).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified LPTIM interrupts.
+  * @param  LPTIMx: where x can be 1.
+  * @param  LPTIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg LPTIM_IT_DOWN: Counter direction change up to down Interrupt source
+  *            @arg LPTIM_IT_UP: Counter direction change down to up Interrupt source
+  *            @arg LPTIM_IT_ARROK: Autoreload register update OK Interrupt source
+  *            @arg LPTIM_IT_CMPOK: Compare register update OK Interrupt source
+  *            @arg LPTIM_IT_EXTTRIG: External trigger edge event Interrupt source
+  *            @arg LPTIM_IT_ARRM: Autoreload match Interrupt source
+  *            @arg LPTIM_IT_CMPM: Compare match Interrupt source
+  * @note   LPTIM_IT_DOWN is available only for LPTIM1.
+  * @note   LPTIM_IT_UP is available only for LPTIM1.
+  * @param  NewState: new state of the TIM interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  *
+  * @note   It is mandatory to disable the peripheral to use this function.
+  */
+void LPTIM_ITConfig(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_IT, FunctionalState NewState)
+ {
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  assert_param(IS_LPTIM_IT(LPTIM_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if(NewState != DISABLE)
+  {
+    /* Enable the Interrupt sources */
+    LPTIMx->IER |= LPTIM_IT;
+  }
+  else
+  {
+    /* Disable the Interrupt sources */
+    LPTIMx->IER &= ~(LPTIM_IT);
+  }
+}
+
+/**
+  * @brief  Checks whether the specified LPTIM flag is set or not.
+  * @param  LPTIMx: where x can be 1.
+  * @param  LPTIM_FLAG: specifies the flag to check.
+  *         This parameter can be any combination of the following values:
+  *            @arg LPTIM_FLAG_DOWN: Counter direction change up Flag
+  *            @arg LPTIM_FLAG_UP: Counter direction change down to up Flag
+  *            @arg LPTIM_FLAG_ARROK: Autoreload register update OK Flag
+  *            @arg LPTIM_FLAG_CMPOK: Compare register update OK Flag
+  *            @arg LPTIM_FLAG_EXTTRIG: External trigger edge event Flag
+  *            @arg LPTIM_FLAG_ARRM: Autoreload match Flag
+  *            @arg LPTIM_FLAG_CMPM: Compare match Flag
+  * @note   LPTIM_Flag_DOWN is generated only for LPTIM1.
+  * @note   LPTIM_Flag_UP is generated only for LPTIM1.
+  * @param  NewState: new state of the TIM interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+FlagStatus LPTIM_GetFlagStatus(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_FLAG)
+{
+  ITStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  assert_param(IS_LPTIM_GET_FLAG(LPTIM_FLAG));
+
+  if((LPTIMx->ISR & LPTIM_FLAG) != (RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the LPTIMx's pending flag.
+  * @param  LPTIMx: where x can be 1.
+  * @param  LPTIM_CLEARF: specifies the pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg LPTIM_CLEARF_DOWN: Counter direction change up Clear Flag
+  *            @arg LPTIM_CLEARF_UP: Counter direction change down to up Clear Flag
+  *            @arg LPTIM_CLEARF_ARROK: Autoreload register update OK Clear Flag
+  *            @arg LPTIM_CLEARF_CMPOK: Compare register update OK Clear Flag
+  *            @arg LPTIM_CLEARF_EXTTRIG: External trigger edge event Clear Flag
+  *            @arg LPTIM_CLEARF_ARRM: Autoreload match Clear Flag
+  *            @arg LPTIM_CLEARF_CMPM: Compare match Clear Flag
+  * @note   LPTIM_Flag_DOWN is generated only for LPTIM1.
+  * @note   LPTIM_Flag_UP is generated only for LPTIM1.
+  * @retval None
+  */
+void LPTIM_ClearFlag(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_CLEARF)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  assert_param(IS_LPTIM_CLEAR_FLAG(LPTIM_CLEARF));
+
+  /* Clear the IT pending Bit */
+  LPTIMx->ICR |= LPTIM_CLEARF;
+}
+
+/**
+  * @brief  Check whether the specified LPTIM interrupt has occurred or not.
+  * @param  LPTIMx: where x can be 1.
+  * @param  LPTIM_IT: specifies the LPTIM interrupt source to check.
+  *            @arg LPTIM_IT_DOWN: Counter direction change up to down Interrupt source
+  *            @arg LPTIM_IT_UP: Counter direction change down to up Interrupt source
+  *            @arg LPTIM_IT_ARROK: Autoreload register update OK Interrupt source
+  *            @arg LPTIM_IT_CMPOK: Compare register update OK Interrupt source
+  *            @arg LPTIM_IT_EXTTRIG: External trigger edge event Interrupt source
+  *            @arg LPTIM_IT_ARRM: Autoreload match Interrupt source
+  *            @arg LPTIM_IT_CMPM: Compare match Interrupt source
+  * @retval The new state of LPTIM_IT (SET or RESET).
+  */
+ITStatus LPTIM_GetITStatus(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t itstatus = 0x0, itenable = 0x0;
+
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
+  assert_param(IS_LPTIM_IT(LPTIM_IT));
+
+  /* Get the Interrupt Status bit value */
+  itstatus = LPTIMx->ISR & LPTIM_IT;
+
+  /* Check if the Interrupt is enabled */
+  itenable = LPTIMx->IER & LPTIM_IT;
+
+  if((itstatus != RESET) && (itenable != RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* STM32F410xx || STM32F413_423xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

底盘/底盘-old/底盘/Library/stm32f4xx_lptim.h

@@ -0,0 +1,378 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_lptim.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the LPTIM
+  *          firmware library
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4XX_LPTIM_H
+#define __STM32F4XX_LPTIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup LPTIM
+  * @{
+  */
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+/* Exported types ------------------------------------------------------------*/
+/**
+  * @brief   LPTIM Init structure definition
+  * @note
+  */
+typedef struct
+{
+  uint32_t LPTIM_ClockSource;          /*!< Selects the clock source.
+                                       This parameter can be a value of @ref LPTIM_Clock_Source */
+
+  uint32_t LPTIM_Prescaler;            /*!< Specifies the timer clock Prescaler.
+                                       This parameter can be a value of @ref LPTIM_Clock_Prescaler */
+
+  uint32_t LPTIM_Waveform;             /*!< Selects the output shape.
+                                       This parameter can be a value of @ref LPTIM_Waveform_Shape */
+
+  uint32_t LPTIM_OutputPolarity;       /*!< Specifies the LPTIM Output pin polarity.
+                                       This parameter can be a value of @ref LPTIM_Output_Polarity */
+}LPTIM_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Constants
+  * @{
+  */
+
+#define IS_LPTIM_ALL_PERIPH(PERIPH)                  ((PERIPH) == LPTIM1)
+
+/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
+  * @{
+  */
+
+#define LPTIM_ClockSource_APBClock_LPosc     ((uint32_t)0x00000000)
+#define LPTIM_ClockSource_ULPTIM             ((uint32_t)0x00000001)
+#define IS_LPTIM_CLOCK_SOURCE(SOURCE)        (((SOURCE) == LPTIM_ClockSource_ULPTIM) || \
+                                              ((SOURCE) == LPTIM_ClockSource_APBClock_LPosc))
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
+  * @{
+  */
+#define LPTIM_Prescaler_DIV1                 ((uint32_t)0x00000000)
+#define LPTIM_Prescaler_DIV2                 ((uint32_t)0x00000200)
+#define LPTIM_Prescaler_DIV4                 ((uint32_t)0x00000400)
+#define LPTIM_Prescaler_DIV8                 ((uint32_t)0x00000600)
+#define LPTIM_Prescaler_DIV16                ((uint32_t)0x00000800)
+#define LPTIM_Prescaler_DIV32                ((uint32_t)0x00000A00)
+#define LPTIM_Prescaler_DIV64                ((uint32_t)0x00000C00)
+#define LPTIM_Prescaler_DIV128               ((uint32_t)0x00000E00)
+#define IS_LPTIM_CLOCK_PRESCALER(PRESCALER) (((PRESCALER) == LPTIM_Prescaler_DIV1) || \
+                                             ((PRESCALER) == LPTIM_Prescaler_DIV2) || \
+                                             ((PRESCALER) == LPTIM_Prescaler_DIV4) || \
+                                             ((PRESCALER) == LPTIM_Prescaler_DIV8) || \
+                                             ((PRESCALER) == LPTIM_Prescaler_DIV16) || \
+                                             ((PRESCALER) == LPTIM_Prescaler_DIV32) || \
+                                             ((PRESCALER) == LPTIM_Prescaler_DIV64) || \
+                                             ((PRESCALER) == LPTIM_Prescaler_DIV128))  
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Waveform_Shape LPTIM Waveform Shape
+  * @{
+  */
+#define LPTIM_Waveform_PWM_OnePulse          ((uint32_t)0x00000000)
+#define LPTIM_Waveform_SetOnce               ((uint32_t)0x00100000)
+#define IS_LPTIM_WAVEFORM(WAVE)             (((WAVE) == LPTIM_Waveform_SetOnce) || \
+                                            ((WAVE) == LPTIM_Waveform_PWM_OnePulse))
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
+  * @{
+  */
+#define LPTIM_OutputPolarity_High            ((uint32_t)0x00000000)
+#define LPTIM_OutputPolarity_Low             ((uint32_t)0x00200000)
+#define IS_LPTIM_OUTPUT_POLARITY(POLARITY)   (((POLARITY) == LPTIM_OutputPolarity_Low ) || \
+                                             ((POLARITY) == LPTIM_OutputPolarity_High))
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
+  * @{
+  */
+#define LPTIM_ClockPolarity_RisingEdge        ((uint32_t)0x00000000)
+#define LPTIM_ClockPolarity_FallingEdge       ((uint32_t)0x00000002)
+#define LPTIM_ClockPolarity_BothEdges         ((uint32_t)0x00000004)
+#define IS_LPTIM_CLOCK_POLARITY(POLARITY)     (((POLARITY) == LPTIM_ClockPolarity_RisingEdge ) || \
+                                             ((POLARITY) == LPTIM_ClockPolarity_FallingEdge ) || \
+                                             ((POLARITY) == LPTIM_ClockPolarity_BothEdges))
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_External_Trigger_Source LPTIM External Trigger Source
+  * @{
+  */
+#define LPTIM_ExtTRGSource_0          ((uint32_t)0x00000000)
+#define LPTIM_ExtTRGSource_1          ((uint32_t)0x00002000)
+#define LPTIM_ExtTRGSource_2          ((uint32_t)0x00004000)
+#define LPTIM_ExtTRGSource_3          ((uint32_t)0x00006000)
+#define LPTIM_ExtTRGSource_4          ((uint32_t)0x00008000)
+#define LPTIM_ExtTRGSource_5          ((uint32_t)0x0000A000)
+#define LPTIM_ExtTRGSource_6          ((uint32_t)0x0000C000)
+#define LPTIM_ExtTRGSource_7          ((uint32_t)0x0000E000)
+#define IS_LPTIM_EXT_TRG_SOURCE(TRIG)         (((TRIG) == LPTIM_ExtTRGSource_0) || \
+                                               ((TRIG) == LPTIM_ExtTRGSource_1) || \
+                                               ((TRIG) == LPTIM_ExtTRGSource_2) || \
+                                               ((TRIG) == LPTIM_ExtTRGSource_3) || \
+                                               ((TRIG) == LPTIM_ExtTRGSource_4) || \
+                                               ((TRIG) == LPTIM_ExtTRGSource_5) || \
+                                               ((TRIG) == LPTIM_ExtTRGSource_6) || \
+                                               ((TRIG) == LPTIM_ExtTRGSource_7))
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
+  * @{
+  */
+#define LPTIM_ExtTRGPolarity_RisingEdge       ((uint32_t)0x00020000)
+#define LPTIM_ExtTRGPolarity_FallingEdge      ((uint32_t)0x00040000)
+#define LPTIM_ExtTRGPolarity_BothEdges        ((uint32_t)0x00060000)
+#define IS_LPTIM_EXT_TRG_POLARITY(POLAR)      (((POLAR) == LPTIM_ExtTRGPolarity_RisingEdge) || \
+                                               ((POLAR) == LPTIM_ExtTRGPolarity_FallingEdge) || \
+                                               ((POLAR) == LPTIM_ExtTRGPolarity_BothEdges))
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
+  * @{
+  */
+#define LPTIM_ClockSampleTime_DirectTransistion  ((uint32_t)0x00000000)
+#define LPTIM_ClockSampleTime_2Transistions      ((uint32_t)0x00000008)
+#define LPTIM_ClockSampleTime_4Transistions      ((uint32_t)0x00000010)
+#define LPTIM_ClockSampleTime_8Transistions      ((uint32_t)0x00000018)
+#define IS_LPTIM_CLOCK_SAMPLE_TIME(SAMPLETIME)   (((SAMPLETIME) == LPTIM_ClockSampleTime_DirectTransistion) || \
+                                                  ((SAMPLETIME) == LPTIM_ClockSampleTime_2Transistions) || \
+                                                  ((SAMPLETIME) == LPTIM_ClockSampleTime_4Transistions) || \
+                                                  ((SAMPLETIME) == LPTIM_ClockSampleTime_8Transistions))
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
+  * @{
+  */
+#define LPTIM_TrigSampleTime_DirectTransistion   ((uint32_t)0x00000000)
+#define LPTIM_TrigSampleTime_2Transistions       ((uint32_t)0x00000040)
+#define LPTIM_TrigSampleTime_4Transistions       ((uint32_t)0x00000080)
+#define LPTIM_TrigSampleTime_8Transistions       ((uint32_t)0x000000C0)
+#define IS_LPTIM_TRIG_SAMPLE_TIME(SAMPLETIME)    (((SAMPLETIME) == LPTIM_TrigSampleTime_DirectTransistion) || \
+                                                  ((SAMPLETIME) == LPTIM_TrigSampleTime_2Transistions) || \
+                                                  ((SAMPLETIME) == LPTIM_TrigSampleTime_4Transistions) || \
+                                                  ((SAMPLETIME) == LPTIM_TrigSampleTime_8Transistions))
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Operating_Mode LPTIM Operating Mode
+  * @{
+  */
+#define LPTIM_Mode_Continuous                    ((uint32_t)0x00000004)
+#define LPTIM_Mode_Single                        ((uint32_t)0x00000002)
+#define IS_LPTIM_MODE(MODE)                      (((MODE) == LPTIM_Mode_Continuous) || \
+                                                  ((MODE) == LPTIM_Mode_Single))
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Updating_Register LPTIM Updating Register
+  * @{
+  */
+#define LPTIM_Update_Immediate                  ((uint32_t)0x00000000)
+#define LPTIM_Update_EndOfPeriod                ((uint32_t)0x00400000)
+#define IS_LPTIM_UPDATE(UPDATE)                 (((UPDATE) == LPTIM_Update_Immediate) || \
+                                                ((UPDATE) == LPTIM_Update_EndOfPeriod))
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
+  * @{
+  */
+#define LPTIM_IT_DOWN                            LPTIM_IER_DOWNIE
+#define LPTIM_IT_UP                              LPTIM_IER_UPIE
+#define LPTIM_IT_ARROK                           LPTIM_IER_ARROKIE
+#define LPTIM_IT_CMPOK                           LPTIM_IER_CMPOKIE
+#define LPTIM_IT_EXTTRIG                         LPTIM_IER_EXTTRIGIE
+#define LPTIM_IT_ARRM                            LPTIM_IER_ARRMIE
+#define LPTIM_IT_CMPM                            LPTIM_IER_CMPMIE
+#define IS_LPTIM_IT(IT)                          (((IT) == LPTIM_IT_DOWN) || \
+                                                  ((IT) == LPTIM_IT_UP) || \
+                                                  ((IT) == LPTIM_IT_ARROK) || \
+                                                  ((IT) == LPTIM_IT_CMPOK) || \
+                                                  ((IT) == LPTIM_IT_EXTTRIG) || \
+                                                  ((IT) == LPTIM_IT_ARRM) || \
+                                                  ((IT) == LPTIM_IT_CMPM))
+
+#define IS_LPTIM_GET_IT(IT)                      (((IT) == LPTIM_IT_DOWN) || \
+                                                  ((IT) == LPTIM_IT_UP) || \
+                                                  ((IT) == LPTIM_IT_ARROK) || \
+                                                  ((IT) == LPTIM_IT_CMPOK) || \
+                                                  ((IT) == LPTIM_IT_EXTTRIG) || \
+                                                  ((IT) == LPTIM_IT_ARRM) || \
+                                                  ((IT) == LPTIM_IT_CMPM))
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Flag_Definition LPTIM Flag Definition
+  * @{
+  */
+#define LPTIM_FLAG_DOWN                          LPTIM_ISR_DOWN
+#define LPTIM_FLAG_UP                            LPTIM_ISR_UP
+#define LPTIM_FLAG_ARROK                         LPTIM_ISR_ARROK
+#define LPTIM_FLAG_CMPOK                         LPTIM_ISR_CMPOK
+#define LPTIM_FLAG_EXTTRIG                       LPTIM_ISR_EXTTRIG
+#define LPTIM_FLAG_ARRM                          LPTIM_ISR_ARRM
+#define LPTIM_FLAG_CMPM                          LPTIM_ISR_CMPM
+#define IS_LPTIM_GET_FLAG(FLAG)                 (((FLAG) == LPTIM_FLAG_DOWN) || \
+                                                 ((FLAG) == LPTIM_FLAG_UP) || \
+                                                 ((FLAG) == LPTIM_FLAG_ARROK) || \
+                                                 ((FLAG) == LPTIM_FLAG_CMPOK) || \
+                                                 ((FLAG) == LPTIM_FLAG_EXTTRIG) || \
+                                                 ((FLAG) == LPTIM_FLAG_ARRM) || \
+                                                 ((FLAG) == LPTIM_FLAG_CMPM))
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Clear_Flag_Definition LPTIM Clear Flag Definition
+  * @{
+  */
+#define LPTIM_CLEAR_DOWN                        LPTIM_ICR_DOWNCF
+#define LPTIM_CLEAR_UP                          LPTIM_ICR_UPCF
+#define LPTIM_CLEAR_ARROK                       LPTIM_ICR_ARROKCF
+#define LPTIM_CLEAR_CMPOK                       LPTIM_ICR_CMPOKCF
+#define LPTIM_CLEAR_EXTTRIG                     LPTIM_ICR_EXTTRIGCF
+#define LPTIM_CLEAR_ARRM                        LPTIM_ICR_ARRMCF
+#define LPTIM_CLEAR_CMPM                        LPTIM_ICR_CMPMCF
+#define IS_LPTIM_CLEAR_FLAG(CLEARF)              (((CLEARF) == LPTIM_CLEAR_DOWN) || \
+                                                  ((CLEARF) == LPTIM_CLEAR_UP) || \
+                                                  ((CLEARF) == LPTIM_CLEAR_ARROK) || \
+                                                  ((CLEARF) == LPTIM_CLEAR_CMPOK) || \
+                                                  ((CLEARF) == LPTIM_CLEAR_EXTTRIG) || \
+                                                  ((CLEARF) == LPTIM_CLEAR_ARRM ) || \
+                                                  ((CLEARF) == LPTIM_CLEAR_CMPM))
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Autorelaod_Value LPTIM Autorelaod Value
+  * @{
+  */
+#define IS_LPTIM_AUTORELOAD(AUTORELOAD)         ((AUTORELOAD) <= 0x0000FFFF)
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Compare_Value LPTIM Compare Value
+  * @{
+  */
+#define IS_LPTIM_COMPARE(COMPARE)               ((COMPARE) <= 0x0000FFFF)
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Option_Register_Definition LPTIM Option Register Definition
+  * @{
+  */
+#define LPTIM_OP_PAD_AF                          ((uint32_t)0x00000000)
+#define LPTIM_OP_PAD_PA4                         LPTIM_OR_OR_0
+#define LPTIM_OP_PAD_PB9                         LPTIM_OR_OR_1
+#define LPTIM_OP_TIM_DAC                         LPTIM_OR_OR
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Initialization functions ***************************************************/
+void LPTIM_DeInit(LPTIM_TypeDef* LPTIMx);
+void LPTIM_Init(LPTIM_TypeDef* LPTIMx, LPTIM_InitTypeDef* LPTIM_InitStruct);
+void LPTIM_StructInit(LPTIM_InitTypeDef* LPTIM_InitStruct);
+
+/* Configuration functions ****************************************************/
+void LPTIM_Cmd(LPTIM_TypeDef* LPTIMx, FunctionalState NewState);
+void LPTIM_SelectClockSource(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_ClockSource);
+void LPTIM_SelectULPTIMClockPolarity(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_ClockPolarity);
+void LPTIM_ConfigPrescaler(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Prescaler);
+void LPTIM_ConfigExternalTrigger(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_ExtTRGSource, uint32_t LPTIM_ExtTRGPolarity);
+void LPTIM_SelectSoftwareStart(LPTIM_TypeDef* LPTIMx);
+void LPTIM_ConfigTriggerGlitchFilter(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_TrigSampleTime);
+void LPTIM_ConfigClockGlitchFilter(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_ClockSampleTime);
+void LPTIM_SelectOperatingMode(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Mode);
+void LPTIM_TimoutCmd(LPTIM_TypeDef* LPTIMx, FunctionalState NewState);
+void LPTIM_ConfigWaveform(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Waveform);
+void LPTIM_ConfigUpdate(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Update);
+void LPTIM_SetAutoreloadValue(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Autoreload);
+void LPTIM_SetCompareValue(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Compare);
+void LPTIM_SelectCounterMode(LPTIM_TypeDef* LPTIMx, FunctionalState NewState);
+void LPTIM_SelectEncoderMode(LPTIM_TypeDef* LPTIMx, FunctionalState NewState);
+void LPTIM_RemapConfig(LPTIM_TypeDef* LPTIMx,uint32_t LPTIM_OPTR);
+uint32_t LPTIM_GetCounterValue(LPTIM_TypeDef* LPTIMx);
+uint32_t LPTIM_GetAutoreloadValue(LPTIM_TypeDef* LPTIMx); 
+uint32_t LPTIM_GetCompareValue(LPTIM_TypeDef* LPTIMx);
+
+/* Interrupts and flags management functions **********************************/
+void LPTIM_ITConfig(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_IT, FunctionalState NewState);
+FlagStatus LPTIM_GetFlagStatus(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_FLAG);
+void LPTIM_ClearFlag(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_CLEARF);
+ITStatus LPTIM_GetITStatus(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_IT);
+
+#endif /* STM32F410xx || STM32F413_423xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_LPTIM_H */
+

底盘/底盘-old/底盘/Library/stm32f4xx_ltdc.h

@@ -0,0 +1,495 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ltdc.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the LTDC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LTDC_H
+#define __STM32F4xx_LTDC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup LTDC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+ 
+/** 
+  * @brief  LTDC Init structure definition  
+  */
+
+typedef struct
+{
+  uint32_t LTDC_HSPolarity;                 /*!< configures the horizontal synchronization polarity.
+                                                 This parameter can be one value of @ref LTDC_HSPolarity */
+
+  uint32_t LTDC_VSPolarity;                 /*!< configures the vertical synchronization polarity.
+                                                 This parameter can be one value of @ref LTDC_VSPolarity */
+
+  uint32_t LTDC_DEPolarity;                 /*!< configures the data enable polarity. This parameter can
+                                                 be one of value of @ref LTDC_DEPolarity */
+
+  uint32_t LTDC_PCPolarity;                 /*!< configures the pixel clock polarity. This parameter can
+                                                 be one of value of @ref LTDC_PCPolarity */
+
+  uint32_t LTDC_HorizontalSync;             /*!< configures the number of Horizontal synchronization 
+                                                 width. This parameter must range from 0x000 to 0xFFF. */
+
+  uint32_t LTDC_VerticalSync;               /*!< configures the number of Vertical synchronization 
+                                                 height. This parameter must range from 0x000 to 0x7FF. */
+
+  uint32_t LTDC_AccumulatedHBP;             /*!< configures the accumulated horizontal back porch width.
+                                                 This parameter must range from LTDC_HorizontalSync to 0xFFF. */
+
+  uint32_t LTDC_AccumulatedVBP;             /*!< configures the accumulated vertical back porch height.
+                                                 This parameter must range from LTDC_VerticalSync to 0x7FF. */
+            
+  uint32_t LTDC_AccumulatedActiveW;         /*!< configures the accumulated active width. This parameter 
+                                                 must range from LTDC_AccumulatedHBP to 0xFFF. */
+
+  uint32_t LTDC_AccumulatedActiveH;         /*!< configures the accumulated active height. This parameter 
+                                                 must range from LTDC_AccumulatedVBP to 0x7FF. */
+
+  uint32_t LTDC_TotalWidth;                 /*!< configures the total width. This parameter 
+                                                 must range from LTDC_AccumulatedActiveW to 0xFFF. */
+
+  uint32_t LTDC_TotalHeigh;                 /*!< configures the total height. This parameter 
+                                                 must range from LTDC_AccumulatedActiveH to 0x7FF. */
+            
+  uint32_t LTDC_BackgroundRedValue;         /*!< configures the background red value.
+                                                 This parameter must range from 0x00 to 0xFF. */
+
+  uint32_t LTDC_BackgroundGreenValue;       /*!< configures the background green value.
+                                                 This parameter must range from 0x00 to 0xFF. */ 
+
+   uint32_t LTDC_BackgroundBlueValue;       /*!< configures the background blue value.
+                                                 This parameter must range from 0x00 to 0xFF. */
+} LTDC_InitTypeDef;
+
+/** 
+  * @brief  LTDC Layer structure definition  
+  */
+
+typedef struct
+{
+  uint32_t LTDC_HorizontalStart;            /*!< Configures the Window Horizontal Start Position.
+                                                 This parameter must range from 0x000 to 0xFFF. */
+            
+  uint32_t LTDC_HorizontalStop;             /*!< Configures the Window Horizontal Stop Position.
+                                                 This parameter must range from 0x0000 to 0xFFFF. */
+  
+  uint32_t LTDC_VerticalStart;              /*!< Configures the Window vertical Start Position.
+                                                 This parameter must range from 0x000 to 0xFFF. */
+
+  uint32_t LTDC_VerticalStop;               /*!< Configures the Window vaertical Stop Position.
+                                                 This parameter must range from 0x0000 to 0xFFFF. */
+  
+  uint32_t LTDC_PixelFormat;                /*!< Specifies the pixel format. This parameter can be 
+                                                 one of value of @ref LTDC_Pixelformat */
+
+  uint32_t LTDC_ConstantAlpha;              /*!< Specifies the constant alpha used for blending.
+                                                 This parameter must range from 0x00 to 0xFF. */
+
+  uint32_t LTDC_DefaultColorBlue;           /*!< Configures the default blue value.
+                                                 This parameter must range from 0x00 to 0xFF. */
+
+  uint32_t LTDC_DefaultColorGreen;          /*!< Configures the default green value.
+                                                 This parameter must range from 0x00 to 0xFF. */
+            
+  uint32_t LTDC_DefaultColorRed;            /*!< Configures the default red value.
+                                                 This parameter must range from 0x00 to 0xFF. */
+
+  uint32_t LTDC_DefaultColorAlpha;          /*!< Configures the default alpha value.
+                                                 This parameter must range from 0x00 to 0xFF. */
+
+  uint32_t LTDC_BlendingFactor_1;           /*!< Select the blending factor 1. This parameter 
+                                                 can be one of value of @ref LTDC_BlendingFactor1 */
+
+  uint32_t LTDC_BlendingFactor_2;           /*!< Select the blending factor 2. This parameter 
+                                                 can be one of value of @ref LTDC_BlendingFactor2 */
+            
+  uint32_t LTDC_CFBStartAdress;             /*!< Configures the color frame buffer address */
+
+  uint32_t LTDC_CFBLineLength;              /*!< Configures the color frame buffer line length. 
+                                                 This parameter must range from 0x0000 to 0x1FFF. */
+
+  uint32_t LTDC_CFBPitch;                   /*!< Configures the color frame buffer pitch in bytes.
+                                                 This parameter must range from 0x0000 to 0x1FFF. */
+                                                 
+  uint32_t LTDC_CFBLineNumber;              /*!< Specifies the number of line in frame buffer. 
+                                                 This parameter must range from 0x000 to 0x7FF. */
+} LTDC_Layer_InitTypeDef;
+
+/** 
+  * @brief  LTDC Position structure definition  
+  */
+typedef struct
+{
+  uint32_t LTDC_POSX;                         /*!<  Current X Position */
+  uint32_t LTDC_POSY;                         /*!<  Current Y Position */
+} LTDC_PosTypeDef;
+
+/** 
+  * @brief  LTDC RGB structure definition  
+  */
+typedef struct
+{
+  uint32_t LTDC_BlueWidth;                        /*!< Blue width */
+  uint32_t LTDC_GreenWidth;                       /*!< Green width */
+  uint32_t LTDC_RedWidth;                         /*!< Red width */
+} LTDC_RGBTypeDef;
+
+/** 
+  * @brief  LTDC Color Keying structure definition  
+  */
+typedef struct
+{
+  uint32_t LTDC_ColorKeyBlue;               /*!< Configures the color key blue value. 
+                                                 This parameter must range from 0x00 to 0xFF. */
+
+  uint32_t LTDC_ColorKeyGreen;              /*!< Configures the color key green value. 
+                                                 This parameter must range from 0x00 to 0xFF. */
+            
+  uint32_t LTDC_ColorKeyRed;                /*!< Configures the color key red value. 
+                                                 This parameter must range from 0x00 to 0xFF. */
+} LTDC_ColorKeying_InitTypeDef;
+
+/** 
+  * @brief  LTDC CLUT structure definition  
+  */
+typedef struct
+{
+  uint32_t LTDC_CLUTAdress;                 /*!< Configures the CLUT address.
+                                                 This parameter must range from 0x00 to 0xFF. */
+
+  uint32_t LTDC_BlueValue;                  /*!< Configures the blue value. 
+                                                 This parameter must range from 0x00 to 0xFF. */
+                                                 
+  uint32_t LTDC_GreenValue;                 /*!< Configures the green value. 
+                                                 This parameter must range from 0x00 to 0xFF. */
+
+  uint32_t LTDC_RedValue;                   /*!< Configures the red value.
+                                                 This parameter must range from 0x00 to 0xFF. */
+} LTDC_CLUT_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LTDC_Exported_Constants
+  * @{
+  */
+  
+/** @defgroup LTDC_SYNC 
+  * @{
+  */
+
+#define LTDC_HorizontalSYNC               ((uint32_t)0x00000FFF)
+#define LTDC_VerticalSYNC                 ((uint32_t)0x000007FF)
+
+#define IS_LTDC_HSYNC(HSYNC) ((HSYNC) <= LTDC_HorizontalSYNC)
+#define IS_LTDC_VSYNC(VSYNC) ((VSYNC) <= LTDC_VerticalSYNC)
+#define IS_LTDC_AHBP(AHBP)  ((AHBP) <= LTDC_HorizontalSYNC)
+#define IS_LTDC_AVBP(AVBP) ((AVBP) <= LTDC_VerticalSYNC)
+#define IS_LTDC_AAW(AAW)   ((AAW) <= LTDC_HorizontalSYNC)
+#define IS_LTDC_AAH(AAH) ((AAH) <= LTDC_VerticalSYNC)
+#define IS_LTDC_TOTALW(TOTALW) ((TOTALW) <= LTDC_HorizontalSYNC)
+#define IS_LTDC_TOTALH(TOTALH) ((TOTALH) <= LTDC_VerticalSYNC)
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_HSPolarity 
+  * @{
+  */
+#define LTDC_HSPolarity_AL                ((uint32_t)0x00000000)                /*!< Horizontal Synchronization is active low. */
+#define LTDC_HSPolarity_AH                LTDC_GCR_HSPOL                        /*!< Horizontal Synchronization is active high. */
+
+#define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPolarity_AL) || \
+                              ((HSPOL) == LTDC_HSPolarity_AH))
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_VSPolarity 
+  * @{
+  */
+#define LTDC_VSPolarity_AL                ((uint32_t)0x00000000)                /*!< Vertical Synchronization is active low. */
+#define LTDC_VSPolarity_AH                LTDC_GCR_VSPOL                        /*!< Vertical Synchronization is active high. */
+
+#define IS_LTDC_VSPOL(VSPOL) (((VSPOL) == LTDC_VSPolarity_AL) || \
+                              ((VSPOL) == LTDC_VSPolarity_AH))  
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_DEPolarity 
+  * @{
+  */
+#define LTDC_DEPolarity_AL                ((uint32_t)0x00000000)                /*!< Data Enable, is active low. */
+#define LTDC_DEPolarity_AH                LTDC_GCR_DEPOL                        /*!< Data Enable, is active high. */
+
+#define IS_LTDC_DEPOL(DEPOL) (((DEPOL) ==  LTDC_VSPolarity_AL) || \
+                              ((DEPOL) ==  LTDC_DEPolarity_AH))
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_PCPolarity 
+  * @{
+  */
+#define LTDC_PCPolarity_IPC               ((uint32_t)0x00000000)                /*!< input pixel clock. */
+#define LTDC_PCPolarity_IIPC              LTDC_GCR_PCPOL                        /*!< inverted input pixel clock. */
+
+#define IS_LTDC_PCPOL(PCPOL) (((PCPOL) ==  LTDC_PCPolarity_IPC) || \
+                              ((PCPOL) ==  LTDC_PCPolarity_IIPC))
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Reload 
+  * @{
+  */
+#define LTDC_IMReload                     LTDC_SRCR_IMR                         /*!< Immediately Reload. */
+#define LTDC_VBReload                     LTDC_SRCR_VBR                         /*!< Vertical Blanking Reload. */
+
+#define IS_LTDC_RELOAD(RELOAD) (((RELOAD) == LTDC_IMReload) || \
+                                ((RELOAD) == LTDC_VBReload))
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Back_Color
+  * @{
+  */
+#define LTDC_Back_Color                   ((uint32_t)0x000000FF)
+
+#define IS_LTDC_BackBlueValue(BBLUE)    ((BBLUE) <= LTDC_Back_Color)
+#define IS_LTDC_BackGreenValue(BGREEN)  ((BGREEN) <= LTDC_Back_Color)
+#define IS_LTDC_BackRedValue(BRED)      ((BRED) <= LTDC_Back_Color) 
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Position 
+  * @{
+  */
+#define LTDC_POS_CY                       LTDC_CPSR_CYPOS
+#define LTDC_POS_CX                       LTDC_CPSR_CXPOS
+
+#define IS_LTDC_GET_POS(POS) (((POS) <= LTDC_POS_CY))
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_LIPosition 
+  * @{
+  */
+#define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF)
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_CurrentStatus 
+  * @{
+  */
+#define LTDC_CD_VDES                     LTDC_CDSR_VDES
+#define LTDC_CD_HDES                     LTDC_CDSR_HDES
+#define LTDC_CD_VSYNC                    LTDC_CDSR_VSYNCS
+#define LTDC_CD_HSYNC                    LTDC_CDSR_HSYNCS
+
+#define IS_LTDC_GET_CD(CD) (((CD) == LTDC_CD_VDES) || ((CD) == LTDC_CD_HDES) || \
+                              ((CD) == LTDC_CD_VSYNC) || ((CD) == LTDC_CD_HSYNC))
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Interrupts 
+  * @{
+  */
+#define LTDC_IT_LI                      LTDC_IER_LIE
+#define LTDC_IT_FU                      LTDC_IER_FUIE
+#define LTDC_IT_TERR                    LTDC_IER_TERRIE
+#define LTDC_IT_RR                      LTDC_IER_RRIE
+
+#define IS_LTDC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF0) == 0x00) && ((IT) != 0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Flag 
+  * @{
+  */
+#define LTDC_FLAG_LI                     LTDC_ISR_LIF
+#define LTDC_FLAG_FU                     LTDC_ISR_FUIF
+#define LTDC_FLAG_TERR                   LTDC_ISR_TERRIF
+#define LTDC_FLAG_RR                     LTDC_ISR_RRIF
+
+#define IS_LTDC_FLAG(FLAG) (((FLAG) == LTDC_FLAG_LI) || ((FLAG) == LTDC_FLAG_FU) || \
+                               ((FLAG) == LTDC_FLAG_TERR) || ((FLAG) == LTDC_FLAG_RR))
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Pixelformat 
+  * @{
+  */
+#define LTDC_Pixelformat_ARGB8888                  ((uint32_t)0x00000000)
+#define LTDC_Pixelformat_RGB888                    ((uint32_t)0x00000001)
+#define LTDC_Pixelformat_RGB565                    ((uint32_t)0x00000002)
+#define LTDC_Pixelformat_ARGB1555                  ((uint32_t)0x00000003)
+#define LTDC_Pixelformat_ARGB4444                  ((uint32_t)0x00000004)
+#define LTDC_Pixelformat_L8                        ((uint32_t)0x00000005)
+#define LTDC_Pixelformat_AL44                      ((uint32_t)0x00000006)
+#define LTDC_Pixelformat_AL88                      ((uint32_t)0x00000007)
+
+#define IS_LTDC_Pixelformat(Pixelformat) (((Pixelformat) == LTDC_Pixelformat_ARGB8888) || ((Pixelformat) == LTDC_Pixelformat_RGB888)   || \
+                        ((Pixelformat) == LTDC_Pixelformat_RGB565)   || ((Pixelformat) == LTDC_Pixelformat_ARGB1555) || \
+                        ((Pixelformat) == LTDC_Pixelformat_ARGB4444) || ((Pixelformat) == LTDC_Pixelformat_L8)       || \
+                        ((Pixelformat) == LTDC_Pixelformat_AL44)     || ((Pixelformat) == LTDC_Pixelformat_AL88))
+
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_BlendingFactor1 
+  * @{
+  */
+#define LTDC_BlendingFactor1_CA                       ((uint32_t)0x00000400)
+#define LTDC_BlendingFactor1_PAxCA                    ((uint32_t)0x00000600)
+
+#define IS_LTDC_BlendingFactor1(BlendingFactor1) (((BlendingFactor1) == LTDC_BlendingFactor1_CA) || ((BlendingFactor1) == LTDC_BlendingFactor1_PAxCA))
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_BlendingFactor2
+  * @{
+  */
+#define LTDC_BlendingFactor2_CA                       ((uint32_t)0x00000005)
+#define LTDC_BlendingFactor2_PAxCA                    ((uint32_t)0x00000007)
+
+#define IS_LTDC_BlendingFactor2(BlendingFactor2) (((BlendingFactor2) == LTDC_BlendingFactor2_CA) || ((BlendingFactor2) == LTDC_BlendingFactor2_PAxCA))
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_LAYER_Config
+  * @{
+  */
+#define LTDC_STOPPosition                 ((uint32_t)0x0000FFFF)
+#define LTDC_STARTPosition                ((uint32_t)0x00000FFF)
+
+#define LTDC_DefaultColorConfig           ((uint32_t)0x000000FF)
+#define LTDC_ColorFrameBuffer             ((uint32_t)0x00001FFF)
+#define LTDC_LineNumber                   ((uint32_t)0x000007FF)
+
+#define IS_LTDC_HCONFIGST(HCONFIGST) ((HCONFIGST) <= LTDC_STARTPosition)
+#define IS_LTDC_HCONFIGSP(HCONFIGSP) ((HCONFIGSP) <= LTDC_STOPPosition)
+#define IS_LTDC_VCONFIGST(VCONFIGST)  ((VCONFIGST) <= LTDC_STARTPosition)
+#define IS_LTDC_VCONFIGSP(VCONFIGSP) ((VCONFIGSP) <= LTDC_STOPPosition)
+
+#define IS_LTDC_DEFAULTCOLOR(DEFAULTCOLOR) ((DEFAULTCOLOR) <= LTDC_DefaultColorConfig)
+
+#define IS_LTDC_CFBP(CFBP) ((CFBP) <= LTDC_ColorFrameBuffer)
+#define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_ColorFrameBuffer)
+
+#define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LineNumber)
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_colorkeying_Config
+  * @{
+  */
+#define LTDC_colorkeyingConfig            ((uint32_t)0x000000FF)
+
+#define IS_LTDC_CKEYING(CKEYING) ((CKEYING) <= LTDC_colorkeyingConfig)
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_CLUT_Config
+  * @{
+  */
+
+#define LTDC_CLUTWR                       ((uint32_t)0x000000FF)
+
+#define IS_LTDC_CLUTWR(CLUTWR)  ((CLUTWR) <= LTDC_CLUTWR)
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/*  Function used to set the LTDC configuration to the default reset state *****/
+void LTDC_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void LTDC_Init(LTDC_InitTypeDef* LTDC_InitStruct);
+void LTDC_StructInit(LTDC_InitTypeDef* LTDC_InitStruct);
+void LTDC_Cmd(FunctionalState NewState);
+void LTDC_DitherCmd(FunctionalState NewState);
+LTDC_RGBTypeDef LTDC_GetRGBWidth(void);
+void LTDC_RGBStructInit(LTDC_RGBTypeDef* LTDC_RGB_InitStruct);
+void LTDC_LIPConfig(uint32_t LTDC_LIPositionConfig);
+void LTDC_ReloadConfig(uint32_t LTDC_Reload);
+void LTDC_LayerInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_Layer_InitTypeDef* LTDC_Layer_InitStruct);
+void LTDC_LayerStructInit(LTDC_Layer_InitTypeDef * LTDC_Layer_InitStruct);
+void LTDC_LayerCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState);
+LTDC_PosTypeDef LTDC_GetPosStatus(void);
+void LTDC_PosStructInit(LTDC_PosTypeDef* LTDC_Pos_InitStruct);
+FlagStatus LTDC_GetCDStatus(uint32_t LTDC_CD);
+void LTDC_ColorKeyingConfig(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct, FunctionalState NewState);
+void LTDC_ColorKeyingStructInit(LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct);
+void LTDC_CLUTCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState);
+void LTDC_CLUTInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct);
+void LTDC_CLUTStructInit(LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct);
+void LTDC_LayerPosition(LTDC_Layer_TypeDef* LTDC_Layerx, uint16_t OffsetX, uint16_t OffsetY);
+void LTDC_LayerAlpha(LTDC_Layer_TypeDef* LTDC_Layerx, uint8_t ConstantAlpha);
+void LTDC_LayerAddress(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Address);
+void LTDC_LayerSize(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Width, uint32_t Height);
+void LTDC_LayerPixelFormat(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t PixelFormat);
+
+/* Interrupts and flags management functions **********************************/
+void LTDC_ITConfig(uint32_t LTDC_IT, FunctionalState NewState);
+FlagStatus LTDC_GetFlagStatus(uint32_t LTDC_FLAG);
+void LTDC_ClearFlag(uint32_t LTDC_FLAG);
+ITStatus LTDC_GetITStatus(uint32_t LTDC_IT);
+void LTDC_ClearITPendingBit(uint32_t LTDC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LTDC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

底盘/底盘-old/底盘/Library/stm32f4xx_pwr.h

@@ -0,0 +1,237 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_pwr.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the PWR firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_PWR_H
+#define __STM32F4xx_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup PWR_PVD_detection_level 
+  * @{
+  */ 
+#define PWR_PVDLevel_0                  PWR_CR_PLS_LEV0
+#define PWR_PVDLevel_1                  PWR_CR_PLS_LEV1
+#define PWR_PVDLevel_2                  PWR_CR_PLS_LEV2
+#define PWR_PVDLevel_3                  PWR_CR_PLS_LEV3
+#define PWR_PVDLevel_4                  PWR_CR_PLS_LEV4
+#define PWR_PVDLevel_5                  PWR_CR_PLS_LEV5
+#define PWR_PVDLevel_6                  PWR_CR_PLS_LEV6
+#define PWR_PVDLevel_7                  PWR_CR_PLS_LEV7
+
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
+                                 ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
+                                 ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
+                                 ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
+/**
+  * @}
+  */
+
+  
+/** @defgroup PWR_Regulator_state_in_STOP_mode 
+  * @{
+  */
+#define PWR_MainRegulator_ON                        ((uint32_t)0x00000000)
+#define PWR_LowPowerRegulator_ON                    PWR_CR_LPDS
+
+/* --- PWR_Legacy ---*/
+#define PWR_Regulator_ON                            PWR_MainRegulator_ON
+#define PWR_Regulator_LowPower                      PWR_LowPowerRegulator_ON
+
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MainRegulator_ON) || \
+                                     ((REGULATOR) == PWR_LowPowerRegulator_ON))
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Regulator_state_in_UnderDrive_mode 
+  * @{
+  */
+#define PWR_MainRegulator_UnderDrive_ON               PWR_CR_MRUDS
+#define PWR_LowPowerRegulator_UnderDrive_ON           ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
+
+#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MainRegulator_UnderDrive_ON) || \
+                                                ((REGULATOR) == PWR_LowPowerRegulator_UnderDrive_ON))
+
+/**
+  * @}
+  */
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+/** @defgroup PWR_Wake_Up_Pin
+  * @{
+  */
+#define PWR_WakeUp_Pin1           ((uint32_t)0x00)
+#define PWR_WakeUp_Pin2           ((uint32_t)0x01)
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+#define PWR_WakeUp_Pin3           ((uint32_t)0x02)
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */
+
+#if defined(STM32F446xx)
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUp_Pin1) || \
+                                ((PIN) == PWR_WakeUp_Pin2))
+#else /* STM32F410xx || STM32F412xG */
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUp_Pin1) || ((PIN) == PWR_WakeUp_Pin2) || \
+                                ((PIN) == PWR_WakeUp_Pin3)) 
+#endif /* STM32F446xx */
+/**
+  * @}
+  */    
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
+
+/** @defgroup PWR_STOP_mode_entry 
+  * @{
+  */
+#define PWR_STOPEntry_WFI               ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE               ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Regulator_Voltage_Scale 
+  * @{
+  */
+#define PWR_Regulator_Voltage_Scale1    ((uint32_t)0x0000C000)
+#define PWR_Regulator_Voltage_Scale2    ((uint32_t)0x00008000)
+#define PWR_Regulator_Voltage_Scale3    ((uint32_t)0x00004000)
+#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || \
+                                           ((VOLTAGE) == PWR_Regulator_Voltage_Scale2) || \
+                                           ((VOLTAGE) == PWR_Regulator_Voltage_Scale3))
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag 
+  * @{
+  */
+#define PWR_FLAG_WU                     PWR_CSR_WUF
+#define PWR_FLAG_SB                     PWR_CSR_SBF
+#define PWR_FLAG_PVDO                   PWR_CSR_PVDO
+#define PWR_FLAG_BRR                    PWR_CSR_BRR
+#define PWR_FLAG_VOSRDY                 PWR_CSR_VOSRDY
+#define PWR_FLAG_ODRDY                  PWR_CSR_ODRDY
+#define PWR_FLAG_ODSWRDY                PWR_CSR_ODSWRDY
+#define PWR_FLAG_UDRDY                  PWR_CSR_UDSWRDY
+
+/* --- FLAG Legacy ---*/
+#define PWR_FLAG_REGRDY                  PWR_FLAG_VOSRDY               
+
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+                               ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \
+                               ((FLAG) == PWR_FLAG_VOSRDY) || ((FLAG) == PWR_FLAG_ODRDY) || \
+                               ((FLAG) == PWR_FLAG_ODSWRDY) || ((FLAG) == PWR_FLAG_UDRDY))
+
+
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+                                 ((FLAG) == PWR_FLAG_UDRDY))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/* Function used to set the PWR configuration to the default reset state ******/ 
+void PWR_DeInit(void);
+
+/* Backup Domain Access function **********************************************/ 
+void PWR_BackupAccessCmd(FunctionalState NewState);
+
+/* PVD configuration functions ************************************************/ 
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_PVDCmd(FunctionalState NewState);
+
+/* WakeUp pins configuration functions ****************************************/
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
+void PWR_WakeUpPinCmd(FunctionalState NewState);
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) ||defined(STM32F446xx)
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPinx, FunctionalState NewState);
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
+/* Main and Backup Regulators configuration functions *************************/ 
+void PWR_BackupRegulatorCmd(FunctionalState NewState);
+void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage);
+void PWR_OverDriveCmd(FunctionalState NewState);
+void PWR_OverDriveSWCmd(FunctionalState NewState);
+void PWR_UnderDriveCmd(FunctionalState NewState);
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
+void PWR_MainRegulatorUnderDriveCmd(FunctionalState NewState);
+void PWR_LowRegulatorUnderDriveCmd(FunctionalState NewState);
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx */
+
+#if defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG) || defined(STM32F413_423xx)
+void PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState);
+void PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState);
+#endif /* STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG || STM32F413_423xx */
+
+/* FLASH Power Down configuration functions ***********************************/ 
+void PWR_FlashPowerDownCmd(FunctionalState NewState);
+
+/* Low Power modes configuration functions ************************************/ 
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+
+/* Flags management functions *************************************************/ 
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_PWR_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

底盘/底盘-old/底盘/Library/stm32f4xx_qspi.c

@@ -0,0 +1,903 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_qspi.c
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Serial peripheral interface (QSPI):
+  *           + Initialization and Configuration
+  *           + Indirect Data Read/Write functions
+  *           + Memory Mapped Mode Data Read functions  
+  *           + Automatic Polling functions
+  *           + DMA transfers management
+  *           + Interrupts and flags management 
+  *
+  *  @verbatim
+  *
+ ===============================================================================
+                       ##### How to use this driver #####
+ ===============================================================================
+    [..]
+        (#) Enable peripheral clock using   RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_QSPI,ENABLE);
+            function.
+
+        (#) Enable CLK, BK1_IO0, BK1_IO1, BK1_IO2, BK1_IO3, BK1_NCS, BK2_IO0, 
+            BK2_IO1, BK2_IO2, BK2_IO3 and BK2_NCS GPIO clocks using 
+            RCC_AHB1PeriphClockCmd() function. 
+  
+        (#) Peripherals alternate function: 
+           (++) Connect the pin to the desired peripherals' Alternate 
+                 Function (AF) using GPIO_PinAFConfig() function.
+           (++) Configure the desired pin in alternate function by:
+                 GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
+           (++) Select the type, pull-up/pull-down and output speed via 
+                 GPIO_PuPd, GPIO_OType and GPIO_Speed members.
+           (++) Call GPIO_Init() function.
+  
+        (#) Program the Flash Size, CS High Time, Sample Shift, Prescaler, Clock Mode 
+            values using the QSPI_Init() function.
+            
+        (#) Enable QSPI using  QSPI_Cmd() function.
+        
+        (#) Set QSPI Data Length using QSPI_SetDataLength() function.
+  
+        (#) Configure the FIFO threshold using QSPI_SetFIFOThreshold() to select 
+            at which threshold the FTF event is generated.
+
+        (#) Enable the NVIC and the corresponding interrupt using the function 
+            QSPI_ITConfig() if you need to use interrupt mode. 
+  
+        (#) When using the DMA mode 
+           (++) Configure the DMA using DMA_Init() function.
+           (++) Active the needed channel Request using SPI_I2S_DMACmd() function.
+   
+        (#) Enable the SPI using the QSPI_DMACmd() function.
+   
+        (#) Enable the DMA using the DMA_Cmd() function when using DMA mode.  
+  
+    @endverbatim 
+   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_qspi.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup QSPI
+  * @brief QSPI driver modules
+  * @{
+  */
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define QSPI_CR_CLEAR_MASK                           0x00FFFFCF
+#define QSPI_DCR_CLEAR_MASK                          0xFFE0F7FE
+#define QSPI_CCR_CLEAR_MASK                          0x90800000
+#define QSPI_PIR_CLEAR_MASK                          0xFFFF0000
+#define QSPI_LPTR_CLEAR_MASK                         0xFFFF0000
+#define QSPI_CCR_CLEAR_INSTRUCTION_MASK              0xFFFFFF00
+#define QSPI_CCR_CLEAR_DCY_MASK                      0xFFC3FFFF
+#define QSPI_CR_CLEAR_FIFOTHRESHOLD_MASK             0xFFFFF0FF
+#define QSPI_CR_INTERRUPT_MASK                       0x001F0000
+#define QSPI_SR_INTERRUPT_MASK                       0x0000001F
+#define QSPI_FSR_INTERRUPT_MASK                      0x0000001B
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/* Initialization and Configuration functions *********************************/
+
+/** @defgroup <PPP>_Private_Functions 
+  * @{
+  */
+
+/** @defgroup <PPP>_Group1 Function Group1 Name
+ *  @brief   Function group1 name description (copied from the header file) 
+ *
+@verbatim  
+ ===============================================================================
+     ##### < Function group1 name (copied from the header file)
+ Note: do not use "Peripheral" or "PPP" word in the function group name >  #####
+ ===============================================================================
+
+       [..] < OPTIONAL:
+              Add here the most important information to know about the IP features
+              covered by this group of function.
+        
+              For system IPs, this section contains how to use this group API.
+            >
+
+@endverbatim
+  * @{
+  */   
+
+/**
+  * @brief  Deinitializes the QSPI peripheral registers to their default
+  *         reset values.
+  * @param  None
+  * @retval None
+  */
+void QSPI_DeInit(void)
+{
+  /* Enable QSPI reset state */
+  RCC_AHB3PeriphResetCmd(RCC_AHB3Periph_QSPI, ENABLE);
+  /* Release QSPI from reset state */
+  RCC_AHB3PeriphResetCmd(RCC_AHB3Periph_QSPI, DISABLE);
+}
+
+/**
+  * @brief  Fills each QSPI_InitStruct member with its default value.
+  * @param  QSPI_InitStruct: pointer to a QSPI_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void QSPI_StructInit(QSPI_InitTypeDef* QSPI_InitStruct)
+{
+/*--------- Reset QSPI init structure parameters default values ------------*/
+  /* Initialize the QSPI_SShift member */
+  QSPI_InitStruct->QSPI_SShift = QSPI_SShift_NoShift ;
+  /* Initialize the QSPI_Prescaler member */  
+  QSPI_InitStruct->QSPI_Prescaler = 0 ;
+  /* Initialize the QSPI_CKMode member */
+  QSPI_InitStruct->QSPI_CKMode = QSPI_CKMode_Mode0 ;
+  /* Initialize the QSPI_CSHTime member */
+  QSPI_InitStruct->QSPI_CSHTime = QSPI_CSHTime_1Cycle ;
+  /* Initialize the QSPI_FSize member */
+  QSPI_InitStruct->QSPI_FSize = 0 ;
+  /* Initialize the QSPI_FSelect member */
+  QSPI_InitStruct->QSPI_FSelect = QSPI_FSelect_1 ;
+  /* Initialize the QSPI_DFlash member */
+  QSPI_InitStruct->QSPI_DFlash = QSPI_DFlash_Disable ;
+}
+
+/**
+  * @brief  Fills each QSPI_ComConfig_InitStruct member with its default value.
+  * @param  QSPI_ComConfig_InitStruct: pointer to a QSPI_ComConfig_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void QSPI_ComConfig_StructInit(QSPI_ComConfig_InitTypeDef* QSPI_ComConfig_InitStruct)
+{
+/*--------- Reset QSPI ComConfig init structure parameters default values ------------*/
+    
+/* Set QSPI Communication configuration structure parameters default values */
+  /* Initialize the QSPI_ComConfig_DDRMode member */
+  QSPI_ComConfig_InitStruct->QSPI_ComConfig_DDRMode = QSPI_ComConfig_DDRMode_Disable ;
+  /* Initialize the QSPI_ComConfig_DHHC member */
+  QSPI_ComConfig_InitStruct->QSPI_ComConfig_DHHC = QSPI_ComConfig_DHHC_Disable ;
+  /* Initialize the QSPI_ComConfig_SIOOMode member */
+  QSPI_ComConfig_InitStruct->QSPI_ComConfig_SIOOMode = QSPI_ComConfig_SIOOMode_Disable ;
+  /* Initialize the QSPI_ComConfig_FMode member */
+  QSPI_ComConfig_InitStruct->QSPI_ComConfig_FMode = QSPI_ComConfig_FMode_Indirect_Write ;
+  /* Initialize the QSPI_ComConfig_DMode member */
+  QSPI_ComConfig_InitStruct->QSPI_ComConfig_DMode = QSPI_ComConfig_DMode_NoData ;
+  /* Initialize the QSPI_ComConfig_DummyCycles member */
+  QSPI_ComConfig_InitStruct->QSPI_ComConfig_DummyCycles = 0 ;
+  /* Initialize the QSPI_ComConfig_ABSize member */
+  QSPI_ComConfig_InitStruct->QSPI_ComConfig_ABSize = QSPI_ComConfig_ABSize_8bit ;
+  /* Initialize the QSPI_ComConfig_ABMode member */
+  QSPI_ComConfig_InitStruct->QSPI_ComConfig_ABMode = QSPI_ComConfig_ABMode_NoAlternateByte ;
+  /* Initialize the QSPI_ComConfig_ADSize member */
+  QSPI_ComConfig_InitStruct->QSPI_ComConfig_ADSize = QSPI_ComConfig_ADSize_8bit ;
+  /* Initialize the QSPI_ComConfig_ADMode member */
+  QSPI_ComConfig_InitStruct->QSPI_ComConfig_ADMode = QSPI_ComConfig_ADMode_NoAddress ;
+  /* Initialize the QSPI_ComConfig_IMode member */
+  QSPI_ComConfig_InitStruct->QSPI_ComConfig_IMode = QSPI_ComConfig_IMode_NoInstruction ;
+  /* Initialize the QSPI_ComConfig_Ins member */
+  QSPI_ComConfig_InitStruct->QSPI_ComConfig_Ins = 0 ;
+}
+
+/**
+  * @brief  Initializes the QSPI peripheral according to the specified 
+  *         parameters in the QSPI_InitStruct.
+  * @param  QSPI_InitStruct: pointer to a QSPI_InitTypeDef structure that
+  *         contains the configuration information for the specified QSPI peripheral.
+  * @retval None
+  */
+void QSPI_Init(QSPI_InitTypeDef* QSPI_InitStruct)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the QSPI parameters */
+  assert_param(IS_QSPI_SSHIFT(QSPI_InitStruct->QSPI_SShift));
+  assert_param(IS_QSPI_PRESCALER(QSPI_InitStruct->QSPI_Prescaler));
+  assert_param(IS_QSPI_CKMODE(QSPI_InitStruct->QSPI_CKMode));
+  assert_param(IS_QSPI_CSHTIME(QSPI_InitStruct->QSPI_CSHTime));
+  assert_param(IS_QSPI_FSIZE(QSPI_InitStruct->QSPI_FSize));
+	assert_param(IS_QSPI_FSEL(QSPI_InitStruct->QSPI_FSelect));
+	assert_param(IS_QSPI_DFM(QSPI_InitStruct->QSPI_DFlash));
+  
+  /*------------------------ QSPI CR Configuration ------------------------*/
+  /* Get the QUADSPI CR1 value */
+  tmpreg = QUADSPI->CR;
+  /* Clear PRESCALER and SSHIFT bits */
+  tmpreg &= QSPI_CR_CLEAR_MASK;
+  /* Configure QUADSPI: Prescaler and Sample Shift */
+  tmpreg |= (uint32_t)(((QSPI_InitStruct->QSPI_Prescaler)<<24)
+                        |(QSPI_InitStruct->QSPI_SShift)
+	                      |(QSPI_InitStruct->QSPI_FSelect)
+	                      |(QSPI_InitStruct->QSPI_DFlash));  
+  /* Write to QUADSPI CR */
+  QUADSPI->CR = tmpreg;
+  
+  /*------------------------ QUADSPI DCR Configuration ------------------------*/
+  /* Get the QUADSPI DCR value */
+  tmpreg = QUADSPI->DCR;
+  /* Clear FSIZE, CSHT and CKMODE bits */
+  tmpreg &= QSPI_DCR_CLEAR_MASK;
+  /* Configure QSPI: Flash Size, Chip Select High Time and Clock Mode */
+  tmpreg |= (uint32_t)(((QSPI_InitStruct->QSPI_FSize)<<16)
+                        |(QSPI_InitStruct->QSPI_CSHTime)
+                        |(QSPI_InitStruct->QSPI_CKMode));  
+  /* Write to QSPI DCR */
+  QUADSPI->DCR = tmpreg;  
+}
+
+/**
+  * @brief  Initializes the QSPI CCR according to the specified 
+  *         parameters in the QSPI_ComConfig_InitStruct.
+  * @param  QSPI_ComConfig_InitStruct: pointer to a QSPI_ComConfig_InitTypeDef structure that
+  *         contains the communication configuration informations about QSPI peripheral.
+  * @retval None
+  */
+void QSPI_ComConfig_Init(QSPI_ComConfig_InitTypeDef* QSPI_ComConfig_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the QSPI Communication Control parameters */
+  assert_param(IS_QSPI_FMODE       (QSPI_ComConfig_InitStruct->QSPI_ComConfig_FMode));
+  assert_param(IS_QSPI_SIOOMODE    (QSPI_ComConfig_InitStruct->QSPI_ComConfig_SIOOMode));
+  assert_param(IS_QSPI_DMODE       (QSPI_ComConfig_InitStruct->QSPI_ComConfig_DMode));
+  assert_param(IS_QSPI_DCY         (QSPI_ComConfig_InitStruct->QSPI_ComConfig_DummyCycles));
+  assert_param(IS_QSPI_ABSIZE      (QSPI_ComConfig_InitStruct->QSPI_ComConfig_ABSize));
+  assert_param(IS_QSPI_ABMODE      (QSPI_ComConfig_InitStruct->QSPI_ComConfig_ABMode));
+  assert_param(IS_QSPI_ADSIZE      (QSPI_ComConfig_InitStruct->QSPI_ComConfig_ADSize));
+  assert_param(IS_QSPI_ADMODE      (QSPI_ComConfig_InitStruct->QSPI_ComConfig_ADMode));
+  assert_param(IS_QSPI_IMODE       (QSPI_ComConfig_InitStruct->QSPI_ComConfig_IMode));
+  assert_param(IS_QSPI_INSTRUCTION (QSPI_ComConfig_InitStruct->QSPI_ComConfig_Ins));
+	assert_param(IS_QSPI_DDRMODE     (QSPI_ComConfig_InitStruct->QSPI_ComConfig_DDRMode));
+	assert_param(IS_QSPI_DHHC        (QSPI_ComConfig_InitStruct->QSPI_ComConfig_DHHC));
+  
+  /*------------------------ QUADSPI CCR Configuration ------------------------*/
+  /* Get the QUADSPI CCR value */
+  tmpreg = QUADSPI->CCR;
+  /* Clear FMODE Mode bits */
+  tmpreg &= QSPI_CCR_CLEAR_MASK;
+  /* Configure QUADSPI: CCR Configuration */
+  tmpreg |=  (uint32_t)( (QSPI_ComConfig_InitStruct->QSPI_ComConfig_FMode)
+                       | (QSPI_ComConfig_InitStruct->QSPI_ComConfig_DDRMode)
+											 | (QSPI_ComConfig_InitStruct->QSPI_ComConfig_DHHC)
+                       | (QSPI_ComConfig_InitStruct->QSPI_ComConfig_SIOOMode)
+                       | (QSPI_ComConfig_InitStruct->QSPI_ComConfig_DMode)
+                       | (QSPI_ComConfig_InitStruct->QSPI_ComConfig_ABSize)
+                       | (QSPI_ComConfig_InitStruct->QSPI_ComConfig_ABMode)                                                                       
+                       | (QSPI_ComConfig_InitStruct->QSPI_ComConfig_ADSize)
+                       | (QSPI_ComConfig_InitStruct->QSPI_ComConfig_ADMode)
+                       | (QSPI_ComConfig_InitStruct->QSPI_ComConfig_IMode)
+                       | (QSPI_ComConfig_InitStruct->QSPI_ComConfig_Ins)
+                       |((QSPI_ComConfig_InitStruct->QSPI_ComConfig_DummyCycles)<<18));    
+  /* Write to QUADSPI DCR */
+  QUADSPI->CCR = tmpreg;      
+}
+
+/**
+  * @brief  Enables or disables QSPI peripheral.
+  * @param  NewState: new state of the QSPI peripheral. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void QSPI_Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable QSPI peripheral */
+    QUADSPI->CR |= QUADSPI_CR_EN;
+  }
+  else
+  {
+    /* Disable QSPI peripheral */
+    QUADSPI->CR &= ~ QUADSPI_CR_EN;
+  }
+}
+
+/**
+  * @brief  Configure the QSPI Automatic Polling Mode.
+  * @param  QSPI_Match: Value to be compared with the masked status register to get a match. 
+  *          This parameter can be any value between 0x00000000 and 0xFFFFFFFF.
+  * @param  QSPI_Mask: Mask to be applied to the status bytes received in polling mode.. 
+  *          This parameter can be any value between 0x00000000 and 0xFFFFFFFF.
+  * @param  QSPI_Match_Mode: indicates which method should be used for determining a <20>match<63> during
+  *         automatic polling mode. 
+  *          This parameter can be any value of :
+  *            @arg QSPI_PMM_AND: AND match mode- SMF is set if all the unmasked bits received from the flash match
+  *                 the corresponding bits in the match register
+  *            @arg QSPI_PMM_OR: OR match mode- SMF is set if any one of the unmasked bits received from the flash
+                    matches its corresponding bit in the match register.
+  * @note   This function is used only in Automatic Polling Mode
+  * @retval None
+  */
+void QSPI_AutoPollingMode_Config(uint32_t QSPI_Match, uint32_t QSPI_Mask , uint32_t QSPI_Match_Mode)
+{
+  /* Check the parameters */
+  assert_param(IS_QSPI_PMM(QSPI_Match_Mode));
+
+  if ((QUADSPI->SR & QUADSPI_SR_BUSY) == RESET)
+  /* Device is not Busy */
+  {
+    /* Set the Match Register */
+    QUADSPI->PSMAR = QSPI_Match ;
+
+    /* Set the Mask Register */
+    QUADSPI->PSMKR = QSPI_Mask ;
+    
+    /* Set the Polling Match Mode */
+    if(QSPI_Match_Mode)
+    /* OR Match Mode */
+    {
+      /* Set the PMM bit */
+      QUADSPI->CR |= QUADSPI_CR_PMM;
+    }
+    else
+    /* AND Match Mode */
+    {
+      /* Reset the PMM bit */
+      QUADSPI->CR &= ~ QUADSPI_CR_PMM;
+    }
+  }
+}
+
+/**
+  * @brief  Sets the number of CLK cycle between two read during automatic polling phases.
+  * @param  QSPI_Interval: The number of CLK cycle between two read during automatic polling phases. 
+  *          This parameter can be any value of between 0x0000 and 0xFFFF
+  * @note   This function is used only in Automatic Polling Mode  
+  * @retval None
+  */
+void QSPI_AutoPollingMode_SetInterval(uint32_t QSPI_Interval)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_QSPI_PIR(QSPI_Interval));
+
+  if ((QUADSPI->SR & QUADSPI_SR_BUSY) == RESET)
+  /* Device is not Busy */
+  {
+    /* Read the PIR Register */
+    tmpreg = QUADSPI->PIR ;
+    /* Clear Polling interval Bits */
+    tmpreg &= QSPI_PIR_CLEAR_MASK ;
+    /* Set the QSPI Polling Interval Bits */
+    tmpreg |= QSPI_Interval;
+    /* Write the PIR Register */
+    QUADSPI->PIR = tmpreg;
+  }
+}
+
+/**
+  * @brief  Sets the value of the Timeout in Memory Mapped mode
+  * @param  QSPI_Timeout: This field indicates how many CLK cycles QSPI waits after the 
+  *         FIFO becomes full until it raises nCS, putting the flash memory 
+  *         in a lowerconsumption state. 
+  *         This parameter can be any value of between 0x0000 and 0xFFFF
+  * @note   This function is used only in Memory Mapped Mode  
+  * @retval None
+  */
+void QSPI_MemoryMappedMode_SetTimeout(uint32_t QSPI_Timeout)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_QSPI_TIMEOUT(QSPI_Timeout));
+
+  if ((QUADSPI->SR & QUADSPI_SR_BUSY) == RESET)
+  /* Device is not Busy */
+  {
+    /* Read the LPTR Register */
+    tmpreg = QUADSPI->LPTR ;
+    /* Clear Timeout Bits */
+    tmpreg &= QSPI_LPTR_CLEAR_MASK ;
+    /* Set Timeout Bits */
+    tmpreg |= QSPI_Timeout;
+    /* Write the LPTR Register */
+    QUADSPI->LPTR = tmpreg;
+  }
+}
+
+/**
+  * @brief  Sets the value of the Address
+  * @param  QSPI_Address: Address to be send to the external flash memory.  
+  *         This parameter can be any value of between 0x00000000 and 0xFFFFFFFF
+  * @note   This function is used only in Indirect Mode  
+  * @retval None
+  */
+void QSPI_SetAddress(uint32_t QSPI_Address)
+{
+  if((QUADSPI->SR & QUADSPI_SR_BUSY) == RESET)
+  /* Device is not Busy */
+  {
+    /* Write the AR Register */
+    QUADSPI->AR = QSPI_Address;
+  }
+}
+
+/**
+  * @brief  Sets the value of the Alternate Bytes
+  * @param  QSPI_AlternateByte: Optional data to be send to the external QSPI device right after the address. 
+  *         This parameter can be any value of between 0x00000000 and 0xFFFFFFFF
+  * @note   This function is used only in Indirect Mode  
+  * @retval None
+  */
+void QSPI_SetAlternateByte(uint32_t QSPI_AlternateByte)
+{
+  if((QUADSPI->SR & QUADSPI_SR_BUSY) == RESET)
+  /* Device is not Busy */
+  {
+    /* Write the ABR Register */
+    QUADSPI->ABR = QSPI_AlternateByte;
+  }
+}
+
+/**
+  * @brief  Sets the FIFO Threshold
+  * @param  QSPI_FIFOThres: Defines, in indirect mode, the threshold number 
+  *           of bytes in the FIFO which will cause the FIFO Threshold Flag 
+  *           FTF to be set.
+  *         This parameter can be any value of between 0x00 and 0x0F
+  * @retval None
+  */
+void QSPI_SetFIFOThreshold(uint32_t QSPI_FIFOThreshold)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_QSPI_FIFOTHRESHOLD(QSPI_FIFOThreshold));
+
+  /* Read the CR Register */
+  tmpreg = QUADSPI->CR ;
+  /* Clear FIFO Threshold Bits */
+  tmpreg &= QSPI_CR_CLEAR_FIFOTHRESHOLD_MASK ;
+  /* Set FIFO Threshold Bits */
+  tmpreg |= (QSPI_FIFOThreshold << 8);
+  /* Write the CR Register */
+  QUADSPI->CR = tmpreg;
+}
+
+/**
+  * @brief  Sets number of Bytes to be transferred 
+  * @param  QSPI_DataLength: Number of data to be retrieved (value+1) 
+  *         in indirect and status-polling modes. A value no greater than 3 
+  *         (indicating 4 bytes) should be used for status-polling mode. 
+  *         All 1s in indirect mode means undefined length, where QSPI will 
+  *         continue until the end of memory, as defined by FSIZE
+  *         This parameter can be any value of between 0x00000000 and 0xFFFFFFFF
+  *             0x0000_0000: 1 byte is to be transferred
+  *             0x0000_0001: 2 bytes are to be transferred
+  *             0x0000_0002: 3 bytes are to be transferred
+  *             0x0000_0003: 4 bytes are to be transferred
+  *             ...
+  *             0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred
+  *             0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred
+  *             0xFFFF_FFFF: undefined length -- all bytes until the end of flash memory (as defined
+  *             by FSIZE) are to be transferred
+  * @note   This function is not used in Memory Mapped Mode.
+  * @retval None
+  */
+void QSPI_SetDataLength(uint32_t QSPI_DataLength)
+{
+  if ((QUADSPI->SR & QUADSPI_SR_BUSY) == RESET)
+  /* Device is not Busy */
+  {
+    /* Write the DLR Register */
+    QUADSPI->DLR = QSPI_DataLength;
+  }
+}
+
+/**
+  * @brief  Enables or disables The Timeout Counter.
+  * @param  NewState: new state of the Timeout Counter. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   This function is used only in Memory Mapped Mode.
+  * @retval None
+  */
+void QSPI_TimeoutCounterCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if ((QUADSPI->SR & QUADSPI_SR_BUSY) == RESET)
+  /* Device is not Busy */
+  {
+    if (NewState != DISABLE)
+    {
+      /* Enable Timeout Counter */
+      QUADSPI->CR |= QUADSPI_CR_TCEN;
+    }
+    else
+    {
+      /* Disable Timeout Counter */
+      QUADSPI->CR &= ~ QUADSPI_CR_TCEN;
+    }
+  }
+}
+
+/**
+  * @brief  Enables or disables Automatic Polling Mode Stop when a match occurs.
+  * @param  NewState: new state of the Automatic Polling Mode Stop. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   This function is used only in Automatic Polling Mode.    
+  * @retval None
+  */
+void QSPI_AutoPollingModeStopCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if ((QUADSPI->SR & QUADSPI_SR_BUSY) == RESET)
+  /* Device is not Busy */
+  {
+    if (NewState != DISABLE)
+    {
+      /* Enable Automatic Polling Mode Stop */
+      QUADSPI->CR |= QUADSPI_CR_APMS;
+    }
+    else
+    {
+      /* Disable Automatic Polling Mode Stop */
+      QUADSPI->CR &= ~ QUADSPI_CR_APMS;
+    }
+  }
+}
+
+/**
+  * @brief  Abort the on-going command sequence.
+  * @param  None
+  * @retval None
+  */
+void QSPI_AbortRequest(void)
+{
+  /* Enable the ABORT request bit in CR */
+  QUADSPI->CR |= QUADSPI_CR_ABORT;
+}
+
+/* Data transfers functions ***************************************************/
+
+/**
+  * @brief  Transmits a 8bit Data through the QSPI peripheral.
+  * @param  Data: Data to be transmitted.
+  * @retval None
+  */
+void QSPI_SendData8(uint8_t Data)
+{
+  uint32_t quadspibase = 0;
+
+  quadspibase = (uint32_t)QUADSPI; 
+  quadspibase += 0x20;
+  
+  *(__IO uint8_t *) quadspibase = Data;
+}
+
+/**
+  * @brief  Transmits a 16bit Data through the QSPI peripheral.
+  * @param  Data: Data to be transmitted.
+  * @retval None
+  */
+void QSPI_SendData16(uint16_t Data)
+{
+  uint32_t quadspibase = 0;
+
+  quadspibase = (uint32_t)QUADSPI; 
+  quadspibase += 0x20;
+  
+  *(__IO uint16_t *) quadspibase = Data;
+}
+
+/**
+  * @brief  Transmits a 32bit Data through the QSPI peripheral.
+  * @param  Data: Data to be transmitted.
+  * @retval None
+  */
+void QSPI_SendData32(uint32_t Data)
+{
+  QUADSPI->DR = Data;
+}
+
+/**
+  * @brief  Returns the most recent received 8bit data by the QSPI peripheral. 
+  * @retval The value of the received data.
+  */
+uint8_t QSPI_ReceiveData8(void)
+{
+  uint32_t quadspibase = 0;
+  
+  quadspibase = (uint32_t)QUADSPI; 
+  quadspibase += 0x20;
+  
+  return *(__IO uint8_t *) quadspibase;
+}
+
+/**
+  * @brief  Returns the most recent received 16bit data by the QSPI peripheral. 
+  * @retval The value of the received data.
+  */
+uint16_t QSPI_ReceiveData16(void)
+{
+  uint32_t quadspibase = 0;
+  
+  quadspibase = (uint32_t)QUADSPI; 
+  quadspibase += 0x20;
+  
+  return *(__IO uint16_t *) quadspibase;
+}
+
+/**
+  * @brief  Returns the most recent received 32bit data by the QSPI peripheral. 
+  * @retval The value of the received data.
+  */
+uint32_t QSPI_ReceiveData32(void)
+{
+  return QUADSPI->DR;
+}
+
+/* DMA transfers management functions *****************************************/
+
+/**
+  * @brief  Enables or disables DMA for Indirect Mode.
+  * @param  NewState: new state of the Timeout Counter. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void QSPI_DMACmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable DMA */
+    QUADSPI->CR |= QUADSPI_CR_DMAEN;
+  }
+  else
+  {
+    /* Disable DMA */
+    QUADSPI->CR &= ~ QUADSPI_CR_DMAEN;
+  }
+}
+
+/* Interrupts and flags management functions **********************************/
+
+/**
+  * @brief  Enables or disables the specified QSPI interrupts.
+  * @param  QSPI_IT: specifies the QSPI interrupt source to be enabled or disabled. 
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_IT_TO: Timeout interrupt
+  *            @arg QSPI_IT_SM: Status Match interrupt
+  *            @arg QSPI_IT_FT: FIFO Threshold
+  *            @arg QSPI_IT_TC: Transfer Complete
+  *            @arg QSPI_IT_TE: Transfer Error      
+  * @param  NewState: new state of the specified QSPI interrupt.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void QSPI_ITConfig(uint32_t QSPI_IT, FunctionalState NewState)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_QSPI_IT(QSPI_IT));
+
+  /* Read the CR Register */
+  tmpreg = QUADSPI->CR ;
+  
+  if(NewState != DISABLE)
+  {
+    /* Enable the selected QSPI interrupt */
+    tmpreg |= (uint32_t)(QSPI_IT & QSPI_CR_INTERRUPT_MASK);
+  }
+  else
+  {
+    /* Disable the selected QSPI interrupt */
+    tmpreg &= ~(uint32_t)(QSPI_IT & QSPI_CR_INTERRUPT_MASK);
+  }
+  /* Write the CR Register */
+  QUADSPI->CR = tmpreg ;  
+}
+
+/**
+  * @brief  Returns the current QSPI FIFO filled level.
+  * @retval Number of valid bytes which are being held in the FIFO.
+  *         0x00 : FIFO is empty
+  *         0x1F : FIFO is full    
+  */
+uint32_t QSPI_GetFIFOLevel(void)
+{
+  /* Get the QSPI FIFO level bits */
+  return ((QUADSPI->SR & QUADSPI_SR_FLEVEL)>> 8);
+}
+
+/**
+  * @brief  Returns the QSPI functional mode.  
+  * @param  None 
+  * @retval QSPI Functional Mode .The returned value can be one of the following:
+  *              - 0x00000000: QSPI_FMode_Indirect_Write
+  *              - 0x04000000: QSPI_FMode_Indirect_Read
+  *              - 0x08000000: QSPI_FMode_AutoPolling
+  *              - 0x0C000000: QSPI_FMode_MemoryMapped
+  */
+uint32_t QSPI_GetFMode(void)
+{
+  /* Return the QSPI_FMode */
+  return  (QUADSPI->CCR & QUADSPI_CCR_FMODE);
+}
+
+/**
+  * @brief  Checks whether the specified QSPI flag is set or not.  
+  * @param  QSPI_FLAG: specifies the QSPI flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_FLAG_TO: Timeout interrupt flag
+  *            @arg QSPI_FLAG_SM: Status Match interrupt flag
+  *            @arg QSPI_FLAG_FT: FIFO Threshold flag
+  *            @arg QSPI_FLAG_TC: Transfer Complete flag
+  *            @arg QSPI_FLAG_TE: Transfer Error flag
+  *            @arg QSPI_FLAG_BUSY: Busy flag      
+  * @retval The new state of QSPI_FLAG (SET or RESET).
+  */
+FlagStatus QSPI_GetFlagStatus(uint32_t QSPI_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_QSPI_GET_FLAG(QSPI_FLAG));
+
+  /* Check the status of the specified QSPI flag */
+  if((QUADSPI->SR & QSPI_FLAG) != RESET)
+  {
+    /* QSPI_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* QSPI_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the QSPI_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the QSPI flag.
+  * @param  QSPI_FLAG: specifies the QSPI flag to clear. 
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_FLAG_TO: Timeout interrupt flag
+  *            @arg QSPI_FLAG_SM: Status Match interrupt flag
+  *            @arg QSPI_FLAG_TC: Transfer Complete flag
+  *            @arg QSPI_FLAG_TE: Transfer Error flag
+  * @retval None
+  */
+void QSPI_ClearFlag(uint32_t QSPI_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_QSPI_CLEAR_FLAG(QSPI_FLAG));
+
+  /* Clear the selected QSPI flags */
+  QUADSPI->FCR = QSPI_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified QSPI interrupt has occurred or not.
+  * @param  QSPI_IT: specifies the QSPI interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_IT_TO: Timeout interrupt 
+  *            @arg QSPI_IT_SM: Status Match interrupt
+  *            @arg QSPI_IT_FT: FIFO Threshold
+  *            @arg QSPI_IT_TC: Transfer Complete
+  *            @arg QSPI_IT_TE: Transfer Error    
+  * @retval The new state of QSPI_IT (SET or RESET).
+  */
+ITStatus QSPI_GetITStatus(uint32_t QSPI_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpcreg = 0, tmpsreg = 0; 
+
+  /* Check the parameters */
+  assert_param(IS_QSPI_IT(QSPI_IT));
+
+  /* Read the QUADSPI CR */
+  tmpcreg = QUADSPI->CR;  
+  tmpcreg &= (uint32_t)(QSPI_IT & QSPI_CR_INTERRUPT_MASK);
+  
+  /* Read the QUADSPI SR */
+  tmpsreg = QUADSPI->SR;  
+  tmpsreg &= (uint32_t)(QSPI_IT & QSPI_SR_INTERRUPT_MASK);
+
+  /* Check the status of the specified QSPI interrupt */
+  if((tmpcreg != RESET) && (tmpsreg != RESET))
+  {
+    /* QSPI_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* QSPI_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the QSPI_IT status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the QSPI's interrupt pending bits.
+  * @param  QSPI_IT: specifies the QSPI pending bit to clear. 
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_IT_TO: Timeout interrupt 
+  *            @arg QSPI_IT_SM: Status Match interrupt
+  *            @arg QSPI_IT_TC: Transfer Complete
+  *            @arg QSPI_IT_TE: Transfer Error 
+  * @retval None
+  */
+void QSPI_ClearITPendingBit(uint32_t QSPI_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_QSPI_CLEAR_IT(QSPI_IT));  
+
+  QUADSPI->FCR = (uint32_t)(QSPI_IT & QSPI_FSR_INTERRUPT_MASK);
+}
+
+/**
+  * @brief  Enables or disables QSPI Dual Flash Mode.
+  * @param  NewState: new state of the QSPI Dual Flash Mode. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void QSPI_DualFlashMode_Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable QSPI Dual Flash Mode */
+    QUADSPI->CR |= QUADSPI_CR_DFM;
+  }
+  else
+  {
+    /* Disable QSPI Dual Flash Mode */
+    QUADSPI->CR &= ~ QUADSPI_CR_DFM;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

底盘/底盘-old/底盘/Library/stm32f4xx_qspi.h

@@ -0,0 +1,485 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_qspi.h
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief   This file contains all the functions prototypes for the QSPI 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4XX_QUADSPI_H
+#define __STM32F4XX_QUADSPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup QSPI
+  * @{
+  */
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  QSPI Communication Configuration Init structure definition  
+  */
+
+typedef struct
+{
+  
+  uint32_t QSPI_ComConfig_FMode;            /* Specifies the Functional Mode
+                                          This parameter can be a value of @ref QSPI_ComConfig_Functional_Mode*/  
+	
+  uint32_t QSPI_ComConfig_DDRMode;          /* Specifies the Double Data Rate Mode
+                                          This parameter can be a value of @ref QSPI_ComConfig_DoubleDataRateMode*/
+	
+  uint32_t QSPI_ComConfig_DHHC;            /* Specifies the Delay Half Hclk Cycle
+                                          This parameter can be a value of @ref QSPI_ComConfig_DelayHalfHclkCycle*/
+  
+  uint32_t QSPI_ComConfig_SIOOMode;         /* Specifies the Send Instruction Only Once Mode
+                                          This parameter can be a value of @ref QSPI_ComConfig_SendInstructionOnlyOnceMode*/
+  
+  uint32_t QSPI_ComConfig_DMode;            /* Specifies the Data Mode
+                                          This parameter can be a value of @ref QSPI_ComConfig_DataMode*/
+  
+  uint32_t QSPI_ComConfig_DummyCycles;      /* Specifies the Number of Dummy Cycles.
+                                           This parameter can be a number between 0x00 and 0x1F */             
+
+  uint32_t QSPI_ComConfig_ABSize;           /* Specifies the Alternate Bytes Size
+                                          This parameter can be a value of @ref QSPI_ComConfig_AlternateBytesSize*/ 
+
+  uint32_t QSPI_ComConfig_ABMode;           /* Specifies the Alternate Bytes Mode
+                                          This parameter can be a value of @ref QSPI_ComConfig_AlternateBytesMode*/     
+ 
+  uint32_t QSPI_ComConfig_ADSize;           /* Specifies the Address Size
+                                          This parameter can be a value of @ref QSPI_ComConfig_AddressSize*/
+
+  uint32_t QSPI_ComConfig_ADMode;           /* Specifies the Address Mode
+                                          This parameter can be a value of @ref QSPI_ComConfig_AddressMode*/
+  
+  uint32_t QSPI_ComConfig_IMode;            /* Specifies the Instruction Mode
+                                          This parameter can be a value of @ref QSPI_ComConfig_InstructionMode*/
+
+  uint32_t QSPI_ComConfig_Ins;      /* Specifies the Instruction Mode
+                                          This parameter can be a value of @ref QSPI_ComConfig_Instruction*/
+  
+}QSPI_ComConfig_InitTypeDef;
+
+/** 
+  * @brief  QSPI Init structure definition  
+  */
+
+typedef struct
+{
+  uint32_t QSPI_SShift;    /* Specifies the Sample Shift
+                              This parameter can be a value of @ref QSPI_Sample_Shift*/
+
+  uint32_t QSPI_Prescaler; /* Specifies the prescaler value used to divide the QSPI clock.
+                              This parameter can be a number between 0x00 and 0xFF */ 
+
+  uint32_t QSPI_CKMode;    /* Specifies the Clock Mode
+                              This parameter can be a value of @ref QSPI_Clock_Mode*/
+
+  uint32_t QSPI_CSHTime;   /* Specifies the Chip Select High Time
+                              This parameter can be a value of @ref QSPI_ChipSelectHighTime*/   
+ 
+  uint32_t QSPI_FSize;     /* Specifies the Flash Size.
+                               QSPI_FSize+1 is effectively the number of address bits required to address the flash memory.
+                               The flash capacity can be up to 4GB (addressed using 32 bits) in indirect mode, but the
+                               addressable space in memory-mapped mode is limited to 512MB
+                               This parameter can be a number between 0x00 and 0x1F */
+  uint32_t QSPI_FSelect;   /* Specifies the Flash which will be used,
+                                 This parameter can be a value of @ref QSPI_Fash_Select*/
+  uint32_t QSPI_DFlash;    /* Specifies the Dual Flash Mode State
+                                 This parameter can be a value of @ref QSPI_Dual_Flash*/
+}QSPI_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup QSPI_Exported_Constants
+  * @{
+  */
+
+/** @defgroup QSPI_Sample_Shift 
+  * @{
+  */
+#define QSPI_SShift_NoShift                        ((uint32_t)0x00000000)
+#define QSPI_SShift_HalfCycleShift                 ((uint32_t)QUADSPI_CR_SSHIFT)
+#define IS_QSPI_SSHIFT(SSHIFT)      (((SSHIFT) == QSPI_SShift_NoShift) ||  ((SSHIFT) == QSPI_SShift_HalfCycleShift))
+/* Legacy Defines */
+#define QUADSPI_CR_SSHIFT_0    QUADSPI_CR_SSHIFT
+/**
+  * @}
+  */
+  
+/** @defgroup QSPI_Prescaler 
+  * @{
+  */
+#define IS_QSPI_PRESCALER(PRESCALER) (((PRESCALER) <= 0xFF))
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_Clock_Mode 
+  * @{
+  */
+#define QSPI_CKMode_Mode0           ((uint32_t)0x00000000)
+#define QSPI_CKMode_Mode3           ((uint32_t)QUADSPI_DCR_CKMODE)
+#define IS_QSPI_CKMODE(CKMode)      (((CKMode) == QSPI_CKMode_Mode0) || ((CKMode) == QSPI_CKMode_Mode3))
+/**
+  * @}
+  */
+  
+/** @defgroup QSPI_ChipSelectHighTime 
+  * @{
+  */
+#define QSPI_CSHTime_1Cycle           ((uint32_t)0x00000000)
+#define QSPI_CSHTime_2Cycle           ((uint32_t)QUADSPI_DCR_CSHT_0)
+#define QSPI_CSHTime_3Cycle           ((uint32_t)QUADSPI_DCR_CSHT_1)
+#define QSPI_CSHTime_4Cycle           ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1)
+#define QSPI_CSHTime_5Cycle           ((uint32_t)QUADSPI_DCR_CSHT_2)
+#define QSPI_CSHTime_6Cycle           ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0)
+#define QSPI_CSHTime_7Cycle           ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1)
+#define QSPI_CSHTime_8Cycle           ((uint32_t)QUADSPI_DCR_CSHT)
+#define IS_QSPI_CSHTIME(CSHTIME)    (((CSHTIME) == QSPI_CSHTime_1Cycle) || \
+                                     ((CSHTIME) == QSPI_CSHTime_2Cycle) || \
+                                     ((CSHTIME) == QSPI_CSHTime_3Cycle) || \
+                                     ((CSHTIME) == QSPI_CSHTime_4Cycle) || \
+                                     ((CSHTIME) == QSPI_CSHTime_5Cycle) || \
+                                     ((CSHTIME) == QSPI_CSHTime_6Cycle) || \
+                                     ((CSHTIME) == QSPI_CSHTime_7Cycle) || \
+                                     ((CSHTIME) == QSPI_CSHTime_8Cycle))
+/**
+  * @}
+  */
+  
+/** @defgroup QSPI_Flash_Size 
+  * @{
+  */
+#define IS_QSPI_FSIZE(FSIZE)         (((FSIZE) <= 0x1F))
+/**
+  * @}
+  */
+	
+/** @defgroup QSPI_Fash_Select 
+  * @{
+  */
+#define QSPI_FSelect_1           ((uint32_t)0x00000000)
+#define QSPI_FSelect_2           ((uint32_t)QUADSPI_CR_FSEL)
+#define IS_QSPI_FSEL(FLA)    (((FLA) == QSPI_FSelect_1) || ((FLA) == QSPI_FSelect_2))
+/**
+  * @}
+  */
+	
+/** @defgroup QSPI_Dual_Flash 
+  * @{
+  */
+#define QSPI_DFlash_Disable           ((uint32_t)0x00000000)
+#define QSPI_DFlash_Enable            ((uint32_t)QUADSPI_CR_DFM)
+#define IS_QSPI_DFM(FLA)    (((FLA) == QSPI_DFlash_Enable) || ((FLA) == QSPI_DFlash_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_ComConfig_Functional_Mode 
+  * @{
+  */  
+#define QSPI_ComConfig_FMode_Indirect_Write     ((uint32_t)0x00000000)
+#define QSPI_ComConfig_FMode_Indirect_Read      ((uint32_t)QUADSPI_CCR_FMODE_0)
+#define QSPI_ComConfig_FMode_Auto_Polling       ((uint32_t)QUADSPI_CCR_FMODE_1)
+#define QSPI_ComConfig_FMode_Memory_Mapped      ((uint32_t)QUADSPI_CCR_FMODE)
+#define IS_QSPI_FMODE(FMODE)                  (((FMODE) == QSPI_ComConfig_FMode_Indirect_Write) || \
+                                               ((FMODE) == QSPI_ComConfig_FMode_Indirect_Read) || \
+                                               ((FMODE) == QSPI_ComConfig_FMode_Auto_Polling) || \
+                                               ((FMODE) == QSPI_ComConfig_FMode_Memory_Mapped))
+/**
+  * @}
+  */
+	
+/** @defgroup QSPI_ComConfig_DoubleDataRateMode 
+  * @{
+  */
+#define QSPI_ComConfig_DDRMode_Disable           ((uint32_t)0x00000000)
+#define QSPI_ComConfig_DDRMode_Enable            ((uint32_t)QUADSPI_CCR_DDRM)
+#define IS_QSPI_DDRMODE(DDRMODE)    (((DDRMODE) == QSPI_ComConfig_DDRMode_Disable) || \
+                                     ((DDRMODE) == QSPI_ComConfig_DDRMode_Enable))
+/**
+  * @}
+  */
+	
+/** @defgroup QSPI_ComConfig_DelayHalfHclkCycle 
+  * @{
+  */
+#define QSPI_ComConfig_DHHC_Disable           ((uint32_t)0x00000000)
+#define QSPI_ComConfig_DHHC_Enable            ((uint32_t)QUADSPI_CCR_DHHC)
+#define IS_QSPI_DHHC(DHHC)          (((DHHC) == QSPI_ComConfig_DHHC_Disable) || \
+                                     ((DHHC) == QSPI_ComConfig_DHHC_Enable))
+/**
+  * @}
+  */
+  
+/** @defgroup QSPI_ComConfig_SendInstructionOnlyOnceMode 
+  * @{
+  */
+#define QSPI_ComConfig_SIOOMode_Disable           ((uint32_t)0x00000000)
+#define QSPI_ComConfig_SIOOMode_Enable            ((uint32_t)QUADSPI_CCR_SIOO)
+#define IS_QSPI_SIOOMODE(SIOOMODE)    (((SIOOMODE) == QSPI_ComConfig_SIOOMode_Disable) || \
+                                       ((SIOOMODE) == QSPI_ComConfig_SIOOMode_Enable))
+/**
+  * @}
+  */  
+
+/** @defgroup QSPI_ComConfig_DataMode 
+  * @{
+  */
+#define QSPI_ComConfig_DMode_NoData          ((uint32_t)0x00000000)
+#define QSPI_ComConfig_DMode_1Line           ((uint32_t)QUADSPI_CCR_DMODE_0)
+#define QSPI_ComConfig_DMode_2Line           ((uint32_t)QUADSPI_CCR_DMODE_1)
+#define QSPI_ComConfig_DMode_4Line           ((uint32_t)QUADSPI_CCR_DMODE)
+#define IS_QSPI_DMODE(DMODE)        (((DMODE) == QSPI_ComConfig_DMode_NoData) || \
+                                     ((DMODE) == QSPI_ComConfig_DMode_1Line) || \
+                                     ((DMODE) == QSPI_ComConfig_DMode_2Line) || \
+                                     ((DMODE) == QSPI_ComConfig_DMode_4Line))
+/**
+  * @}
+  */
+  
+/** @defgroup QSPI_ComConfig_AlternateBytesSize 
+  * @{
+  */
+#define QSPI_ComConfig_ABSize_8bit            ((uint32_t)0x00000000)
+#define QSPI_ComConfig_ABSize_16bit           ((uint32_t)QUADSPI_CCR_ABSIZE_0)
+#define QSPI_ComConfig_ABSize_24bit           ((uint32_t)QUADSPI_CCR_ABSIZE_1)
+#define QSPI_ComConfig_ABSize_32bit           ((uint32_t)QUADSPI_CCR_ABSIZE)
+#define IS_QSPI_ABSIZE(ABSIZE)      (((ABSIZE) == QSPI_ComConfig_ABSize_8bit) || \
+                                     ((ABSIZE) == QSPI_ComConfig_ABSize_16bit) || \
+                                     ((ABSIZE) == QSPI_ComConfig_ABSize_24bit) || \
+                                     ((ABSIZE) == QSPI_ComConfig_ABSize_32bit))
+/**
+  * @}
+  */
+  
+/** @defgroup QSPI_ComConfig_AlternateBytesMode 
+  * @{
+  */
+#define QSPI_ComConfig_ABMode_NoAlternateByte          ((uint32_t)0x00000000)
+#define QSPI_ComConfig_ABMode_1Line                    ((uint32_t)QUADSPI_CCR_ABMODE_0)
+#define QSPI_ComConfig_ABMode_2Line                    ((uint32_t)QUADSPI_CCR_ABMODE_1)
+#define QSPI_ComConfig_ABMode_4Line                    ((uint32_t)QUADSPI_CCR_ABMODE)
+#define IS_QSPI_ABMODE(ABMODE)      (((ABMODE) == QSPI_ComConfig_ABMode_NoAlternateByte) || \
+                                     ((ABMODE) == QSPI_ComConfig_ABMode_1Line) || \
+                                     ((ABMODE) == QSPI_ComConfig_ABMode_2Line) || \
+                                     ((ABMODE) == QSPI_ComConfig_ABMode_4Line))
+/**
+  * @}
+  */
+  
+/** @defgroup QSPI_ComConfig_AddressSize 
+  * @{
+  */
+#define QSPI_ComConfig_ADSize_8bit            ((uint32_t)0x00000000)
+#define QSPI_ComConfig_ADSize_16bit           ((uint32_t)QUADSPI_CCR_ADSIZE_0)
+#define QSPI_ComConfig_ADSize_24bit           ((uint32_t)QUADSPI_CCR_ADSIZE_1)
+#define QSPI_ComConfig_ADSize_32bit           ((uint32_t)QUADSPI_CCR_ADSIZE)
+#define IS_QSPI_ADSIZE(ADSIZE)      (((ADSIZE) == QSPI_ComConfig_ADSize_8bit) || \
+                                     ((ADSIZE) == QSPI_ComConfig_ADSize_16bit) || \
+                                     ((ADSIZE) == QSPI_ComConfig_ADSize_24bit) || \
+                                     ((ADSIZE) == QSPI_ComConfig_ADSize_32bit))
+/**
+  * @}
+  */
+  
+/** @defgroup QSPI_ComConfig_AddressMode 
+  * @{
+  */
+#define QSPI_ComConfig_ADMode_NoAddress          ((uint32_t)0x00000000)
+#define QSPI_ComConfig_ADMode_1Line              ((uint32_t)QUADSPI_CCR_ADMODE_0)
+#define QSPI_ComConfig_ADMode_2Line              ((uint32_t)QUADSPI_CCR_ADMODE_1)
+#define QSPI_ComConfig_ADMode_4Line              ((uint32_t)QUADSPI_CCR_ADMODE)
+#define IS_QSPI_ADMODE(ADMODE)        (((ADMODE) == QSPI_ComConfig_ADMode_NoAddress) || \
+                                       ((ADMODE) == QSPI_ComConfig_ADMode_1Line) || \
+                                       ((ADMODE) == QSPI_ComConfig_ADMode_2Line) || \
+                                       ((ADMODE) == QSPI_ComConfig_ADMode_4Line))
+/**
+  * @}
+  */  
+  
+/** @defgroup QSPI_ComConfig_InstructionMode 
+  * @{
+  */
+#define QSPI_ComConfig_IMode_NoInstruction          ((uint32_t)0x00000000)
+#define QSPI_ComConfig_IMode_1Line                  ((uint32_t)QUADSPI_CCR_IMODE_0)
+#define QSPI_ComConfig_IMode_2Line                  ((uint32_t)QUADSPI_CCR_IMODE_1)
+#define QSPI_ComConfig_IMode_4Line                  ((uint32_t)QUADSPI_CCR_IMODE)
+#define IS_QSPI_IMODE(IMODE)        (((IMODE) == QSPI_ComConfig_IMode_NoInstruction) || \
+                                     ((IMODE) == QSPI_ComConfig_IMode_1Line) || \
+                                     ((IMODE) == QSPI_ComConfig_IMode_2Line) || \
+                                     ((IMODE) == QSPI_ComConfig_IMode_4Line))
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_ComConfig_Instruction 
+  * @{
+  */
+#define IS_QSPI_INSTRUCTION(INSTRUCTION)           ((INSTRUCTION) <= 0xFF) 
+/**
+  * @}
+  */ 
+
+/** @defgroup QSPI_InterruptsDefinition 
+  * @{
+  */
+#define QSPI_IT_TO                (uint32_t)(QUADSPI_CR_TOIE | QUADSPI_SR_TOF)
+#define QSPI_IT_SM                (uint32_t)(QUADSPI_CR_SMIE | QUADSPI_SR_SMF)
+#define QSPI_IT_FT                (uint32_t)(QUADSPI_CR_FTIE | QUADSPI_SR_FTF)
+#define QSPI_IT_TC                (uint32_t)(QUADSPI_CR_TCIE | QUADSPI_SR_TCF)
+#define QSPI_IT_TE                (uint32_t)(QUADSPI_CR_TEIE | QUADSPI_SR_TEF)
+#define IS_QSPI_IT(IT)   ((((IT) & 0xFFE0FFE0) == 0) && ((IT) != 0))
+#define IS_QSPI_CLEAR_IT(IT)   ((((IT) & 0xFFE4FFE4) == 0) && ((IT) != 0))  
+/**
+  * @}
+  */
+  
+/** @defgroup QSPI_FlagsDefinition 
+  * @{
+  */
+#define QSPI_FLAG_TO                  QUADSPI_SR_TOF
+#define QSPI_FLAG_SM                  QUADSPI_SR_SMF
+#define QSPI_FLAG_FT                  QUADSPI_SR_FTF
+#define QSPI_FLAG_TC                  QUADSPI_SR_TCF
+#define QSPI_FLAG_TE                  QUADSPI_SR_TEF
+#define QSPI_FLAG_BUSY                QUADSPI_SR_BUSY
+#define IS_QSPI_GET_FLAG(FLAG)   (((FLAG) == QSPI_FLAG_TO) || ((FLAG) == QSPI_FLAG_SM) || \
+                                  ((FLAG) == QSPI_FLAG_FT) || ((FLAG) == QSPI_FLAG_TC) || \
+                                  ((FLAG) == QSPI_FLAG_TE) || ((FLAG) == QSPI_FLAG_BUSY))
+#define IS_QSPI_CLEAR_FLAG(FLAG)  (((FLAG) == QSPI_FLAG_TO) || ((FLAG) == QSPI_FLAG_SM) || \
+                                  ((FLAG) == QSPI_FLAG_TC) ||  ((FLAG) == QSPI_FLAG_TE))
+
+/**
+  * @}
+  */
+  
+/** @defgroup QSPI_Polling_Match_Mode 
+  * @{
+  */
+#define QSPI_PMM_AND                 ((uint32_t)0x00000000)
+#define QSPI_PMM_OR                  ((uint32_t)QUADSPI_CR_PMM)
+#define IS_QSPI_PMM(PMM)      (((PMM) == QSPI_PMM_AND) || ((PMM) == QSPI_PMM_OR)) 
+/**
+  * @}
+  */
+  
+/** @defgroup QSPI_Polling_Interval 
+  * @{
+  */
+#define IS_QSPI_PIR(PIR)                 ((PIR) <= QUADSPI_PIR_INTERVAL) 
+/**
+  * @}
+  */
+  
+/** @defgroup QSPI_Timeout 
+  * @{
+  */
+#define IS_QSPI_TIMEOUT(TIMEOUT)         ((TIMEOUT) <= QUADSPI_LPTR_TIMEOUT) 
+/**
+  * @}
+  */
+  
+/** @defgroup QSPI_DummyCycle 
+  * @{
+  */
+#define IS_QSPI_DCY(DCY)                 ((DCY) <= 0x1F) 
+/**
+  * @}
+  */
+  
+/** @defgroup QSPI_FIFOThreshold 
+  * @{
+  */
+#define IS_QSPI_FIFOTHRESHOLD(FIFOTHRESHOLD)        ((FIFOTHRESHOLD) <= 0x0F) 
+/**
+  * @}
+  */  
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Initialization and Configuration functions *********************************/
+void QSPI_DeInit(void);
+void QSPI_Init(QSPI_InitTypeDef* QSPI_InitStruct);
+void QSPI_StructInit(QSPI_InitTypeDef* QSPI_InitStruct);
+void QSPI_ComConfig_Init(QSPI_ComConfig_InitTypeDef* QSPI_ComConfig_InitStruct);
+void QSPI_ComConfig_StructInit(QSPI_ComConfig_InitTypeDef* QSPI_ComConfig_InitStruct);
+void QSPI_Cmd(FunctionalState NewState);
+void QSPI_AutoPollingMode_Config(uint32_t QSPI_Match, uint32_t QSPI_Mask , uint32_t QSPI_Match_Mode);
+void QSPI_AutoPollingMode_SetInterval(uint32_t QSPI_Interval);
+void QSPI_MemoryMappedMode_SetTimeout(uint32_t QSPI_Timeout);
+void QSPI_SetAddress(uint32_t QSPI_Address);
+void QSPI_SetAlternateByte(uint32_t QSPI_AlternateByte);
+void QSPI_SetFIFOThreshold(uint32_t QSPI_FIFOThreshold);
+void QSPI_SetDataLength(uint32_t QSPI_DataLength);
+void QSPI_TimeoutCounterCmd(FunctionalState NewState);
+void QSPI_AutoPollingModeStopCmd(FunctionalState NewState);
+void QSPI_AbortRequest(void);
+void QSPI_DualFlashMode_Cmd(FunctionalState NewState);
+
+/* Data transfers functions ***************************************************/
+void     QSPI_SendData8(uint8_t Data);
+void     QSPI_SendData16(uint16_t Data);
+void     QSPI_SendData32(uint32_t Data);
+uint8_t  QSPI_ReceiveData8(void);
+uint16_t QSPI_ReceiveData16(void);
+uint32_t QSPI_ReceiveData32(void);
+
+/* DMA transfers management functions *****************************************/
+void QSPI_DMACmd(FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void       QSPI_ITConfig(uint32_t QSPI_IT, FunctionalState NewState);
+uint32_t   QSPI_GetFIFOLevel(void);
+FlagStatus QSPI_GetFlagStatus(uint32_t QSPI_FLAG);
+void       QSPI_ClearFlag(uint32_t QSPI_FLAG);
+ITStatus   QSPI_GetITStatus(uint32_t QSPI_IT);
+void       QSPI_ClearITPendingBit(uint32_t QSPI_IT);
+uint32_t   QSPI_GetFMode(void);
+
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4XX_QUADSPI_H */
+

底盘/底盘-old/底盘/Library/stm32f4xx_rng.c

@@ -0,0 +1,398 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_rng.c
+  * @author  MCD Application Team
+  * @version V1.8.1
+  * @date    27-January-2022
+  * @brief This file provides firmware functions to manage the following 
+  *          functionalities of the Random Number Generator (RNG) peripheral:           
+  *           + Initialization and Configuration 
+  *           + Get 32 bit Random number      
+  *           + Interrupts and flags management       
+  *         
+@verbatim
+                                 
+ ===================================================================      
+                 ##### How to use this driver #####
+ ===================================================================          
+ [..]
+   (#) Enable The RNG controller clock using 
+       RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function.
+                
+   (#) Activate the RNG peripheral using RNG_Cmd() function.
+            
+   (#) Wait until the 32 bit Random number Generator contains a valid  random data
+      (using polling/interrupt mode). For more details, refer to "Interrupts and 
+      flags management functions" module description.
+             
+   (#) Get the 32 bit Random number using RNG_GetRandomNumber() function
+            
+   (#) To get another 32 bit Random number, go to step 3.       
+         
+                
+@endverbatim
+  *         
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_rng.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup RNG 
+  * @brief RNG driver modules
+  * @{
+  */ 
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)  
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RNG_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup RNG_Group1 Initialization and Configuration functions
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+             ##### Initialization and Configuration functions #####
+ ===============================================================================  
+ [..] This section provides functions allowing to 
+   (+) Initialize the RNG peripheral
+   (+) Enable or disable the RNG peripheral
+   
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  De-initializes the RNG peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void RNG_DeInit(void)
+{
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)  
+  /* Enable RNG reset state */
+  RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, ENABLE);
+
+  /* Release RNG from reset state */
+  RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, DISABLE);
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
+#if defined(STM32F410xx)
+   /* Enable RNG reset state */
+  RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_RNG, ENABLE);
+
+  /* Release RNG from reset state */
+  RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_RNG, DISABLE); 
+#endif /* STM32F410xx*/  
+}
+
+/**
+  * @brief  Enables or disables the RNG peripheral.
+  * @param  NewState: new state of the RNG peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RNG_Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the RNG */
+    RNG->CR |= RNG_CR_RNGEN;
+  }
+  else
+  {
+    /* Disable the RNG */
+    RNG->CR &= ~RNG_CR_RNGEN;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup RNG_Group2 Get 32 bit Random number function
+ *  @brief    Get 32 bit Random number function 
+ *
+
+@verbatim    
+ ===============================================================================
+                 ##### Get 32 bit Random number function #####
+ ===============================================================================  
+ [..] This section provides a function allowing to get the 32 bit Random number  
+  
+   (@)  Before to call this function you have to wait till DRDY flag is set,
+        using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. 
+   
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Returns a 32-bit random number.
+  *   
+  * @note   Before to call this function you have to wait till DRDY (data ready)
+  *         flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function.
+  * @note   Each time the Random number data is read (using RNG_GetRandomNumber()
+  *         function), the RNG_FLAG_DRDY flag is automatically cleared.
+  * @note   In the case of a seed error, the generation of random numbers is 
+  *         interrupted for as long as the SECS bit is '1'. If a number is 
+  *         available in the RNG_DR register, it must not be used because it may 
+  *         not have enough entropy. In this case, it is recommended to clear the 
+  *         SEIS bit(using RNG_ClearFlag(RNG_FLAG_SECS) function), then disable 
+  *         and enable the RNG peripheral (using RNG_Cmd() function) to 
+  *         reinitialize and restart the RNG.
+  * @note   In the case of a clock error, the RNG is no more able to generate 
+  *         random numbers because the PLL48CLK clock is not correct. User have 
+  *         to check that the clock controller is correctly configured to provide
+  *         the RNG clock and clear the CEIS bit (using RNG_ClearFlag(RNG_FLAG_CECS) 
+  *         function) . The clock error has no impact on the previously generated 
+  *         random numbers, and the RNG_DR register contents can be used.
+  *         
+  * @param  None
+  * @retval 32-bit random number.
+  */
+uint32_t RNG_GetRandomNumber(void)
+{
+  /* Return the 32 bit random number from the DR register */
+  return RNG->DR;
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RNG_Group3 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+             ##### Interrupts and flags management functions #####
+ ===============================================================================  
+
+ [..] This section provides functions allowing to configure the RNG Interrupts and 
+      to get the status and clear flags and Interrupts pending bits.
+  
+ [..] The RNG provides 3 Interrupts sources and 3 Flags:
+  
+ *** Flags : ***
+ ===============
+ [..] 
+    (#) RNG_FLAG_DRDY :  In the case of the RNG_DR register contains valid 
+        random data. it is cleared by reading the valid data(using 
+        RNG_GetRandomNumber() function).
+
+    (#) RNG_FLAG_CECS : In the case of a seed error detection. 
+      
+    (#) RNG_FLAG_SECS : In the case of a clock error detection.
+              
+ *** Interrupts ***
+ ==================
+ [..] If enabled, an RNG interrupt is pending :
+    
+   (#) In the case of the RNG_DR register contains valid random data. 
+       This interrupt source is cleared once the RNG_DR register has been read 
+       (using RNG_GetRandomNumber() function) until a new valid value is 
+       computed; or 
+   (#) In the case of a seed error : One of the following faulty sequences has 
+       been detected:
+       (++) More than 64 consecutive bits at the same value (0 or 1)
+       (++) More than 32 consecutive alternance of 0 and 1 (0101010101...01)
+       This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI)
+       function; or
+   (#) In the case of a clock error : the PLL48CLK (RNG peripheral clock source) 
+       was not correctly detected (fPLL48CLK< fHCLK/16). This interrupt source is
+       cleared using RNG_ClearITPendingBit(RNG_IT_CEI) function.
+       -@- note In this case, User have to check that the clock controller is 
+           correctly configured to provide the RNG clock. 
+
+ *** Managing the RNG controller events : ***
+ ============================================
+ [..] The user should identify which mode will be used in his application to manage 
+      the RNG controller events: Polling mode or Interrupt mode.
+  
+   (#) In the Polling Mode it is advised to use the following functions:
+       (++) RNG_GetFlagStatus() : to check if flags events occur. 
+       (++) RNG_ClearFlag()     : to clear the flags events.
+  
+       -@@- RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only 
+            by reading the Random number data.      
+  
+   (#)  In the Interrupt Mode it is advised to use the following functions:
+        (++) RNG_ITConfig()       : to enable or disable the interrupt source.
+        (++) RNG_GetITStatus()    : to check if Interrupt occurs.
+        (++) RNG_ClearITPendingBit() : to clear the Interrupt pending Bit 
+             (corresponding Flag). 
+  
+@endverbatim
+  * @{
+  */ 
+
+/**
+  * @brief  Enables or disables the RNG interrupt.
+  * @note   The RNG provides 3 interrupt sources,
+  *           - Computed data is ready event (DRDY), and           
+  *           - Seed error Interrupt (SEI) and 
+  *           - Clock error Interrupt (CEI), 
+  *         all these interrupts sources are enabled by setting the IE bit in 
+  *         CR register. However, each interrupt have its specific status bit
+  *         (see RNG_GetITStatus() function) and clear bit except the DRDY event
+  *         (see RNG_ClearITPendingBit() function).
+  * @param  NewState: new state of the RNG interrupt.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RNG_ITConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the RNG interrupt */
+    RNG->CR |= RNG_CR_IE;
+  }
+  else
+  {
+    /* Disable the RNG interrupt */
+    RNG->CR &= ~RNG_CR_IE;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified RNG flag is set or not.
+  * @param  RNG_FLAG: specifies the RNG flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg RNG_FLAG_DRDY: Data Ready flag.
+  *            @arg RNG_FLAG_CECS: Clock Error Current flag.
+  *            @arg RNG_FLAG_SECS: Seed Error Current flag.
+  * @retval The new state of RNG_FLAG (SET or RESET).
+  */
+FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_RNG_GET_FLAG(RNG_FLAG));
+
+  /* Check the status of the specified RNG flag */
+  if ((RNG->SR & RNG_FLAG) != (uint8_t)RESET)
+  {
+    /* RNG_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* RNG_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the RNG_FLAG status */
+  return  bitstatus;
+}
+
+
+/**
+  * @brief  Clears the RNG flags.
+  * @param  RNG_FLAG: specifies the flag to clear. 
+  *          This parameter can be any combination of the following values:
+  *            @arg RNG_FLAG_CECS: Clock Error Current flag.
+  *            @arg RNG_FLAG_SECS: Seed Error Current flag.
+  * @note   RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag() function. 
+  *         This flag is cleared only by reading the Random number data (using 
+  *         RNG_GetRandomNumber() function).                           
+  * @retval None
+  */
+void RNG_ClearFlag(uint8_t RNG_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_RNG_CLEAR_FLAG(RNG_FLAG));
+  /* Clear the selected RNG flags */
+  RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4);
+}
+
+/**
+  * @brief  Checks whether the specified RNG interrupt has occurred or not.
+  * @param  RNG_IT: specifies the RNG interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg RNG_IT_CEI: Clock Error Interrupt.
+  *            @arg RNG_IT_SEI: Seed Error Interrupt.                   
+  * @retval The new state of RNG_IT (SET or RESET).
+  */
+ITStatus RNG_GetITStatus(uint8_t RNG_IT)
+{
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_RNG_GET_IT(RNG_IT));
+
+  /* Check the status of the specified RNG interrupt */
+  if ((RNG->SR & RNG_IT) != (uint8_t)RESET)
+  {
+    /* RNG_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* RNG_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the RNG_IT status */
+  return bitstatus;
+}
+
+
+/**
+  * @brief  Clears the RNG interrupt pending bit(s).
+  * @param  RNG_IT: specifies the RNG interrupt pending bit(s) to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg RNG_IT_CEI: Clock Error Interrupt.
+  *            @arg RNG_IT_SEI: Seed Error Interrupt.
+  * @retval None
+  */
+void RNG_ClearITPendingBit(uint8_t RNG_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_RNG_IT(RNG_IT));
+
+  /* Clear the selected RNG interrupt pending bit */
+  RNG->SR = (uint8_t)~RNG_IT;
+}
+/**
+  * @}
+  */ 
+  
+/**
+  * @}
+  */ 
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F429_439xx || STM32F469_479xx */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+