ADC_IRQHandler ⇒ ADC_IRQHandler
-
-
-
-Function Pointers
-
- - ADC_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- BusFault_Handler from stm32f4xx_it.o(i.BusFault_Handler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- CAN1_RX0_IRQHandler from can.o(i.CAN1_RX0_IRQHandler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- CAN1_RX1_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- CAN1_SCE_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- CAN1_TX_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- CAN2_RX0_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- CAN2_RX1_IRQHandler from can.o(i.CAN2_RX1_IRQHandler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- CAN2_SCE_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- CAN2_TX_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- CRYP_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DCMI_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA1_Stream0_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA1_Stream1_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA1_Stream2_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA1_Stream3_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA1_Stream4_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA1_Stream5_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA1_Stream6_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA1_Stream7_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA2_Stream0_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA2_Stream1_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA2_Stream2_IRQHandler from bmi088.o(i.DMA2_Stream2_IRQHandler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA2_Stream3_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA2_Stream4_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA2_Stream5_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA2_Stream6_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA2_Stream7_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DebugMon_Handler from stm32f4xx_it.o(i.DebugMon_Handler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- ETH_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- ETH_WKUP_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- EXTI0_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- EXTI15_10_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- EXTI1_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- EXTI2_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- EXTI3_IRQHandler from ist8310.o(i.EXTI3_IRQHandler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- EXTI4_IRQHandler from bmi088.o(i.EXTI4_IRQHandler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- EXTI9_5_IRQHandler from bmi088.o(i.EXTI9_5_IRQHandler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- FLASH_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- FPU_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- FSMC_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- HASH_RNG_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- HardFault_Handler from stm32f4xx_it.o(i.HardFault_Handler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- I2C1_ER_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- I2C1_EV_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- I2C2_ER_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- I2C2_EV_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- I2C3_ER_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- I2C3_EV_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- MemManage_Handler from stm32f4xx_it.o(i.MemManage_Handler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- NMI_Handler from stm32f4xx_it.o(i.NMI_Handler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- OTG_FS_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- OTG_FS_WKUP_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- OTG_HS_EP1_IN_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- OTG_HS_EP1_OUT_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- OTG_HS_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- OTG_HS_WKUP_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- PVD_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- PendSV_Handler from stm32f4xx_it.o(i.PendSV_Handler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- RCC_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- RTC_Alarm_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- RTC_WKUP_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- Reset_Handler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- SDIO_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- SPI1_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- SPI2_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- SPI3_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- SVC_Handler from stm32f4xx_it.o(i.SVC_Handler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- SysTick_Handler from stm32f4xx_it.o(i.SysTick_Handler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- SystemInit from system_stm32f4xx.o(i.SystemInit) referenced from startup_stm32f40_41xxx.o(.text)
-
- TAMP_STAMP_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM1_BRK_TIM9_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM1_CC_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM1_TRG_COM_TIM11_IRQHandler from attitudealgorithms.o(i.TIM1_TRG_COM_TIM11_IRQHandler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM1_UP_TIM10_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM2_IRQHandler from tim.o(i.TIM2_IRQHandler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM3_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM4_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM5_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM6_DAC_IRQHandler from closeloopcontrol.o(i.TIM6_DAC_IRQHandler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM7_IRQHandler from remote.o(i.TIM7_IRQHandler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM8_BRK_TIM12_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM8_CC_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM8_TRG_COM_TIM14_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM8_UP_TIM13_IRQHandler from linkcheck.o(i.TIM8_UP_TIM13_IRQHandler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- UART4_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- UART5_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- USART1_IRQHandler from visual.o(i.USART1_IRQHandler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- USART2_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- USART3_IRQHandler from remote.o(i.USART3_IRQHandler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- USART6_IRQHandler from refereesystem.o(i.USART6_IRQHandler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- UsageFault_Handler from stm32f4xx_it.o(i.UsageFault_Handler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- WWDG_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- __main from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f40_41xxx.o(.text)
-
- main from main.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
-
-
-
-Global Symbols
-
-__main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(.text)
-
-_main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))
-
-
_main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
-
[Calls]
-
-__main_after_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
-
[Called By]
-
-_main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))
-
-
_main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))
-
-
_main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))
-
-
__rt_lib_shutdown_fini (Thumb, 0 bytes, Stack size unknown bytes, entry12b.o(.ARM.Collect$$$$0000000E))
-
-
__rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000F))
-
-
__rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$00000011))
-
-
Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-ADC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-CAN2_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-CAN2_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-CAN2_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-CRYP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DCMI_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA1_Stream0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA1_Stream1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA1_Stream2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA1_Stream3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA1_Stream4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA1_Stream5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA1_Stream6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA1_Stream7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA2_Stream0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA2_Stream1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA2_Stream3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA2_Stream4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA2_Stream5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA2_Stream6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA2_Stream7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-ETH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-ETH_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-FPU_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-FSMC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-HASH_RNG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-I2C3_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-I2C3_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-OTG_FS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-OTG_FS_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-OTG_HS_EP1_IN_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-OTG_HS_EP1_OUT_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-OTG_HS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-OTG_HS_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-RTC_Alarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-RTC_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-SDIO_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-SPI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-TAMP_STAMP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-TIM1_BRK_TIM9_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-TIM1_UP_TIM10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-TIM5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-TIM8_BRK_TIM12_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-TIM8_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-TIM8_TRG_COM_TIM14_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-UART4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-UART5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-__aeabi_ldivmod (Thumb, 98 bytes, Stack size 24 bytes, ldiv.o(.text))
-
[Stack]
- Max Depth = 64
- Call Chain = __aeabi_ldivmod ⇒ __aeabi_uldivmod
-
-
[Calls]
-
[Called By]- >> M3508_CANDataProcess
-
- >> M2006_CANDataProcess
-
-
-__aeabi_memset (Thumb, 14 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
-
[Called By]
- >> _memset$wrapper
-
- >> __aeabi_memclr
-
-
-__aeabi_memset4 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
-
-
__aeabi_memset8 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
-
-
__aeabi_memclr (Thumb, 4 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
-
[Calls]
-
-__aeabi_memclr4 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text))
-
[Called By]
-
-__aeabi_memclr8 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
-
-
_memset$wrapper (Thumb, 18 bytes, Stack size 8 bytes, memseta.o(.text), UNUSED)
-
[Calls]
-
-__aeabi_l2f (Thumb, 44 bytes, Stack size 16 bytes, ffltl.o(.text))
-
[Stack]
- Max Depth = 20
- Call Chain = __aeabi_l2f ⇒ _float_epilogue
-
-
[Calls]
-
[Called By]- >> M3508_CANDataProcess
-
- >> M2006_CANDataProcess
-
- >> TIM1_TRG_COM_TIM11_IRQHandler
-
-
-__aeabi_f2lz (Thumb, 66 bytes, Stack size 8 bytes, ffixl.o(.text))
-
[Stack]
- Max Depth = 8
- Call Chain = __aeabi_f2lz
-
-
[Calls]
-
[Called By]- >> M3508_CANDataProcess
-
- >> M2006_CANDataProcess
-
-
-__aeabi_uldivmod (Thumb, 98 bytes, Stack size 40 bytes, uldiv.o(.text))
-
[Stack]
- Max Depth = 40
- Call Chain = __aeabi_uldivmod
-
-
[Calls]- >> __aeabi_llsr
-
- >> __aeabi_llsl
-
-
[Called By]
-
-__aeabi_llsl (Thumb, 30 bytes, Stack size 0 bytes, llshl.o(.text))
-
[Called By]
- >> __aeabi_f2lz
-
- >> __aeabi_uldivmod
-
-
-_ll_shift_l (Thumb, 0 bytes, Stack size 0 bytes, llshl.o(.text), UNUSED)
-
-
__I$use$fp (Thumb, 0 bytes, Stack size 0 bytes, iusefp.o(.text), UNUSED)
-
-
_float_round (Thumb, 18 bytes, Stack size 0 bytes, fepilogue.o(.text), UNUSED)
-
-
_float_epilogue (Thumb, 92 bytes, Stack size 4 bytes, fepilogue.o(.text))
-
[Stack]
- Max Depth = 4
- Call Chain = _float_epilogue
-
-
[Called By]
-
-__scatterload (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
-
[Calls]
- >> __main_after_scatterload
-
-
[Called By]
-
-__scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)
-
-
__aeabi_llsr (Thumb, 32 bytes, Stack size 0 bytes, llushr.o(.text))
-
[Called By]
-
-_ll_ushift_r (Thumb, 0 bytes, Stack size 0 bytes, llushr.o(.text), UNUSED)
-
-
__decompress (Thumb, 0 bytes, Stack size unknown bytes, __dczerorl2.o(.text), UNUSED)
-
-
__decompress1 (Thumb, 86 bytes, Stack size unknown bytes, __dczerorl2.o(.text), UNUSED)
-
-
AHRS_asinf (Thumb, 24 bytes, Stack size 16 bytes, ahrs_middleware.o(i.AHRS_asinf))
-
[Stack]
- Max Depth = 48
- Call Chain = AHRS_asinf ⇒ __hardfp_asinf ⇒ sqrtf
-
-
[Calls]
-
[Called By]- >> get_angle
-
- >> AHRS_init
-
-
-AHRS_atan2f (Thumb, 32 bytes, Stack size 16 bytes, ahrs_middleware.o(i.AHRS_atan2f))
-
[Stack]
- Max Depth = 48
- Call Chain = AHRS_atan2f ⇒ __hardfp_atan2f
-
-
[Calls]
-
[Called By]- >> get_angle
-
- >> AHRS_init
-
-
-AHRS_cosf (Thumb, 24 bytes, Stack size 16 bytes, ahrs_middleware.o(i.AHRS_cosf))
-
[Stack]
- Max Depth = 44
- Call Chain = AHRS_cosf ⇒ __hardfp_cosf ⇒ __mathlib_rredf2
-
-
[Calls]
-
[Called By]- >> AHRS_init
-
- >> angle_to_quat
-
-
-AHRS_get_height (Thumb, 12 bytes, Stack size 0 bytes, ahrs_middleware.o(i.AHRS_get_height))
-
[Called By]
-
-AHRS_get_latitude (Thumb, 12 bytes, Stack size 0 bytes, ahrs_middleware.o(i.AHRS_get_latitude))
-
[Called By]
-
-AHRS_init (Thumb, 626 bytes, Stack size 80 bytes, ahrs.o(i.AHRS_init))
-
[Stack]
- Max Depth = 180
- Call Chain = AHRS_init ⇒ angle_to_quat ⇒ AHRS_sinf ⇒ __hardfp_sinf ⇒ __mathlib_rredf2
-
-
[Calls]- >> AHRS_sinf
-
- >> AHRS_invSqrt
-
- >> AHRS_get_latitude
-
- >> AHRS_get_height
-
- >> AHRS_cosf
-
- >> AHRS_atan2f
-
- >> AHRS_asinf
-
- >> angle_to_quat
-
-
[Called By]- >> AttitudeAlgorithms_Init
-
-
-AHRS_invSqrt (Thumb, 36 bytes, Stack size 16 bytes, ahrs_middleware.o(i.AHRS_invSqrt))
-
[Stack]
- Max Depth = 32
- Call Chain = AHRS_invSqrt ⇒ __hardfp_sqrtf
-
-
[Calls]
-
[Called By]- >> AHRS_init
-
- >> quat_normalization
-
- >> accel_update_kp_ki
-
- >> accel_comple_filter
-
-
-AHRS_sinf (Thumb, 24 bytes, Stack size 16 bytes, ahrs_middleware.o(i.AHRS_sinf))
-
[Stack]
- Max Depth = 52
- Call Chain = AHRS_sinf ⇒ __hardfp_sinf ⇒ __mathlib_rredf2
-
-
[Calls]
-
[Called By]- >> AHRS_init
-
- >> angle_to_quat
-
-
-AHRS_update (Thumb, 314 bytes, Stack size 136 bytes, ahrs.o(i.AHRS_update))
-
[Stack]
- Max Depth = 272
- Call Chain = AHRS_update ⇒ accel_comple_filter ⇒ accel_update_kp_ki ⇒ AHRS_invSqrt ⇒ __hardfp_sqrtf
-
-
[Calls]- >> __aeabi_memclr4
-
- >> update_w
-
- >> quat_normalization
-
- >> accel_comple_filter
-
-
[Called By]- >> TIM1_TRG_COM_TIM11_IRQHandler
-
-
-AttitudeAlgorithms_Init (Thumb, 134 bytes, Stack size 24 bytes, attitudealgorithms.o(i.AttitudeAlgorithms_Init))
-
[Stack]
- Max Depth = 204
- Call Chain = AttitudeAlgorithms_Init ⇒ AHRS_init ⇒ angle_to_quat ⇒ AHRS_sinf ⇒ __hardfp_sinf ⇒ __mathlib_rredf2
-
-
[Calls]- >> NVIC_PriorityGroupConfig
-
- >> NVIC_Init
-
- >> RCC_APB2PeriphClockCmd
-
- >> IST8310_Init
-
- >> BMI088_Init
-
- >> TIM_TimeBaseInit
-
- >> TIM_InternalClockConfig
-
- >> TIM_ITConfig
-
- >> TIM_Cmd
-
- >> TIM_ClearFlag
-
- >> AHRS_init
-
-
[Called By]
-
-BMI088_CheckAndCloseDMA (Thumb, 76 bytes, Stack size 8 bytes, bmi088.o(i.BMI088_CheckAndCloseDMA))
-
[Stack]
- Max Depth = 20
- Call Chain = BMI088_CheckAndCloseDMA ⇒ DMA_GetFlagStatus
-
-
[Calls]- >> DMA_GetFlagStatus
-
- >> DMA_Cmd
-
- >> DMA_ClearFlag
-
- >> SPI_I2S_GetFlagStatus
-
-
[Called By]- >> EXTI9_5_IRQHandler
-
- >> EXTI4_IRQHandler
-
- >> DMA2_Stream2_IRQHandler
-
-
-BMI088_Delay_us (Thumb, 74 bytes, Stack size 0 bytes, bmi088.o(i.BMI088_Delay_us))
-
[Called By]
-
-BMI088_Init (Thumb, 868 bytes, Stack size 104 bytes, bmi088.o(i.BMI088_Init))
-
[Stack]
- Max Depth = 124
- Call Chain = BMI088_Init ⇒ GPIO_PinAFConfig
-
-
[Calls]- >> NVIC_PriorityGroupConfig
-
- >> NVIC_Init
-
- >> DMA_Init
-
- >> DMA_ITConfig
-
- >> DMA_Cmd
-
- >> GPIO_WriteBit
-
- >> GPIO_PinAFConfig
-
- >> GPIO_Init
-
- >> EXTI_Init
-
- >> RCC_APB2PeriphClockCmd
-
- >> RCC_AHB1PeriphClockCmd
-
- >> SYSCFG_EXTILineConfig
-
- >> SPI_Init
-
- >> SPI_I2S_DMACmd
-
- >> SPI_Cmd
-
- >> Warming_BMI088LinkError
-
- >> BMI088_SPI_GyroWriteRegister
-
- >> BMI088_SPI_GyroReadRegister
-
- >> BMI088_SPI_AccelWriteRegister
-
- >> BMI088_SPI_AccelReadRegister
-
- >> BMI088_Delay_us
-
- >> Delay_ms
-
-
[Called By]- >> AttitudeAlgorithms_Init
-
-
-BMI088_OpenDMA (Thumb, 68 bytes, Stack size 8 bytes, bmi088.o(i.BMI088_OpenDMA))
-
[Stack]
- Max Depth = 8
- Call Chain = BMI088_OpenDMA
-
-
[Calls]- >> DMA_SetCurrDataCounter
-
- >> DMA_GetCmdStatus
-
- >> DMA_Cmd
-
-
[Called By]- >> EXTI9_5_IRQHandler
-
- >> EXTI4_IRQHandler
-
- >> DMA2_Stream2_IRQHandler
-
-
-BMI088_ProcessAccelData (Thumb, 140 bytes, Stack size 0 bytes, bmi088.o(i.BMI088_ProcessAccelData))
-
[Called By]
- >> DMA2_Stream2_IRQHandler
-
-
-BMI088_ProcessGyroData (Thumb, 140 bytes, Stack size 0 bytes, bmi088.o(i.BMI088_ProcessGyroData))
-
[Called By]
- >> DMA2_Stream2_IRQHandler
-
-
-BMI088_ProcessTemperatureData (Thumb, 72 bytes, Stack size 0 bytes, bmi088.o(i.BMI088_ProcessTemperatureData))
-
[Called By]
- >> DMA2_Stream2_IRQHandler
-
-
-BMI088_SPI_AccelReadRegister (Thumb, 156 bytes, Stack size 8 bytes, bmi088.o(i.BMI088_SPI_AccelReadRegister))
-
[Stack]
- Max Depth = 8
- Call Chain = BMI088_SPI_AccelReadRegister
-
-
[Calls]- >> GPIO_WriteBit
-
- >> SPI_I2S_SendData
-
- >> SPI_I2S_ReceiveData
-
- >> SPI_I2S_GetFlagStatus
-
-
[Called By]
-
-BMI088_SPI_AccelWriteRegister (Thumb, 114 bytes, Stack size 16 bytes, bmi088.o(i.BMI088_SPI_AccelWriteRegister))
-
[Stack]
- Max Depth = 16
- Call Chain = BMI088_SPI_AccelWriteRegister
-
-
[Calls]- >> GPIO_WriteBit
-
- >> SPI_I2S_SendData
-
- >> SPI_I2S_ReceiveData
-
- >> SPI_I2S_GetFlagStatus
-
-
[Called By]
-
-BMI088_SPI_GyroReadRegister (Thumb, 114 bytes, Stack size 8 bytes, bmi088.o(i.BMI088_SPI_GyroReadRegister))
-
[Stack]
- Max Depth = 8
- Call Chain = BMI088_SPI_GyroReadRegister
-
-
[Calls]- >> GPIO_WriteBit
-
- >> SPI_I2S_SendData
-
- >> SPI_I2S_ReceiveData
-
- >> SPI_I2S_GetFlagStatus
-
-
[Called By]
-
-BMI088_SPI_GyroWriteRegister (Thumb, 114 bytes, Stack size 16 bytes, bmi088.o(i.BMI088_SPI_GyroWriteRegister))
-
[Stack]
- Max Depth = 16
- Call Chain = BMI088_SPI_GyroWriteRegister
-
-
[Calls]- >> GPIO_WriteBit
-
- >> SPI_I2S_SendData
-
- >> SPI_I2S_ReceiveData
-
- >> SPI_I2S_GetFlagStatus
-
-
[Called By]
-
-BusFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.BusFault_Handler))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-Buzzer_Init (Thumb, 156 bytes, Stack size 48 bytes, buzzer.o(i.Buzzer_Init))
-
[Stack]
- Max Depth = 68
- Call Chain = Buzzer_Init ⇒ GPIO_PinAFConfig
-
-
[Calls]- >> GPIO_PinAFConfig
-
- >> GPIO_Init
-
- >> RCC_APB1PeriphClockCmd
-
- >> RCC_AHB1PeriphClockCmd
-
- >> TIM_TimeBaseInit
-
- >> TIM_OCStructInit
-
- >> TIM_OC3Init
-
- >> TIM_InternalClockConfig
-
- >> TIM_Cmd
-
-
[Called By]
-
-Buzzer_ON (Thumb, 50 bytes, Stack size 8 bytes, buzzer.o(i.Buzzer_ON))
-
[Stack]
- Max Depth = 8
- Call Chain = Buzzer_ON
-
-
[Calls]- >> TIM_SetCompare3
-
- >> TIM_PrescalerConfig
-
- >> TIM_Cmd
-
-
[Called By]- >> Warming_BuzzerClean
-
- >> Warming_LinkError
-
-
-CAN1_RX0_IRQHandler (Thumb, 320 bytes, Stack size 16 bytes, can.o(i.CAN1_RX0_IRQHandler))
-
[Stack]
- Max Depth = 104
- Call Chain = CAN1_RX0_IRQHandler ⇒ M3508_CANDataProcess ⇒ __aeabi_ldivmod ⇒ __aeabi_uldivmod
-
-
[Calls]- >> CAN_GetITStatus
-
- >> CAN_ClearITPendingBit
-
- >> Warming_BuzzerClean
-
- >> M3508_CANDataProcess
-
- >> M2006_CANDataProcess
-
- >> LinkCheck_ON
-
- >> LinkCheck_OFF
-
- >> GM6020_CANDataProcess
-
- >> CAN_CAN2ChangeID
-
- >> CAN_CAN1Receive
-
- >> CAN_CAN1ChangeID
-
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-CAN2_RX1_IRQHandler (Thumb, 334 bytes, Stack size 16 bytes, can.o(i.CAN2_RX1_IRQHandler))
-
[Stack]
- Max Depth = 56
- Call Chain = CAN2_RX1_IRQHandler ⇒ CAN_CAN2Receive ⇒ CAN_Receive
-
-
[Calls]- >> CAN_GetITStatus
-
- >> CAN_ClearITPendingBit
-
- >> Warming_BuzzerClean
-
- >> LinkCheck_ON
-
- >> LinkCheck_OFF
-
- >> GM6020_CANDataProcess
-
- >> CToC_CANDataProcess
-
- >> CAN_CAN2Receive
-
- >> CAN_CAN2ChangeID
-
- >> CAN_CAN1ChangeID
-
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-CAN_CAN1ChangeID (Thumb, 50 bytes, Stack size 0 bytes, can.o(i.CAN_CAN1ChangeID))
-
[Called By]
- >> CAN_CAN_GetRefereeSystemData
-
- >> CAN_CANIDReset
-
- >> CAN2_RX1_IRQHandler
-
- >> CAN1_RX0_IRQHandler
-
-
-CAN_CAN1Receive (Thumb, 54 bytes, Stack size 32 bytes, can.o(i.CAN_CAN1Receive))
-
[Stack]
- Max Depth = 40
- Call Chain = CAN_CAN1Receive ⇒ CAN_Receive
-
-
[Calls]- >> CAN_Receive
-
- >> CAN_MessagePending
-
-
[Called By]
-
-CAN_CAN2ChangeID (Thumb, 50 bytes, Stack size 0 bytes, can.o(i.CAN_CAN2ChangeID))
-
[Called By]
- >> CAN_CAN_GetRefereeSystemData
-
- >> CAN_CANIDReset
-
- >> CAN2_RX1_IRQHandler
-
- >> CAN1_RX0_IRQHandler
-
-
-CAN_CAN2Receive (Thumb, 54 bytes, Stack size 32 bytes, can.o(i.CAN_CAN2Receive))
-
[Stack]
- Max Depth = 40
- Call Chain = CAN_CAN2Receive ⇒ CAN_Receive
-
-
[Calls]- >> CAN_Receive
-
- >> CAN_MessagePending
-
-
[Called By]
-
-CAN_CANIDReset (Thumb, 24 bytes, Stack size 4 bytes, can.o(i.CAN_CANIDReset))
-
[Stack]
- Max Depth = 4
- Call Chain = CAN_CANIDReset
-
-
[Calls]- >> CAN_CAN2ChangeID
-
- >> CAN_CAN1ChangeID
-
-
[Called By]- >> TIM8_UP_TIM13_IRQHandler
-
-
-CAN_CANInit (Thumb, 378 bytes, Stack size 48 bytes, can.o(i.CAN_CANInit))
-
[Stack]
- Max Depth = 68
- Call Chain = CAN_CANInit ⇒ GPIO_PinAFConfig
-
-
[Calls]- >> CAN_Init
-
- >> CAN_ITConfig
-
- >> CAN_FilterInit
-
- >> NVIC_PriorityGroupConfig
-
- >> NVIC_Init
-
- >> GPIO_PinAFConfig
-
- >> GPIO_Init
-
- >> RCC_APB1PeriphClockCmd
-
- >> RCC_AHB1PeriphClockCmd
-
-
[Called By]
-
-CAN_CAN_GetRefereeSystemData (Thumb, 24 bytes, Stack size 4 bytes, can.o(i.CAN_CAN_GetRefereeSystemData))
-
[Stack]
- Max Depth = 4
- Call Chain = CAN_CAN_GetRefereeSystemData
-
-
[Calls]- >> CAN_CAN2ChangeID
-
- >> CAN_CAN1ChangeID
-
-
[Called By]- >> TIM8_UP_TIM13_IRQHandler
-
-
-CAN_ClearITPendingBit (Thumb, 162 bytes, Stack size 0 bytes, stm32f4xx_can.o(i.CAN_ClearITPendingBit))
-
[Called By]
- >> CAN2_RX1_IRQHandler
-
- >> CAN1_RX0_IRQHandler
-
-
-CAN_FilterInit (Thumb, 258 bytes, Stack size 8 bytes, stm32f4xx_can.o(i.CAN_FilterInit))
-
[Stack]
- Max Depth = 8
- Call Chain = CAN_FilterInit
-
-
[Called By]
-
-CAN_GetITStatus (Thumb, 284 bytes, Stack size 16 bytes, stm32f4xx_can.o(i.CAN_GetITStatus))
-
[Stack]
- Max Depth = 16
- Call Chain = CAN_GetITStatus
-
-
[Calls]
-
[Called By]- >> CAN2_RX1_IRQHandler
-
- >> CAN1_RX0_IRQHandler
-
-
-CAN_ITConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f4xx_can.o(i.CAN_ITConfig))
-
[Called By]
-
-CAN_Init (Thumb, 276 bytes, Stack size 12 bytes, stm32f4xx_can.o(i.CAN_Init))
-
[Stack]
- Max Depth = 12
- Call Chain = CAN_Init
-
-
[Called By]
-
-CAN_MessagePending (Thumb, 30 bytes, Stack size 0 bytes, stm32f4xx_can.o(i.CAN_MessagePending))
-
[Called By]
- >> CAN_CAN2Receive
-
- >> CAN_CAN1Receive
-
-
-CAN_Receive (Thumb, 232 bytes, Stack size 8 bytes, stm32f4xx_can.o(i.CAN_Receive))
-
[Stack]
- Max Depth = 8
- Call Chain = CAN_Receive
-
-
[Called By]- >> CAN_CAN2Receive
-
- >> CAN_CAN1Receive
-
-
-CAN_Transmit (Thumb, 294 bytes, Stack size 8 bytes, stm32f4xx_can.o(i.CAN_Transmit))
-
[Stack]
- Max Depth = 8
- Call Chain = CAN_Transmit
-
-
[Called By]- >> CToC_MasterSendData
-
- >> CToC_MasterSendControl
-
- >> M2006_CANSetHIDCurrent
-
- >> GM6020_CAN2SetLIDVoltage
-
- >> M3508_CANSetLIDCurrent
-
-
-CAN_TransmitStatus (Thumb, 138 bytes, Stack size 8 bytes, stm32f4xx_can.o(i.CAN_TransmitStatus))
-
[Stack]
- Max Depth = 8
- Call Chain = CAN_TransmitStatus
-
-
[Called By]- >> CToC_MasterSendData
-
- >> CToC_MasterSendControl
-
- >> M2006_CANSetHIDCurrent
-
- >> GM6020_CAN2SetLIDVoltage
-
- >> M3508_CANSetLIDCurrent
-
-
-CToC_CANDataProcess (Thumb, 38 bytes, Stack size 0 bytes, ctoc.o(i.CToC_CANDataProcess))
-
[Called By]
-
-CToC_MasterSendControl (Thumb, 138 bytes, Stack size 32 bytes, ctoc.o(i.CToC_MasterSendControl))
-
[Stack]
- Max Depth = 40
- Call Chain = CToC_MasterSendControl ⇒ CAN_TransmitStatus
-
-
[Calls]- >> CAN_TransmitStatus
-
- >> CAN_Transmit
-
-
[Called By]
-
-CToC_MasterSendData (Thumb, 478 bytes, Stack size 32 bytes, ctoc.o(i.CToC_MasterSendData))
-
[Stack]
- Max Depth = 40
- Call Chain = CToC_MasterSendData ⇒ CAN_TransmitStatus
-
-
[Calls]- >> CAN_TransmitStatus
-
- >> CAN_Transmit
-
-
[Called By]
-
-CloseLoopControl_Init (Thumb, 126 bytes, Stack size 24 bytes, closeloopcontrol.o(i.CloseLoopControl_Init))
-
[Stack]
- Max Depth = 68
- Call Chain = CloseLoopControl_Init ⇒ Gimbal_Init ⇒ Laser_Init ⇒ GPIO_Init
-
-
[Calls]- >> NVIC_PriorityGroupConfig
-
- >> NVIC_Init
-
- >> RCC_APB1PeriphClockCmd
-
- >> TIM_TimeBaseInit
-
- >> TIM_InternalClockConfig
-
- >> TIM_ITConfig
-
- >> TIM_Cmd
-
- >> TIM_ClearFlag
-
- >> IMUTemperatureControl_PIDInit
-
- >> Gimbal_Init
-
-
[Called By]
-
-DMA2_Stream2_IRQHandler (Thumb, 136 bytes, Stack size 8 bytes, bmi088.o(i.DMA2_Stream2_IRQHandler))
-
[Stack]
- Max Depth = 28
- Call Chain = DMA2_Stream2_IRQHandler ⇒ BMI088_CheckAndCloseDMA ⇒ DMA_GetFlagStatus
-
-
[Calls]- >> DMA_GetITStatus
-
- >> DMA_ClearITPendingBit
-
- >> GPIO_WriteBit
-
- >> BMI088_ProcessTemperatureData
-
- >> BMI088_ProcessGyroData
-
- >> BMI088_ProcessAccelData
-
- >> BMI088_OpenDMA
-
- >> BMI088_CheckAndCloseDMA
-
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-DMA_ClearFlag (Thumb, 38 bytes, Stack size 0 bytes, stm32f4xx_dma.o(i.DMA_ClearFlag))
-
[Called By]
- >> BMI088_CheckAndCloseDMA
-
- >> Remote_TransferReset
-
-
-DMA_ClearITPendingBit (Thumb, 38 bytes, Stack size 0 bytes, stm32f4xx_dma.o(i.DMA_ClearITPendingBit))
-
[Called By]
- >> DMA2_Stream2_IRQHandler
-
-
-DMA_Cmd (Thumb, 22 bytes, Stack size 0 bytes, stm32f4xx_dma.o(i.DMA_Cmd))
-
[Called By]
- >> EXTI9_5_IRQHandler
-
- >> EXTI4_IRQHandler
-
- >> BMI088_OpenDMA
-
- >> BMI088_Init
-
- >> BMI088_CheckAndCloseDMA
-
- >> Remote_TransferReset
-
- >> Remote_Init
-
-
-DMA_DoubleBufferModeCmd (Thumb, 22 bytes, Stack size 0 bytes, stm32f4xx_dma.o(i.DMA_DoubleBufferModeCmd))
-
[Called By]
-
-DMA_DoubleBufferModeConfig (Thumb, 24 bytes, Stack size 0 bytes, stm32f4xx_dma.o(i.DMA_DoubleBufferModeConfig))
-
[Called By]
-
-DMA_GetCmdStatus (Thumb, 20 bytes, Stack size 0 bytes, stm32f4xx_dma.o(i.DMA_GetCmdStatus))
-
[Called By]
- >> BMI088_OpenDMA
-
- >> Remote_TransferReset
-
-
-DMA_GetCurrDataCounter (Thumb, 8 bytes, Stack size 0 bytes, stm32f4xx_dma.o(i.DMA_GetCurrDataCounter))
-
[Called By]
-
-DMA_GetCurrentMemoryTarget (Thumb, 20 bytes, Stack size 0 bytes, stm32f4xx_dma.o(i.DMA_GetCurrentMemoryTarget))
-
[Called By]
-
-DMA_GetFlagStatus (Thumb, 54 bytes, Stack size 12 bytes, stm32f4xx_dma.o(i.DMA_GetFlagStatus))
-
[Stack]
- Max Depth = 12
- Call Chain = DMA_GetFlagStatus
-
-
[Called By]- >> BMI088_CheckAndCloseDMA
-
- >> Remote_TransferReset
-
-
-DMA_GetITStatus (Thumb, 82 bytes, Stack size 16 bytes, stm32f4xx_dma.o(i.DMA_GetITStatus))
-
[Stack]
- Max Depth = 16
- Call Chain = DMA_GetITStatus
-
-
[Called By]- >> DMA2_Stream2_IRQHandler
-
-
-DMA_ITConfig (Thumb, 58 bytes, Stack size 8 bytes, stm32f4xx_dma.o(i.DMA_ITConfig))
-
[Stack]
- Max Depth = 8
- Call Chain = DMA_ITConfig
-
-
[Called By]
-
-DMA_Init (Thumb, 82 bytes, Stack size 8 bytes, stm32f4xx_dma.o(i.DMA_Init))
-
[Stack]
- Max Depth = 8
- Call Chain = DMA_Init
-
-
[Called By]- >> BMI088_Init
-
- >> Remote_Init
-
-
-DMA_SetCurrDataCounter (Thumb, 4 bytes, Stack size 0 bytes, stm32f4xx_dma.o(i.DMA_SetCurrDataCounter))
-
[Called By]
- >> BMI088_OpenDMA
-
- >> Remote_TransferReset
-
-
-DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.DebugMon_Handler))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-Delay_ms (Thumb, 24 bytes, Stack size 8 bytes, delay.o(i.Delay_ms))
-
[Stack]
- Max Depth = 8
- Call Chain = Delay_ms
-
-
[Calls]
-
[Called By]- >> IST8310_Init
-
- >> BMI088_Init
-
- >> Delay_s
-
-
-Delay_s (Thumb, 24 bytes, Stack size 8 bytes, delay.o(i.Delay_s))
-
[Stack]
- Max Depth = 16
- Call Chain = Delay_s ⇒ Delay_ms
-
-
[Calls]
-
[Called By]
-
-Delay_us (Thumb, 74 bytes, Stack size 0 bytes, delay.o(i.Delay_us))
-
[Called By]
-
-EXTI3_IRQHandler (Thumb, 30 bytes, Stack size 8 bytes, ist8310.o(i.EXTI3_IRQHandler))
-
[Stack]
- Max Depth = 96
- Call Chain = EXTI3_IRQHandler ⇒ IST8310_GetData ⇒ MyI2C_ContinuousReadRegister ⇒ MyI2C_SendAck ⇒ MyI2C_SDA
-
-
[Calls]- >> EXTI_GetITStatus
-
- >> EXTI_ClearITPendingBit
-
- >> IST8310_GetData
-
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-EXTI4_IRQHandler (Thumb, 114 bytes, Stack size 8 bytes, bmi088.o(i.EXTI4_IRQHandler))
-
[Stack]
- Max Depth = 28
- Call Chain = EXTI4_IRQHandler ⇒ BMI088_CheckAndCloseDMA ⇒ DMA_GetFlagStatus
-
-
[Calls]- >> DMA_Cmd
-
- >> GPIO_WriteBit
-
- >> EXTI_GetITStatus
-
- >> EXTI_ClearITPendingBit
-
- >> BMI088_OpenDMA
-
- >> BMI088_CheckAndCloseDMA
-
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-EXTI9_5_IRQHandler (Thumb, 114 bytes, Stack size 8 bytes, bmi088.o(i.EXTI9_5_IRQHandler))
-
[Stack]
- Max Depth = 28
- Call Chain = EXTI9_5_IRQHandler ⇒ BMI088_CheckAndCloseDMA ⇒ DMA_GetFlagStatus
-
-
[Calls]- >> DMA_Cmd
-
- >> GPIO_WriteBit
-
- >> EXTI_GetITStatus
-
- >> EXTI_ClearITPendingBit
-
- >> BMI088_OpenDMA
-
- >> BMI088_CheckAndCloseDMA
-
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-EXTI_ClearITPendingBit (Thumb, 6 bytes, Stack size 0 bytes, stm32f4xx_exti.o(i.EXTI_ClearITPendingBit))
-
[Called By]
- >> EXTI3_IRQHandler
-
- >> EXTI9_5_IRQHandler
-
- >> EXTI4_IRQHandler
-
-
-EXTI_GetITStatus (Thumb, 20 bytes, Stack size 0 bytes, stm32f4xx_exti.o(i.EXTI_GetITStatus))
-
[Called By]
- >> EXTI3_IRQHandler
-
- >> EXTI9_5_IRQHandler
-
- >> EXTI4_IRQHandler
-
-
-EXTI_Init (Thumb, 142 bytes, Stack size 0 bytes, stm32f4xx_exti.o(i.EXTI_Init))
-
[Called By]
- >> IST8310_Init
-
- >> BMI088_Init
-
-
-GM6020_CAN2SetLIDVoltage (Thumb, 146 bytes, Stack size 48 bytes, gm6020.o(i.GM6020_CAN2SetLIDVoltage))
-
[Stack]
- Max Depth = 56
- Call Chain = GM6020_CAN2SetLIDVoltage ⇒ CAN_TransmitStatus
-
-
[Calls]- >> CAN_TransmitStatus
-
- >> CAN_Transmit
-
-
[Called By]- >> Gimbal_YawControl
-
- >> Warming_MotorControl
-
-
-GM6020_CANDataProcess (Thumb, 352 bytes, Stack size 20 bytes, gm6020.o(i.GM6020_CANDataProcess))
-
[Stack]
- Max Depth = 20
- Call Chain = GM6020_CANDataProcess
-
-
[Called By]- >> CAN2_RX1_IRQHandler
-
- >> CAN1_RX0_IRQHandler
-
-
-GPIO_Init (Thumb, 144 bytes, Stack size 20 bytes, stm32f4xx_gpio.o(i.GPIO_Init))
-
[Stack]
- Max Depth = 20
- Call Chain = GPIO_Init
-
-
[Called By]- >> Laser_Init
-
- >> IST8310_Init
-
- >> BMI088_Init
-
- >> Remote_Init
-
- >> Buzzer_Init
-
- >> LED_Init
-
- >> CAN_CANInit
-
- >> MyI2C_Init
-
- >> UART2_SendInit
-
- >> UART1_Init
-
-
-GPIO_PinAFConfig (Thumb, 70 bytes, Stack size 20 bytes, stm32f4xx_gpio.o(i.GPIO_PinAFConfig))
-
[Stack]
- Max Depth = 20
- Call Chain = GPIO_PinAFConfig
-
-
[Called By]- >> BMI088_Init
-
- >> Remote_Init
-
- >> Buzzer_Init
-
- >> CAN_CANInit
-
- >> UART2_SendInit
-
- >> UART1_Init
-
-
-GPIO_ReadInputDataBit (Thumb, 18 bytes, Stack size 0 bytes, stm32f4xx_gpio.o(i.GPIO_ReadInputDataBit))
-
[Called By]
-
-GPIO_ResetBits (Thumb, 6 bytes, Stack size 0 bytes, stm32f4xx_gpio.o(i.GPIO_ResetBits))
-
[Called By]
- >> Laser_OFF
-
- >> Laser_Init
-
- >> LED_ROFF
-
- >> LED_Init
-
- >> LED_GOFF
-
- >> LED_BOFF
-
-
-GPIO_SetBits (Thumb, 4 bytes, Stack size 0 bytes, stm32f4xx_gpio.o(i.GPIO_SetBits))
-
[Called By]
- >> Laser_ON
-
- >> LED_RON
-
- >> LED_GON
-
- >> LED_BON
-
-
-GPIO_WriteBit (Thumb, 12 bytes, Stack size 0 bytes, stm32f4xx_gpio.o(i.GPIO_WriteBit))
-
[Called By]
- >> IST8310_RSTN
-
- >> EXTI9_5_IRQHandler
-
- >> EXTI4_IRQHandler
-
- >> DMA2_Stream2_IRQHandler
-
- >> BMI088_SPI_GyroWriteRegister
-
- >> BMI088_SPI_GyroReadRegister
-
- >> BMI088_SPI_AccelWriteRegister
-
- >> BMI088_SPI_AccelReadRegister
-
- >> BMI088_Init
-
- >> MyI2C_SDA
-
- >> MyI2C_SCL
-
-
-Gimbal_CleanPID (Thumb, 46 bytes, Stack size 8 bytes, gimbal.o(i.Gimbal_CleanPID))
-
[Stack]
- Max Depth = 8
- Call Chain = Gimbal_CleanPID
-
-
[Calls]
-
[Called By]
-
-Gimbal_FiringMechanismControl (Thumb, 182 bytes, Stack size 8 bytes, gimbal.o(i.Gimbal_FiringMechanismControl))
-
[Stack]
- Max Depth = 64
- Call Chain = Gimbal_FiringMechanismControl ⇒ M3508_CANSetLIDCurrent ⇒ CAN_TransmitStatus
-
-
[Calls]- >> Laser_ON
-
- >> Laser_OFF
-
- >> PID_PositionCalc
-
- >> M3508_CANSetLIDCurrent
-
-
[Called By]
-
-Gimbal_Init (Thumb, 400 bytes, Stack size 8 bytes, gimbal.o(i.Gimbal_Init))
-
[Stack]
- Max Depth = 44
- Call Chain = Gimbal_Init ⇒ Laser_Init ⇒ GPIO_Init
-
-
[Calls]- >> Laser_Init
-
- >> PID_PositionStructureInit
-
- >> PID_PositionSetParameter
-
- >> PID_PositionSetOUTRange
-
- >> PID_PositionSetEkRange
-
-
[Called By]- >> CloseLoopControl_Init
-
-
-Gimbal_MoveControl (Thumb, 20 bytes, Stack size 8 bytes, gimbal.o(i.Gimbal_MoveControl))
-
[Stack]
- Max Depth = 72
- Call Chain = Gimbal_MoveControl ⇒ Gimbal_YawControl ⇒ GM6020_CAN2SetLIDVoltage ⇒ CAN_TransmitStatus
-
-
[Calls]- >> Gimbal_YawControl
-
- >> Gimbal_Rammer
-
- >> Gimbal_PitchControl
-
- >> Gimbal_FiringMechanismControl
-
-
[Called By]
-
-Gimbal_PitchControl (Thumb, 386 bytes, Stack size 8 bytes, gimbal.o(i.Gimbal_PitchControl))
-
[Stack]
- Max Depth = 8
- Call Chain = Gimbal_PitchControl
-
-
[Calls]
-
[Called By]
-
-Gimbal_Rammer (Thumb, 176 bytes, Stack size 8 bytes, gimbal.o(i.Gimbal_Rammer))
-
[Stack]
- Max Depth = 64
- Call Chain = Gimbal_Rammer ⇒ M2006_CANSetHIDCurrent ⇒ CAN_TransmitStatus
-
-
[Calls]- >> PID_PositionCalc
-
- >> M2006_CANSetHIDCurrent
-
-
[Called By]
-
-Gimbal_YawControl (Thumb, 426 bytes, Stack size 8 bytes, gimbal.o(i.Gimbal_YawControl))
-
[Stack]
- Max Depth = 64
- Call Chain = Gimbal_YawControl ⇒ GM6020_CAN2SetLIDVoltage ⇒ CAN_TransmitStatus
-
-
[Calls]- >> PID_PositionCalc
-
- >> GM6020_CAN2SetLIDVoltage
-
-
[Called By]
-
-HardFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.HardFault_Handler))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-IMUTemperatureControl_PIDInit (Thumb, 60 bytes, Stack size 8 bytes, imutemperaturecontrol.o(i.IMUTemperatureControl_PIDInit))
-
[Stack]
- Max Depth = 8
- Call Chain = IMUTemperatureControl_PIDInit
-
-
[Calls]- >> PID_PositionStructureInit
-
- >> PID_PositionSetParameter
-
- >> PID_PositionSetOUTRange
-
- >> PID_PositionSetEkRange
-
-
[Called By]- >> CloseLoopControl_Init
-
-
-IMUTemperatureControl_TemperatureControl (Thumb, 80 bytes, Stack size 8 bytes, imutemperaturecontrol.o(i.IMUTemperatureControl_TemperatureControl))
-
[Stack]
- Max Depth = 24
- Call Chain = IMUTemperatureControl_TemperatureControl ⇒ Warming_IMUTemperatureTooHigh ⇒ LED_GON
-
-
[Calls]- >> TIM_SetCompare1
-
- >> PID_PositionCalc
-
- >> Warming_IMUTemperatureTooHigh
-
-
[Called By]
-
-IST8310_Delay_us (Thumb, 68 bytes, Stack size 0 bytes, ist8310.o(i.IST8310_Delay_us))
-
[Called By]
-
-IST8310_GetData (Thumb, 218 bytes, Stack size 24 bytes, ist8310.o(i.IST8310_GetData))
-
[Stack]
- Max Depth = 88
- Call Chain = IST8310_GetData ⇒ MyI2C_ContinuousReadRegister ⇒ MyI2C_SendAck ⇒ MyI2C_SDA
-
-
[Calls]- >> MyI2C_ReadRegister
-
- >> MyI2C_ContinuousReadRegister
-
-
[Called By]
-
-IST8310_Init (Thumb, 286 bytes, Stack size 24 bytes, ist8310.o(i.IST8310_Init))
-
[Stack]
- Max Depth = 80
- Call Chain = IST8310_Init ⇒ MyI2C_WriteRegister ⇒ MyI2C_Send8bits ⇒ MyI2C_SDA
-
-
[Calls]- >> NVIC_PriorityGroupConfig
-
- >> NVIC_Init
-
- >> GPIO_Init
-
- >> EXTI_Init
-
- >> RCC_APB2PeriphClockCmd
-
- >> RCC_AHB1PeriphClockCmd
-
- >> SYSCFG_EXTILineConfig
-
- >> Warming_IST8310LinkError
-
- >> IST8310_Reset
-
- >> MyI2C_WriteRegister
-
- >> MyI2C_Init
-
- >> MyI2C_CheckWhoAmI
-
- >> MyI2C_CheckDevice
-
- >> Delay_ms
-
-
[Called By]- >> AttitudeAlgorithms_Init
-
-
-IST8310_RSTN (Thumb, 20 bytes, Stack size 8 bytes, ist8310.o(i.IST8310_RSTN))
-
[Stack]
- Max Depth = 8
- Call Chain = IST8310_RSTN
-
-
[Calls]- >> GPIO_WriteBit
-
- >> IST8310_Delay_us
-
-
[Called By]
-
-IST8310_Reset (Thumb, 16 bytes, Stack size 8 bytes, ist8310.o(i.IST8310_Reset))
-
[Stack]
- Max Depth = 16
- Call Chain = IST8310_Reset ⇒ IST8310_RSTN
-
-
[Calls]
-
[Called By]
-
-IWDG_Enable (Thumb, 10 bytes, Stack size 0 bytes, stm32f4xx_iwdg.o(i.IWDG_Enable))
-
[Called By]
-
-IWDG_ReloadCounter (Thumb, 10 bytes, Stack size 0 bytes, stm32f4xx_iwdg.o(i.IWDG_ReloadCounter))
-
[Called By]
-
-IWDG_SetPrescaler (Thumb, 6 bytes, Stack size 0 bytes, stm32f4xx_iwdg.o(i.IWDG_SetPrescaler))
-
[Called By]
-
-IWDG_SetReload (Thumb, 6 bytes, Stack size 0 bytes, stm32f4xx_iwdg.o(i.IWDG_SetReload))
-
[Called By]
-
-IWDG_WriteAccessCmd (Thumb, 6 bytes, Stack size 0 bytes, stm32f4xx_iwdg.o(i.IWDG_WriteAccessCmd))
-
[Called By]
-
-Keyboard_DataProcess (Thumb, 308 bytes, Stack size 0 bytes, keyboard.o(i.Keyboard_DataProcess))
-
[Called By]
-
-Keyboard_Init (Thumb, 8 bytes, Stack size 8 bytes, keyboard.o(i.Keyboard_Init))
-
[Stack]
- Max Depth = 108
- Call Chain = Keyboard_Init ⇒ UART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq
-
-
[Calls]
-
[Called By]
-
-LED_BOFF (Thumb, 14 bytes, Stack size 8 bytes, led.o(i.LED_BOFF))
-
[Stack]
- Max Depth = 8
- Call Chain = LED_BOFF
-
-
[Calls]
-
[Called By]
-
-LED_BON (Thumb, 14 bytes, Stack size 8 bytes, led.o(i.LED_BON))
-
[Stack]
- Max Depth = 8
- Call Chain = LED_BON
-
-
[Calls]
-
[Called By]
-
-LED_GOFF (Thumb, 14 bytes, Stack size 8 bytes, led.o(i.LED_GOFF))
-
[Stack]
- Max Depth = 8
- Call Chain = LED_GOFF
-
-
[Calls]
-
[Called By]- >> Warming_IST8310LinkError
-
- >> Warming_BMI088LinkError
-
- >> Warming_LEDClean
-
-
-LED_GON (Thumb, 14 bytes, Stack size 8 bytes, led.o(i.LED_GON))
-
[Stack]
- Max Depth = 8
- Call Chain = LED_GON
-
-
[Calls]
-
[Called By]- >> Warming_IST8310LinkError
-
- >> Warming_BMI088LinkError
-
- >> Warming_IMUTemperatureTooHigh
-
-
-LED_Init (Thumb, 80 bytes, Stack size 16 bytes, led.o(i.LED_Init))
-
[Stack]
- Max Depth = 36
- Call Chain = LED_Init ⇒ GPIO_Init
-
-
[Calls]- >> GPIO_ResetBits
-
- >> GPIO_Init
-
- >> RCC_AHB1PeriphClockCmd
-
-
[Called By]
-
-LED_ROFF (Thumb, 14 bytes, Stack size 8 bytes, led.o(i.LED_ROFF))
-
[Stack]
- Max Depth = 8
- Call Chain = LED_ROFF
-
-
[Calls]
-
[Called By]- >> Warming_RemoteNoCheck
-
- >> Warming_LEDClean
-
-
-LED_RON (Thumb, 14 bytes, Stack size 8 bytes, led.o(i.LED_RON))
-
[Stack]
- Max Depth = 8
- Call Chain = LED_RON
-
-
[Calls]
-
[Called By]- >> Warming_RemoteNoCheck
-
- >> Warming_RemoteDataERROR
-
-
-Laser_Init (Thumb, 58 bytes, Stack size 16 bytes, laser.o(i.Laser_Init))
-
[Stack]
- Max Depth = 36
- Call Chain = Laser_Init ⇒ GPIO_Init
-
-
[Calls]- >> GPIO_ResetBits
-
- >> GPIO_Init
-
- >> RCC_AHB1PeriphClockCmd
-
-
[Called By]
-
-Laser_OFF (Thumb, 14 bytes, Stack size 8 bytes, laser.o(i.Laser_OFF))
-
[Stack]
- Max Depth = 8
- Call Chain = Laser_OFF
-
-
[Calls]
-
[Called By]- >> Gimbal_FiringMechanismControl
-
-
-Laser_ON (Thumb, 14 bytes, Stack size 8 bytes, laser.o(i.Laser_ON))
-
[Stack]
- Max Depth = 8
- Call Chain = Laser_ON
-
-
[Calls]
-
[Called By]- >> Gimbal_FiringMechanismControl
-
-
-LinkCheck_Init (Thumb, 120 bytes, Stack size 24 bytes, linkcheck.o(i.LinkCheck_Init))
-
[Stack]
- Max Depth = 92
- Call Chain = LinkCheck_Init ⇒ CAN_CANInit ⇒ GPIO_PinAFConfig
-
-
[Calls]- >> NVIC_PriorityGroupConfig
-
- >> NVIC_Init
-
- >> RCC_APB1PeriphClockCmd
-
- >> CAN_CANInit
-
- >> TIM_TimeBaseInit
-
- >> TIM_InternalClockConfig
-
- >> TIM_ITConfig
-
- >> TIM_Cmd
-
- >> TIM_ClearFlag
-
-
[Called By]
-
-LinkCheck_OFF (Thumb, 12 bytes, Stack size 8 bytes, linkcheck.o(i.LinkCheck_OFF))
-
[Stack]
- Max Depth = 8
- Call Chain = LinkCheck_OFF
-
-
[Calls]
-
[Called By]- >> CAN2_RX1_IRQHandler
-
- >> CAN1_RX0_IRQHandler
-
-
-LinkCheck_ON (Thumb, 20 bytes, Stack size 8 bytes, linkcheck.o(i.LinkCheck_ON))
-
[Stack]
- Max Depth = 8
- Call Chain = LinkCheck_ON
-
-
[Calls]- >> TIM_SetCounter
-
- >> TIM_Cmd
-
-
[Called By]- >> CAN2_RX1_IRQHandler
-
- >> CAN1_RX0_IRQHandler
-
-
-M2006_CANDataProcess (Thumb, 970 bytes, Stack size 24 bytes, m2006.o(i.M2006_CANDataProcess))
-
[Stack]
- Max Depth = 88
- Call Chain = M2006_CANDataProcess ⇒ __aeabi_ldivmod ⇒ __aeabi_uldivmod
-
-
[Calls]- >> __aeabi_l2f
-
- >> __aeabi_f2lz
-
- >> __aeabi_ldivmod
-
-
[Called By]
-
-M2006_CANSetHIDCurrent (Thumb, 146 bytes, Stack size 48 bytes, m2006.o(i.M2006_CANSetHIDCurrent))
-
[Stack]
- Max Depth = 56
- Call Chain = M2006_CANSetHIDCurrent ⇒ CAN_TransmitStatus
-
-
[Calls]- >> CAN_TransmitStatus
-
- >> CAN_Transmit
-
-
[Called By]- >> Gimbal_Rammer
-
- >> Warming_MotorControl
-
-
-M3508_CANDataProcess (Thumb, 998 bytes, Stack size 24 bytes, m3508.o(i.M3508_CANDataProcess))
-
[Stack]
- Max Depth = 88
- Call Chain = M3508_CANDataProcess ⇒ __aeabi_ldivmod ⇒ __aeabi_uldivmod
-
-
[Calls]- >> __aeabi_l2f
-
- >> __aeabi_f2lz
-
- >> __aeabi_ldivmod
-
-
[Called By]
-
-M3508_CANSetLIDCurrent (Thumb, 146 bytes, Stack size 48 bytes, m3508.o(i.M3508_CANSetLIDCurrent))
-
[Stack]
- Max Depth = 56
- Call Chain = M3508_CANSetLIDCurrent ⇒ CAN_TransmitStatus
-
-
[Calls]- >> CAN_TransmitStatus
-
- >> CAN_Transmit
-
-
[Called By]- >> Gimbal_FiringMechanismControl
-
- >> Warming_MotorControl
-
-
-MemManage_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.MemManage_Handler))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-MyI2C_CheckDevice (Thumb, 40 bytes, Stack size 16 bytes, myi2c.o(i.MyI2C_CheckDevice))
-
[Stack]
- Max Depth = 48
- Call Chain = MyI2C_CheckDevice ⇒ MyI2C_Send8bits ⇒ MyI2C_SDA
-
-
[Calls]- >> MyI2C_Stop
-
- >> MyI2C_Start
-
- >> MyI2C_Send8bits
-
- >> MyI2C_ReceiveAck
-
-
[Called By]
-
-MyI2C_CheckWhoAmI (Thumb, 118 bytes, Stack size 24 bytes, myi2c.o(i.MyI2C_CheckWhoAmI))
-
[Stack]
- Max Depth = 56
- Call Chain = MyI2C_CheckWhoAmI ⇒ MyI2C_SendAck ⇒ MyI2C_SDA
-
-
[Calls]- >> MyI2C_Stop
-
- >> MyI2C_Start
-
- >> MyI2C_SendAck
-
- >> MyI2C_Send8bits
-
- >> MyI2C_ReceiveAck
-
- >> MyI2C_Receive8bits
-
-
[Called By]
-
-MyI2C_ContinuousReadRegister (Thumb, 158 bytes, Stack size 32 bytes, myi2c.o(i.MyI2C_ContinuousReadRegister))
-
[Stack]
- Max Depth = 64
- Call Chain = MyI2C_ContinuousReadRegister ⇒ MyI2C_SendAck ⇒ MyI2C_SDA
-
-
[Calls]- >> MyI2C_Stop
-
- >> MyI2C_Start
-
- >> MyI2C_SendAck
-
- >> MyI2C_Send8bits
-
- >> MyI2C_ReceiveAck
-
- >> MyI2C_Receive8bits
-
-
[Called By]
-
-MyI2C_Delay_us (Thumb, 70 bytes, Stack size 0 bytes, myi2c.o(i.MyI2C_Delay_us))
-
[Called By]
- >> MyI2C_SDA
-
- >> MyI2C_SCL
-
- >> MyI2C_Read_SDA
-
-
-MyI2C_Init (Thumb, 82 bytes, Stack size 16 bytes, myi2c.o(i.MyI2C_Init))
-
[Stack]
- Max Depth = 36
- Call Chain = MyI2C_Init ⇒ GPIO_Init
-
-
[Calls]- >> GPIO_Init
-
- >> RCC_AHB1PeriphClockCmd
-
- >> MyI2C_SDA
-
- >> MyI2C_SCL
-
-
[Called By]
-
-MyI2C_ReadRegister (Thumb, 120 bytes, Stack size 24 bytes, myi2c.o(i.MyI2C_ReadRegister))
-
[Stack]
- Max Depth = 56
- Call Chain = MyI2C_ReadRegister ⇒ MyI2C_SendAck ⇒ MyI2C_SDA
-
-
[Calls]- >> MyI2C_Stop
-
- >> MyI2C_Start
-
- >> MyI2C_SendAck
-
- >> MyI2C_Send8bits
-
- >> MyI2C_ReceiveAck
-
- >> MyI2C_Receive8bits
-
-
[Called By]
-
-MyI2C_Read_SDA (Thumb, 26 bytes, Stack size 16 bytes, myi2c.o(i.MyI2C_Read_SDA))
-
[Stack]
- Max Depth = 16
- Call Chain = MyI2C_Read_SDA
-
-
[Calls]- >> GPIO_ReadInputDataBit
-
- >> MyI2C_Delay_us
-
-
[Called By]- >> MyI2C_ReceiveAck
-
- >> MyI2C_Receive8bits
-
-
-MyI2C_Receive8bits (Thumb, 60 bytes, Stack size 16 bytes, myi2c.o(i.MyI2C_Receive8bits))
-
[Stack]
- Max Depth = 32
- Call Chain = MyI2C_Receive8bits ⇒ MyI2C_SDA
-
-
[Calls]- >> MyI2C_SDA
-
- >> MyI2C_SCL
-
- >> MyI2C_Read_SDA
-
-
[Called By]- >> MyI2C_ReadRegister
-
- >> MyI2C_ContinuousReadRegister
-
- >> MyI2C_CheckWhoAmI
-
-
-MyI2C_ReceiveAck (Thumb, 48 bytes, Stack size 16 bytes, myi2c.o(i.MyI2C_ReceiveAck))
-
[Stack]
- Max Depth = 32
- Call Chain = MyI2C_ReceiveAck ⇒ MyI2C_SDA
-
-
[Calls]- >> MyI2C_SDA
-
- >> MyI2C_SCL
-
- >> MyI2C_Read_SDA
-
-
[Called By]- >> MyI2C_WriteRegister
-
- >> MyI2C_ReadRegister
-
- >> MyI2C_ContinuousReadRegister
-
- >> MyI2C_CheckWhoAmI
-
- >> MyI2C_CheckDevice
-
-
-MyI2C_SCL (Thumb, 26 bytes, Stack size 16 bytes, myi2c.o(i.MyI2C_SCL))
-
[Stack]
- Max Depth = 16
- Call Chain = MyI2C_SCL
-
-
[Calls]- >> GPIO_WriteBit
-
- >> MyI2C_Delay_us
-
-
[Called By]- >> MyI2C_Stop
-
- >> MyI2C_Start
-
- >> MyI2C_SendAck
-
- >> MyI2C_Send8bits
-
- >> MyI2C_ReceiveAck
-
- >> MyI2C_Receive8bits
-
- >> MyI2C_Init
-
-
-MyI2C_SDA (Thumb, 26 bytes, Stack size 16 bytes, myi2c.o(i.MyI2C_SDA))
-
[Stack]
- Max Depth = 16
- Call Chain = MyI2C_SDA
-
-
[Calls]- >> GPIO_WriteBit
-
- >> MyI2C_Delay_us
-
-
[Called By]- >> MyI2C_Stop
-
- >> MyI2C_Start
-
- >> MyI2C_SendAck
-
- >> MyI2C_Send8bits
-
- >> MyI2C_ReceiveAck
-
- >> MyI2C_Receive8bits
-
- >> MyI2C_Init
-
-
-MyI2C_Send8bits (Thumb, 58 bytes, Stack size 16 bytes, myi2c.o(i.MyI2C_Send8bits))
-
[Stack]
- Max Depth = 32
- Call Chain = MyI2C_Send8bits ⇒ MyI2C_SDA
-
-
[Calls]- >> MyI2C_SDA
-
- >> MyI2C_SCL
-
-
[Called By]- >> MyI2C_WriteRegister
-
- >> MyI2C_ReadRegister
-
- >> MyI2C_ContinuousReadRegister
-
- >> MyI2C_CheckWhoAmI
-
- >> MyI2C_CheckDevice
-
-
-MyI2C_SendAck (Thumb, 48 bytes, Stack size 16 bytes, myi2c.o(i.MyI2C_SendAck))
-
[Stack]
- Max Depth = 32
- Call Chain = MyI2C_SendAck ⇒ MyI2C_SDA
-
-
[Calls]- >> MyI2C_SDA
-
- >> MyI2C_SCL
-
-
[Called By]- >> MyI2C_ReadRegister
-
- >> MyI2C_ContinuousReadRegister
-
- >> MyI2C_CheckWhoAmI
-
-
-MyI2C_Start (Thumb, 38 bytes, Stack size 8 bytes, myi2c.o(i.MyI2C_Start))
-
[Stack]
- Max Depth = 24
- Call Chain = MyI2C_Start ⇒ MyI2C_SDA
-
-
[Calls]- >> MyI2C_SDA
-
- >> MyI2C_SCL
-
-
[Called By]- >> MyI2C_WriteRegister
-
- >> MyI2C_ReadRegister
-
- >> MyI2C_ContinuousReadRegister
-
- >> MyI2C_CheckWhoAmI
-
- >> MyI2C_CheckDevice
-
-
-MyI2C_Stop (Thumb, 30 bytes, Stack size 8 bytes, myi2c.o(i.MyI2C_Stop))
-
[Stack]
- Max Depth = 24
- Call Chain = MyI2C_Stop ⇒ MyI2C_SDA
-
-
[Calls]- >> MyI2C_SDA
-
- >> MyI2C_SCL
-
-
[Called By]- >> MyI2C_WriteRegister
-
- >> MyI2C_ReadRegister
-
- >> MyI2C_ContinuousReadRegister
-
- >> MyI2C_CheckWhoAmI
-
- >> MyI2C_CheckDevice
-
-
-MyI2C_WriteRegister (Thumb, 90 bytes, Stack size 24 bytes, myi2c.o(i.MyI2C_WriteRegister))
-
[Stack]
- Max Depth = 56
- Call Chain = MyI2C_WriteRegister ⇒ MyI2C_Send8bits ⇒ MyI2C_SDA
-
-
[Calls]- >> MyI2C_Stop
-
- >> MyI2C_Start
-
- >> MyI2C_Send8bits
-
- >> MyI2C_ReceiveAck
-
-
[Called By]
-
-NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.NMI_Handler))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-NVIC_Init (Thumb, 106 bytes, Stack size 16 bytes, misc.o(i.NVIC_Init))
-
[Stack]
- Max Depth = 16
- Call Chain = NVIC_Init
-
-
[Called By]- >> IST8310_Init
-
- >> BMI088_Init
-
- >> Remote_Init
-
- >> CAN_CANInit
-
- >> UART1_Init
-
- >> AttitudeAlgorithms_Init
-
- >> CloseLoopControl_Init
-
- >> LinkCheck_Init
-
-
-NVIC_PriorityGroupConfig (Thumb, 10 bytes, Stack size 0 bytes, misc.o(i.NVIC_PriorityGroupConfig))
-
[Called By]
- >> IST8310_Init
-
- >> BMI088_Init
-
- >> Remote_Init
-
- >> CAN_CANInit
-
- >> UART1_Init
-
- >> AttitudeAlgorithms_Init
-
- >> CloseLoopControl_Init
-
- >> LinkCheck_Init
-
-
-PID_PositionCalc (Thumb, 230 bytes, Stack size 0 bytes, pid.o(i.PID_PositionCalc))
-
[Called By]
- >> Gimbal_YawControl
-
- >> Gimbal_Rammer
-
- >> Gimbal_PitchControl
-
- >> Gimbal_FiringMechanismControl
-
- >> IMUTemperatureControl_TemperatureControl
-
-
-PID_PositionClean (Thumb, 18 bytes, Stack size 0 bytes, pid.o(i.PID_PositionClean))
-
[Called By]
-
-PID_PositionSetEkRange (Thumb, 10 bytes, Stack size 0 bytes, pid.o(i.PID_PositionSetEkRange))
-
[Called By]
- >> IMUTemperatureControl_PIDInit
-
- >> Gimbal_Init
-
-
-PID_PositionSetOUTRange (Thumb, 10 bytes, Stack size 0 bytes, pid.o(i.PID_PositionSetOUTRange))
-
[Called By]
- >> IMUTemperatureControl_PIDInit
-
- >> Gimbal_Init
-
-
-PID_PositionSetParameter (Thumb, 14 bytes, Stack size 0 bytes, pid.o(i.PID_PositionSetParameter))
-
[Called By]
- >> IMUTemperatureControl_PIDInit
-
- >> Gimbal_Init
-
-
-PID_PositionStructureInit (Thumb, 78 bytes, Stack size 0 bytes, pid.o(i.PID_PositionStructureInit))
-
[Called By]
- >> IMUTemperatureControl_PIDInit
-
- >> Gimbal_Init
-
-
-PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.PendSV_Handler))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-RCC_AHB1PeriphClockCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f4xx_rcc.o(i.RCC_AHB1PeriphClockCmd))
-
[Called By]
- >> Laser_Init
-
- >> IST8310_Init
-
- >> BMI088_Init
-
- >> Remote_Init
-
- >> Buzzer_Init
-
- >> LED_Init
-
- >> CAN_CANInit
-
- >> MyI2C_Init
-
- >> UART2_SendInit
-
- >> UART1_Init
-
-
-RCC_APB1PeriphClockCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f4xx_rcc.o(i.RCC_APB1PeriphClockCmd))
-
[Called By]
- >> Remote_Init
-
- >> Buzzer_Init
-
- >> CAN_CANInit
-
- >> CloseLoopControl_Init
-
- >> LinkCheck_Init
-
-
-RCC_APB2PeriphClockCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f4xx_rcc.o(i.RCC_APB2PeriphClockCmd))
-
[Called By]
- >> IST8310_Init
-
- >> BMI088_Init
-
- >> UART2_SendInit
-
- >> UART1_Init
-
- >> AttitudeAlgorithms_Init
-
-
-RCC_GetClocksFreq (Thumb, 214 bytes, Stack size 20 bytes, stm32f4xx_rcc.o(i.RCC_GetClocksFreq))
-
[Stack]
- Max Depth = 20
- Call Chain = RCC_GetClocksFreq
-
-
[Called By]
-
-RefereeSystem_GetCRC16CheckSum (Thumb, 38 bytes, Stack size 12 bytes, refereesystem.o(i.RefereeSystem_GetCRC16CheckSum))
-
[Stack]
- Max Depth = 12
- Call Chain = RefereeSystem_GetCRC16CheckSum
-
-
[Called By]- >> RefereeSystem_VerifyCRC16CheckSum
-
-
-RefereeSystem_GetCRC8CheckSum (Thumb, 32 bytes, Stack size 12 bytes, refereesystem.o(i.RefereeSystem_GetCRC8CheckSum))
-
[Stack]
- Max Depth = 12
- Call Chain = RefereeSystem_GetCRC8CheckSum
-
-
[Called By]- >> RefereeSystem_VerifyCRC8CheckSum
-
-
-RefereeSystem_Init (Thumb, 8 bytes, Stack size 8 bytes, refereesystem.o(i.RefereeSystem_Init))
-
[Stack]
- Max Depth = 116
- Call Chain = RefereeSystem_Init ⇒ Keyboard_Init ⇒ UART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq
-
-
[Calls]
-
[Called By]
-
-RefereeSystem_VerifyCRC16CheckSum (Thumb, 60 bytes, Stack size 16 bytes, refereesystem.o(i.RefereeSystem_VerifyCRC16CheckSum))
-
[Stack]
- Max Depth = 28
- Call Chain = RefereeSystem_VerifyCRC16CheckSum ⇒ RefereeSystem_GetCRC16CheckSum
-
-
[Calls]- >> RefereeSystem_GetCRC16CheckSum
-
-
[Called By]
-
-RefereeSystem_VerifyCRC8CheckSum (Thumb, 50 bytes, Stack size 16 bytes, refereesystem.o(i.RefereeSystem_VerifyCRC8CheckSum))
-
[Stack]
- Max Depth = 28
- Call Chain = RefereeSystem_VerifyCRC8CheckSum ⇒ RefereeSystem_GetCRC8CheckSum
-
-
[Calls]- >> RefereeSystem_GetCRC8CheckSum
-
-
[Called By]
-
-Remote_DataProcess (Thumb, 464 bytes, Stack size 16 bytes, remote.o(i.Remote_DataProcess))
-
[Stack]
- Max Depth = 16
- Call Chain = Remote_DataProcess
-
-
[Calls]- >> DMA_GetCurrentMemoryTarget
-
-
[Called By]
-
-Remote_Init (Thumb, 402 bytes, Stack size 104 bytes, remote.o(i.Remote_Init))
-
[Stack]
- Max Depth = 172
- Call Chain = Remote_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq
-
-
[Calls]- >> NVIC_PriorityGroupConfig
-
- >> NVIC_Init
-
- >> DMA_Init
-
- >> DMA_DoubleBufferModeConfig
-
- >> DMA_DoubleBufferModeCmd
-
- >> DMA_Cmd
-
- >> GPIO_PinAFConfig
-
- >> GPIO_Init
-
- >> IWDG_WriteAccessCmd
-
- >> IWDG_SetReload
-
- >> IWDG_SetPrescaler
-
- >> IWDG_Enable
-
- >> RCC_APB1PeriphClockCmd
-
- >> RCC_AHB1PeriphClockCmd
-
- >> USART_Init
-
- >> USART_ITConfig
-
- >> USART_DMACmd
-
- >> USART_Cmd
-
- >> TIM_TimeBaseInit
-
- >> TIM_InternalClockConfig
-
- >> TIM_ITConfig
-
- >> TIM_Cmd
-
- >> TIM_ClearFlag
-
-
[Called By]
-
-Remote_TransferReset (Thumb, 62 bytes, Stack size 8 bytes, remote.o(i.Remote_TransferReset))
-
[Stack]
- Max Depth = 20
- Call Chain = Remote_TransferReset ⇒ DMA_GetFlagStatus
-
-
[Calls]- >> DMA_SetCurrDataCounter
-
- >> DMA_GetFlagStatus
-
- >> DMA_GetCmdStatus
-
- >> DMA_Cmd
-
- >> DMA_ClearFlag
-
-
[Called By]
-
-SPI_Cmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f4xx_spi.o(i.SPI_Cmd))
-
[Called By]
-
-SPI_I2S_DMACmd (Thumb, 18 bytes, Stack size 0 bytes, stm32f4xx_spi.o(i.SPI_I2S_DMACmd))
-
[Called By]
-
-SPI_I2S_GetFlagStatus (Thumb, 18 bytes, Stack size 0 bytes, stm32f4xx_spi.o(i.SPI_I2S_GetFlagStatus))
-
[Called By]
- >> BMI088_SPI_GyroWriteRegister
-
- >> BMI088_SPI_GyroReadRegister
-
- >> BMI088_SPI_AccelWriteRegister
-
- >> BMI088_SPI_AccelReadRegister
-
- >> BMI088_CheckAndCloseDMA
-
-
-SPI_I2S_ReceiveData (Thumb, 6 bytes, Stack size 0 bytes, stm32f4xx_spi.o(i.SPI_I2S_ReceiveData))
-
[Called By]
- >> BMI088_SPI_GyroWriteRegister
-
- >> BMI088_SPI_GyroReadRegister
-
- >> BMI088_SPI_AccelWriteRegister
-
- >> BMI088_SPI_AccelReadRegister
-
-
-SPI_I2S_SendData (Thumb, 4 bytes, Stack size 0 bytes, stm32f4xx_spi.o(i.SPI_I2S_SendData))
-
[Called By]
- >> BMI088_SPI_GyroWriteRegister
-
- >> BMI088_SPI_GyroReadRegister
-
- >> BMI088_SPI_AccelWriteRegister
-
- >> BMI088_SPI_AccelReadRegister
-
-
-SPI_Init (Thumb, 60 bytes, Stack size 8 bytes, stm32f4xx_spi.o(i.SPI_Init))
-
[Stack]
- Max Depth = 8
- Call Chain = SPI_Init
-
-
[Called By]
-
-SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.SVC_Handler))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-SYSCFG_EXTILineConfig (Thumb, 60 bytes, Stack size 12 bytes, stm32f4xx_syscfg.o(i.SYSCFG_EXTILineConfig))
-
[Stack]
- Max Depth = 12
- Call Chain = SYSCFG_EXTILineConfig
-
-
[Called By]- >> IST8310_Init
-
- >> BMI088_Init
-
-
-SysTick_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.SysTick_Handler))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-SystemInit (Thumb, 88 bytes, Stack size 8 bytes, system_stm32f4xx.o(i.SystemInit))
-
[Stack]
- Max Depth = 20
- Call Chain = SystemInit ⇒ SetSysClock
-
-
[Calls]
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(.text)
-
-TIM1_TRG_COM_TIM11_IRQHandler (Thumb, 272 bytes, Stack size 8 bytes, attitudealgorithms.o(i.TIM1_TRG_COM_TIM11_IRQHandler))
-
[Stack]
- Max Depth = 280
- Call Chain = TIM1_TRG_COM_TIM11_IRQHandler ⇒ AHRS_update ⇒ accel_comple_filter ⇒ accel_update_kp_ki ⇒ AHRS_invSqrt ⇒ __hardfp_sqrtf
-
-
[Calls]- >> TIM_GetITStatus
-
- >> TIM_ClearITPendingBit
-
- >> get_angle
-
- >> AHRS_update
-
- >> __aeabi_l2f
-
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-TIM2_IRQHandler (Thumb, 24 bytes, Stack size 8 bytes, tim.o(i.TIM2_IRQHandler))
-
[Stack]
- Max Depth = 20
- Call Chain = TIM2_IRQHandler ⇒ TIM_GetITStatus
-
-
[Calls]- >> TIM_GetITStatus
-
- >> TIM_ClearITPendingBit
-
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-TIM6_DAC_IRQHandler (Thumb, 104 bytes, Stack size 8 bytes, closeloopcontrol.o(i.TIM6_DAC_IRQHandler))
-
[Stack]
- Max Depth = 80
- Call Chain = TIM6_DAC_IRQHandler ⇒ Gimbal_MoveControl ⇒ Gimbal_YawControl ⇒ GM6020_CAN2SetLIDVoltage ⇒ CAN_TransmitStatus
-
-
[Calls]- >> TIM_GetITStatus
-
- >> TIM_ClearITPendingBit
-
- >> IMUTemperatureControl_TemperatureControl
-
- >> Gimbal_MoveControl
-
- >> Gimbal_CleanPID
-
- >> Warming_MotorControl
-
- >> Warming_LinkError
-
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-TIM7_IRQHandler (Thumb, 44 bytes, Stack size 8 bytes, remote.o(i.TIM7_IRQHandler))
-
[Stack]
- Max Depth = 24
- Call Chain = TIM7_IRQHandler ⇒ Warming_RemoteNoCheck ⇒ LED_RON
-
-
[Calls]- >> Warming_RemoteNoCheck
-
- >> TIM_GetITStatus
-
- >> TIM_ClearITPendingBit
-
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-TIM8_UP_TIM13_IRQHandler (Thumb, 68 bytes, Stack size 8 bytes, linkcheck.o(i.TIM8_UP_TIM13_IRQHandler))
-
[Stack]
- Max Depth = 20
- Call Chain = TIM8_UP_TIM13_IRQHandler ⇒ TIM_GetITStatus
-
-
[Calls]- >> CAN_CAN_GetRefereeSystemData
-
- >> CAN_CANIDReset
-
- >> TIM_GetITStatus
-
- >> TIM_ClearITPendingBit
-
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-TIM_ClearFlag (Thumb, 6 bytes, Stack size 0 bytes, stm32f4xx_tim.o(i.TIM_ClearFlag))
-
[Called By]
- >> Remote_Init
-
- >> AttitudeAlgorithms_Init
-
- >> CloseLoopControl_Init
-
- >> LinkCheck_Init
-
-
-TIM_ClearITPendingBit (Thumb, 6 bytes, Stack size 0 bytes, stm32f4xx_tim.o(i.TIM_ClearITPendingBit))
-
[Called By]
- >> TIM7_IRQHandler
-
- >> TIM2_IRQHandler
-
- >> TIM1_TRG_COM_TIM11_IRQHandler
-
- >> TIM6_DAC_IRQHandler
-
- >> TIM8_UP_TIM13_IRQHandler
-
-
-TIM_Cmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f4xx_tim.o(i.TIM_Cmd))
-
[Called By]
- >> USART3_IRQHandler
-
- >> Remote_Init
-
- >> Buzzer_ON
-
- >> Buzzer_Init
-
- >> LinkCheck_ON
-
- >> LinkCheck_OFF
-
- >> USART6_IRQHandler
-
- >> AttitudeAlgorithms_Init
-
- >> CloseLoopControl_Init
-
- >> LinkCheck_Init
-
-
-TIM_GetITStatus (Thumb, 34 bytes, Stack size 12 bytes, stm32f4xx_tim.o(i.TIM_GetITStatus))
-
[Stack]
- Max Depth = 12
- Call Chain = TIM_GetITStatus
-
-
[Called By]- >> TIM7_IRQHandler
-
- >> TIM2_IRQHandler
-
- >> TIM1_TRG_COM_TIM11_IRQHandler
-
- >> TIM6_DAC_IRQHandler
-
- >> TIM8_UP_TIM13_IRQHandler
-
-
-TIM_ITConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f4xx_tim.o(i.TIM_ITConfig))
-
[Called By]
- >> Remote_Init
-
- >> AttitudeAlgorithms_Init
-
- >> CloseLoopControl_Init
-
- >> LinkCheck_Init
-
-
-TIM_InternalClockConfig (Thumb, 12 bytes, Stack size 0 bytes, stm32f4xx_tim.o(i.TIM_InternalClockConfig))
-
[Called By]
- >> Remote_Init
-
- >> Buzzer_Init
-
- >> AttitudeAlgorithms_Init
-
- >> CloseLoopControl_Init
-
- >> LinkCheck_Init
-
-
-TIM_OC3Init (Thumb, 150 bytes, Stack size 16 bytes, stm32f4xx_tim.o(i.TIM_OC3Init))
-
[Stack]
- Max Depth = 16
- Call Chain = TIM_OC3Init
-
-
[Called By]
-
-TIM_OCStructInit (Thumb, 20 bytes, Stack size 0 bytes, stm32f4xx_tim.o(i.TIM_OCStructInit))
-
[Called By]
-
-TIM_PrescalerConfig (Thumb, 6 bytes, Stack size 0 bytes, stm32f4xx_tim.o(i.TIM_PrescalerConfig))
-
[Called By]
-
-TIM_SetCompare1 (Thumb, 4 bytes, Stack size 0 bytes, stm32f4xx_tim.o(i.TIM_SetCompare1))
-
[Called By]
- >> IMUTemperatureControl_TemperatureControl
-
-
-TIM_SetCompare3 (Thumb, 4 bytes, Stack size 0 bytes, stm32f4xx_tim.o(i.TIM_SetCompare3))
-
[Called By]
-
-TIM_SetCounter (Thumb, 4 bytes, Stack size 0 bytes, stm32f4xx_tim.o(i.TIM_SetCounter))
-
[Called By]
- >> USART3_IRQHandler
-
- >> LinkCheck_ON
-
- >> USART6_IRQHandler
-
-
-TIM_TimeBaseInit (Thumb, 104 bytes, Stack size 0 bytes, stm32f4xx_tim.o(i.TIM_TimeBaseInit))
-
[Called By]
- >> Remote_Init
-
- >> Buzzer_Init
-
- >> AttitudeAlgorithms_Init
-
- >> CloseLoopControl_Init
-
- >> LinkCheck_Init
-
-
-UART1_Init (Thumb, 176 bytes, Stack size 32 bytes, uart.o(i.UART1_Init))
-
[Stack]
- Max Depth = 100
- Call Chain = UART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq
-
-
[Calls]- >> NVIC_PriorityGroupConfig
-
- >> NVIC_Init
-
- >> GPIO_PinAFConfig
-
- >> GPIO_Init
-
- >> RCC_APB2PeriphClockCmd
-
- >> RCC_AHB1PeriphClockCmd
-
- >> USART_Init
-
- >> USART_ITConfig
-
- >> USART_Cmd
-
-
[Called By]
-
-UART2_SendArray (Thumb, 26 bytes, Stack size 16 bytes, uart.o(i.UART2_SendArray))
-
[Stack]
- Max Depth = 24
- Call Chain = UART2_SendArray ⇒ UART2_SendByte
-
-
[Calls]
-
[Called By]
-
-UART2_SendByte (Thumb, 28 bytes, Stack size 8 bytes, uart.o(i.UART2_SendByte))
-
[Stack]
- Max Depth = 8
- Call Chain = UART2_SendByte
-
-
[Calls]- >> USART_SendData
-
- >> USART_GetFlagStatus
-
-
[Called By]- >> UART2_SendArray
-
- >> Visual_SendData
-
-
-UART2_SendInit (Thumb, 118 bytes, Stack size 32 bytes, uart.o(i.UART2_SendInit))
-
[Stack]
- Max Depth = 100
- Call Chain = UART2_SendInit ⇒ USART_Init ⇒ RCC_GetClocksFreq
-
-
[Calls]- >> GPIO_PinAFConfig
-
- >> GPIO_Init
-
- >> RCC_APB2PeriphClockCmd
-
- >> RCC_AHB1PeriphClockCmd
-
- >> USART_Init
-
- >> USART_Cmd
-
-
[Called By]
-
-USART1_IRQHandler (Thumb, 246 bytes, Stack size 24 bytes, visual.o(i.USART1_IRQHandler))
-
[Stack]
- Max Depth = 72
- Call Chain = USART1_IRQHandler ⇒ Visual_SendData ⇒ UART2_SendArray ⇒ UART2_SendByte
-
-
[Calls]- >> USART_ReceiveData
-
- >> USART_GetITStatus
-
- >> USART_ClearITPendingBit
-
- >> Visual_SendData
-
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-USART3_IRQHandler (Thumb, 126 bytes, Stack size 8 bytes, remote.o(i.USART3_IRQHandler))
-
[Stack]
- Max Depth = 28
- Call Chain = USART3_IRQHandler ⇒ Remote_TransferReset ⇒ DMA_GetFlagStatus
-
-
[Calls]- >> DMA_GetCurrDataCounter
-
- >> Warming_RemoteDataERROR
-
- >> Warming_LEDClean
-
- >> Remote_TransferReset
-
- >> Remote_DataProcess
-
- >> USART_ClearITPendingBit
-
- >> TIM_SetCounter
-
- >> TIM_Cmd
-
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-USART6_IRQHandler (Thumb, 348 bytes, Stack size 8 bytes, refereesystem.o(i.USART6_IRQHandler))
-
[Stack]
- Max Depth = 36
- Call Chain = USART6_IRQHandler ⇒ RefereeSystem_VerifyCRC8CheckSum ⇒ RefereeSystem_GetCRC8CheckSum
-
-
[Calls]- >> Warming_LEDClean
-
- >> USART_ReceiveData
-
- >> USART_GetITStatus
-
- >> USART_ClearITPendingBit
-
- >> TIM_SetCounter
-
- >> TIM_Cmd
-
- >> Keyboard_DataProcess
-
- >> RefereeSystem_VerifyCRC8CheckSum
-
- >> RefereeSystem_VerifyCRC16CheckSum
-
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-USART_ClearITPendingBit (Thumb, 30 bytes, Stack size 8 bytes, stm32f4xx_usart.o(i.USART_ClearITPendingBit))
-
[Stack]
- Max Depth = 8
- Call Chain = USART_ClearITPendingBit
-
-
[Called By]- >> USART3_IRQHandler
-
- >> USART1_IRQHandler
-
- >> USART6_IRQHandler
-
-
-USART_Cmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f4xx_usart.o(i.USART_Cmd))
-
[Called By]
- >> Remote_Init
-
- >> UART2_SendInit
-
- >> UART1_Init
-
-
-USART_DMACmd (Thumb, 18 bytes, Stack size 0 bytes, stm32f4xx_usart.o(i.USART_DMACmd))
-
[Called By]
-
-USART_GetFlagStatus (Thumb, 26 bytes, Stack size 0 bytes, stm32f4xx_usart.o(i.USART_GetFlagStatus))
-
[Called By]
-
-USART_GetITStatus (Thumb, 84 bytes, Stack size 16 bytes, stm32f4xx_usart.o(i.USART_GetITStatus))
-
[Stack]
- Max Depth = 16
- Call Chain = USART_GetITStatus
-
-
[Called By]- >> USART1_IRQHandler
-
- >> USART6_IRQHandler
-
-
-USART_ITConfig (Thumb, 74 bytes, Stack size 20 bytes, stm32f4xx_usart.o(i.USART_ITConfig))
-
[Stack]
- Max Depth = 20
- Call Chain = USART_ITConfig
-
-
[Called By]- >> Remote_Init
-
- >> UART1_Init
-
-
-USART_Init (Thumb, 204 bytes, Stack size 48 bytes, stm32f4xx_usart.o(i.USART_Init))
-
[Stack]
- Max Depth = 68
- Call Chain = USART_Init ⇒ RCC_GetClocksFreq
-
-
[Calls]
-
[Called By]- >> Remote_Init
-
- >> UART2_SendInit
-
- >> UART1_Init
-
-
-USART_ReceiveData (Thumb, 10 bytes, Stack size 0 bytes, stm32f4xx_usart.o(i.USART_ReceiveData))
-
[Called By]
- >> USART1_IRQHandler
-
- >> USART6_IRQHandler
-
-
-USART_SendData (Thumb, 8 bytes, Stack size 0 bytes, stm32f4xx_usart.o(i.USART_SendData))
-
[Called By]
-
-UsageFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.UsageFault_Handler))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-Visual_Init (Thumb, 8 bytes, Stack size 8 bytes, visual.o(i.Visual_Init))
-
[Stack]
- Max Depth = 56
- Call Chain = Visual_Init ⇒ Visual_SendData ⇒ UART2_SendArray ⇒ UART2_SendByte
-
-
[Calls]
-
[Called By]
-
-Visual_SendData (Thumb, 68 bytes, Stack size 24 bytes, visual.o(i.Visual_SendData))
-
[Stack]
- Max Depth = 48
- Call Chain = Visual_SendData ⇒ UART2_SendArray ⇒ UART2_SendByte
-
-
[Calls]- >> UART2_SendByte
-
- >> UART2_SendArray
-
-
[Called By]- >> Visual_Init
-
- >> USART1_IRQHandler
-
-
-Warming_BMI088LinkError (Thumb, 84 bytes, Stack size 8 bytes, warming.o(i.Warming_BMI088LinkError))
-
[Stack]
- Max Depth = 16
- Call Chain = Warming_BMI088LinkError ⇒ LED_GON
-
-
[Calls]- >> LED_GON
-
- >> LED_GOFF
-
-
[Called By]
-
-Warming_BuzzerClean (Thumb, 10 bytes, Stack size 8 bytes, warming.o(i.Warming_BuzzerClean))
-
[Stack]
- Max Depth = 16
- Call Chain = Warming_BuzzerClean ⇒ Buzzer_ON
-
-
[Calls]
-
[Called By]- >> CAN2_RX1_IRQHandler
-
- >> CAN1_RX0_IRQHandler
-
-
-Warming_IMUTemperatureTooHigh (Thumb, 8 bytes, Stack size 8 bytes, warming.o(i.Warming_IMUTemperatureTooHigh))
-
[Stack]
- Max Depth = 16
- Call Chain = Warming_IMUTemperatureTooHigh ⇒ LED_GON
-
-
[Calls]
-
[Called By]- >> IMUTemperatureControl_TemperatureControl
-
-
-Warming_IST8310LinkError (Thumb, 56 bytes, Stack size 8 bytes, warming.o(i.Warming_IST8310LinkError))
-
[Stack]
- Max Depth = 16
- Call Chain = Warming_IST8310LinkError ⇒ LED_GON
-
-
[Calls]- >> LED_GON
-
- >> LED_GOFF
-
-
[Called By]
-
-Warming_Init (Thumb, 12 bytes, Stack size 8 bytes, warming.o(i.Warming_Init))
-
[Stack]
- Max Depth = 76
- Call Chain = Warming_Init ⇒ Buzzer_Init ⇒ GPIO_PinAFConfig
-
-
[Calls]- >> Buzzer_Init
-
- >> LED_Init
-
-
[Called By]
-
-Warming_LEDClean (Thumb, 16 bytes, Stack size 8 bytes, warming.o(i.Warming_LEDClean))
-
[Stack]
- Max Depth = 16
- Call Chain = Warming_LEDClean ⇒ LED_ROFF
-
-
[Calls]- >> LED_ROFF
-
- >> LED_GOFF
-
- >> LED_BOFF
-
-
[Called By]- >> USART3_IRQHandler
-
- >> USART6_IRQHandler
-
-
-Warming_LinkError (Thumb, 136 bytes, Stack size 8 bytes, warming.o(i.Warming_LinkError))
-
[Stack]
- Max Depth = 16
- Call Chain = Warming_LinkError ⇒ Buzzer_ON
-
-
[Calls]
-
[Called By]
-
-Warming_MotorControl (Thumb, 40 bytes, Stack size 8 bytes, warming.o(i.Warming_MotorControl))
-
[Stack]
- Max Depth = 64
- Call Chain = Warming_MotorControl ⇒ M2006_CANSetHIDCurrent ⇒ CAN_TransmitStatus
-
-
[Calls]- >> M2006_CANSetHIDCurrent
-
- >> GM6020_CAN2SetLIDVoltage
-
- >> M3508_CANSetLIDCurrent
-
-
[Called By]
-
-Warming_RemoteDataERROR (Thumb, 8 bytes, Stack size 8 bytes, warming.o(i.Warming_RemoteDataERROR))
-
[Stack]
- Max Depth = 16
- Call Chain = Warming_RemoteDataERROR ⇒ LED_RON
-
-
[Calls]
-
[Called By]
-
-Warming_RemoteNoCheck (Thumb, 84 bytes, Stack size 8 bytes, warming.o(i.Warming_RemoteNoCheck))
-
[Stack]
- Max Depth = 16
- Call Chain = Warming_RemoteNoCheck ⇒ LED_RON
-
-
[Calls]- >> LED_RON
-
- >> LED_ROFF
-
-
[Called By]
-
-__ARM_fpclassifyf (Thumb, 38 bytes, Stack size 0 bytes, fpclassifyf.o(i.__ARM_fpclassifyf))
-
[Called By]
- >> __hardfp_sinf
-
- >> __hardfp_atan2f
-
- >> __hardfp_asinf
-
-
-__hardfp_asinf (Thumb, 258 bytes, Stack size 16 bytes, asinf.o(i.__hardfp_asinf))
-
[Stack]
- Max Depth = 32
- Call Chain = __hardfp_asinf ⇒ sqrtf
-
-
[Calls]- >> __set_errno
-
- >> __mathlib_flt_underflow
-
- >> __mathlib_flt_invalid
-
- >> __mathlib_flt_infnan
-
- >> __ARM_fpclassifyf
-
- >> sqrtf
-
-
[Called By]
-
-__hardfp_atan2f (Thumb, 594 bytes, Stack size 32 bytes, atan2f.o(i.__hardfp_atan2f))
-
[Stack]
- Max Depth = 32
- Call Chain = __hardfp_atan2f
-
-
[Calls]- >> __set_errno
-
- >> __mathlib_flt_underflow
-
- >> __mathlib_flt_infnan2
-
- >> __ARM_fpclassifyf
-
-
[Called By]
-
-__hardfp_cosf (Thumb, 280 bytes, Stack size 8 bytes, cosf.o(i.__hardfp_cosf))
-
[Stack]
- Max Depth = 28
- Call Chain = __hardfp_cosf ⇒ __mathlib_rredf2
-
-
[Calls]- >> __set_errno
-
- >> __mathlib_rredf2
-
- >> __mathlib_flt_invalid
-
- >> __mathlib_flt_infnan
-
-
[Called By]
-
-__hardfp_sinf (Thumb, 344 bytes, Stack size 16 bytes, sinf.o(i.__hardfp_sinf))
-
[Stack]
- Max Depth = 36
- Call Chain = __hardfp_sinf ⇒ __mathlib_rredf2
-
-
[Calls]- >> __set_errno
-
- >> __mathlib_rredf2
-
- >> __mathlib_flt_underflow
-
- >> __mathlib_flt_invalid
-
- >> __mathlib_flt_infnan
-
- >> __ARM_fpclassifyf
-
-
[Called By]
-
-__hardfp_sqrtf (Thumb, 58 bytes, Stack size 16 bytes, sqrtf.o(i.__hardfp_sqrtf))
-
[Stack]
- Max Depth = 16
- Call Chain = __hardfp_sqrtf
-
-
[Calls]
-
[Called By]
-
-__mathlib_flt_infnan (Thumb, 6 bytes, Stack size 0 bytes, funder.o(i.__mathlib_flt_infnan))
-
[Called By]
- >> __hardfp_sinf
-
- >> __hardfp_cosf
-
- >> __hardfp_asinf
-
-
-__mathlib_flt_infnan2 (Thumb, 6 bytes, Stack size 0 bytes, funder.o(i.__mathlib_flt_infnan2))
-
[Called By]
-
-__mathlib_flt_invalid (Thumb, 10 bytes, Stack size 0 bytes, funder.o(i.__mathlib_flt_invalid))
-
[Called By]
- >> __hardfp_sinf
-
- >> __hardfp_cosf
-
- >> __hardfp_asinf
-
-
-__mathlib_flt_underflow (Thumb, 10 bytes, Stack size 0 bytes, funder.o(i.__mathlib_flt_underflow))
-
[Called By]
- >> __hardfp_sinf
-
- >> __hardfp_atan2f
-
- >> __hardfp_asinf
-
-
-__mathlib_rredf2 (Thumb, 316 bytes, Stack size 20 bytes, rredf.o(i.__mathlib_rredf2))
-
[Stack]
- Max Depth = 20
- Call Chain = __mathlib_rredf2
-
-
[Called By]- >> __hardfp_sinf
-
- >> __hardfp_cosf
-
-
-__scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)
-
-
__scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)
-
-
__scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)
-
-
__set_errno (Thumb, 6 bytes, Stack size 0 bytes, errno.o(i.__set_errno))
-
[Called By]
- >> sqrtf
-
- >> __hardfp_sqrtf
-
- >> __hardfp_sinf
-
- >> __hardfp_cosf
-
- >> __hardfp_atan2f
-
- >> __hardfp_asinf
-
-
-get_angle (Thumb, 232 bytes, Stack size 24 bytes, ahrs.o(i.get_angle))
-
[Stack]
- Max Depth = 72
- Call Chain = get_angle ⇒ AHRS_atan2f ⇒ __hardfp_atan2f
-
-
[Calls]- >> AHRS_atan2f
-
- >> AHRS_asinf
-
-
[Called By]- >> TIM1_TRG_COM_TIM11_IRQHandler
-
-
-main (Thumb, 64 bytes, Stack size 0 bytes, main.o(i.main))
-
[Stack]
- Max Depth = 204
- Call Chain = main ⇒ AttitudeAlgorithms_Init ⇒ AHRS_init ⇒ angle_to_quat ⇒ AHRS_sinf ⇒ __hardfp_sinf ⇒ __mathlib_rredf2
-
-
[Calls]- >> IWDG_ReloadCounter
-
- >> Remote_Init
-
- >> LED_BON
-
- >> UART2_SendInit
-
- >> Delay_us
-
- >> Delay_s
-
- >> Visual_Init
-
- >> RefereeSystem_Init
-
- >> AttitudeAlgorithms_Init
-
- >> CloseLoopControl_Init
-
- >> CToC_MasterSendData
-
- >> CToC_MasterSendControl
-
- >> Warming_Init
-
- >> LinkCheck_Init
-
-
[Address Reference Count : 1]- entry9a.o(.ARM.Collect$$$$0000000B)
-
-sqrtf (Thumb, 62 bytes, Stack size 16 bytes, sqrtf.o(i.sqrtf))
-
[Stack]
- Max Depth = 16
- Call Chain = sqrtf
-
-
[Calls]
-
[Called By]
-
-
-Local Symbols
-
-SetSysClock (Thumb, 220 bytes, Stack size 12 bytes, system_stm32f4xx.o(i.SetSysClock))
-
[Stack]
- Max Depth = 12
- Call Chain = SetSysClock
-
-
[Called By]
-
-CheckITStatus (Thumb, 18 bytes, Stack size 0 bytes, stm32f4xx_can.o(i.CheckITStatus))
-
[Called By]
-
-AHRS_fabs (Thumb, 26 bytes, Stack size 0 bytes, ahrs.o(i.AHRS_fabs))
-
[Called By]
-
-accel_comple_filter (Thumb, 454 bytes, Stack size 64 bytes, ahrs.o(i.accel_comple_filter))
-
[Stack]
- Max Depth = 136
- Call Chain = accel_comple_filter ⇒ accel_update_kp_ki ⇒ AHRS_invSqrt ⇒ __hardfp_sqrtf
-
-
[Calls]- >> AHRS_invSqrt
-
- >> accel_update_kp_ki
-
-
[Called By]
-
-accel_update_kp_ki (Thumb, 370 bytes, Stack size 40 bytes, ahrs.o(i.accel_update_kp_ki))
-
[Stack]
- Max Depth = 72
- Call Chain = accel_update_kp_ki ⇒ AHRS_invSqrt ⇒ __hardfp_sqrtf
-
-
[Calls]- >> AHRS_invSqrt
-
- >> AHRS_fabs
-
-
[Called By]
-
-angle_to_quat (Thumb, 364 bytes, Stack size 48 bytes, ahrs.o(i.angle_to_quat))
-
[Stack]
- Max Depth = 100
- Call Chain = angle_to_quat ⇒ AHRS_sinf ⇒ __hardfp_sinf ⇒ __mathlib_rredf2
-
-
[Calls]- >> AHRS_sinf
-
- >> AHRS_cosf
-
-
[Called By]
-
-quat_normalization (Thumb, 126 bytes, Stack size 16 bytes, ahrs.o(i.quat_normalization))
-
[Stack]
- Max Depth = 48
- Call Chain = quat_normalization ⇒ AHRS_invSqrt ⇒ __hardfp_sqrtf
-
-
[Calls]
-
[Called By]
-
-update_w (Thumb, 122 bytes, Stack size 0 bytes, ahrs.o(i.update_w))
-
[Called By]
-
-
-Undefined Global Symbols
-
diff --git a/云台/云台-old/Objects/Project.lnp b/云台/云台-old/Objects/Project.lnp
deleted file mode 100644
index 5c20ca3..0000000
--- a/云台/云台-old/Objects/Project.lnp
+++ /dev/null
@@ -1,79 +0,0 @@
---cpu=Cortex-M4.fp.sp
-".\objects\startup_stm32f40_41xxx.o"
-".\objects\system_stm32f4xx.o"
-".\objects\misc.o"
-".\objects\stm32f4xx_adc.o"
-".\objects\stm32f4xx_can.o"
-".\objects\stm32f4xx_cec.o"
-".\objects\stm32f4xx_crc.o"
-".\objects\stm32f4xx_cryp.o"
-".\objects\stm32f4xx_cryp_aes.o"
-".\objects\stm32f4xx_cryp_des.o"
-".\objects\stm32f4xx_cryp_tdes.o"
-".\objects\stm32f4xx_dac.o"
-".\objects\stm32f4xx_dbgmcu.o"
-".\objects\stm32f4xx_dcmi.o"
-".\objects\stm32f4xx_dfsdm.o"
-".\objects\stm32f4xx_dma.o"
-".\objects\stm32f4xx_dma2d.o"
-".\objects\stm32f4xx_dsi.o"
-".\objects\stm32f4xx_exti.o"
-".\objects\stm32f4xx_flash.o"
-".\objects\stm32f4xx_flash_ramfunc.o"
-".\objects\stm32f4xx_fmpi2c.o"
-".\objects\stm32f4xx_fsmc.o"
-".\objects\stm32f4xx_gpio.o"
-".\objects\stm32f4xx_hash.o"
-".\objects\stm32f4xx_hash_md5.o"
-".\objects\stm32f4xx_hash_sha1.o"
-".\objects\stm32f4xx_i2c.o"
-".\objects\stm32f4xx_iwdg.o"
-".\objects\stm32f4xx_lptim.o"
-".\objects\stm32f4xx_ltdc.o"
-".\objects\stm32f4xx_pwr.o"
-".\objects\stm32f4xx_qspi.o"
-".\objects\stm32f4xx_rcc.o"
-".\objects\stm32f4xx_rng.o"
-".\objects\stm32f4xx_rtc.o"
-".\objects\stm32f4xx_sai.o"
-".\objects\stm32f4xx_sdio.o"
-".\objects\stm32f4xx_spdifrx.o"
-".\objects\stm32f4xx_spi.o"
-".\objects\stm32f4xx_syscfg.o"
-".\objects\stm32f4xx_tim.o"
-".\objects\stm32f4xx_usart.o"
-".\objects\stm32f4xx_wwdg.o"
-".\objects\delay.o"
-".\objects\tim.o"
-".\objects\uart.o"
-".\objects\myi2c.o"
-".\objects\can.o"
-".\AHRS\AHRS.lib"
-".\objects\ahrs_middleware.o"
-".\objects\user_lib.o"
-".\objects\led.o"
-".\objects\buzzer.o"
-".\objects\remote.o"
-".\objects\bmi088.o"
-".\objects\ist8310.o"
-".\objects\laser.o"
-".\objects\m3508.o"
-".\objects\gm6020.o"
-".\objects\m2006.o"
-".\objects\linkcheck.o"
-".\objects\warming.o"
-".\objects\ctoc.o"
-".\objects\closeloopcontrol.o"
-".\objects\attitudealgorithms.o"
-".\objects\imutemperaturecontrol.o"
-".\objects\pid.o"
-".\objects\gimbal.o"
-".\objects\refereesystem.o"
-".\objects\visual.o"
-".\objects\keyboard.o"
-".\objects\main.o"
-".\objects\stm32f4xx_it.o"
---library_type=microlib --strict --scatter ".\Objects\Project.sct"
---summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
---info sizes --info totals --info unused --info veneers
---list ".\Listings\Project.map" -o .\Objects\Project.axf
\ No newline at end of file
diff --git a/云台/云台-old/Objects/Project.sct b/云台/云台-old/Objects/Project.sct
deleted file mode 100644
index 3bb4046..0000000
--- a/云台/云台-old/Objects/Project.sct
+++ /dev/null
@@ -1,16 +0,0 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x08000000 0x00100000 { ; load region size_region
- ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- .ANY (+XO)
- }
- RW_IRAM1 0x20000000 0x00020000 { ; RW data
- .ANY (+RW +ZI)
- }
-}
-
diff --git a/云台/云台-old/Objects/Project_Target 1.dep b/云台/云台-old/Objects/Project_Target 1.dep
deleted file mode 100644
index e17c9f2..0000000
--- a/云台/云台-old/Objects/Project_Target 1.dep
+++ /dev/null
@@ -1,2706 +0,0 @@
-Dependencies for Project 'Project', Target 'Target 1': (DO NOT MODIFY !)
-CompilerVersion: 5060960::V5.06 update 7 (build 960)::.\ARMCOMPLIER506
-F (.\Start\core_cm4.h)(0x64D03162)()
-F (.\Start\core_cmFunc.h)(0x64D03162)()
-F (.\Start\core_cmInstr.h)(0x64D03162)()
-F (.\Start\core_cmSimd.h)(0x64D03162)()
-F (.\Start\startup_stm32f40_41xxx.s)(0x64D03132)(--cpu Cortex-M4.fp.sp -g --apcs=interwork --pd "__MICROLIB SETA 1"
-IC:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.17.1\Drivers\CMSIS\Device\ST\STM32F4xx\Include
--pd "__UVISION_VERSION SETA 538" --pd "STM32F407xx SETA 1"
--list .\listings\startup_stm32f40_41xxx.lst --xref -o .\objects\startup_stm32f40_41xxx.o --depend .\objects\startup_stm32f40_41xxx.d)
-F (.\Start\stm32f4xx.h)(0x66256792)()
-F (.\Start\system_stm32f4xx.c)(0x6548FDF8)(--c99 -c --cpu Cortex-M4.fp.sp -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Start -I .\Library -I .\System -I .\Algorithm -I .\AHRS -I .\Hardware -I .\Motor -I .\Function -I .\Control -I .\CarBody -I .\User --diag_suppress=188 --no-multibyte-chars --diag_suppress=186
-IC:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.17.1\Drivers\CMSIS\Device\ST\STM32F4xx\Include
-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -DARM_MATH_CM4 -D__FPU_PRESENT="1U"
-o .\objects\system_stm32f4xx.o --omf_browse .\objects\system_stm32f4xx.crf --depend .\objects\system_stm32f4xx.d)
-I (Start\stm32f4xx.h)(0x66256792)
-I (Start\core_cm4.h)(0x64D03162)
-I (C:\Keil_v5\ARM\ARMCOMPLIER506\include\stdint.h)(0x5E8E3CC2)
-I (.\Start\core_cmInstr.h)(0x64D03162)
-I (.\Start\core_cmFunc.h)(0x64D03162)
-I (.\Start\core_cmSimd.h)(0x64D03162)
-I (Start\system_stm32f4xx.h)(0x64D03132)
-I (.\User\stm32f4xx_conf.h)(0x64D03180)
-I (.\Library\stm32f4xx_adc.h)(0x64D03164)
-I (.\Start\stm32f4xx.h)(0x66256792)
-I (.\Library\stm32f4xx_crc.h)(0x64D03164)
-I (.\Library\stm32f4xx_dbgmcu.h)(0x64D03164)
-I (.\Library\stm32f4xx_dma.h)(0x64D03164)
-I (.\Library\stm32f4xx_exti.h)(0x64D03164)
-I (.\Library\stm32f4xx_flash.h)(0x64D03164)
-I (.\Library\stm32f4xx_gpio.h)(0x64D03164)
-I (.\Library\stm32f4xx_i2c.h)(0x64D03164)
-I (.\Library\stm32f4xx_iwdg.h)(0x64D03164)
-I (.\Library\stm32f4xx_pwr.h)(0x64D03164)
-I (.\Library\stm32f4xx_rcc.h)(0x64D03164)
-I (.\Library\stm32f4xx_rtc.h)(0x64D03164)
-I (.\Library\stm32f4xx_sdio.h)(0x64D03164)
-I (.\Library\stm32f4xx_spi.h)(0x64D03164)
-I (.\Library\stm32f4xx_syscfg.h)(0x64D03164)
-I (.\Library\stm32f4xx_tim.h)(0x64D03164)
-I (.\Library\stm32f4xx_usart.h)(0x64D03164)
-I (.\Library\stm32f4xx_wwdg.h)(0x64D03164)
-I (.\Library\misc.h)(0x64D03164)
-I (.\Library\stm32f4xx_cryp.h)(0x64D03164)
-I (.\Library\stm32f4xx_hash.h)(0x64D03164)
-I (.\Library\stm32f4xx_rng.h)(0x64D03164)
-I (.\Library\stm32f4xx_can.h)(0x64D03164)
-I (.\Library\stm32f4xx_dac.h)(0x64D03164)
-I (.\Library\stm32f4xx_dcmi.h)(0x64D03164)
-I (.\Library\stm32f4xx_fsmc.h)(0x64D03164)
-F (.\Start\system_stm32f4xx.h)(0x64D03132)()
-F (.\Library\misc.c)(0x64D03164)(--c99 -c --cpu Cortex-M4.fp.sp -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Start -I .\Library -I .\System -I .\Algorithm -I .\AHRS -I .\Hardware -I .\Motor -I .\Function -I .\Control -I .\CarBody -I .\User --diag_suppress=188 --no-multibyte-chars --diag_suppress=186
-IC:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.17.1\Drivers\CMSIS\Device\ST\STM32F4xx\Include
-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -DARM_MATH_CM4 -D__FPU_PRESENT="1U"
-o .\objects\misc.o --omf_browse .\objects\misc.crf --depend .\objects\misc.d)
-I (Library\misc.h)(0x64D03164)
-I (.\Start\stm32f4xx.h)(0x66256792)
-I (.\Start\core_cm4.h)(0x64D03162)
-I (C:\Keil_v5\ARM\ARMCOMPLIER506\include\stdint.h)(0x5E8E3CC2)
-I (.\Start\core_cmInstr.h)(0x64D03162)
-I (.\Start\core_cmFunc.h)(0x64D03162)
-I (.\Start\core_cmSimd.h)(0x64D03162)
-I (.\Start\system_stm32f4xx.h)(0x64D03132)
-I (.\User\stm32f4xx_conf.h)(0x64D03180)
-I (.\Library\stm32f4xx_adc.h)(0x64D03164)
-I (.\Library\stm32f4xx_crc.h)(0x64D03164)
-I (.\Library\stm32f4xx_dbgmcu.h)(0x64D03164)
-I (.\Library\stm32f4xx_dma.h)(0x64D03164)
-I (.\Library\stm32f4xx_exti.h)(0x64D03164)
-I (.\Library\stm32f4xx_flash.h)(0x64D03164)
-I (.\Library\stm32f4xx_gpio.h)(0x64D03164)
-I (.\Library\stm32f4xx_i2c.h)(0x64D03164)
-I (.\Library\stm32f4xx_iwdg.h)(0x64D03164)
-I (.\Library\stm32f4xx_pwr.h)(0x64D03164)
-I (.\Library\stm32f4xx_rcc.h)(0x64D03164)
-I (.\Library\stm32f4xx_rtc.h)(0x64D03164)
-I (.\Library\stm32f4xx_sdio.h)(0x64D03164)
-I (.\Library\stm32f4xx_spi.h)(0x64D03164)
-I (.\Library\stm32f4xx_syscfg.h)(0x64D03164)
-I (.\Library\stm32f4xx_tim.h)(0x64D03164)
-I (.\Library\stm32f4xx_usart.h)(0x64D03164)
-I (.\Library\stm32f4xx_wwdg.h)(0x64D03164)
-I (.\Library\misc.h)(0x64D03164)
-I (.\Library\stm32f4xx_cryp.h)(0x64D03164)
-I (.\Library\stm32f4xx_hash.h)(0x64D03164)
-I (.\Library\stm32f4xx_rng.h)(0x64D03164)
-I (.\Library\stm32f4xx_can.h)(0x64D03164)
-I (.\Library\stm32f4xx_dac.h)(0x64D03164)
-I (.\Library\stm32f4xx_dcmi.h)(0x64D03164)
-I (.\Library\stm32f4xx_fsmc.h)(0x64D03164)
-F (.\Library\misc.h)(0x64D03164)()
-F (.\Library\stm32f4xx_adc.c)(0x64D03164)(--c99 -c --cpu Cortex-M4.fp.sp -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Start -I .\Library -I .\System -I .\Algorithm -I .\AHRS -I .\Hardware -I .\Motor -I .\Function -I .\Control -I .\CarBody -I .\User --diag_suppress=188 --no-multibyte-chars --diag_suppress=186
-IC:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.17.1\Drivers\CMSIS\Device\ST\STM32F4xx\Include
-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -DARM_MATH_CM4 -D__FPU_PRESENT="1U"
-o .\objects\stm32f4xx_adc.o --omf_browse .\objects\stm32f4xx_adc.crf --depend .\objects\stm32f4xx_adc.d)
-I (Library\stm32f4xx_adc.h)(0x64D03164)
-I (.\Start\stm32f4xx.h)(0x66256792)
-I (.\Start\core_cm4.h)(0x64D03162)
-I (C:\Keil_v5\ARM\ARMCOMPLIER506\include\stdint.h)(0x5E8E3CC2)
-I (.\Start\core_cmInstr.h)(0x64D03162)
-I (.\Start\core_cmFunc.h)(0x64D03162)
-I (.\Start\core_cmSimd.h)(0x64D03162)
-I (.\Start\system_stm32f4xx.h)(0x64D03132)
-I (.\User\stm32f4xx_conf.h)(0x64D03180)
-I (.\Library\stm32f4xx_adc.h)(0x64D03164)
-I (.\Library\stm32f4xx_crc.h)(0x64D03164)
-I (.\Library\stm32f4xx_dbgmcu.h)(0x64D03164)
-I (.\Library\stm32f4xx_dma.h)(0x64D03164)
-I (.\Library\stm32f4xx_exti.h)(0x64D03164)
-I (.\Library\stm32f4xx_flash.h)(0x64D03164)
-I (.\Library\stm32f4xx_gpio.h)(0x64D03164)
-I (.\Library\stm32f4xx_i2c.h)(0x64D03164)
-I (.\Library\stm32f4xx_iwdg.h)(0x64D03164)
-I (.\Library\stm32f4xx_pwr.h)(0x64D03164)
-I (.\Library\stm32f4xx_rcc.h)(0x64D03164)
-I (.\Library\stm32f4xx_rtc.h)(0x64D03164)
-I (.\Library\stm32f4xx_sdio.h)(0x64D03164)
-I (.\Library\stm32f4xx_spi.h)(0x64D03164)
-I (.\Library\stm32f4xx_syscfg.h)(0x64D03164)
-I (.\Library\stm32f4xx_tim.h)(0x64D03164)
-I (.\Library\stm32f4xx_usart.h)(0x64D03164)
-I (.\Library\stm32f4xx_wwdg.h)(0x64D03164)
-I (.\Library\misc.h)(0x64D03164)
-I (.\Library\stm32f4xx_cryp.h)(0x64D03164)
-I (.\Library\stm32f4xx_hash.h)(0x64D03164)
-I (.\Library\stm32f4xx_rng.h)(0x64D03164)
-I (.\Library\stm32f4xx_can.h)(0x64D03164)
-I (.\Library\stm32f4xx_dac.h)(0x64D03164)
-I (.\Library\stm32f4xx_dcmi.h)(0x64D03164)
-I (.\Library\stm32f4xx_fsmc.h)(0x64D03164)
-F (.\Library\stm32f4xx_adc.h)(0x64D03164)()
-F (.\Library\stm32f4xx_can.c)(0x64D03164)(--c99 -c --cpu Cortex-M4.fp.sp -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Start -I .\Library -I .\System -I .\Algorithm -I .\AHRS -I .\Hardware -I .\Motor -I .\Function -I .\Control -I .\CarBody -I .\User --diag_suppress=188 --no-multibyte-chars --diag_suppress=186
-IC:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.17.1\Drivers\CMSIS\Device\ST\STM32F4xx\Include
-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -DARM_MATH_CM4 -D__FPU_PRESENT="1U"
-o .\objects\stm32f4xx_can.o --omf_browse .\objects\stm32f4xx_can.crf --depend .\objects\stm32f4xx_can.d)
-I (Library\stm32f4xx_can.h)(0x64D03164)
-I (.\Start\stm32f4xx.h)(0x66256792)
-I (.\Start\core_cm4.h)(0x64D03162)
-I (C:\Keil_v5\ARM\ARMCOMPLIER506\include\stdint.h)(0x5E8E3CC2)
-I (.\Start\core_cmInstr.h)(0x64D03162)
-I (.\Start\core_cmFunc.h)(0x64D03162)
-I (.\Start\core_cmSimd.h)(0x64D03162)
-I (.\Start\system_stm32f4xx.h)(0x64D03132)
-I (.\User\stm32f4xx_conf.h)(0x64D03180)
-I (.\Library\stm32f4xx_adc.h)(0x64D03164)
-I (.\Library\stm32f4xx_crc.h)(0x64D03164)
-I (.\Library\stm32f4xx_dbgmcu.h)(0x64D03164)
-I (.\Library\stm32f4xx_dma.h)(0x64D03164)
-I (.\Library\stm32f4xx_exti.h)(0x64D03164)
-I (.\Library\stm32f4xx_flash.h)(0x64D03164)
-I (.\Library\stm32f4xx_gpio.h)(0x64D03164)
-I (.\Library\stm32f4xx_i2c.h)(0x64D03164)
-I (.\Library\stm32f4xx_iwdg.h)(0x64D03164)
-I (.\Library\stm32f4xx_pwr.h)(0x64D03164)
-I (.\Library\stm32f4xx_rcc.h)(0x64D03164)
-I (.\Library\stm32f4xx_rtc.h)(0x64D03164)
-I (.\Library\stm32f4xx_sdio.h)(0x64D03164)
-I (.\Library\stm32f4xx_spi.h)(0x64D03164)
-I (.\Library\stm32f4xx_syscfg.h)(0x64D03164)
-I (.\Library\stm32f4xx_tim.h)(0x64D03164)
-I (.\Library\stm32f4xx_usart.h)(0x64D03164)
-I (.\Library\stm32f4xx_wwdg.h)(0x64D03164)
-I (.\Library\misc.h)(0x64D03164)
-I (.\Library\stm32f4xx_cryp.h)(0x64D03164)
-I (.\Library\stm32f4xx_hash.h)(0x64D03164)
-I (.\Library\stm32f4xx_rng.h)(0x64D03164)
-I (.\Library\stm32f4xx_can.h)(0x64D03164)
-I (.\Library\stm32f4xx_dac.h)(0x64D03164)
-I (.\Library\stm32f4xx_dcmi.h)(0x64D03164)
-I (.\Library\stm32f4xx_fsmc.h)(0x64D03164)
-F (.\Library\stm32f4xx_can.h)(0x64D03164)()
-F (.\Library\stm32f4xx_cec.c)(0x64D03164)(--c99 -c --cpu Cortex-M4.fp.sp -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Start -I .\Library -I .\System -I .\Algorithm -I .\AHRS -I .\Hardware -I .\Motor -I .\Function -I .\Control -I .\CarBody -I .\User --diag_suppress=188 --no-multibyte-chars --diag_suppress=186
-IC:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.17.1\Drivers\CMSIS\Device\ST\STM32F4xx\Include
-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -DARM_MATH_CM4 -D__FPU_PRESENT="1U"
-o .\objects\stm32f4xx_cec.o --omf_browse .\objects\stm32f4xx_cec.crf --depend .\objects\stm32f4xx_cec.d)
-I (Library\stm32f4xx_cec.h)(0x64D03164)
-I (.\Start\stm32f4xx.h)(0x66256792)
-I (.\Start\core_cm4.h)(0x64D03162)
-I (C:\Keil_v5\ARM\ARMCOMPLIER506\include\stdint.h)(0x5E8E3CC2)
-I (.\Start\core_cmInstr.h)(0x64D03162)
-I (.\Start\core_cmFunc.h)(0x64D03162)
-I (.\Start\core_cmSimd.h)(0x64D03162)
-I (.\Start\system_stm32f4xx.h)(0x64D03132)
-I (.\User\stm32f4xx_conf.h)(0x64D03180)
-I (.\Library\stm32f4xx_adc.h)(0x64D03164)
-I (.\Library\stm32f4xx_crc.h)(0x64D03164)
-I (.\Library\stm32f4xx_dbgmcu.h)(0x64D03164)
-I (.\Library\stm32f4xx_dma.h)(0x64D03164)
-I (.\Library\stm32f4xx_exti.h)(0x64D03164)
-I (.\Library\stm32f4xx_flash.h)(0x64D03164)
-I (.\Library\stm32f4xx_gpio.h)(0x64D03164)
-I (.\Library\stm32f4xx_i2c.h)(0x64D03164)
-I (.\Library\stm32f4xx_iwdg.h)(0x64D03164)
-I (.\Library\stm32f4xx_pwr.h)(0x64D03164)
-I (.\Library\stm32f4xx_rcc.h)(0x64D03164)
-I (.\Library\stm32f4xx_rtc.h)(0x64D03164)
-I (.\Library\stm32f4xx_sdio.h)(0x64D03164)
-I (.\Library\stm32f4xx_spi.h)(0x64D03164)
-I (.\Library\stm32f4xx_syscfg.h)(0x64D03164)
-I (.\Library\stm32f4xx_tim.h)(0x64D03164)
-I (.\Library\stm32f4xx_usart.h)(0x64D03164)
-I (.\Library\stm32f4xx_wwdg.h)(0x64D03164)
-I (.\Library\misc.h)(0x64D03164)
-I (.\Library\stm32f4xx_cryp.h)(0x64D03164)
-I (.\Library\stm32f4xx_hash.h)(0x64D03164)
-I (.\Library\stm32f4xx_rng.h)(0x64D03164)
-I (.\Library\stm32f4xx_can.h)(0x64D03164)
-I (.\Library\stm32f4xx_dac.h)(0x64D03164)
-I (.\Library\stm32f4xx_dcmi.h)(0x64D03164)
-I (.\Library\stm32f4xx_fsmc.h)(0x64D03164)
-F (.\Library\stm32f4xx_cec.h)(0x64D03164)()
-F (.\Library\stm32f4xx_crc.c)(0x64D03164)(--c99 -c --cpu Cortex-M4.fp.sp -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Start -I .\Library -I .\System -I .\Algorithm -I .\AHRS -I .\Hardware -I .\Motor -I .\Function -I .\Control -I .\CarBody -I .\User --diag_suppress=188 --no-multibyte-chars --diag_suppress=186
-IC:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.17.1\Drivers\CMSIS\Device\ST\STM32F4xx\Include
-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -DARM_MATH_CM4 -D__FPU_PRESENT="1U"
-o .\objects\stm32f4xx_crc.o --omf_browse .\objects\stm32f4xx_crc.crf --depend .\objects\stm32f4xx_crc.d)
-I (Library\stm32f4xx_crc.h)(0x64D03164)
-I (.\Start\stm32f4xx.h)(0x66256792)
-I (.\Start\core_cm4.h)(0x64D03162)
-I (C:\Keil_v5\ARM\ARMCOMPLIER506\include\stdint.h)(0x5E8E3CC2)
-I (.\Start\core_cmInstr.h)(0x64D03162)
-I (.\Start\core_cmFunc.h)(0x64D03162)
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-I (.\Start\system_stm32f4xx.h)(0x64D03132)
-I (.\User\stm32f4xx_conf.h)(0x64D03180)
-I (.\Library\stm32f4xx_adc.h)(0x64D03164)
-I (.\Library\stm32f4xx_crc.h)(0x64D03164)
-I (.\Library\stm32f4xx_dbgmcu.h)(0x64D03164)
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-I (.\Library\stm32f4xx_i2c.h)(0x64D03164)
-I (.\Library\stm32f4xx_iwdg.h)(0x64D03164)
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-I (.\Library\stm32f4xx_rcc.h)(0x64D03164)
-I (.\Library\stm32f4xx_rtc.h)(0x64D03164)
-I (.\Library\stm32f4xx_sdio.h)(0x64D03164)
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-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -DARM_MATH_CM4 -D__FPU_PRESENT="1U"
-o .\objects\stm32f4xx_cryp.o --omf_browse .\objects\stm32f4xx_cryp.crf --depend .\objects\stm32f4xx_cryp.d)
-I (Library\stm32f4xx_cryp.h)(0x64D03164)
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-o .\objects\stm32f4xx_cryp_aes.o --omf_browse .\objects\stm32f4xx_cryp_aes.crf --depend .\objects\stm32f4xx_cryp_aes.d)
-I (Library\stm32f4xx_cryp.h)(0x64D03164)
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-o .\objects\stm32f4xx_cryp_des.o --omf_browse .\objects\stm32f4xx_cryp_des.crf --depend .\objects\stm32f4xx_cryp_des.d)
-I (Library\stm32f4xx_cryp.h)(0x64D03164)
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-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -DARM_MATH_CM4 -D__FPU_PRESENT="1U"
-o .\objects\stm32f4xx_cryp_tdes.o --omf_browse .\objects\stm32f4xx_cryp_tdes.crf --depend .\objects\stm32f4xx_cryp_tdes.d)
-I (Library\stm32f4xx_cryp.h)(0x64D03164)
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-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -DARM_MATH_CM4 -D__FPU_PRESENT="1U"
-o .\objects\stm32f4xx_dac.o --omf_browse .\objects\stm32f4xx_dac.crf --depend .\objects\stm32f4xx_dac.d)
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-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -DARM_MATH_CM4 -D__FPU_PRESENT="1U"
-o .\objects\stm32f4xx_dbgmcu.o --omf_browse .\objects\stm32f4xx_dbgmcu.crf --depend .\objects\stm32f4xx_dbgmcu.d)
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-I (.\Library\stm32f4xx_adc.h)(0x64D03164)
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-I (.\Library\stm32f4xx_dbgmcu.h)(0x64D03164)
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-I (.\Library\stm32f4xx_i2c.h)(0x64D03164)
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-I (Library\stm32f4xx_rtc.h)(0x64D03164)
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-o .\objects\stm32f4xx_sai.o --omf_browse .\objects\stm32f4xx_sai.crf --depend .\objects\stm32f4xx_sai.d)
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-I (.\Library\stm32f4xx_dcmi.h)(0x64D03164)
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-I (Library\stm32f4xx_spi.h)(0x64D03164)
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-I (Library\stm32f4xx_syscfg.h)(0x64D03164)
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-o .\objects\stm32f4xx_tim.o --omf_browse .\objects\stm32f4xx_tim.crf --depend .\objects\stm32f4xx_tim.d)
-I (Library\stm32f4xx_tim.h)(0x64D03164)
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-o .\objects\stm32f4xx_usart.o --omf_browse .\objects\stm32f4xx_usart.crf --depend .\objects\stm32f4xx_usart.d)
-I (Library\stm32f4xx_usart.h)(0x64D03164)
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-o .\objects\stm32f4xx_wwdg.o --omf_browse .\objects\stm32f4xx_wwdg.crf --depend .\objects\stm32f4xx_wwdg.d)
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-I (.\Start\stm32f4xx.h)(0x66256792)
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-I (.\Library\stm32f4xx_adc.h)(0x64D03164)
-I (.\Library\stm32f4xx_crc.h)(0x64D03164)
-I (.\Library\stm32f4xx_dbgmcu.h)(0x64D03164)
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-o .\objects\uart.o --omf_browse .\objects\uart.crf --depend .\objects\uart.d)
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-I (C:\Keil_v5\ARM\ARMCOMPLIER506\include\stdio.h)(0x5E8E3CC2)
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-o .\objects\myi2c.o --omf_browse .\objects\myi2c.crf --depend .\objects\myi2c.d)
-I (.\Start\stm32f4xx.h)(0x66256792)
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-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -DARM_MATH_CM4 -D__FPU_PRESENT="1U"
-o .\objects\can.o --omf_browse .\objects\can.crf --depend .\objects\can.d)
-I (.\Start\stm32f4xx.h)(0x66256792)
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-I (System\CAN.h)(0x65FA62FA)
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-I (.\Motor\GM6020.h)(0x669D1130)
-I (.\Motor\M2006.h)(0x669D1190)
-I (.\Function\LinkCheck.h)(0x65FBCE1A)
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-I (.\Function\CToC.h)(0x67B560A8)
-I (.\CarBody\RefereeSystem.h)(0x66A1C17E)
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-IC:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.17.1\Drivers\CMSIS\Device\ST\STM32F4xx\Include
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-o .\objects\ahrs_middleware.o --omf_browse .\objects\ahrs_middleware.crf --depend .\objects\ahrs_middleware.d)
-I (AHRS\AHRS_MiddleWare.h)(0x64E14258)
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-I (C:\Keil_v5\ARM\ARMCOMPLIER506\include\string.h)(0x5E8E3CC2)
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-o .\objects\user_lib.o --omf_browse .\objects\user_lib.crf --depend .\objects\user_lib.d)
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-o .\objects\led.o --omf_browse .\objects\led.crf --depend .\objects\led.d)
-I (.\Start\stm32f4xx.h)(0x66256792)
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-I (.\Start\system_stm32f4xx.h)(0x64D03132)
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-I (.\Library\stm32f4xx_adc.h)(0x64D03164)
-I (.\Library\stm32f4xx_crc.h)(0x64D03164)
-I (.\Library\stm32f4xx_dbgmcu.h)(0x64D03164)
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-o .\objects\buzzer.o --omf_browse .\objects\buzzer.crf --depend .\objects\buzzer.d)
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-I (.\Library\stm32f4xx_wwdg.h)(0x64D03164)
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-I (.\Library\stm32f4xx_dac.h)(0x64D03164)
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-o .\objects\linkcheck.o --omf_browse .\objects\linkcheck.crf --depend .\objects\linkcheck.d)
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-o .\objects\warming.o --omf_browse .\objects\warming.crf --depend .\objects\warming.d)
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-o .\objects\ctoc.o --omf_browse .\objects\ctoc.crf --depend .\objects\ctoc.d)
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-o .\objects\attitudealgorithms.o --omf_browse .\objects\attitudealgorithms.crf --depend .\objects\attitudealgorithms.d)
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-o .\objects\imutemperaturecontrol.o --omf_browse .\objects\imutemperaturecontrol.crf --depend .\objects\imutemperaturecontrol.d)
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-I (.\Hardware\Buzzer.h)(0x6513BE16)
-I (.\Hardware\Remote.h)(0x669D1538)
-I (.\Hardware\BMI088.h)(0x65C25DDC)
-I (.\Hardware\IST8310.h)(0x65BE1E28)
-I (.\Hardware\Laser.h)(0x65C3A0BC)
-I (.\Motor\M3508.h)(0x669D1100)
-I (.\Motor\GM6020.h)(0x669D1130)
-I (.\Motor\M2006.h)(0x669D1190)
-I (.\System\UART.h)(0x669D08B6)
-I (.\System\MyI2C.h)(0x65C0681A)
-I (.\System\CAN.h)(0x65FA62FA)
-I (.\Control\PID.h)(0x6503C236)
-I (.\Function\LinkCheck.h)(0x65FBCE1A)
-I (.\Function\CloseLoopControl.h)(0x65B10F2C)
-I (.\Function\CToC.h)(0x67B560A8)
-I (.\Function\IMUTemperatureControl.h)(0x65C36CAE)
-I (.\Function\AttitudeAlgorithms.h)(0x660A3E88)
-I (.\Function\Warming.h)(0x66A19ADE)
-I (User\Parameter.h)(0x67B69A2D)
-I (.\CarBody\Gimbal.h)(0x67B149C3)
-I (.\CarBody\Visual.h)(0x67B57221)
-I (.\CarBody\RefereeSystem.h)(0x66A1C17E)
-I (.\CarBody\Keyboard.h)(0x66A1BD42)
-F (.\User\RM_C.h)(0x66A2BE9A)()
-F (.\User\Parameter.h)(0x67B69A2D)()
-F (.\User\stm32f4xx_conf.h)(0x64D03180)()
-F (.\User\stm32f4xx_it.c)(0x64D032D2)(--c99 -c --cpu Cortex-M4.fp.sp -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Start -I .\Library -I .\System -I .\Algorithm -I .\AHRS -I .\Hardware -I .\Motor -I .\Function -I .\Control -I .\CarBody -I .\User --diag_suppress=188 --no-multibyte-chars --diag_suppress=186
-IC:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.17.1\Drivers\CMSIS\Device\ST\STM32F4xx\Include
-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -DARM_MATH_CM4 -D__FPU_PRESENT="1U"
-o .\objects\stm32f4xx_it.o --omf_browse .\objects\stm32f4xx_it.crf --depend .\objects\stm32f4xx_it.d)
-I (User\stm32f4xx_it.h)(0x64D03180)
-I (.\Start\stm32f4xx.h)(0x66256792)
-I (.\Start\core_cm4.h)(0x64D03162)
-I (C:\Keil_v5\ARM\ARMCOMPLIER506\include\stdint.h)(0x5E8E3CC2)
-I (.\Start\core_cmInstr.h)(0x64D03162)
-I (.\Start\core_cmFunc.h)(0x64D03162)
-I (.\Start\core_cmSimd.h)(0x64D03162)
-I (.\Start\system_stm32f4xx.h)(0x64D03132)
-I (.\User\stm32f4xx_conf.h)(0x64D03180)
-I (.\Library\stm32f4xx_adc.h)(0x64D03164)
-I (.\Library\stm32f4xx_crc.h)(0x64D03164)
-I (.\Library\stm32f4xx_dbgmcu.h)(0x64D03164)
-I (.\Library\stm32f4xx_dma.h)(0x64D03164)
-I (.\Library\stm32f4xx_exti.h)(0x64D03164)
-I (.\Library\stm32f4xx_flash.h)(0x64D03164)
-I (.\Library\stm32f4xx_gpio.h)(0x64D03164)
-I (.\Library\stm32f4xx_i2c.h)(0x64D03164)
-I (.\Library\stm32f4xx_iwdg.h)(0x64D03164)
-I (.\Library\stm32f4xx_pwr.h)(0x64D03164)
-I (.\Library\stm32f4xx_rcc.h)(0x64D03164)
-I (.\Library\stm32f4xx_rtc.h)(0x64D03164)
-I (.\Library\stm32f4xx_sdio.h)(0x64D03164)
-I (.\Library\stm32f4xx_spi.h)(0x64D03164)
-I (.\Library\stm32f4xx_syscfg.h)(0x64D03164)
-I (.\Library\stm32f4xx_tim.h)(0x64D03164)
-I (.\Library\stm32f4xx_usart.h)(0x64D03164)
-I (.\Library\stm32f4xx_wwdg.h)(0x64D03164)
-I (.\Library\misc.h)(0x64D03164)
-I (.\Library\stm32f4xx_cryp.h)(0x64D03164)
-I (.\Library\stm32f4xx_hash.h)(0x64D03164)
-I (.\Library\stm32f4xx_rng.h)(0x64D03164)
-I (.\Library\stm32f4xx_can.h)(0x64D03164)
-I (.\Library\stm32f4xx_dac.h)(0x64D03164)
-I (.\Library\stm32f4xx_dcmi.h)(0x64D03164)
-I (.\Library\stm32f4xx_fsmc.h)(0x64D03164)
-F (.\User\stm32f4xx_it.h)(0x64D03180)()
diff --git a/云台/云台-old/Objects/ahrs_middleware.crf b/云台/云台-old/Objects/ahrs_middleware.crf
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diff --git a/云台/云台-old/Objects/attitudealgorithms.crf b/云台/云台-old/Objects/attitudealgorithms.crf
deleted file mode 100644
index 85e0ede..0000000
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diff --git a/云台/云台-old/Objects/bmi088.crf b/云台/云台-old/Objects/bmi088.crf
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index cd7dec8..0000000
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diff --git a/云台/云台-old/Objects/buzzer.crf b/云台/云台-old/Objects/buzzer.crf
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index 6afaee8..0000000
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diff --git a/云台/云台-old/Objects/can.crf b/云台/云台-old/Objects/can.crf
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index c82e490..0000000
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diff --git a/云台/云台-old/Objects/closeloopcontrol.crf b/云台/云台-old/Objects/closeloopcontrol.crf
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diff --git a/云台/云台-old/Objects/ctoc.crf b/云台/云台-old/Objects/ctoc.crf
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diff --git a/云台/云台-old/Objects/delay.crf b/云台/云台-old/Objects/delay.crf
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diff --git a/云台/云台-old/Objects/gimbal.crf b/云台/云台-old/Objects/gimbal.crf
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index cf69d0f..0000000
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diff --git a/云台/云台-old/Objects/gm6020.crf b/云台/云台-old/Objects/gm6020.crf
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diff --git a/云台/云台-old/Objects/imutemperaturecontrol.crf b/云台/云台-old/Objects/imutemperaturecontrol.crf
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index 66dcc84..0000000
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diff --git a/云台/云台-old/Objects/ist8310.crf b/云台/云台-old/Objects/ist8310.crf
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index 6d3f6b3..0000000
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diff --git a/云台/云台-old/Objects/keyboard.crf b/云台/云台-old/Objects/keyboard.crf
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diff --git a/云台/云台-old/Objects/laser.crf b/云台/云台-old/Objects/laser.crf
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index e3f85cf..0000000
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diff --git a/云台/云台-old/Objects/led.crf b/云台/云台-old/Objects/led.crf
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diff --git a/云台/云台-old/Objects/linkcheck.crf b/云台/云台-old/Objects/linkcheck.crf
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diff --git a/云台/云台-old/Objects/m2006.crf b/云台/云台-old/Objects/m2006.crf
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diff --git a/云台/云台-old/Objects/m3508.crf b/云台/云台-old/Objects/m3508.crf
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diff --git a/云台/云台-old/Objects/main.crf b/云台/云台-old/Objects/main.crf
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diff --git a/云台/云台-old/Objects/misc.crf b/云台/云台-old/Objects/misc.crf
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diff --git a/云台/云台-old/Objects/myi2c.crf b/云台/云台-old/Objects/myi2c.crf
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diff --git a/云台/云台-old/Objects/pid.crf b/云台/云台-old/Objects/pid.crf
deleted file mode 100644
index 51f6a0c..0000000
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diff --git a/云台/云台-old/Objects/refereesystem.crf b/云台/云台-old/Objects/refereesystem.crf
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diff --git a/云台/云台-old/Objects/remote.crf b/云台/云台-old/Objects/remote.crf
deleted file mode 100644
index 66d5215..0000000
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diff --git a/云台/云台-old/Objects/stm32f4xx_adc.crf b/云台/云台-old/Objects/stm32f4xx_adc.crf
deleted file mode 100644
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diff --git a/云台/云台-old/Objects/stm32f4xx_can.crf b/云台/云台-old/Objects/stm32f4xx_can.crf
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index 059d5ed..0000000
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diff --git a/云台/云台-old/Objects/stm32f4xx_cec.crf b/云台/云台-old/Objects/stm32f4xx_cec.crf
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diff --git a/云台/云台-old/Objects/stm32f4xx_crc.crf b/云台/云台-old/Objects/stm32f4xx_crc.crf
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diff --git a/云台/云台-old/Objects/stm32f4xx_cryp.crf b/云台/云台-old/Objects/stm32f4xx_cryp.crf
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diff --git a/云台/云台-old/Objects/stm32f4xx_cryp_aes.crf b/云台/云台-old/Objects/stm32f4xx_cryp_aes.crf
deleted file mode 100644
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diff --git a/云台/云台-old/Objects/stm32f4xx_cryp_des.crf b/云台/云台-old/Objects/stm32f4xx_cryp_des.crf
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diff --git a/云台/云台-old/Objects/stm32f4xx_cryp_tdes.crf b/云台/云台-old/Objects/stm32f4xx_cryp_tdes.crf
deleted file mode 100644
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diff --git a/云台/云台-old/Objects/stm32f4xx_dac.crf b/云台/云台-old/Objects/stm32f4xx_dac.crf
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index 9c3e235..0000000
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diff --git a/云台/云台-old/Objects/stm32f4xx_dbgmcu.crf b/云台/云台-old/Objects/stm32f4xx_dbgmcu.crf
deleted file mode 100644
index 864d60c..0000000
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diff --git a/云台/云台-old/Objects/stm32f4xx_dcmi.crf b/云台/云台-old/Objects/stm32f4xx_dcmi.crf
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diff --git a/云台/云台-old/Objects/stm32f4xx_dfsdm.crf b/云台/云台-old/Objects/stm32f4xx_dfsdm.crf
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diff --git a/云台/云台-old/Objects/stm32f4xx_dma.crf b/云台/云台-old/Objects/stm32f4xx_dma.crf
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diff --git a/云台/云台-old/Objects/stm32f4xx_dma2d.crf b/云台/云台-old/Objects/stm32f4xx_dma2d.crf
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diff --git a/云台/云台-old/Objects/stm32f4xx_dsi.crf b/云台/云台-old/Objects/stm32f4xx_dsi.crf
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diff --git a/云台/云台-old/Objects/stm32f4xx_exti.crf b/云台/云台-old/Objects/stm32f4xx_exti.crf
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diff --git a/云台/云台-old/Objects/stm32f4xx_flash.crf b/云台/云台-old/Objects/stm32f4xx_flash.crf
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index ea56ae4..0000000
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diff --git a/云台/云台-old/Objects/stm32f4xx_flash_ramfunc.crf b/云台/云台-old/Objects/stm32f4xx_flash_ramfunc.crf
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diff --git a/云台/云台-old/Objects/stm32f4xx_fmpi2c.crf b/云台/云台-old/Objects/stm32f4xx_fmpi2c.crf
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diff --git a/云台/云台-old/Objects/stm32f4xx_fsmc.crf b/云台/云台-old/Objects/stm32f4xx_fsmc.crf
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diff --git a/云台/云台-old/Objects/stm32f4xx_gpio.crf b/云台/云台-old/Objects/stm32f4xx_gpio.crf
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diff --git a/云台/云台-old/Objects/stm32f4xx_hash.crf b/云台/云台-old/Objects/stm32f4xx_hash.crf
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diff --git a/云台/云台-old/Objects/stm32f4xx_hash_md5.crf b/云台/云台-old/Objects/stm32f4xx_hash_md5.crf
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diff --git a/云台/云台-old/Objects/stm32f4xx_i2c.crf b/云台/云台-old/Objects/stm32f4xx_i2c.crf
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diff --git a/云台/云台-old/Objects/stm32f4xx_lptim.crf b/云台/云台-old/Objects/stm32f4xx_lptim.crf
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diff --git a/云台/云台-old/Objects/stm32f4xx_ltdc.crf b/云台/云台-old/Objects/stm32f4xx_ltdc.crf
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diff --git a/云台/云台-old/Objects/stm32f4xx_pwr.crf b/云台/云台-old/Objects/stm32f4xx_pwr.crf
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diff --git a/云台/云台-old/Objects/stm32f4xx_qspi.crf b/云台/云台-old/Objects/stm32f4xx_qspi.crf
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diff --git a/云台/云台-old/Project.uvguix.peng1 b/云台/云台-old/Project.uvguix.peng1
deleted file mode 100644
index f87c25e..0000000
--- a/云台/云台-old/Project.uvguix.peng1
+++ /dev/null
@@ -1,2202 +0,0 @@
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diff --git a/云台/云台-old/Project.uvoptx b/云台/云台-old/Project.uvoptx
deleted file mode 100644
index 0263cfa..0000000
--- a/云台/云台-old/Project.uvoptx
+++ /dev/null
@@ -1,2271 +0,0 @@
-
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- ### uVision Project, (C) Keil Software
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diff --git a/云台/云台-old/Project.uvprojx b/云台/云台-old/Project.uvprojx
deleted file mode 100644
index 4b433b5..0000000
--- a/云台/云台-old/Project.uvprojx
+++ /dev/null
@@ -1,1197 +0,0 @@
-
-
-
- 2.1
-
- ### uVision Project, (C) Keil Software
-
-
-
- Target 1
- 0x4
- ARM-ADS
- 5060960::V5.06 update 7 (build 960)::.\ARMCOMPLIER506
- 0
-
-
- STM32F407IGHx
- STMicroelectronics
- Keil.STM32F4xx_DFP.2.17.1
- https://www.keil.com/pack/
- IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE
-
-
- UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407IGHx$CMSIS\Flash\STM32F4xx_1024.FLM))
- 0
- $$Device:STM32F407IGHx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h
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- 3
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- SARMCM3.DLL
- -REMAP -MPU
- DCM.DLL
- -pCM4
- SARMCM3.DLL
- -MPU
- TCM.DLL
- -pCM4
-
-
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- "" ()
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- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
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-
- 0
- 0
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- 8
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-
- --diag_suppress=188 --no-multibyte-chars --diag_suppress=186
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-
- stm32f4xx_flash.h
- 5
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-
- stm32f4xx_flash_ramfunc.c
- 1
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-
-
- stm32f4xx_flash_ramfunc.h
- 5
- .\Library\stm32f4xx_flash_ramfunc.h
-
-
- stm32f4xx_fmpi2c.c
- 1
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-
-
- stm32f4xx_fmpi2c.h
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-
-
- stm32f4xx_fsmc.c
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-
-
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-
-
- stm32f4xx_gpio.c
- 1
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-
-
- stm32f4xx_gpio.h
- 5
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-
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-
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-
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-
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-
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-
-
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-
-
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-
-
-
-
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-
-
- LED.c
- 1
- .\Hardware\LED.c
-
-
- LED.h
- 5
- .\Hardware\LED.h
-
-
- Buzzer.c
- 1
- .\Hardware\Buzzer.c
-
-
- Buzzer.h
- 5
- .\Hardware\Buzzer.h
-
-
- Remote.c
- 1
- .\Hardware\Remote.c
-
-
- Remote.h
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- .\Hardware\Remote.h
-
-
- BMI088.c
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-
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- .\Hardware\BMI088.h
-
-
- IST8310.c
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- .\Hardware\IST8310.c
-
-
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-
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-
-
-
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-
-
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-
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- .\Motor\M3508.h
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-
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-
-
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-
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-
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-
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-
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-
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-
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-
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-
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-
-
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-
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-
-
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-
-
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-
-
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-
-
-
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-
-
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-
-
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-
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-
-
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-
-
- RefereeSystem_CRCTable.h
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-
-
- Visual.c
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-
-
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- .\CarBody\Visual.h
-
-
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-
-
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- .\CarBody\Keyboard.h
-
-
-
-
- User
-
-
- main.c
- 1
- .\User\main.c
-
-
- RM_C.h
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- .\User\RM_C.h
-
-
- Parameter.h
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- .\User\Parameter.h
-
-
- stm32f4xx_conf.h
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-
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-
-
-
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-
diff --git a/云台/云台-old/Start/core_cm4.h b/云台/云台-old/Start/core_cm4.h
deleted file mode 100644
index 9749c27..0000000
--- a/云台/云台-old/Start/core_cm4.h
+++ /dev/null
@@ -1,1858 +0,0 @@
-/**************************************************************************//**
- * @file core_cm4.h
- * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version V4.10
- * @date 18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M4
- @{
- */
-
-/* CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
-#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
- __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x04) /*!< Cortex-M Core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TMS470__ )
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __CSMC__ )
- #define __packed
- #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
- #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
- #define __STATIC_INLINE static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __TMS470__ )
- #if defined __TI_VFP_SUPPORT__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __CSMC__ ) /* Cosmic */
- #if ( __CSMC__ & 0x400) // FPU present for parser
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-#endif
-
-#include /* standard types definitions */
-#include /* Core Instruction Access */
-#include /* Core Function Access */
-#include /* Compiler specific SIMD Intrinsics */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM4_REV
- #define __CM4_REV 0x0000
- #warning "__CM4_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- IO Type Qualifiers are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/*@} end of group Cortex_M4 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core FPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/** \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31 /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30 /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29 /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28 /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-#define APSR_Q_Pos 27 /*!< APSR: Q Position */
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos 16 /*!< APSR: GE Position */
-#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
-
-
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31 /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29 /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28 /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
-#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos 24 /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
-#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/** \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24];
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24];
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24];
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24];
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56];
- __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644];
- __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/** \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[5];
- __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/** \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1];
- __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/** \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __O union
- {
- __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864];
- __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15];
- __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15];
- __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29];
- __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43];
- __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6];
- __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1];
- __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1];
- __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1];
- __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/** \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2];
- __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55];
- __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131];
- __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759];
- __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1];
- __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39];
- __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8];
- __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/** \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if (__FPU_PRESENT == 1)
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_FPU Floating Point Unit (FPU)
- \brief Type definitions for the Floating Point Unit (FPU)
- @{
- */
-
-/** \brief Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
- uint32_t RESERVED0[1];
- __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
- __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
- __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
- __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
- __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register */
-#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register */
-#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register */
-#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-#endif
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/** \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-#if (__FPU_PRESENT == 1)
- #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
- #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/** \brief Set Priority Grouping
-
- The function sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/** \brief Get Priority Grouping
-
- The function reads the priority grouping field from the NVIC Interrupt Controller.
-
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/** \brief Enable External Interrupt
-
- The function enables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief Disable External Interrupt
-
- The function disables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief Get Pending Interrupt
-
- The function reads the pending register in the NVIC and returns the pending bit
- for the specified interrupt.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief Set Pending Interrupt
-
- The function sets the pending bit of an external interrupt.
-
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief Clear Pending Interrupt
-
- The function clears the pending bit of an external interrupt.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief Get Active Interrupt
-
- The function reads the active register in NVIC and returns the active bit.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief Set Interrupt Priority
-
- The function sets the priority of an interrupt.
-
- \note The priority cannot be set for every core interrupt.
-
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if((int32_t)IRQn < 0) {
- SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else {
- NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/** \brief Get Interrupt Priority
-
- The function reads the priority of an interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
-
-
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented
- priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if((int32_t)IRQn < 0) {
- return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
- }
- else {
- return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/** \brief Encode Priority
-
- The function encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/** \brief Decode Priority
-
- The function decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/** \brief System Reset
-
- The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1) { __NOP(); } /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief System Tick Configuration
-
- The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
-
- \param [in] ticks Number of ticks between two interrupts.
-
- \return 0 Function succeeded.
- \return 1 Function failed.
-
- \note When the variable __Vendor_SysTickConfig is set to 1, then the
- function SysTick_Config is not included. In this case, the file device.h
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief ITM Send Character
-
- The function transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
- \param [in] ch Character to transmit.
-
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
- ITM->PORT[0].u8 = (uint8_t)ch;
- }
- return (ch);
-}
-
-
-/** \brief ITM Receive Character
-
- The function inputs a character via the external variable \ref ITM_RxBuffer.
-
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/** \brief ITM Check Character
-
- The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/云台/云台-old/Start/core_cmFunc.h b/云台/云台-old/Start/core_cmFunc.h
deleted file mode 100644
index b6ad0a4..0000000
--- a/云台/云台-old/Start/core_cmFunc.h
+++ /dev/null
@@ -1,664 +0,0 @@
-/**************************************************************************//**
- * @file core_cmFunc.h
- * @brief CMSIS Cortex-M Core Function Access Header File
- * @version V4.10
- * @date 18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* intrinsic void __enable_irq(); */
-/* intrinsic void __disable_irq(); */
-
-/** \brief Get Control Register
-
- This function returns the content of the Control Register.
-
- \return Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
-
-
-/** \brief Set Control Register
-
- This function writes the given value to the Control Register.
-
- \param [in] control Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-
-/** \brief Get IPSR Register
-
- This function returns the content of the IPSR Register.
-
- \return IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
- register uint32_t __regIPSR __ASM("ipsr");
- return(__regIPSR);
-}
-
-
-/** \brief Get APSR Register
-
- This function returns the content of the APSR Register.
-
- \return APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
- register uint32_t __regAPSR __ASM("apsr");
- return(__regAPSR);
-}
-
-
-/** \brief Get xPSR Register
-
- This function returns the content of the xPSR Register.
-
- \return xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
- register uint32_t __regXPSR __ASM("xpsr");
- return(__regXPSR);
-}
-
-
-/** \brief Get Process Stack Pointer
-
- This function returns the current value of the Process Stack Pointer (PSP).
-
- \return PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- return(__regProcessStackPointer);
-}
-
-
-/** \brief Set Process Stack Pointer
-
- This function assigns the given value to the Process Stack Pointer (PSP).
-
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief Get Main Stack Pointer
-
- This function returns the current value of the Main Stack Pointer (MSP).
-
- \return MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- return(__regMainStackPointer);
-}
-
-
-/** \brief Set Main Stack Pointer
-
- This function assigns the given value to the Main Stack Pointer (MSP).
-
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief Get Priority Mask
-
- This function returns the current state of the priority mask bit from the Priority Mask Register.
-
- \return Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-
-
-/** \brief Set Priority Mask
-
- This function assigns the given value to the Priority Mask Register.
-
- \param [in] priMask Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-
-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief Enable FIQ
-
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq __enable_fiq
-
-
-/** \brief Disable FIQ
-
- This function disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq __disable_fiq
-
-
-/** \brief Get Base Priority
-
- This function returns the current value of the Base Priority register.
-
- \return Base Priority register value
- */
-__STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- register uint32_t __regBasePri __ASM("basepri");
- return(__regBasePri);
-}
-
-
-/** \brief Set Base Priority
-
- This function assigns the given value to the Base Priority register.
-
- \param [in] basePri Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
- register uint32_t __regBasePri __ASM("basepri");
- __regBasePri = (basePri & 0xff);
-}
-
-
-/** \brief Set Base Priority with condition
-
- This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
- or the new value increases the BASEPRI priority level.
-
- \param [in] basePri Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
- register uint32_t __regBasePriMax __ASM("basepri_max");
- __regBasePriMax = (basePri & 0xff);
-}
-
-
-/** \brief Get Fault Mask
-
- This function returns the current value of the Fault Mask register.
-
- \return Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- return(__regFaultMask);
-}
-
-
-/** \brief Set Fault Mask
-
- This function assigns the given value to the Fault Mask register.
-
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
-
-/** \brief Get FPSCR
-
- This function returns the current value of the Floating Point Status/Control register.
-
- \return Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- return(__regfpscr);
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Set FPSCR
-
- This function assigns the given value to the Floating Point Status/Control register.
-
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief Enable IRQ Interrupts
-
- This function enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
- __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/** \brief Disable IRQ Interrupts
-
- This function disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
-{
- __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/** \brief Get Control Register
-
- This function returns the content of the Control Register.
-
- \return Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Control Register
-
- This function writes the given value to the Control Register.
-
- \param [in] control Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-/** \brief Get IPSR Register
-
- This function returns the content of the IPSR Register.
-
- \return IPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Get APSR Register
-
- This function returns the content of the APSR Register.
-
- \return APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Get xPSR Register
-
- This function returns the content of the xPSR Register.
-
- \return xPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Get Process Stack Pointer
-
- This function returns the current value of the Process Stack Pointer (PSP).
-
- \return PSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Process Stack Pointer
-
- This function assigns the given value to the Process Stack Pointer (PSP).
-
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
-}
-
-
-/** \brief Get Main Stack Pointer
-
- This function returns the current value of the Main Stack Pointer (MSP).
-
- \return MSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Main Stack Pointer
-
- This function assigns the given value to the Main Stack Pointer (MSP).
-
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
-}
-
-
-/** \brief Get Priority Mask
-
- This function returns the current state of the priority mask bit from the Priority Mask Register.
-
- \return Priority Mask value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Priority Mask
-
- This function assigns the given value to the Priority Mask Register.
-
- \param [in] priMask Priority Mask
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Enable FIQ
-
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
-{
- __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/** \brief Disable FIQ
-
- This function disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
-{
- __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/** \brief Get Base Priority
-
- This function returns the current value of the Base Priority register.
-
- \return Base Priority register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Base Priority
-
- This function assigns the given value to the Base Priority register.
-
- \param [in] basePri Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
-}
-
-
-/** \brief Set Base Priority with condition
-
- This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
- or the new value increases the BASEPRI priority level.
-
- \param [in] basePri Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
-{
- __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
-}
-
-
-/** \brief Get Fault Mask
-
- This function returns the current value of the Fault Mask register.
-
- \return Fault Mask register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Fault Mask
-
- This function assigns the given value to the Fault Mask register.
-
- \param [in] faultMask Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
-
-/** \brief Get FPSCR
-
- This function returns the current value of the Floating Point Status/Control register.
-
- \return Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- uint32_t result;
-
- /* Empty asm statement works as a scheduling barrier */
- __ASM volatile ("");
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
- __ASM volatile ("");
- return(result);
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Set FPSCR
-
- This function assigns the given value to the Floating Point Status/Control register.
-
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- /* Empty asm statement works as a scheduling barrier */
- __ASM volatile ("");
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
- __ASM volatile ("");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-#endif /* __CORE_CMFUNC_H */
diff --git a/云台/云台-old/Start/core_cmInstr.h b/云台/云台-old/Start/core_cmInstr.h
deleted file mode 100644
index fca425c..0000000
--- a/云台/云台-old/Start/core_cmInstr.h
+++ /dev/null
@@ -1,916 +0,0 @@
-/**************************************************************************//**
- * @file core_cmInstr.h
- * @brief CMSIS Cortex-M Core Instruction Access Header File
- * @version V4.10
- * @date 18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ########################## Core Instruction Access ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
- Access to dedicated instructions
- @{
-*/
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief No Operation
-
- No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP __nop
-
-
-/** \brief Wait For Interrupt
-
- Wait For Interrupt is a hint instruction that suspends execution
- until one of a number of events occurs.
- */
-#define __WFI __wfi
-
-
-/** \brief Wait For Event
-
- Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-#define __WFE __wfe
-
-
-/** \brief Send Event
-
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV __sev
-
-
-/** \brief Instruction Synchronization Barrier
-
- Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or
- memory, after the instruction has been completed.
- */
-#define __ISB() do {\
- __schedule_barrier();\
- __isb(0xF);\
- __schedule_barrier();\
- } while (0)
-
-/** \brief Data Synchronization Barrier
-
- This function acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() do {\
- __schedule_barrier();\
- __dsb(0xF);\
- __schedule_barrier();\
- } while (0)
-
-/** \brief Data Memory Barrier
-
- This function ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-#define __DMB() do {\
- __schedule_barrier();\
- __dmb(0xF);\
- __schedule_barrier();\
- } while (0)
-
-/** \brief Reverse byte order (32 bit)
-
- This function reverses the byte order in integer value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __REV __rev
-
-
-/** \brief Reverse byte order (16 bit)
-
- This function reverses the byte order in two unsigned short values.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
- rev16 r0, r0
- bx lr
-}
-#endif
-
-/** \brief Reverse byte order in signed short value
-
- This function reverses the byte order in a signed short value with sign extension to integer.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
- revsh r0, r0
- bx lr
-}
-#endif
-
-
-/** \brief Rotate Right in unsigned value (32 bit)
-
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
- \param [in] value Value to rotate
- \param [in] value Number of Bits to rotate
- \return Rotated value
- */
-#define __ROR __ror
-
-
-/** \brief Breakpoint
-
- This function causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __breakpoint(value)
-
-
-/** \brief Reverse bit order of value
-
- This function reverses the bit order of the given value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
- #define __RBIT __rbit
-#else
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
- uint32_t result;
- int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
-
- result = value; // r will be reversed bits of v; first get LSB of v
- for (value >>= 1; value; value >>= 1)
- {
- result <<= 1;
- result |= value & 1;
- s--;
- }
- result <<= s; // shift when v's highest bits are zero
- return(result);
-}
-#endif
-
-
-/** \brief Count leading zeros
-
- This function counts the number of leading zeros of a data value.
-
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-#define __CLZ __clz
-
-
-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief LDR Exclusive (8 bit)
-
- This function executes a exclusive LDR instruction for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief LDR Exclusive (16 bit)
-
- This function executes a exclusive LDR instruction for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
-
-
-/** \brief LDR Exclusive (32 bit)
-
- This function executes a exclusive LDR instruction for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief STR Exclusive (8 bit)
-
- This function executes a exclusive STR instruction for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXB(value, ptr) __strex(value, ptr)
-
-
-/** \brief STR Exclusive (16 bit)
-
- This function executes a exclusive STR instruction for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXH(value, ptr) __strex(value, ptr)
-
-
-/** \brief STR Exclusive (32 bit)
-
- This function executes a exclusive STR instruction for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXW(value, ptr) __strex(value, ptr)
-
-
-/** \brief Remove the exclusive lock
-
- This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX __clrex
-
-
-/** \brief Signed Saturate
-
- This function saturates a signed value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT __ssat
-
-
-/** \brief Unsigned Saturate
-
- This function saturates an unsigned value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT __usat
-
-
-/** \brief Rotate Right with Extend (32 bit)
-
- This function moves each bit of a bitstring right by one bit.
- The carry input is shifted in at the left end of the bitstring.
-
- \param [in] value Value to rotate
- \return Rotated value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
-{
- rrx r0, r0
- bx lr
-}
-#endif
-
-
-/** \brief LDRT Unprivileged (8 bit)
-
- This function executes a Unprivileged LDRT instruction for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
-
-
-/** \brief LDRT Unprivileged (16 bit)
-
- This function executes a Unprivileged LDRT instruction for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
-
-
-/** \brief LDRT Unprivileged (32 bit)
-
- This function executes a Unprivileged LDRT instruction for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
-
-
-/** \brief STRT Unprivileged (8 bit)
-
- This function executes a Unprivileged STRT instruction for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-#define __STRBT(value, ptr) __strt(value, ptr)
-
-
-/** \brief STRT Unprivileged (16 bit)
-
- This function executes a Unprivileged STRT instruction for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-#define __STRHT(value, ptr) __strt(value, ptr)
-
-
-/** \brief STRT Unprivileged (32 bit)
-
- This function executes a Unprivileged STRT instruction for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-#define __STRT(value, ptr) __strt(value, ptr)
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constrant "l"
- * Otherwise, use general registers, specified by constrant "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/** \brief No Operation
-
- No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
-{
- __ASM volatile ("nop");
-}
-
-
-/** \brief Wait For Interrupt
-
- Wait For Interrupt is a hint instruction that suspends execution
- until one of a number of events occurs.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
-{
- __ASM volatile ("wfi");
-}
-
-
-/** \brief Wait For Event
-
- Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
-{
- __ASM volatile ("wfe");
-}
-
-
-/** \brief Send Event
-
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
-{
- __ASM volatile ("sev");
-}
-
-
-/** \brief Instruction Synchronization Barrier
-
- Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or
- memory, after the instruction has been completed.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
-{
- __ASM volatile ("isb 0xF":::"memory");
-}
-
-
-/** \brief Data Synchronization Barrier
-
- This function acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
-{
- __ASM volatile ("dsb 0xF":::"memory");
-}
-
-
-/** \brief Data Memory Barrier
-
- This function ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
-{
- __ASM volatile ("dmb 0xF":::"memory");
-}
-
-
-/** \brief Reverse byte order (32 bit)
-
- This function reverses the byte order in integer value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
- return __builtin_bswap32(value);
-#else
- uint32_t result;
-
- __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-#endif
-}
-
-
-/** \brief Reverse byte order (16 bit)
-
- This function reverses the byte order in two unsigned short values.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/** \brief Reverse byte order in signed short value
-
- This function reverses the byte order in a signed short value with sign extension to integer.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- return (short)__builtin_bswap16(value);
-#else
- uint32_t result;
-
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-#endif
-}
-
-
-/** \brief Rotate Right in unsigned value (32 bit)
-
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
- \param [in] value Value to rotate
- \param [in] value Number of Bits to rotate
- \return Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
- return (op1 >> op2) | (op1 << (32 - op2));
-}
-
-
-/** \brief Breakpoint
-
- This function causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __ASM volatile ("bkpt "#value)
-
-
-/** \brief Reverse bit order of value
-
- This function reverses the bit order of the given value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
- uint32_t result;
-
-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
- int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
-
- result = value; // r will be reversed bits of v; first get LSB of v
- for (value >>= 1; value; value >>= 1)
- {
- result <<= 1;
- result |= value & 1;
- s--;
- }
- result <<= s; // shift when v's highest bits are zero
-#endif
- return(result);
-}
-
-
-/** \brief Count leading zeros
-
- This function counts the number of leading zeros of a data value.
-
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-#define __CLZ __builtin_clz
-
-
-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief LDR Exclusive (8 bit)
-
- This function executes a exclusive LDR instruction for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint8_t) result); /* Add explicit type cast here */
-}
-
-
-/** \brief LDR Exclusive (16 bit)
-
- This function executes a exclusive LDR instruction for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint16_t) result); /* Add explicit type cast here */
-}
-
-
-/** \brief LDR Exclusive (32 bit)
-
- This function executes a exclusive LDR instruction for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- return(result);
-}
-
-
-/** \brief STR Exclusive (8 bit)
-
- This function executes a exclusive STR instruction for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/** \brief STR Exclusive (16 bit)
-
- This function executes a exclusive STR instruction for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/** \brief STR Exclusive (32 bit)
-
- This function executes a exclusive STR instruction for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- return(result);
-}
-
-
-/** \brief Remove the exclusive lock
-
- This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
-{
- __ASM volatile ("clrex" ::: "memory");
-}
-
-
-/** \brief Signed Saturate
-
- This function saturates a signed value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/** \brief Unsigned Saturate
-
- This function saturates an unsigned value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/** \brief Rotate Right with Extend (32 bit)
-
- This function moves each bit of a bitstring right by one bit.
- The carry input is shifted in at the left end of the bitstring.
-
- \param [in] value Value to rotate
- \return Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/** \brief LDRT Unprivileged (8 bit)
-
- This function executes a Unprivileged LDRT instruction for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint8_t) result); /* Add explicit type cast here */
-}
-
-
-/** \brief LDRT Unprivileged (16 bit)
-
- This function executes a Unprivileged LDRT instruction for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint16_t) result); /* Add explicit type cast here */
-}
-
-
-/** \brief LDRT Unprivileged (32 bit)
-
- This function executes a Unprivileged LDRT instruction for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
- return(result);
-}
-
-
-/** \brief STRT Unprivileged (8 bit)
-
- This function executes a Unprivileged STRT instruction for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
-{
- __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
-}
-
-
-/** \brief STRT Unprivileged (16 bit)
-
- This function executes a Unprivileged STRT instruction for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
-{
- __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
-}
-
-
-/** \brief STRT Unprivileged (32 bit)
-
- This function executes a Unprivileged STRT instruction for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
-{
- __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
-}
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */
diff --git a/云台/云台-old/Start/core_cmSimd.h b/云台/云台-old/Start/core_cmSimd.h
deleted file mode 100644
index 7b8e37f..0000000
--- a/云台/云台-old/Start/core_cmSimd.h
+++ /dev/null
@@ -1,697 +0,0 @@
-/**************************************************************************//**
- * @file core_cmSimd.h
- * @brief CMSIS Cortex-M SIMD Header File
- * @version V4.10
- * @date 18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CMSIMD_H
-#define __CORE_CMSIMD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- ******************************************************************************/
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
- Access to dedicated SIMD instructions
- @{
-*/
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-#define __SADD8 __sadd8
-#define __QADD8 __qadd8
-#define __SHADD8 __shadd8
-#define __UADD8 __uadd8
-#define __UQADD8 __uqadd8
-#define __UHADD8 __uhadd8
-#define __SSUB8 __ssub8
-#define __QSUB8 __qsub8
-#define __SHSUB8 __shsub8
-#define __USUB8 __usub8
-#define __UQSUB8 __uqsub8
-#define __UHSUB8 __uhsub8
-#define __SADD16 __sadd16
-#define __QADD16 __qadd16
-#define __SHADD16 __shadd16
-#define __UADD16 __uadd16
-#define __UQADD16 __uqadd16
-#define __UHADD16 __uhadd16
-#define __SSUB16 __ssub16
-#define __QSUB16 __qsub16
-#define __SHSUB16 __shsub16
-#define __USUB16 __usub16
-#define __UQSUB16 __uqsub16
-#define __UHSUB16 __uhsub16
-#define __SASX __sasx
-#define __QASX __qasx
-#define __SHASX __shasx
-#define __UASX __uasx
-#define __UQASX __uqasx
-#define __UHASX __uhasx
-#define __SSAX __ssax
-#define __QSAX __qsax
-#define __SHSAX __shsax
-#define __USAX __usax
-#define __UQSAX __uqsax
-#define __UHSAX __uhsax
-#define __USAD8 __usad8
-#define __USADA8 __usada8
-#define __SSAT16 __ssat16
-#define __USAT16 __usat16
-#define __UXTB16 __uxtb16
-#define __UXTAB16 __uxtab16
-#define __SXTB16 __sxtb16
-#define __SXTAB16 __sxtab16
-#define __SMUAD __smuad
-#define __SMUADX __smuadx
-#define __SMLAD __smlad
-#define __SMLADX __smladx
-#define __SMLALD __smlald
-#define __SMLALDX __smlaldx
-#define __SMUSD __smusd
-#define __SMUSDX __smusdx
-#define __SMLSD __smlsd
-#define __SMLSDX __smlsdx
-#define __SMLSLD __smlsld
-#define __SMLSLDX __smlsldx
-#define __SEL __sel
-#define __QADD __qadd
-#define __QSUB __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
- ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
-
-#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
- ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
-
-#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
- ((int64_t)(ARG3) << 32) ) >> 32))
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ // Little endian
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else // Big endian
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ // Little endian
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else // Big endian
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ // Little endian
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else // Big endian
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ // Little endian
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else // Big endian
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- if (ARG3 == 0) \
- __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
- else \
- __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/* not yet supported */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include
-
-#endif
-
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CMSIMD_H */
diff --git a/云台/云台-old/Start/startup_stm32f401xx.s b/云台/云台-old/Start/startup_stm32f401xx.s
deleted file mode 100644
index 6f44c76..0000000
--- a/云台/云台-old/Start/startup_stm32f401xx.s
+++ /dev/null
@@ -1,379 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f401xx.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F401xx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure the system clock
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD 0 ; Reserved
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD 0 ; Reserved
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD FPU_IRQHandler ; FPU
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SPI4_IRQHandler ; SPI4
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-DMA1_Stream7_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-ETH_IRQHandler
-OTG_FS_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-FPU_IRQHandler
-SPI4_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/云台/云台-old/Start/startup_stm32f40_41xxx.s b/云台/云台-old/Start/startup_stm32f40_41xxx.s
deleted file mode 100644
index 817309a..0000000
--- a/云台/云台-old/Start/startup_stm32f40_41xxx.s
+++ /dev/null
@@ -1,429 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f40_41xxx.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure the system clock and the external SRAM mounted on
-;* STM324xG-EVAL board to be used as data memory (optional,
-;* to be enabled by user)
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD CAN1_TX_IRQHandler ; CAN1 TX
- DCD CAN1_RX0_IRQHandler ; CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FSMC_IRQHandler ; FSMC
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD ETH_IRQHandler ; Ethernet
- DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD DCMI_IRQHandler ; DCMI
- DCD CRYP_IRQHandler ; CRYP crypto
- DCD HASH_RNG_IRQHandler ; Hash and Rng
- DCD FPU_IRQHandler ; FPU
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT CAN1_TX_IRQHandler [WEAK]
- EXPORT CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
- EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT FSMC_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT ETH_IRQHandler [WEAK]
- EXPORT ETH_WKUP_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
- EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_HS_IRQHandler [WEAK]
- EXPORT DCMI_IRQHandler [WEAK]
- EXPORT CRYP_IRQHandler [WEAK]
- EXPORT HASH_RNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-DMA1_Stream7_IRQHandler
-FSMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-ETH_IRQHandler
-ETH_WKUP_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-OTG_HS_EP1_OUT_IRQHandler
-OTG_HS_EP1_IN_IRQHandler
-OTG_HS_WKUP_IRQHandler
-OTG_HS_IRQHandler
-DCMI_IRQHandler
-CRYP_IRQHandler
-HASH_RNG_IRQHandler
-FPU_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/云台/云台-old/Start/startup_stm32f40xx.s b/云台/云台-old/Start/startup_stm32f40xx.s
deleted file mode 100644
index 836de4d..0000000
--- a/云台/云台-old/Start/startup_stm32f40xx.s
+++ /dev/null
@@ -1,430 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f40xx.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
-;* Same as startup_stm32f40_41xxx.s and maintained for legacy purpose
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure the system clock and the external SRAM mounted on
-;* STM324xG-EVAL board to be used as data memory (optional,
-;* to be enabled by user)
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD CAN1_TX_IRQHandler ; CAN1 TX
- DCD CAN1_RX0_IRQHandler ; CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FSMC_IRQHandler ; FSMC
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD ETH_IRQHandler ; Ethernet
- DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD DCMI_IRQHandler ; DCMI
- DCD CRYP_IRQHandler ; CRYP crypto
- DCD HASH_RNG_IRQHandler ; Hash and Rng
- DCD FPU_IRQHandler ; FPU
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT CAN1_TX_IRQHandler [WEAK]
- EXPORT CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
- EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT FSMC_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT ETH_IRQHandler [WEAK]
- EXPORT ETH_WKUP_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
- EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_HS_IRQHandler [WEAK]
- EXPORT DCMI_IRQHandler [WEAK]
- EXPORT CRYP_IRQHandler [WEAK]
- EXPORT HASH_RNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-DMA1_Stream7_IRQHandler
-FSMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-ETH_IRQHandler
-ETH_WKUP_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-OTG_HS_EP1_OUT_IRQHandler
-OTG_HS_EP1_IN_IRQHandler
-OTG_HS_WKUP_IRQHandler
-OTG_HS_IRQHandler
-DCMI_IRQHandler
-CRYP_IRQHandler
-HASH_RNG_IRQHandler
-FPU_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/云台/云台-old/Start/startup_stm32f410xx.s b/云台/云台-old/Start/startup_stm32f410xx.s
deleted file mode 100644
index 8854ffb..0000000
--- a/云台/云台-old/Start/startup_stm32f410xx.s
+++ /dev/null
@@ -1,383 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f410xx.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F410xx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_IRQHandler ; TIM1 Update
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD 0 ; Reserved
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TIM5_IRQHandler ; TIM5
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
- DCD 0 ; Reserved
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD RNG_IRQHandler ; RNG
- DCD FPU_IRQHandler ; FPU
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SPI5_IRQHandler ; SPI5
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event
- DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error
- DCD LPTIM1_IRQHandler ; LP TIM1
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT RNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT SPI5_IRQHandler [WEAK]
- EXPORT FMPI2C1_EV_IRQHandler [WEAK]
- EXPORT FMPI2C1_ER_IRQHandler [WEAK]
- EXPORT LPTIM1_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-DMA1_Stream7_IRQHandler
-TIM5_IRQHandler
-TIM6_DAC_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-RNG_IRQHandler
-FPU_IRQHandler
-SPI5_IRQHandler
-FMPI2C1_EV_IRQHandler
-FMPI2C1_ER_IRQHandler
-LPTIM1_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/云台/云台-old/Start/startup_stm32f411xe.s b/云台/云台-old/Start/startup_stm32f411xe.s
deleted file mode 100644
index e5a1811..0000000
--- a/云台/云台-old/Start/startup_stm32f411xe.s
+++ /dev/null
@@ -1,380 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f411xe.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F411xExx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD 0 ; Reserved
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD 0 ; Reserved
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD FPU_IRQHandler ; FPU
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SPI4_IRQHandler ; SPI4
- DCD SPI5_IRQHandler ; SPI5
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SPI5_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-DMA1_Stream7_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-OTG_FS_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-FPU_IRQHandler
-SPI4_IRQHandler
-SPI5_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/云台/云台-old/Start/startup_stm32f412xg.s b/云台/云台-old/Start/startup_stm32f412xg.s
deleted file mode 100644
index cb7d9d7..0000000
--- a/云台/云台-old/Start/startup_stm32f412xg.s
+++ /dev/null
@@ -1,434 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f412xg.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F412xG devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD CAN1_TX_IRQHandler ; CAN1 TX
- DCD CAN1_RX0_IRQHandler ; CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD 0 ; Reserved
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TIM6_IRQHandler ; TIM6
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global interrupt
- DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global interrupt
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD RNG_IRQHandler ; RNG
- DCD FPU_IRQHandler ; FPU
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SPI4_IRQHandler ; SPI4
- DCD SPI5_IRQHandler ; SPI5
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD QUADSPI_IRQHandler ; QuadSPI
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event
- DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT CAN1_TX_IRQHandler [WEAK]
- EXPORT CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
- EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT TIM6_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
- EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT RNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SPI5_IRQHandler [WEAK]
- EXPORT QUADSPI_IRQHandler [WEAK]
- EXPORT FMPI2C1_EV_IRQHandler [WEAK]
- EXPORT FMPI2C1_ER_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-DMA1_Stream7_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-DFSDM1_FLT0_IRQHandler
-DFSDM1_FLT1_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-RNG_IRQHandler
-FPU_IRQHandler
-SPI4_IRQHandler
-SPI5_IRQHandler
-QUADSPI_IRQHandler
-FMPI2C1_EV_IRQHandler
-FMPI2C1_ER_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/云台/云台-old/Start/startup_stm32f413_423xx.s b/云台/云台-old/Start/startup_stm32f413_423xx.s
deleted file mode 100644
index c7908a6..0000000
--- a/云台/云台-old/Start/startup_stm32f413_423xx.s
+++ /dev/null
@@ -1,475 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f423xx.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F423xx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD CAN1_TX_IRQHandler ; CAN1 TX
- DCD CAN1_RX0_IRQHandler ; CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FSMC_IRQHandler ; FSMC
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6, DAC1 and DAC2
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global interrupt
- DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global interrupt
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD CAN3_TX_IRQHandler ; CAN3 TX
- DCD CAN3_RX0_IRQHandler ; CAN3 RX0
- DCD CAN3_RX1_IRQHandler ; CAN3 RX1
- DCD CAN3_SCE_IRQHandler ; CAN3 SCE
- DCD 0 ; Reserved
- DCD AES_IRQHandler ; AES
- DCD RNG_IRQHandler ; RNG
- DCD FPU_IRQHandler ; FPU
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
- DCD SPI4_IRQHandler ; SPI4
- DCD SPI5_IRQHandler ; SPI5
- DCD 0 ; Reserved
- DCD SAI1_IRQHandler ; SAI1
- DCD UART9_IRQHandler ; UART9
- DCD UART10_IRQHandler ; UART10
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD QUADSPI_IRQHandler ; QuadSPI
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event
- DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error
- DCD LPTIM1_IRQHandler ; LPTIM1
- DCD DFSDM2_FLT0_IRQHandler ; DFSDM2 Filter0
- DCD DFSDM2_FLT1_IRQHandler ; DFSDM2 Filter1
- DCD DFSDM2_FLT2_IRQHandler ; DFSDM2 Filter2
- DCD DFSDM2_FLT3_IRQHandler ; DFSDM2 Filter3
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT CAN1_TX_IRQHandler [WEAK]
- EXPORT CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
- EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT FSMC_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
- EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT CAN3_TX_IRQHandler [WEAK]
- EXPORT CAN3_RX0_IRQHandler [WEAK]
- EXPORT CAN3_RX1_IRQHandler [WEAK]
- EXPORT CAN3_SCE_IRQHandler [WEAK]
- EXPORT AES_IRQHandler [WEAK]
- EXPORT RNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
- EXPORT UART8_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SPI5_IRQHandler [WEAK]
- EXPORT SAI1_IRQHandler [WEAK]
- EXPORT UART9_IRQHandler [WEAK]
- EXPORT UART10_IRQHandler [WEAK]
- EXPORT QUADSPI_IRQHandler [WEAK]
- EXPORT FMPI2C1_EV_IRQHandler [WEAK]
- EXPORT FMPI2C1_ER_IRQHandler [WEAK]
- EXPORT LPTIM1_IRQHandler [WEAK]
- EXPORT DFSDM2_FLT0_IRQHandler [WEAK]
- EXPORT DFSDM2_FLT1_IRQHandler [WEAK]
- EXPORT DFSDM2_FLT2_IRQHandler [WEAK]
- EXPORT DFSDM2_FLT3_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-DMA1_Stream7_IRQHandler
-FSMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-DFSDM1_FLT0_IRQHandler
-DFSDM1_FLT1_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-CAN3_TX_IRQHandler
-CAN3_RX0_IRQHandler
-CAN3_RX1_IRQHandler
-CAN3_SCE_IRQHandler
-AES_IRQHandler
-RNG_IRQHandler
-FPU_IRQHandler
-UART7_IRQHandler
-UART8_IRQHandler
-SPI4_IRQHandler
-SPI5_IRQHandler
-SAI1_IRQHandler
-UART9_IRQHandler
-UART10_IRQHandler
-QUADSPI_IRQHandler
-FMPI2C1_EV_IRQHandler
-FMPI2C1_ER_IRQHandler
-LPTIM1_IRQHandler
-DFSDM2_FLT0_IRQHandler
-DFSDM2_FLT1_IRQHandler
-DFSDM2_FLT2_IRQHandler
-DFSDM2_FLT3_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/云台/云台-old/Start/startup_stm32f427_437xx.s b/云台/云台-old/Start/startup_stm32f427_437xx.s
deleted file mode 100644
index a3f3d1c..0000000
--- a/云台/云台-old/Start/startup_stm32f427_437xx.s
+++ /dev/null
@@ -1,451 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f427_437xx.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F427xx/437xx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure the system clock and the external SRAM/SDRAM mounted
-;* on STM324x7I-EVAL board to be used as data memory
-;* (optional, to be enabled by user)
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD CAN1_TX_IRQHandler ; CAN1 TX
- DCD CAN1_RX0_IRQHandler ; CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FMC_IRQHandler ; FMC
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD ETH_IRQHandler ; Ethernet
- DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD DCMI_IRQHandler ; DCMI
- DCD CRYP_IRQHandler ; CRYP crypto
- DCD HASH_RNG_IRQHandler ; Hash and Rng
- DCD FPU_IRQHandler ; FPU
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
- DCD SPI4_IRQHandler ; SPI4
- DCD SPI5_IRQHandler ; SPI5
- DCD SPI6_IRQHandler ; SPI6
- DCD SAI1_IRQHandler ; SAI1
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA2D_IRQHandler ; DMA2D
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT CAN1_TX_IRQHandler [WEAK]
- EXPORT CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
- EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT FMC_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT ETH_IRQHandler [WEAK]
- EXPORT ETH_WKUP_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
- EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_HS_IRQHandler [WEAK]
- EXPORT DCMI_IRQHandler [WEAK]
- EXPORT CRYP_IRQHandler [WEAK]
- EXPORT HASH_RNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
- EXPORT UART8_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SPI5_IRQHandler [WEAK]
- EXPORT SPI6_IRQHandler [WEAK]
- EXPORT SAI1_IRQHandler [WEAK]
- EXPORT DMA2D_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-DMA1_Stream7_IRQHandler
-FMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-ETH_IRQHandler
-ETH_WKUP_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-OTG_HS_EP1_OUT_IRQHandler
-OTG_HS_EP1_IN_IRQHandler
-OTG_HS_WKUP_IRQHandler
-OTG_HS_IRQHandler
-DCMI_IRQHandler
-CRYP_IRQHandler
-HASH_RNG_IRQHandler
-FPU_IRQHandler
-UART7_IRQHandler
-UART8_IRQHandler
-SPI4_IRQHandler
-SPI5_IRQHandler
-SPI6_IRQHandler
-SAI1_IRQHandler
-DMA2D_IRQHandler
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/云台/云台-old/Start/startup_stm32f427x.s b/云台/云台-old/Start/startup_stm32f427x.s
deleted file mode 100644
index 4250781..0000000
--- a/云台/云台-old/Start/startup_stm32f427x.s
+++ /dev/null
@@ -1,452 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f427x.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F427xx/437xx devices vector table for MDK-ARM toolchain.
-;* Same as startup_stm32f427_437xx.s and maintained for legacy purpose
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure the system clock and the external SRAM/SDRAM mounted
-;* on STM324x9I-EVAL/STM324x7I-EVALs board to be used as data memory
-;* (optional, to be enabled by user)
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD CAN1_TX_IRQHandler ; CAN1 TX
- DCD CAN1_RX0_IRQHandler ; CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FMC_IRQHandler ; FMC
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD ETH_IRQHandler ; Ethernet
- DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD DCMI_IRQHandler ; DCMI
- DCD CRYP_IRQHandler ; CRYP crypto
- DCD HASH_RNG_IRQHandler ; Hash and Rng
- DCD FPU_IRQHandler ; FPU
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
- DCD SPI4_IRQHandler ; SPI4
- DCD SPI5_IRQHandler ; SPI5
- DCD SPI6_IRQHandler ; SPI6
- DCD SAI1_IRQHandler ; SAI1
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA2D_IRQHandler ; DMA2D
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT CAN1_TX_IRQHandler [WEAK]
- EXPORT CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
- EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT FMC_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT ETH_IRQHandler [WEAK]
- EXPORT ETH_WKUP_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
- EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_HS_IRQHandler [WEAK]
- EXPORT DCMI_IRQHandler [WEAK]
- EXPORT CRYP_IRQHandler [WEAK]
- EXPORT HASH_RNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
- EXPORT UART8_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SPI5_IRQHandler [WEAK]
- EXPORT SPI6_IRQHandler [WEAK]
- EXPORT SAI1_IRQHandler [WEAK]
- EXPORT DMA2D_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-DMA1_Stream7_IRQHandler
-FMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-ETH_IRQHandler
-ETH_WKUP_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-OTG_HS_EP1_OUT_IRQHandler
-OTG_HS_EP1_IN_IRQHandler
-OTG_HS_WKUP_IRQHandler
-OTG_HS_IRQHandler
-DCMI_IRQHandler
-CRYP_IRQHandler
-HASH_RNG_IRQHandler
-FPU_IRQHandler
-UART7_IRQHandler
-UART8_IRQHandler
-SPI4_IRQHandler
-SPI5_IRQHandler
-SPI6_IRQHandler
-SAI1_IRQHandler
-DMA2D_IRQHandler
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/云台/云台-old/Start/startup_stm32f429_439xx.s b/云台/云台-old/Start/startup_stm32f429_439xx.s
deleted file mode 100644
index a520435..0000000
--- a/云台/云台-old/Start/startup_stm32f429_439xx.s
+++ /dev/null
@@ -1,455 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f429_439xx.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F429xx/439xx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure the system clock and the external SRAM/SDRAM mounted
-;* on STM324x9I-EVAL boards to be used as data memory
-;* (optional, to be enabled by user)
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD CAN1_TX_IRQHandler ; CAN1 TX
- DCD CAN1_RX0_IRQHandler ; CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FMC_IRQHandler ; FMC
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD ETH_IRQHandler ; Ethernet
- DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD DCMI_IRQHandler ; DCMI
- DCD CRYP_IRQHandler ; CRYP crypto
- DCD HASH_RNG_IRQHandler ; Hash and Rng
- DCD FPU_IRQHandler ; FPU
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
- DCD SPI4_IRQHandler ; SPI4
- DCD SPI5_IRQHandler ; SPI5
- DCD SPI6_IRQHandler ; SPI6
- DCD SAI1_IRQHandler ; SAI1
- DCD LTDC_IRQHandler ; LTDC
- DCD LTDC_ER_IRQHandler ; LTDC error
- DCD DMA2D_IRQHandler ; DMA2D
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT CAN1_TX_IRQHandler [WEAK]
- EXPORT CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
- EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT FMC_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT ETH_IRQHandler [WEAK]
- EXPORT ETH_WKUP_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
- EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_HS_IRQHandler [WEAK]
- EXPORT DCMI_IRQHandler [WEAK]
- EXPORT CRYP_IRQHandler [WEAK]
- EXPORT HASH_RNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
- EXPORT UART8_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SPI5_IRQHandler [WEAK]
- EXPORT SPI6_IRQHandler [WEAK]
- EXPORT SAI1_IRQHandler [WEAK]
- EXPORT LTDC_IRQHandler [WEAK]
- EXPORT LTDC_ER_IRQHandler [WEAK]
- EXPORT DMA2D_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-DMA1_Stream7_IRQHandler
-FMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-ETH_IRQHandler
-ETH_WKUP_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-OTG_HS_EP1_OUT_IRQHandler
-OTG_HS_EP1_IN_IRQHandler
-OTG_HS_WKUP_IRQHandler
-OTG_HS_IRQHandler
-DCMI_IRQHandler
-CRYP_IRQHandler
-HASH_RNG_IRQHandler
-FPU_IRQHandler
-UART7_IRQHandler
-UART8_IRQHandler
-SPI4_IRQHandler
-SPI5_IRQHandler
-SPI6_IRQHandler
-SAI1_IRQHandler
-LTDC_IRQHandler
-LTDC_ER_IRQHandler
-DMA2D_IRQHandler
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/云台/云台-old/Start/startup_stm32f446xx.s b/云台/云台-old/Start/startup_stm32f446xx.s
deleted file mode 100644
index 01b9988..0000000
--- a/云台/云台-old/Start/startup_stm32f446xx.s
+++ /dev/null
@@ -1,447 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f446xx.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F446x devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD CAN1_TX_IRQHandler ; CAN1 TX
- DCD CAN1_RX0_IRQHandler ; CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FMC_IRQHandler ; FMC
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD DCMI_IRQHandler ; DCMI
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD FPU_IRQHandler ; FPU
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SAI1_IRQHandler ; SAI1
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SAI2_IRQHandler ; SAI2
- DCD QuadSPI_IRQHandler ; QuadSPI
- DCD CEC_IRQHandler ; CEC
- DCD SPDIF_RX_IRQHandler ; SPDIF RX
- DCD FMPI2C1_Event_IRQHandler ; I2C 4 Event
- DCD FMPI2C1_Error_IRQHandler ; I2C 4 Error
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT CAN1_TX_IRQHandler [WEAK]
- EXPORT CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
- EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT FMC_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
- EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_HS_IRQHandler [WEAK]
- EXPORT DCMI_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SAI1_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SAI1_IRQHandler [WEAK]
- EXPORT SAI2_IRQHandler [WEAK]
- EXPORT QuadSPI_IRQHandler [WEAK]
- EXPORT CEC_IRQHandler [WEAK]
- EXPORT SPDIF_RX_IRQHandler [WEAK]
- EXPORT FMPI2C1_Event_IRQHandler [WEAK]
- EXPORT FMPI2C1_Error_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-DMA1_Stream7_IRQHandler
-FMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-OTG_HS_EP1_OUT_IRQHandler
-OTG_HS_EP1_IN_IRQHandler
-OTG_HS_WKUP_IRQHandler
-OTG_HS_IRQHandler
-DCMI_IRQHandler
-FPU_IRQHandler
-SPI4_IRQHandler
-SAI1_IRQHandler
-SAI2_IRQHandler
-QuadSPI_IRQHandler
-CEC_IRQHandler
-SPDIF_RX_IRQHandler
-FMPI2C1_Event_IRQHandler
-FMPI2C1_Error_IRQHandler
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/云台/云台-old/Start/startup_stm32f469_479xx.s b/云台/云台-old/Start/startup_stm32f469_479xx.s
deleted file mode 100644
index c823897..0000000
--- a/云台/云台-old/Start/startup_stm32f469_479xx.s
+++ /dev/null
@@ -1,458 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f469_479xx.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F469xx/479xx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD CAN1_TX_IRQHandler ; CAN1 TX
- DCD CAN1_RX0_IRQHandler ; CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FMC_IRQHandler ; FMC
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD ETH_IRQHandler ; Ethernet
- DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD DCMI_IRQHandler ; DCMI
- DCD CRYP_IRQHandler ; CRYPTO
- DCD HASH_RNG_IRQHandler ; Hash and Rng
- DCD FPU_IRQHandler ; FPU
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
- DCD SPI4_IRQHandler ; SPI4
- DCD SPI5_IRQHandler ; SPI5
- DCD SPI6_IRQHandler ; SPI6
- DCD SAI1_IRQHandler ; SAI1
- DCD LTDC_IRQHandler ; LTDC
- DCD LTDC_ER_IRQHandler ; LTDC error
- DCD DMA2D_IRQHandler ; DMA2D
- DCD QUADSPI_IRQHandler ; QUADSPI
- DCD DSI_IRQHandler ; DSI
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT CAN1_TX_IRQHandler [WEAK]
- EXPORT CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
- EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT FMC_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT ETH_IRQHandler [WEAK]
- EXPORT ETH_WKUP_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
- EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_HS_IRQHandler [WEAK]
- EXPORT DCMI_IRQHandler [WEAK]
- EXPORT CRYP_IRQHandler [WEAK]
- EXPORT HASH_RNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
- EXPORT UART8_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SPI5_IRQHandler [WEAK]
- EXPORT SPI6_IRQHandler [WEAK]
- EXPORT SAI1_IRQHandler [WEAK]
- EXPORT LTDC_IRQHandler [WEAK]
- EXPORT LTDC_ER_IRQHandler [WEAK]
- EXPORT DMA2D_IRQHandler [WEAK]
- EXPORT QUADSPI_IRQHandler [WEAK]
- EXPORT DSI_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-DMA1_Stream7_IRQHandler
-FMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-ETH_IRQHandler
-ETH_WKUP_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-OTG_HS_EP1_OUT_IRQHandler
-OTG_HS_EP1_IN_IRQHandler
-OTG_HS_WKUP_IRQHandler
-OTG_HS_IRQHandler
-DCMI_IRQHandler
-CRYP_IRQHandler
-HASH_RNG_IRQHandler
-FPU_IRQHandler
-UART7_IRQHandler
-UART8_IRQHandler
-SPI4_IRQHandler
-SPI5_IRQHandler
-SPI6_IRQHandler
-SAI1_IRQHandler
-LTDC_IRQHandler
-LTDC_ER_IRQHandler
-DMA2D_IRQHandler
-QUADSPI_IRQHandler
-DSI_IRQHandler
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/云台/云台-old/Start/stm32f4xx.h b/云台/云台-old/Start/stm32f4xx.h
deleted file mode 100644
index aa3b395..0000000
--- a/云台/云台-old/Start/stm32f4xx.h
+++ /dev/null
@@ -1,12059 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
- * This file contains all the peripheral register's definitions, bits
- * definitions and memory mapping for STM32F4xx devices.
- *
- * The file is the unique include file that the application programmer
- * is using in the C source code, usually in main.c. This file contains:
- * - Configuration section that allows to select:
- * - The device used in the target application
- * - To use or not the peripherals drivers in application code(i.e.
- * code will be based on direct access to peripherals registers
- * rather than drivers API), this option is controlled by
- * "#define USE_STDPERIPH_DRIVER"
- * - To change few application-specific parameters such as the HSE
- * crystal frequency
- * - Data structures and the address mapping for all peripherals
- * - Peripherals registers declarations and bits definition
- * - Macros to access peripherals registers hardware
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f4xx
- * @{
- */
-
-#ifndef __STM32F4xx_H
-#define __STM32F4xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Library_configuration_section
- * @{
- */
-
-/* Uncomment the line below according to the target STM32 device used in your
- application
- */
-
-#if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F410xx) && \
- !defined(STM32F411xE) && !defined(STM32F412xG) && !defined(STM32F413_423xx) && !defined(STM32F446xx) && !defined(STM32F469_479xx)
- /* #define STM32F40_41xxx */ /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG,
- STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE,
- STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
-
- /* #define STM32F427_437xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II,
- STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices */
-
- /* #define STM32F429_439xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI,
- STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI,
- STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI,
- STM32F439IG and STM32F439II Devices */
-
- /* #define STM32F401xx */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB, STM32F401VC,
- STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CExx, STM32F401RE and STM32F401VE Devices */
-
- /* #define STM32F410xx */ /*!< STM32F410Tx, STM32F410Cx and STM32F410Rx */
-
- /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
-
- /* #define STM32F412xG */ /*!< STM32F412CEU, STM32F412CGU, STM32F412ZET, STM32F412ZGT, STM32F412ZEJ, STM32F412ZGJ,
- STM32F412VET, STM32F412VGT, STM32F412VEH, STM32F412VGH, STM32F412RET, STM32F412RGT,
- STM32F412REY and STM32F412RGY Devices */
-
- /* #define STM32F413_423xx */ /*!< STM32F413CGU, STM32F413CHU, STM32F413MGY, STM32F413MHY, STM32F413RGT, STM32F413VGT,
- STM32F413ZGT, STM32F413RHT, STM32F413VHT, STM32F413ZHT, STM32F413VGH, STM32F413ZGJ,
- STM32F413VHH, STM32F413ZHJ, STM32F423CHU, STM32F423RHT, STM32F423VHT, STM32F423ZHT,
- STM32F423VHH and STM32F423ZHJ devices */
-
- /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC
- and STM32F446ZE Devices */
-
- /* #define STM32F469_479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG,
- STM32F479NG, STM32F479AE, STM32F479IE, STM32F479BE, STM32F479NE Devices */
-
-#endif /* STM32F40_41xxx && STM32F427_437xx && STM32F429_439xx && STM32F401xx && STM32F410xx && STM32F411xE && STM32F412xG && STM32F413_423xx && STM32F446xx && STM32F469_479xx */
-
-/* Old STM32F40XX definition, maintained for legacy purpose */
-#ifdef STM32F40XX
- #define STM32F40_41xxx
-#endif /* STM32F40XX */
-
-/* Old STM32F427X definition, maintained for legacy purpose */
-#ifdef STM32F427X
- #define STM32F427_437xx
-#endif /* STM32F427X */
-
-/* Tip: To avoid modifying this file each time you need to switch between these
- devices, you can define the device in your toolchain compiler preprocessor.
- */
-
-#if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F410xx) && \
- !defined(STM32F411xE) && !defined(STM32F412xG) && !defined(STM32F413_423xx) && !defined(STM32F446xx) && !defined(STM32F469_479xx)
- #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
-#endif /* STM32F40_41xxx && STM32F427_437xx && STM32F429_439xx && STM32F401xx && STM32F410xx && STM32F411xE && STM32F412xG && STM32F413_23xx && STM32F446xx && STM32F469_479xx */
-
-#if !defined (USE_STDPERIPH_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
- In this case, these drivers will not be included and the application code will
- be based on direct access to peripherals registers
- */
- /*#define USE_STDPERIPH_DRIVER */
-#endif /* USE_STDPERIPH_DRIVER */
-
-/**
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)
- used in your application
-
- Tip: To avoid modifying this file each time you need to use different HSE, you
- can define the HSE value in your toolchain compiler preprocessor.
- */
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || \
- defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
- #if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)12000000) /*!< Value of the External oscillator in Hz */
- #endif /* HSE_VALUE */
-#elif defined (STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
- #if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
- #endif /* HSE_VALUE */
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */
-/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
- Timeout value
- */
-#if !defined (HSE_STARTUP_TIMEOUT)
- #define HSE_STARTUP_TIMEOUT ((uint16_t)0x05000) /*!< Time out for HSE start up */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
- * @brief STM32F4XX Standard Peripherals Library version number V1.8.0
- */
-#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */
-#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
-#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
- |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
- |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
- |(__STM32F4XX_STDPERIPH_VERSION_RC))
-
-/**
- * @}
- */
-
-/** @addtogroup Configuration_section_for_CMSIS
- * @{
- */
-
-/**
- * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
- */
-#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-//#define __FPU_PRESENT 1 /*!< FPU present */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device
- * in @ref Library_configuration_section
- */
-typedef enum IRQn
-{
-/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
-/****** STM32 specific Interrupt Numbers **********************************************************************/
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
- TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
- RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
- FLASH_IRQn = 4, /*!< FLASH global Interrupt */
- RCC_IRQn = 5, /*!< RCC global Interrupt */
- EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
- EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
- EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
- EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
- EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
- DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
- DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
- DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
- DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
- DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
- DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
- DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
- ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
-
-#if defined(STM32F40_41xxx)
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FSMC_IRQn = 48, /*!< FSMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
- DCMI_IRQn = 78, /*!< DCMI global interrupt */
- CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
- HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
- FPU_IRQn = 81 /*!< FPU global interrupt */
-#endif /* STM32F40_41xxx */
-
-#if defined(STM32F427_437xx)
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FMC_IRQn = 48, /*!< FMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
- DCMI_IRQn = 78, /*!< DCMI global interrupt */
- CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
- HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- UART7_IRQn = 82, /*!< UART7 global interrupt */
- UART8_IRQn = 83, /*!< UART8 global interrupt */
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
- SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
- SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
- DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
-#endif /* STM32F427_437xx */
-
-#if defined(STM32F429_439xx)
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FMC_IRQn = 48, /*!< FMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
- DCMI_IRQn = 78, /*!< DCMI global interrupt */
- CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
- HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- UART7_IRQn = 82, /*!< UART7 global interrupt */
- UART8_IRQn = 83, /*!< UART8 global interrupt */
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
- SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
- SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
- LTDC_IRQn = 88, /*!< LTDC global Interrupt */
- LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
- DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
-#endif /* STM32F429_439xx */
-
-#if defined(STM32F410xx)
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global Interrupt and DAC Global Interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- RNG_IRQn = 80, /*!< RNG global Interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
- FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
- FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
- LPTIM1_IRQn = 97 /*!< LPTIM1 interrupt */
-#endif /* STM32F410xx */
-
-#if defined(STM32F401xx) || defined(STM32F411xE)
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
-#if defined(STM32F401xx)
- SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
-#endif /* STM32F411xE */
-#if defined(STM32F411xE)
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SPI5_IRQn = 85 /*!< SPI5 global Interrupt */
-#endif /* STM32F411xE */
-#endif /* STM32F401xx || STM32F411xE */
-
-#if defined(STM32F469_479xx)
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FMC_IRQn = 48, /*!< FMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
- DCMI_IRQn = 78, /*!< DCMI global interrupt */
- CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
- HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- UART7_IRQn = 82, /*!< UART7 global interrupt */
- UART8_IRQn = 83, /*!< UART8 global interrupt */
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
- SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
- SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
- LTDC_IRQn = 88, /*!< LTDC global Interrupt */
- LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
- DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
- QUADSPI_IRQn = 91, /*!< QUADSPI global Interrupt */
- DSI_IRQn = 92 /*!< DSI global Interrupt */
-#endif /* STM32F469_479xx */
-
-#if defined(STM32F446xx)
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FMC_IRQn = 48, /*!< FMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
- DCMI_IRQn = 78, /*!< DCMI global interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
- SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
- QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
- CEC_IRQn = 93, /*!< QuadSPI global Interrupt */
- SPDIF_RX_IRQn = 94, /*!< QuadSPI global Interrupt */
- FMPI2C1_EV_IRQn = 95, /*!< FMPI2C Event Interrupt */
- FMPI2C1_ER_IRQn = 96 /*!< FMPCI2C Error Interrupt */
-#endif /* STM32F446xx */
-
-#if defined(STM32F412xG)
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FSMC_IRQn = 48, /*!< FSMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- TIM6_IRQn = 54, /*!< TIM6 global interrupt */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
- DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- RNG_IRQn = 80, /*!< RNG global Interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
- QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
- FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
- FMPI2C1_ER_IRQn = 96 /*!< FMPI2C1 Error Interrupt */
-#endif /* STM32F412xG */
-
-#if defined(STM32F413_423xx)
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC1&2 global Interrupt */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
- DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- CAN3_TX_IRQn = 74, /*!< CAN3 TX Interrupt */
- CAN3_RX0_IRQn = 75, /*!< CAN3 RX0 Interrupt */
- CAN3_RX1_IRQn = 76, /*!< CAN3 RX1 Interrupt */
- CAN3_SCE_IRQn = 77, /*!< CAN3 SCE Interrupt */
- RNG_IRQn = 80, /*!< RNG global Interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- UART7_IRQn = 82, /*!< UART7 global interrupt */
- UART8_IRQn = 83, /*!< UART8 global interrupt */
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
- SAI1_IRQn = 87, /*!< Serial Audio Interface 1 global interrupt */
- UART9_IRQn = 88, /*!< UART9 global Interrupt */
- UART10_IRQn = 89, /*!< UART10 global Interrupt */
- QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
- FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
- FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
- LPTIM1_IRQn = 97, /*!< LP TIM1 interrupt */
- DFSDM2_FLT0_IRQn = 98, /*!< DFSDM2 Filter 0 global Interrupt */
- DFSDM2_FLT1_IRQn = 99, /*!< DFSDM2 Filter 1 global Interrupt */
- DFSDM2_FLT2_IRQn = 100, /*!< DFSDM2 Filter 2 global Interrupt */
- DFSDM2_FLT3_IRQn = 101 /*!< DFSDM2 Filter 3 global Interrupt */
-#endif /* STM32F413_423xx */
-} IRQn_Type;
-
-/**
- * @}
- */
-
-#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include
-
-/** @addtogroup Exported_types
- * @{
- */
-/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
-typedef int32_t s32;
-typedef int16_t s16;
-typedef int8_t s8;
-
-typedef const int32_t sc32; /*!< Read Only */
-typedef const int16_t sc16; /*!< Read Only */
-typedef const int8_t sc8; /*!< Read Only */
-
-typedef __IO int32_t vs32;
-typedef __IO int16_t vs16;
-typedef __IO int8_t vs8;
-
-typedef __I int32_t vsc32; /*!< Read Only */
-typedef __I int16_t vsc16; /*!< Read Only */
-typedef __I int8_t vsc8; /*!< Read Only */
-
-typedef uint32_t u32;
-typedef uint16_t u16;
-typedef uint8_t u8;
-
-typedef const uint32_t uc32; /*!< Read Only */
-typedef const uint16_t uc16; /*!< Read Only */
-typedef const uint8_t uc8; /*!< Read Only */
-
-typedef __IO uint32_t vu32;
-typedef __IO uint16_t vu16;
-typedef __IO uint8_t vu8;
-
-typedef __I uint32_t vuc32; /*!< Read Only */
-typedef __I uint16_t vuc16; /*!< Read Only */
-typedef __I uint8_t vuc8; /*!< Read Only */
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Analog to Digital Converter
- */
-
-typedef struct
-{
- __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
- __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
- __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
- __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
- __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
- __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
- __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
- __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
- __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
- __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
- __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
- __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
- __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
- __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
- __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38 */
- __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
- __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
- __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
- __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
- __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
- __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
- __IO uint32_t CDR; /*!< ADC common regular data register for dual
- AND triple modes, Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/**
- * @brief Controller Area Network TxMailBox
- */
-
-typedef struct
-{
- __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
- __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
- __IO uint32_t TDLR; /*!< CAN mailbox data low register */
- __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FIFOMailBox
- */
-
-typedef struct
-{
- __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
- __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
- __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
- __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FilterRegister
- */
-
-typedef struct
-{
- __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
- __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/**
- * @brief Controller Area Network
- */
-
-typedef struct
-{
- __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
- __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
- __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
- __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
- __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
- __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
- __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
- __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
- uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
- CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
- CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
- uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
- __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
- __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
- uint32_t RESERVED2; /*!< Reserved, 0x208 */
- __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
- uint32_t RESERVED3; /*!< Reserved, 0x210 */
- __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
- uint32_t RESERVED4; /*!< Reserved, 0x218 */
- __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
- uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
- CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
-} CAN_TypeDef;
-
-#if defined(STM32F446xx)
-/**
- * @brief Consumer Electronics Control
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
- __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
- __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
- __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
- __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
- __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
-}CEC_TypeDef;
-#endif /* STM32F446xx */
-
-/**
- * @brief CRC calculation unit
- */
-
-typedef struct
-{
- __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
- __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
- uint8_t RESERVED0; /*!< Reserved, 0x05 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
-} CRC_TypeDef;
-
-/**
- * @brief Digital to Analog Converter
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
- __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
- __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
- __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
- __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
- __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
- __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
- __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
- __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
- __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
- __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
- __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
- __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
- __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
-} DAC_TypeDef;
-
-#if defined(STM32F412xG) || defined(STM32F413_423xx)
-/**
- * @brief DFSDM module registers
- */
-typedef struct
-{
- __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
- __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
- __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
- __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
- __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
- __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
- __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
- __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
- __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
- __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
- __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
- __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
- __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
- __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
- __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
-} DFSDM_Filter_TypeDef;
-
-/**
- * @brief DFSDM channel configuration registers
- */
-typedef struct
-{
- __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
- __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
- __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
- short circuit detector register, Address offset: 0x08 */
- __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
- __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
-} DFSDM_Channel_TypeDef;
-
-/* Legacy Defines */
-#define DFSDM_TypeDef DFSDM_Filter_TypeDef
-#endif /* STM32F412xG || STM32F413_423xx */
-/**
- * @brief Debug MCU
- */
-
-typedef struct
-{
- __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
- __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
- __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
- __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/**
- * @brief DCMI
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
- __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
- __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
- __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
- __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
- __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
- __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
- __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
- __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
- __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
- __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/**
- * @brief DMA Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DMA stream x configuration register */
- __IO uint32_t NDTR; /*!< DMA stream x number of data register */
- __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
- __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
- __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
- __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
- __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
- __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
- __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
- __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-/**
- * @brief DMA2D Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
- __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
- __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
- __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
- __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
- __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
- __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
- __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
- __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
- __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
- __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
- __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
- __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
- __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
- __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
- __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
- __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
- __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
- __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
- __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
- uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
- __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
- __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
-} DMA2D_TypeDef;
-
-#if defined(STM32F469_479xx)
-/**
- * @brief DSI Controller
- */
-
-typedef struct
-{
- __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
- __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
- __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
- __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
- __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
- __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
- __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
- uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
- __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
- __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
- __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
- __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
- __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
- __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
- __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
- __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
- __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
- __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
- __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
- __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
- __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
- __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
- __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
- __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
- __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
- __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
- __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
- __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
- __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
- __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
- __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
- __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
- __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
- __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
- __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
- __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
- __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
- uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
- __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
- __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
- uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
- __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
- uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */
- __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
- uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */
- __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
- __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
- uint32_t RESERVED5; /*!< Reserved, 0x114 */
- __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
- uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
- __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
- __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
- __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
- __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
- __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
- __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
- __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
- __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
- __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
- __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
- __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
- uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */
- __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
- uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */
- __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
- __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
- __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
- __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
- __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
- uint32_t RESERVED9; /*!< Reserved, 0x414 */
- __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
- uint32_t RESERVED10; /*!< Reserved, 0x42C */
- __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
-} DSI_TypeDef;
-#endif /* STM32F469_479xx */
-
-/**
- * @brief Ethernet MAC
- */
-
-typedef struct
-{
- __IO uint32_t MACCR;
- __IO uint32_t MACFFR;
- __IO uint32_t MACHTHR;
- __IO uint32_t MACHTLR;
- __IO uint32_t MACMIIAR;
- __IO uint32_t MACMIIDR;
- __IO uint32_t MACFCR;
- __IO uint32_t MACVLANTR; /* 8 */
- uint32_t RESERVED0[2];
- __IO uint32_t MACRWUFFR; /* 11 */
- __IO uint32_t MACPMTCSR;
- uint32_t RESERVED1[2];
- __IO uint32_t MACSR; /* 15 */
- __IO uint32_t MACIMR;
- __IO uint32_t MACA0HR;
- __IO uint32_t MACA0LR;
- __IO uint32_t MACA1HR;
- __IO uint32_t MACA1LR;
- __IO uint32_t MACA2HR;
- __IO uint32_t MACA2LR;
- __IO uint32_t MACA3HR;
- __IO uint32_t MACA3LR; /* 24 */
- uint32_t RESERVED2[40];
- __IO uint32_t MMCCR; /* 65 */
- __IO uint32_t MMCRIR;
- __IO uint32_t MMCTIR;
- __IO uint32_t MMCRIMR;
- __IO uint32_t MMCTIMR; /* 69 */
- uint32_t RESERVED3[14];
- __IO uint32_t MMCTGFSCCR; /* 84 */
- __IO uint32_t MMCTGFMSCCR;
- uint32_t RESERVED4[5];
- __IO uint32_t MMCTGFCR;
- uint32_t RESERVED5[10];
- __IO uint32_t MMCRFCECR;
- __IO uint32_t MMCRFAECR;
- uint32_t RESERVED6[10];
- __IO uint32_t MMCRGUFCR;
- uint32_t RESERVED7[334];
- __IO uint32_t PTPTSCR;
- __IO uint32_t PTPSSIR;
- __IO uint32_t PTPTSHR;
- __IO uint32_t PTPTSLR;
- __IO uint32_t PTPTSHUR;
- __IO uint32_t PTPTSLUR;
- __IO uint32_t PTPTSAR;
- __IO uint32_t PTPTTHR;
- __IO uint32_t PTPTTLR;
- __IO uint32_t RESERVED8;
- __IO uint32_t PTPTSSR;
- uint32_t RESERVED9[565];
- __IO uint32_t DMABMR;
- __IO uint32_t DMATPDR;
- __IO uint32_t DMARPDR;
- __IO uint32_t DMARDLAR;
- __IO uint32_t DMATDLAR;
- __IO uint32_t DMASR;
- __IO uint32_t DMAOMR;
- __IO uint32_t DMAIER;
- __IO uint32_t DMAMFBOCR;
- __IO uint32_t DMARSWTR;
- uint32_t RESERVED10[8];
- __IO uint32_t DMACHTDR;
- __IO uint32_t DMACHRDR;
- __IO uint32_t DMACHTBAR;
- __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/**
- * @brief External Interrupt/Event Controller
- */
-
-typedef struct
-{
- __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
- __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
- __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
- __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
- __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
- __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/**
- * @brief FLASH Registers
- */
-
-typedef struct
-{
- __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
- __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
- __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
- __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
- __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
- __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
- __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
-/**
- * @brief Flexible Static Memory Controller
- */
-
-typedef struct
-{
- __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
-} FSMC_Bank1_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank1E
- */
-
-typedef struct
-{
- __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FSMC_Bank1E_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank2
- */
-
-typedef struct
-{
- __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
- __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
- __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
- __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
- uint32_t RESERVED0; /*!< Reserved, 0x70 */
- __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
-} FSMC_Bank2_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank3
- */
-
-typedef struct
-{
- __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
- __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
- __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
- __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
- uint32_t RESERVED0; /*!< Reserved, 0x90 */
- __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
-} FSMC_Bank3_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank4
- */
-
-typedef struct
-{
- __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
- __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
- __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
- __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
- __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
-} FSMC_Bank4_TypeDef;
-#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-/**
- * @brief Flexible Memory Controller
- */
-
-typedef struct
-{
- __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
-} FMC_Bank1_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank1E
- */
-
-typedef struct
-{
- __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FMC_Bank1E_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank2
- */
-
-typedef struct
-{
- __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
- __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
- __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
- __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
- uint32_t RESERVED0; /*!< Reserved, 0x70 */
- __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
-} FMC_Bank2_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank3
- */
-
-typedef struct
-{
- __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
- __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
- __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
- __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
- uint32_t RESERVED0; /*!< Reserved, 0x90 */
- __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
-} FMC_Bank3_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank4
- */
-
-typedef struct
-{
- __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
- __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
- __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
- __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
- __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
-} FMC_Bank4_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank5_6
- */
-
-typedef struct
-{
- __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
- __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
- __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
- __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
- __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
-} FMC_Bank5_6_TypeDef;
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-/**
- * @brief General Purpose I/O
- */
-
-typedef struct
-{
- __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
- __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
- __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
- __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
- __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
- __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
- __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
- __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/**
- * @brief System configuration controller
- */
-
-typedef struct
-{
- __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
- __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-#if defined (STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
- uint32_t RESERVED; /*!< Reserved, 0x18 */
- __IO uint32_t CFGR2; /*!< Reserved, 0x1C */
- __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
- uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
- __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
-#else /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx || STM32F469_479xx */
- uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
- __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
-#endif /* STM32F410xx || defined(STM32F412xG) || defined(STM32F413_423xx) */
-#if defined(STM32F413_423xx)
- __IO uint32_t MCHDLYCR; /*!< SYSCFG multi-channel delay register, Address offset: 0x30 */
-#endif /* STM32F413_423xx */
-} SYSCFG_TypeDef;
-
-/**
- * @brief Inter-integrated Circuit Interface
- */
-
-typedef struct
-{
- __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
- __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
- uint16_t RESERVED7; /*!< Reserved, 0x1E */
- __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
- uint16_t RESERVED8; /*!< Reserved, 0x22 */
- __IO uint16_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
- uint16_t RESERVED9; /*!< Reserved, 0x26 */
-} I2C_TypeDef;
-
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-/**
- * @brief Inter-integrated Circuit Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
- __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
- __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
- __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
- __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
- __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
- __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
- __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
- __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
- __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
-}FMPI2C_TypeDef;
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
-
-/**
- * @brief Independent WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
- __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
- __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
- __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/**
- * @brief LCD-TFT Display Controller
- */
-
-typedef struct
-{
- uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
- __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
- __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
- __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
- __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
- __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
- uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
- __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
- uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
- __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
- uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
- __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
- __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
- __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
- __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
- __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
- __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
-} LTDC_TypeDef;
-
-/**
- * @brief LCD-TFT Display layer x Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
- __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
- __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
- __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
- __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
- __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
- __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
- __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
- uint32_t RESERVED0[2]; /*!< Reserved */
- __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
- __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
- __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
- uint32_t RESERVED1[3]; /*!< Reserved */
- __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
-
-} LTDC_Layer_TypeDef;
-
-/**
- * @brief Power Control
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
- __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/**
- * @brief Reset and Clock Control
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
- __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
- __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
- __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
- __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
- __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
- __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
- uint32_t RESERVED0; /*!< Reserved, 0x1C */
- __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
- __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
- uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
- __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
- __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
- __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
- uint32_t RESERVED2; /*!< Reserved, 0x3C */
- __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
- __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
- uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
- __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
- __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
- __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
- uint32_t RESERVED4; /*!< Reserved, 0x5C */
- __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
- __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
- uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
- __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
- __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
- uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
- __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
- __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
- __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
- __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
- __IO uint32_t CKGATENR; /*!< RCC Clocks Gated Enable Register, Address offset: 0x90 */ /* Only for STM32F412xG, STM32413_423xx and STM32F446xx devices */
- __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */ /* Only for STM32F410xx, STM32F412xG, STM32413_423xx and STM32F446xx devices */
-
-} RCC_TypeDef;
-
-/**
- * @brief Real-Time Clock
- */
-
-typedef struct
-{
- __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
- __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
- __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
- __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
- __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
- __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
- __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
- __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
- __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
- __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
- __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
- __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
- __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
- __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
- __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
- __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
- __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
- __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
- uint32_t RESERVED7; /*!< Reserved, 0x4C */
- __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
- __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
- __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
- __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
- __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
- __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
- __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
- __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
- __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
- __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
- __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
- __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
- __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
- __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
- __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
- __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
- __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
- __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
- __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
- __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
-} RTC_TypeDef;
-
-
-/**
- * @brief Serial Audio Interface
- */
-
-typedef struct
-{
- __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
-} SAI_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
- __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
- __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
- __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
- __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
- __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
- __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
- __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
-} SAI_Block_TypeDef;
-
-/**
- * @brief SD host Interface
- */
-
-typedef struct
-{
- __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
- __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
- __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
- __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
- __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
- __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
- __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
- __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
- __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
- __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
- __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
- __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
- __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
- __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
- __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
- __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
- uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
- __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
- uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
- __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/**
- * @brief Serial Peripheral Interface
- */
-
-typedef struct
-{
- __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
- __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
- uint16_t RESERVED7; /*!< Reserved, 0x1E */
- __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
- uint16_t RESERVED8; /*!< Reserved, 0x22 */
-} SPI_TypeDef;
-
-#if defined(STM32F446xx)
-/**
- * @brief SPDIFRX Interface
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
- __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
- uint16_t RESERVED0; /*!< Reserved, 0x06 */
- __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
- __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
- uint16_t RESERVED1; /*!< Reserved, 0x0E */
- __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
- __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
- __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
- uint16_t RESERVED2; /*!< Reserved, 0x1A */
-} SPDIFRX_TypeDef;
-#endif /* STM32F446xx */
-
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-/**
- * @brief QUAD Serial Peripheral Interface
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
- __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
- __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
- __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
- __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
- __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
- __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
- __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
- __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
- __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
- __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
- __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
-} QUADSPI_TypeDef;
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F446xx)
-/**
- * @brief SPDIF-RX Interface
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
- __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
- uint16_t RESERVED0; /*!< Reserved, 0x06 */
- __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
- __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
- uint16_t RESERVED1; /*!< Reserved, 0x0E */
- __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
- __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
- __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
- uint16_t RESERVED2; /*!< Reserved, 0x1A */
-} SPDIF_TypeDef;
-#endif /* STM32F446xx */
-
-/**
- * @brief TIM
- */
-
-typedef struct
-{
- __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
- __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
- uint16_t RESERVED7; /*!< Reserved, 0x1E */
- __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
- uint16_t RESERVED8; /*!< Reserved, 0x22 */
- __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
- __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
- uint16_t RESERVED9; /*!< Reserved, 0x2A */
- __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
- __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
- uint16_t RESERVED10; /*!< Reserved, 0x32 */
- __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
- __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
- __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
- __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
- __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
- uint16_t RESERVED11; /*!< Reserved, 0x46 */
- __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
- uint16_t RESERVED12; /*!< Reserved, 0x4A */
- __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
- uint16_t RESERVED13; /*!< Reserved, 0x4E */
- __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
- uint16_t RESERVED14; /*!< Reserved, 0x52 */
-} TIM_TypeDef;
-
-/**
- * @brief Universal Synchronous Asynchronous Receiver Transmitter
- */
-
-typedef struct
-{
- __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
-} USART_TypeDef;
-
-/**
- * @brief Window WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
- __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/**
- * @brief Crypto Processor
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
- __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
- __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
- __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
- __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
- __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
- __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
- __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
- __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
- __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
- __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
- __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
- __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
- __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
- __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
- __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
- __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
- __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
- __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
- __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
- __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
- __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
- __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
- __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
- __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
- __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
- __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
- __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
- __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
- __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
- __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
- __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
- __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
- __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
- __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
- __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
-} CRYP_TypeDef;
-
-/**
- * @brief HASH
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
- __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
- __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
- __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
- __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
- __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
- uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
- __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
-} HASH_TypeDef;
-
-/**
- * @brief HASH_DIGEST
- */
-
-typedef struct
-{
- __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
-} HASH_DIGEST_TypeDef;
-
-/**
- * @brief RNG
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
- __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
- __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
-} RNG_TypeDef;
-
-#if defined(STM32F410xx) || defined(STM32F413_423xx)
-/**
- * @brief LPTIMER
- */
-typedef struct
-{
- __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
- __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
- __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
- __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
- __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
- __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
- __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
- __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
- __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
-} LPTIM_TypeDef;
-#endif /* STM32F410xx || STM32F413_423xx */
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_memory_map
- * @{
- */
-
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
-#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
-#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
-#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
-#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
-#elif defined(STM32F469_479xx)
-#define SRAM2_BASE ((uint32_t)0x20028000) /*!< SRAM2(16 KB) base address in the alias region */
-#define SRAM3_BASE ((uint32_t)0x20030000) /*!< SRAM3(64 KB) base address in the alias region */
-#elif defined(STM32F413_423xx)
-#define SRAM2_BASE ((uint32_t)0x20040000) /*!< SRAM2(16 KB) base address in the alias region */
-#else /* STM32F411xE || STM32F410xx || STM32F412xG */
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-#if defined (STM32F40_41xxx) || (STM32F427_437xx) || (STM32F429_439xx) || (STM32F410xx) || (STM32F412xG) || (STM32F413_423xx) || (STM32F446xx) || (STM32F469_479xx)
-#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
-#endif /* STM32F40_41xxx || (STM32F427_437xx || STM32F429_439xx || STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
-#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
-#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< QuadSPI registers base address */
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
-
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
-#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
-#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
-#define SRAM3_BB_BASE ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */
-#elif defined(STM32F469_479xx)
-#define SRAM2_BB_BASE ((uint32_t)0x22500000) /*!< SRAM2(16 KB) base address in the bit-band region */
-#define SRAM3_BB_BASE ((uint32_t)0x22600000) /*!< SRAM3(64 KB) base address in the bit-band region */
-#elif defined(STM32F413_423xx)
-#define SRAM2_BB_BASE ((uint32_t)0x22800000) /*!< SRAM2(64 KB) base address in the bit-band region */
-#else /* STM32F411xE || STM32F410xx || STM32F412xG */
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
-
-/* Legacy defines */
-#define SRAM_BASE SRAM1_BASE
-#define SRAM_BB_BASE SRAM1_BB_BASE
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
-#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
-#if defined(STM32F410xx) || defined(STM32F413_423xx)
-#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400)
-#endif /* STM32F410xx || STM32F413_423xx */
-#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
-#if defined(STM32F446xx)
-#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000)
-#endif /* STM32F446xx */
-#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000)
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
-#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
-#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
-#if defined(STM32F413_423xx)
-#define CAN3_BASE (APB1PERIPH_BASE + 0x6C00)
-#endif /* STM32F413_423xx */
-#if defined(STM32F446xx)
-#define CEC_BASE (APB1PERIPH_BASE + 0x6C00)
-#endif /* STM32F446xx */
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
-#define UART7_BASE (APB1PERIPH_BASE + 0x7800)
-#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
-#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
-#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
-#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
-#define UART9_BASE (APB2PERIPH_BASE + 0x1800U)
-#define UART10_BASE (APB2PERIPH_BASE + 0x1C00U)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
-#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
-#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
-#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
-#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
-#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
-#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
-#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
-#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
-#define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
-#define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
-#define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
-#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
-#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
-#if defined(STM32F446xx)
-#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00)
-#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
-#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
-#endif /* STM32F446xx */
-#define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
-#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
-#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
-#if defined(STM32F469_479xx)
-#define DSI_BASE (APB2PERIPH_BASE + 0x6C00)
-#endif /* STM32F469_479xx */
-#if defined(STM32F412xG) || defined(STM32F413_423xx)
-#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000)
-#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
-#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
-#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40)
-#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60)
-#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100)
-#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180)
-#define DFSDM1_0 ((DFSDM_TypeDef *) DFSDM1_Filter0_BASE)
-#define DFSDM1_1 ((DFSDM_TypeDef *) DFSDM1_Filter1_BASE)
-/* Legacy Defines */
-#define DFSDM0 DFSDM1_0
-#define DFSDM1 DFSDM1_1
-#if defined(STM32F413_423xx)
-#define DFSDM2_BASE (APB2PERIPH_BASE + 0x6400U)
-#define DFSDM2_Channel0_BASE (DFSDM2_BASE + 0x00U)
-#define DFSDM2_Channel1_BASE (DFSDM2_BASE + 0x20U)
-#define DFSDM2_Channel2_BASE (DFSDM2_BASE + 0x40U)
-#define DFSDM2_Channel3_BASE (DFSDM2_BASE + 0x60U)
-#define DFSDM2_Channel4_BASE (DFSDM2_BASE + 0x80U)
-#define DFSDM2_Channel5_BASE (DFSDM2_BASE + 0xA0U)
-#define DFSDM2_Channel6_BASE (DFSDM2_BASE + 0xC0U)
-#define DFSDM2_Channel7_BASE (DFSDM2_BASE + 0xE0U)
-#define DFSDM2_Filter0_BASE (DFSDM2_BASE + 0x100U)
-#define DFSDM2_Filter1_BASE (DFSDM2_BASE + 0x180U)
-#define DFSDM2_Filter2_BASE (DFSDM2_BASE + 0x200U)
-#define DFSDM2_Filter3_BASE (DFSDM2_BASE + 0x280U)
-#define DFSDM2_0 ((DFSDM_TypeDef *) DFSDM2_Filter0_BASE)
-#define DFSDM2_1 ((DFSDM_TypeDef *) DFSDM2_Filter1_BASE)
-#define DFSDM2_2 ((DFSDM_TypeDef *) DFSDM2_Filter2_BASE)
-#define DFSDM2_3 ((DFSDM_TypeDef *) DFSDM2_Filter3_BASE)
-#endif /* STM32F413_423xx */
-#endif /* STM32F412xG || STM32F413_423xx */
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
-#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
-#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
-#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
-#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
-#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
-#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
-#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
-#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
-#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
-#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
-#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
-#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
-#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
-#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
-#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
-#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
-#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
-#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
-#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
-#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
-#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
-#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
-#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
-#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
-#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
-#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
-#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
-#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
-#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
-#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
-#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
-#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
-#define ETH_MAC_BASE (ETH_BASE)
-#define ETH_MMC_BASE (ETH_BASE + 0x0100)
-#define ETH_PTP_BASE (ETH_BASE + 0x0700)
-#define ETH_DMA_BASE (ETH_BASE + 0x1000)
-#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)
-
-/*!< AHB2 peripherals */
-#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
-#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
-#define HASH_BASE (AHB2PERIPH_BASE + 0x60400)
-#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710)
-#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
-
-#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
-/*!< FSMC Bankx registers base address */
-#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
-#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
-#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
-#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
-#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
-#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-/*!< FMC Bankx registers base address */
-#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
-#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
-#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)
-#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
-#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
-#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE ((uint32_t )0xE0042000)
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_declaration
- * @{
- */
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#if defined(STM32F446xx)
-#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
-#endif /* STM32F446xx */
-#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define UART4 ((USART_TypeDef *) UART4_BASE)
-#define UART5 ((USART_TypeDef *) UART5_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
-#if defined(STM32F410xx) || defined(STM32F413_423xx)
-#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
-#endif /* STM32F410xx || STM32F413_423xx */
-#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
-#if defined(STM32F413_423xx)
-#define CAN3 ((CAN_TypeDef *) CAN3_BASE)
-#endif /* STM32F413_423xx */
-#if defined(STM32F446xx)
-#define CEC ((CEC_TypeDef *) CEC_BASE)
-#endif /* STM32F446xx */
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define UART7 ((USART_TypeDef *) UART7_BASE)
-#define UART8 ((USART_TypeDef *) UART8_BASE)
-#define UART9 ((USART_TypeDef *) UART9_BASE)
-#define UART10 ((USART_TypeDef *) UART10_BASE)
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define USART6 ((USART_TypeDef *) USART6_BASE)
-#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
-#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
-#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
-#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
-#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
-#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
-#if defined(STM32F446xx)
-#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
-#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
-#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
-#endif /* STM32F446xx */
-#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
-#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
-#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
-#if defined(STM32F469_479xx)
-#define DSI ((DSI_TypeDef *)DSI_BASE)
-#endif /* STM32F469_479xx */
-#if defined(STM32F412xG) || defined(STM32F413_423xx)
-#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
-#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
-#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
-#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
-#define DFSDM1_Filter0 ((DFSDM_TypeDef *) DFSDM_Filter0_BASE)
-#define DFSDM1_Filter1 ((DFSDM_TypeDef *) DFSDM_Filter1_BASE)
-#if defined(STM32F413_423xx)
-#define DFSDM2_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)
-#define DFSDM2_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)
-#define DFSDM2_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel2_BASE)
-#define DFSDM2_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel3_BASE)
-#define DFSDM2_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel4_BASE)
-#define DFSDM2_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel5_BASE)
-#define DFSDM2_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel6_BASE)
-#define DFSDM2_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel7_BASE)
-#define DFSDM2_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter0_BASE)
-#define DFSDM2_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter1_BASE)
-#define DFSDM2_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter2_BASE)
-#define DFSDM2_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter3_BASE)
-#endif /* STM32F413_423xx */
-#endif /* STM32F412xG || STM32F413_423xx */
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
-#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
-#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define ETH ((ETH_TypeDef *) ETH_BASE)
-#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
-#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
-#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
-#define HASH ((HASH_TypeDef *) HASH_BASE)
-#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
-#define RNG ((RNG_TypeDef *) RNG_BASE)
-
-#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
-#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
-#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
-#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
-#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
-#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
-#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
-#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
-#define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
-#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
-#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
-#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_constants
- * @{
- */
-
- /** @addtogroup Peripheral_Registers_Bits_Definition
- * @{
- */
-
-/******************************************************************************/
-/* Peripheral Registers_Bits_Definition */
-/******************************************************************************/
-
-/******************************************************************************/
-/* */
-/* Analog to Digital Converter */
-/* */
-/******************************************************************************/
-/******************** Bit definition for ADC_SR register ********************/
-#define ADC_SR_AWD ((uint8_t)0x01) /*!CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- #endif
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x24003010;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-
-#if defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM)
- SystemInit_ExtMemCtl();
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
- /* Configure the System clock source, PLL Multiplier and Divider factors,
- AHB/APBx prescalers and Flash settings ----------------------------------*/
- SetSysClock();
-
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
- * 16 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
- * 25 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate(void)
-{
- uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
- uint32_t pllr = 2;
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock source */
- SystemCoreClock = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock source */
- SystemCoreClock = HSE_VALUE;
- break;
- case 0x08: /* PLL P used as system clock source */
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
- SYSCLK = PLL_VCO / PLL_P
- */
- pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
- if (pllsource != 0)
- {
- /* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
- else
- {
- /* HSI used as PLL clock source */
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
-#elif defined(STM32F410xx) || defined(STM32F411xE)
-#if defined(USE_HSE_BYPASS)
- if (pllsource != 0)
- {
- /* HSE used as PLL clock source */
- pllvco = (HSE_BYPASS_INPUT_FREQUENCY / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
-#else
- if (pllsource == 0)
- {
- /* HSI used as PLL clock source */
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
-#endif /* USE_HSE_BYPASS */
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
- pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
- SystemCoreClock = pllvco/pllp;
- break;
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
- case 0x0C: /* PLL R used as system clock source */
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
- SYSCLK = PLL_VCO / PLL_R
- */
- pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
- if (pllsource != 0)
- {
- /* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
- else
- {
- /* HSI used as PLL clock source */
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
-
- pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >>28) + 1 ) *2;
- SystemCoreClock = pllvco/pllr;
- break;
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
- default:
- SystemCoreClock = HSI_VALUE;
- break;
- }
- /* Compute HCLK frequency --------------------------------------------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @brief Configures the System clock source, PLL Multiplier and Divider factors,
- * AHB/APBx prescalers and Flash settings
- * @Note This function should be called only once the RCC clock configuration
- * is reset to the default reset state (done in SystemInit() function).
- * @param None
- * @retval None
- */
-static void SetSysClock(void)
-{
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)|| defined(STM32F469_479xx)
-/******************************************************************************/
-/* PLL (clocked by HSE) used as System clock source */
-/******************************************************************************/
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Select regulator voltage output Scale 1 mode */
- RCC->APB1ENR |= RCC_APB1ENR_PWREN;
- PWR->CR |= PWR_CR_VOS;
-
- /* HCLK = SYSCLK / 1*/
- RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
-
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
- /* PCLK2 = HCLK / 2*/
- RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
-
- /* PCLK1 = HCLK / 4*/
- RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
-#endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx || STM32F412xG || STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F401xx) || defined(STM32F413_423xx)
- /* PCLK2 = HCLK / 1*/
- RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK / 2*/
- RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
-#endif /* STM32F401xx || STM32F413_423xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F469_479xx)
- /* Configure the main PLL */
- RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
- (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
-#endif /* STM32F40_41xxx || STM32F401xx || STM32F427_437x || STM32F429_439xx || STM32F469_479xx */
-
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
- /* Configure the main PLL */
- RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
- (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24) | (PLL_R << 28);
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
-
- /* Enable the main PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till the main PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
- /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
- PWR->CR |= PWR_CR_ODEN;
- while((PWR->CSR & PWR_CSR_ODRDY) == 0)
- {
- }
- PWR->CR |= PWR_CR_ODSWEN;
- while((PWR->CSR & PWR_CSR_ODSWRDY) == 0)
- {
- }
- /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
- FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
-#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F412xG)
- /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
- FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
-#endif /* STM32F40_41xxx || STM32F412xG */
-
-#if defined(STM32F413_423xx)
- /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
- FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS;
-#endif /* STM32F413_423xx */
-
-#if defined(STM32F401xx)
- /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
- FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
-#endif /* STM32F401xx */
-
- /* Select the main PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= RCC_CFGR_SW_PLL;
-
- /* Wait till the main PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-#elif defined(STM32F410xx) || defined(STM32F411xE)
-#if defined(USE_HSE_BYPASS)
-/******************************************************************************/
-/* PLL (clocked by HSE) used as System clock source */
-/******************************************************************************/
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* Enable HSE and HSE BYPASS */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON | RCC_CR_HSEBYP);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Select regulator voltage output Scale 1 mode */
- RCC->APB1ENR |= RCC_APB1ENR_PWREN;
- PWR->CR |= PWR_CR_VOS;
-
- /* HCLK = SYSCLK / 1*/
- RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK / 2*/
- RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK / 4*/
- RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
-
- /* Configure the main PLL */
- RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
- (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
-
- /* Enable the main PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till the main PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
- FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS;
-
- /* Select the main PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= RCC_CFGR_SW_PLL;
-
- /* Wait till the main PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-#else /* HSI will be used as PLL clock source */
- /* Select regulator voltage output Scale 1 mode */
- RCC->APB1ENR |= RCC_APB1ENR_PWREN;
- PWR->CR |= PWR_CR_VOS;
-
- /* HCLK = SYSCLK / 1*/
- RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK / 2*/
- RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK / 4*/
- RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
-
- /* Configure the main PLL */
- RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (PLL_Q << 24);
-
- /* Enable the main PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till the main PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
- FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS;
-
- /* Select the main PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= RCC_CFGR_SW_PLL;
-
- /* Wait till the main PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
- {
- }
-#endif /* USE_HSE_BYPASS */
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F469_479xx */
-}
-#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F469xx) || defined(STM32F479xx)
-/**
- * @brief Setup the external memory controller.
- * Called in startup_stm32f4xx.s before jump to main.
- * This function configures the external memories (SRAM/SDRAM)
- * This SRAM/SDRAM will be used as program data memory (including heap and stack).
- * @param None
- * @retval None
- */
-void SystemInit_ExtMemCtl(void)
-{
- __IO uint32_t tmp = 0x00;
-
- register uint32_t tmpreg = 0, timeout = 0xFFFF;
- register uint32_t index;
-
- /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
- RCC->AHB1ENR |= 0x000001F8;
-
- /* Delay after an RCC peripheral clock enabling */
- tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
-
- /* Connect PDx pins to FMC Alternate function */
- GPIOD->AFR[0] = 0x00CCC0CC;
- GPIOD->AFR[1] = 0xCCCCCCCC;
- /* Configure PDx pins in Alternate function mode */
- GPIOD->MODER = 0xAAAA0A8A;
- /* Configure PDx pins speed to 100 MHz */
- GPIOD->OSPEEDR = 0xFFFF0FCF;
- /* Configure PDx pins Output type to push-pull */
- GPIOD->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PDx pins */
- GPIOD->PUPDR = 0x00000000;
-
- /* Connect PEx pins to FMC Alternate function */
- GPIOE->AFR[0] = 0xC00CC0CC;
- GPIOE->AFR[1] = 0xCCCCCCCC;
- /* Configure PEx pins in Alternate function mode */
- GPIOE->MODER = 0xAAAA828A;
- /* Configure PEx pins speed to 100 MHz */
- GPIOE->OSPEEDR = 0xFFFFC3CF;
- /* Configure PEx pins Output type to push-pull */
- GPIOE->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PEx pins */
- GPIOE->PUPDR = 0x00000000;
-
- /* Connect PFx pins to FMC Alternate function */
- GPIOF->AFR[0] = 0xCCCCCCCC;
- GPIOF->AFR[1] = 0xCCCCCCCC;
- /* Configure PFx pins in Alternate function mode */
- GPIOF->MODER = 0xAA800AAA;
- /* Configure PFx pins speed to 50 MHz */
- GPIOF->OSPEEDR = 0xAA800AAA;
- /* Configure PFx pins Output type to push-pull */
- GPIOF->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PFx pins */
- GPIOF->PUPDR = 0x00000000;
-
- /* Connect PGx pins to FMC Alternate function */
- GPIOG->AFR[0] = 0xCCCCCCCC;
- GPIOG->AFR[1] = 0xCCCCCCCC;
- /* Configure PGx pins in Alternate function mode */
- GPIOG->MODER = 0xAAAAAAAA;
- /* Configure PGx pins speed to 50 MHz */
- GPIOG->OSPEEDR = 0xAAAAAAAA;
- /* Configure PGx pins Output type to push-pull */
- GPIOG->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PGx pins */
- GPIOG->PUPDR = 0x00000000;
-
- /* Connect PHx pins to FMC Alternate function */
- GPIOH->AFR[0] = 0x00C0CC00;
- GPIOH->AFR[1] = 0xCCCCCCCC;
- /* Configure PHx pins in Alternate function mode */
- GPIOH->MODER = 0xAAAA08A0;
- /* Configure PHx pins speed to 50 MHz */
- GPIOH->OSPEEDR = 0xAAAA08A0;
- /* Configure PHx pins Output type to push-pull */
- GPIOH->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PHx pins */
- GPIOH->PUPDR = 0x00000000;
-
- /* Connect PIx pins to FMC Alternate function */
- GPIOI->AFR[0] = 0xCCCCCCCC;
- GPIOI->AFR[1] = 0x00000CC0;
- /* Configure PIx pins in Alternate function mode */
- GPIOI->MODER = 0x0028AAAA;
- /* Configure PIx pins speed to 50 MHz */
- GPIOI->OSPEEDR = 0x0028AAAA;
- /* Configure PIx pins Output type to push-pull */
- GPIOI->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PIx pins */
- GPIOI->PUPDR = 0x00000000;
-
-/*-- FMC Configuration -------------------------------------------------------*/
- /* Enable the FMC interface clock */
- RCC->AHB3ENR |= 0x00000001;
- /* Delay after an RCC peripheral clock enabling */
- tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
- FMC_Bank5_6->SDCR[0] = 0x000019E4;
- FMC_Bank5_6->SDTR[0] = 0x01115351;
-
- /* SDRAM initialization sequence */
- /* Clock enable command */
- FMC_Bank5_6->SDCMR = 0x00000011;
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- while((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* Delay */
- for (index = 0; index<1000; index++);
-
- /* PALL command */
- FMC_Bank5_6->SDCMR = 0x00000012;
- timeout = 0xFFFF;
- while((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* Auto refresh command */
- FMC_Bank5_6->SDCMR = 0x00000073;
- timeout = 0xFFFF;
- while((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* MRD register program */
- FMC_Bank5_6->SDCMR = 0x00046014;
- timeout = 0xFFFF;
- while((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* Set refresh count */
- tmpreg = FMC_Bank5_6->SDRTR;
- FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
-
- /* Disable write protection */
- tmpreg = FMC_Bank5_6->SDCR[0];
- FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
- /* Configure and enable Bank1_SRAM2 */
- FMC_Bank1->BTCR[2] = 0x00001011;
- FMC_Bank1->BTCR[3] = 0x00000201;
- FMC_Bank1E->BWTR[2] = 0x0fffffff;
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-#if defined(STM32F469xx) || defined(STM32F479xx)
- /* Configure and enable Bank1_SRAM2 */
- FMC_Bank1->BTCR[2] = 0x00001091;
- FMC_Bank1->BTCR[3] = 0x00110212;
- FMC_Bank1E->BWTR[2] = 0x0fffffff;
-#endif /* STM32F469xx || STM32F479xx */
-
- (void)(tmp);
-}
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-#elif defined (DATA_IN_ExtSRAM)
-/**
- * @brief Setup the external memory controller. Called in startup_stm32f4xx.s
- * before jump to __main
- * @param None
- * @retval None
- */
-/**
- * @brief Setup the external memory controller.
- * Called in startup_stm32f4xx.s before jump to main.
- * This function configures the external SRAM mounted on STM324xG_EVAL/STM324x7I boards
- * This SRAM will be used as program data memory (including heap and stack).
- * @param None
- * @retval None
- */
-void SystemInit_ExtMemCtl(void)
-{
-/*-- GPIOs Configuration -----------------------------------------------------*/
-/*
- +-------------------+--------------------+------------------+--------------+
- + SRAM pins assignment +
- +-------------------+--------------------+------------------+--------------+
- | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 |
- | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 |
- | PD4 <-> FMC_NOE | PE3 <-> FMC_A19 | PF2 <-> FMC_A2 | PG2 <-> FMC_A12 |
- | PD5 <-> FMC_NWE | PE4 <-> FMC_A20 | PF3 <-> FMC_A3 | PG3 <-> FMC_A13 |
- | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF4 <-> FMC_A4 | PG4 <-> FMC_A14 |
- | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF5 <-> FMC_A5 | PG5 <-> FMC_A15 |
- | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF12 <-> FMC_A6 | PG9 <-> FMC_NE2 |
- | PD11 <-> FMC_A16 | PE10 <-> FMC_D7 | PF13 <-> FMC_A7 |-----------------+
- | PD12 <-> FMC_A17 | PE11 <-> FMC_D8 | PF14 <-> FMC_A8 |
- | PD13 <-> FMC_A18 | PE12 <-> FMC_D9 | PF15 <-> FMC_A9 |
- | PD14 <-> FMC_D0 | PE13 <-> FMC_D10 |-----------------+
- | PD15 <-> FMC_D1 | PE14 <-> FMC_D11 |
- | | PE15 <-> FMC_D12 |
- +------------------+------------------+
-*/
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
- RCC->AHB1ENR |= 0x00000078;
-
- /* Connect PDx pins to FMC Alternate function */
- GPIOD->AFR[0] = 0x00cc00cc;
- GPIOD->AFR[1] = 0xcccccccc;
- /* Configure PDx pins in Alternate function mode */
- GPIOD->MODER = 0xaaaa0a0a;
- /* Configure PDx pins speed to 100 MHz */
- GPIOD->OSPEEDR = 0xffff0f0f;
- /* Configure PDx pins Output type to push-pull */
- GPIOD->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PDx pins */
- GPIOD->PUPDR = 0x00000000;
-
- /* Connect PEx pins to FMC Alternate function */
- GPIOE->AFR[0] = 0xcccccccc;
- GPIOE->AFR[1] = 0xcccccccc;
- /* Configure PEx pins in Alternate function mode */
- GPIOE->MODER = 0xaaaaaaaa;
- /* Configure PEx pins speed to 100 MHz */
- GPIOE->OSPEEDR = 0xffffffff;
- /* Configure PEx pins Output type to push-pull */
- GPIOE->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PEx pins */
- GPIOE->PUPDR = 0x00000000;
-
- /* Connect PFx pins to FMC Alternate function */
- GPIOF->AFR[0] = 0x00cccccc;
- GPIOF->AFR[1] = 0xcccc0000;
- /* Configure PFx pins in Alternate function mode */
- GPIOF->MODER = 0xaa000aaa;
- /* Configure PFx pins speed to 100 MHz */
- GPIOF->OSPEEDR = 0xff000fff;
- /* Configure PFx pins Output type to push-pull */
- GPIOF->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PFx pins */
- GPIOF->PUPDR = 0x00000000;
-
- /* Connect PGx pins to FMC Alternate function */
- GPIOG->AFR[0] = 0x00cccccc;
- GPIOG->AFR[1] = 0x000000c0;
- /* Configure PGx pins in Alternate function mode */
- GPIOG->MODER = 0x00080aaa;
- /* Configure PGx pins speed to 100 MHz */
- GPIOG->OSPEEDR = 0x000c0fff;
- /* Configure PGx pins Output type to push-pull */
- GPIOG->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PGx pins */
- GPIOG->PUPDR = 0x00000000;
-
-/*-- FMC Configuration ------------------------------------------------------*/
- /* Enable the FMC/FSMC interface clock */
- RCC->AHB3ENR |= 0x00000001;
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
- /* Configure and enable Bank1_SRAM2 */
- FMC_Bank1->BTCR[2] = 0x00001011;
- FMC_Bank1->BTCR[3] = 0x00000201;
- FMC_Bank1E->BWTR[2] = 0x0fffffff;
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F40_41xxx)
- /* Configure and enable Bank1_SRAM2 */
- FSMC_Bank1->BTCR[2] = 0x00001011;
- FSMC_Bank1->BTCR[3] = 0x00000201;
- FSMC_Bank1E->BWTR[2] = 0x0fffffff;
-#endif /* STM32F40_41xxx */
-
-/*
- Bank1_SRAM2 is configured as follow:
- In case of FSMC configuration
- NORSRAMTimingStructure.FSMC_AddressSetupTime = 1;
- NORSRAMTimingStructure.FSMC_AddressHoldTime = 0;
- NORSRAMTimingStructure.FSMC_DataSetupTime = 2;
- NORSRAMTimingStructure.FSMC_BusTurnAroundDuration = 0;
- NORSRAMTimingStructure.FSMC_CLKDivision = 0;
- NORSRAMTimingStructure.FSMC_DataLatency = 0;
- NORSRAMTimingStructure.FSMC_AccessMode = FMC_AccessMode_A;
-
- FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
- FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
- FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
- FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
- FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
- FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
- FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
- FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
- FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
- FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
- FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
- FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
- FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
- FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
- FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &NORSRAMTimingStructure;
-
- In case of FMC configuration
- NORSRAMTimingStructure.FMC_AddressSetupTime = 1;
- NORSRAMTimingStructure.FMC_AddressHoldTime = 0;
- NORSRAMTimingStructure.FMC_DataSetupTime = 2;
- NORSRAMTimingStructure.FMC_BusTurnAroundDuration = 0;
- NORSRAMTimingStructure.FMC_CLKDivision = 0;
- NORSRAMTimingStructure.FMC_DataLatency = 0;
- NORSRAMTimingStructure.FMC_AccessMode = FMC_AccessMode_A;
-
- FMC_NORSRAMInitStructure.FMC_Bank = FMC_Bank1_NORSRAM2;
- FMC_NORSRAMInitStructure.FMC_DataAddressMux = FMC_DataAddressMux_Disable;
- FMC_NORSRAMInitStructure.FMC_MemoryType = FMC_MemoryType_SRAM;
- FMC_NORSRAMInitStructure.FMC_MemoryDataWidth = FMC_MemoryDataWidth_16b;
- FMC_NORSRAMInitStructure.FMC_BurstAccessMode = FMC_BurstAccessMode_Disable;
- FMC_NORSRAMInitStructure.FMC_AsynchronousWait = FMC_AsynchronousWait_Disable;
- FMC_NORSRAMInitStructure.FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low;
- FMC_NORSRAMInitStructure.FMC_WrapMode = FMC_WrapMode_Disable;
- FMC_NORSRAMInitStructure.FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState;
- FMC_NORSRAMInitStructure.FMC_WriteOperation = FMC_WriteOperation_Enable;
- FMC_NORSRAMInitStructure.FMC_WaitSignal = FMC_WaitSignal_Disable;
- FMC_NORSRAMInitStructure.FMC_ExtendedMode = FMC_ExtendedMode_Disable;
- FMC_NORSRAMInitStructure.FMC_WriteBurst = FMC_WriteBurst_Disable;
- FMC_NORSRAMInitStructure.FMC_ContinousClock = FMC_CClock_SyncOnly;
- FMC_NORSRAMInitStructure.FMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
- FMC_NORSRAMInitStructure.FMC_WriteTimingStruct = &NORSRAMTimingStructure;
-*/
-
-}
-#elif defined (DATA_IN_ExtSDRAM)
-/**
- * @brief Setup the external memory controller.
- * Called in startup_stm32f4xx.s before jump to main.
- * This function configures the external SDRAM mounted on STM324x9I_EVAL board
- * This SDRAM will be used as program data memory (including heap and stack).
- * @param None
- * @retval None
- */
-void SystemInit_ExtMemCtl(void)
-{
- register uint32_t tmpreg = 0, timeout = 0xFFFF;
- register uint32_t index;
-
- /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
- clock */
- RCC->AHB1ENR |= 0x000001FC;
-
- /* Connect PCx pins to FMC Alternate function */
- GPIOC->AFR[0] = 0x0000000c;
- GPIOC->AFR[1] = 0x00007700;
- /* Configure PCx pins in Alternate function mode */
- GPIOC->MODER = 0x00a00002;
- /* Configure PCx pins speed to 50 MHz */
- GPIOC->OSPEEDR = 0x00a00002;
- /* Configure PCx pins Output type to push-pull */
- GPIOC->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PCx pins */
- GPIOC->PUPDR = 0x00500000;
-
- /* Connect PDx pins to FMC Alternate function */
- GPIOD->AFR[0] = 0x000000CC;
- GPIOD->AFR[1] = 0xCC000CCC;
- /* Configure PDx pins in Alternate function mode */
- GPIOD->MODER = 0xA02A000A;
- /* Configure PDx pins speed to 50 MHz */
- GPIOD->OSPEEDR = 0xA02A000A;
- /* Configure PDx pins Output type to push-pull */
- GPIOD->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PDx pins */
- GPIOD->PUPDR = 0x00000000;
-
- /* Connect PEx pins to FMC Alternate function */
- GPIOE->AFR[0] = 0xC00000CC;
- GPIOE->AFR[1] = 0xCCCCCCCC;
- /* Configure PEx pins in Alternate function mode */
- GPIOE->MODER = 0xAAAA800A;
- /* Configure PEx pins speed to 50 MHz */
- GPIOE->OSPEEDR = 0xAAAA800A;
- /* Configure PEx pins Output type to push-pull */
- GPIOE->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PEx pins */
- GPIOE->PUPDR = 0x00000000;
-
- /* Connect PFx pins to FMC Alternate function */
- GPIOF->AFR[0] = 0xcccccccc;
- GPIOF->AFR[1] = 0xcccccccc;
- /* Configure PFx pins in Alternate function mode */
- GPIOF->MODER = 0xAA800AAA;
- /* Configure PFx pins speed to 50 MHz */
- GPIOF->OSPEEDR = 0xAA800AAA;
- /* Configure PFx pins Output type to push-pull */
- GPIOF->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PFx pins */
- GPIOF->PUPDR = 0x00000000;
-
- /* Connect PGx pins to FMC Alternate function */
- GPIOG->AFR[0] = 0xcccccccc;
- GPIOG->AFR[1] = 0xcccccccc;
- /* Configure PGx pins in Alternate function mode */
- GPIOG->MODER = 0xaaaaaaaa;
- /* Configure PGx pins speed to 50 MHz */
- GPIOG->OSPEEDR = 0xaaaaaaaa;
- /* Configure PGx pins Output type to push-pull */
- GPIOG->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PGx pins */
- GPIOG->PUPDR = 0x00000000;
-
- /* Connect PHx pins to FMC Alternate function */
- GPIOH->AFR[0] = 0x00C0CC00;
- GPIOH->AFR[1] = 0xCCCCCCCC;
- /* Configure PHx pins in Alternate function mode */
- GPIOH->MODER = 0xAAAA08A0;
- /* Configure PHx pins speed to 50 MHz */
- GPIOH->OSPEEDR = 0xAAAA08A0;
- /* Configure PHx pins Output type to push-pull */
- GPIOH->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PHx pins */
- GPIOH->PUPDR = 0x00000000;
-
- /* Connect PIx pins to FMC Alternate function */
- GPIOI->AFR[0] = 0xCCCCCCCC;
- GPIOI->AFR[1] = 0x00000CC0;
- /* Configure PIx pins in Alternate function mode */
- GPIOI->MODER = 0x0028AAAA;
- /* Configure PIx pins speed to 50 MHz */
- GPIOI->OSPEEDR = 0x0028AAAA;
- /* Configure PIx pins Output type to push-pull */
- GPIOI->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PIx pins */
- GPIOI->PUPDR = 0x00000000;
-
-/*-- FMC Configuration ------------------------------------------------------*/
- /* Enable the FMC interface clock */
- RCC->AHB3ENR |= 0x00000001;
-
- /* Configure and enable SDRAM bank1 */
- FMC_Bank5_6->SDCR[0] = 0x000039D0;
- FMC_Bank5_6->SDTR[0] = 0x01115351;
-
- /* SDRAM initialization sequence */
- /* Clock enable command */
- FMC_Bank5_6->SDCMR = 0x00000011;
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- while((tmpreg != 0) & (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* Delay */
- for (index = 0; index<1000; index++);
-
- /* PALL command */
- FMC_Bank5_6->SDCMR = 0x00000012;
- timeout = 0xFFFF;
- while((tmpreg != 0) & (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* Auto refresh command */
- FMC_Bank5_6->SDCMR = 0x00000073;
- timeout = 0xFFFF;
- while((tmpreg != 0) & (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* MRD register program */
- FMC_Bank5_6->SDCMR = 0x00046014;
- timeout = 0xFFFF;
- while((tmpreg != 0) & (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* Set refresh count */
- tmpreg = FMC_Bank5_6->SDRTR;
- FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
-
- /* Disable write protection */
- tmpreg = FMC_Bank5_6->SDCR[0];
- FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
-
-/*
- Bank1_SDRAM is configured as follow:
-
- FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;
- FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 6;
- FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;
- FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 6;
- FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;
- FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;
- FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;
-
- FMC_SDRAMInitStructure.FMC_Bank = SDRAM_BANK;
- FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
- FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_11b;
- FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b;
- FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
- FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3;
- FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
- FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2;
- FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_disable;
- FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;
- FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
-*/
-
-}
-#endif /* DATA_IN_ExtSDRAM && DATA_IN_ExtSRAM */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/云台/云台-old/Start/system_stm32f4xx.h b/云台/云台-old/Start/system_stm32f4xx.h
deleted file mode 100644
index f82217c..0000000
--- a/云台/云台-old/Start/system_stm32f4xx.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f4xx.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f4xx_system
- * @{
- */
-
-/**
- * @brief Define to prevent recursive inclusion
- */
-#ifndef __SYSTEM_STM32F4XX_H
-#define __SYSTEM_STM32F4XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup STM32F4xx_System_Includes
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @addtogroup STM32F4xx_System_Exported_types
- * @{
- */
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Exported_Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Exported_Functions
- * @{
- */
-
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32F4XX_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/云台/云台-old/System/CAN.c b/云台/云台-old/System/CAN.c
deleted file mode 100644
index 2d6a606..0000000
--- a/云台/云台-old/System/CAN.c
+++ /dev/null
@@ -1,280 +0,0 @@
-#include "stm32f4xx.h" // Device header
-#include "stm32f4xx_conf.h"
-#include "CAN.h"
-#include "M3508.h"
-#include "GM6020.h"
-#include "M2006.h"
-#include "LinkCheck.h"
-#include "Warming.h"
-#include "CToC.h"
-#include "RefereeSystem.h"
-
-uint8_t CAN_CAN1DeviceNumber=4;//CAN1总线上设备数量
-uint8_t CAN_CAN2DeviceNumber=2;//CAN2总线上设备数量
-uint8_t CAN_DeviceNumber=6;//CAN总线上设备数量
-uint32_t CAN_CAN1IDList[10][2]={{CAN_GM6020,GM6020_2},{CAN_M2006,M2006_7},{CAN_M3508,M3508_1},{CAN_M3508,M3508_2},0};//CAN1总线上设备ID列表
-uint32_t CAN_CAN2IDList[10][2]={{CAN_GM6020,GM6020_1},{CAN_RoboMasterC,CToC_MasterID1},0};//CAN2总线上设备ID列表
-int8_t CAN_IDSelect=0;//CAN总线上ID列表选择位
-
-/*
- *函数简介:CAN总线初始化
- *参数说明:无
- *返回类型:无
- *备注:默认使用CAN1(CAN1-Tx为PD1,CAN1-Rx为PD0),CAN2(CAN2-Tx为PB6,CAN2-Rx为PB5)
- *备注:CAN波特率1M,默认1Tq=1/14us≈0.07us
- *备注:使用CAN2需要在打开CAN2时钟之前打开CAN1时钟,且CAN2筛选器编号为15~27
- */
-void CAN_CANInit(void)
-{
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1,ENABLE);
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2,ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB,ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD,ENABLE);//开启时钟
-
- GPIO_InitTypeDef GPIO_InitStructure;
- GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//复用推挽
- GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
- GPIO_InitStructure.GPIO_Pin=GPIO_Pin_0 | GPIO_Pin_1;
- GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
- GPIO_Init(GPIOD,&GPIO_InitStructure);//配置PD0(CAN1-Rx)和PD1(CAN1-Tx)
- GPIO_InitStructure.GPIO_Pin=GPIO_Pin_5 | GPIO_Pin_6;
- GPIO_Init(GPIOB,&GPIO_InitStructure);//配置PB5(CAN2-Rx)和PB6(CAN2-Tx)
-
- GPIO_PinAFConfig(GPIOD,GPIO_PinSource0,GPIO_AF_CAN1);//开启PD0的CAN1复用模式
- GPIO_PinAFConfig(GPIOD,GPIO_PinSource1,GPIO_AF_CAN1);//开启PD1的CAN1复用模式
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource5,GPIO_AF_CAN2);//开启PB5的CAN2复用模式
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource6,GPIO_AF_CAN2);//开启PB6的CAN2复用模式
-
- CAN_InitTypeDef CAN_InitStructure;
- CAN_InitStructure.CAN_Mode=CAN_Mode_Normal;//正常模式
- CAN_InitStructure.CAN_Prescaler=3;//时钟分频,1Tq=Prescaler/T_PCLK=Prescaler/42M
- CAN_InitStructure.CAN_SJW=CAN_SJW_1tq;//SJW极限值
- CAN_InitStructure.CAN_BS1=CAN_BS1_10tq;//PBS1段长度
- CAN_InitStructure.CAN_BS2=CAN_BS2_3tq;//PBS2段长度,1/Baudrate=T_1bit=(1+BS1+BS2)Tq
- CAN_InitStructure.CAN_TTCM=DISABLE;//关闭时间触发功能
- CAN_InitStructure.CAN_ABOM=ENABLE;//开启自动离线管理功能
- CAN_InitStructure.CAN_AWUM=ENABLE;//开启自动唤醒功能
- CAN_InitStructure.CAN_NART=ENABLE;//禁止自动重传功能
- CAN_InitStructure.CAN_RFLM=DISABLE;//关闭锁定FIFO功能
- CAN_InitStructure.CAN_TXFP=DISABLE;//配置报文优先级判定为标识符决定
- CAN_Init(CAN1,&CAN_InitStructure);
- CAN_Init(CAN2,&CAN_InitStructure);
-
- CAN_FilterInitTypeDef CAN_FilterInitStructure;
- CAN_FilterInitStructure.CAN_FilterNumber=0;//筛选器编号0(编号0~14属于CAN1,编号15~27属于CAN2)
- CAN_FilterInitStructure.CAN_FilterFIFOAssignment=CAN_Filter_FIFO0;//存入FIFO0
- CAN_FilterInitStructure.CAN_FilterMode=CAN_FilterMode_IdMask;//掩码模式
- CAN_FilterInitStructure.CAN_FilterScale=CAN_FilterScale_16bit;//筛选器尺度为16bits
- CAN_FilterInitStructure.CAN_FilterIdHigh=(CAN_CAN1IDList[0][1]<<5);//标识符=STID[15:5]+RTR[4:4](0)+IDE[3:3](0)+EXID[2:0](000)
- CAN_FilterInitStructure.CAN_FilterIdLow=(CAN_CAN1IDList[0][1]<<5);//筛选器尺度为16bits,故没有高低位之分
- CAN_FilterInitStructure.CAN_FilterMaskIdHigh=0xFFE3;//掩码(1111 1111 0000 0011),1对应位必须匹配,0对应位无需匹配
- CAN_FilterInitStructure.CAN_FilterMaskIdLow=0xFFE3;//筛选器尺度为16bits,故没有高低位之分
- CAN_FilterInitStructure.CAN_FilterActivation=ENABLE;//使能筛选器
- CAN_FilterInit(&CAN_FilterInitStructure);
- CAN_FilterInitStructure.CAN_FilterNumber=15;//筛选器编号15(编号0~14属于CAN1,编号15~27属于CAN2)
- CAN_FilterInitStructure.CAN_FilterFIFOAssignment=CAN_Filter_FIFO1;//存入FIFO1
- CAN_FilterInitStructure.CAN_FilterIdHigh=(0x000<<5);//标识符=STID[15:5](189/0001 1000 1001)+RTR[4:4](0)+IDE[3:3](0)+EXID[2:0](000)
- CAN_FilterInitStructure.CAN_FilterIdLow=(0x000<<5);//CAN2先给0,默认从CAN1开始串行接收
- CAN_FilterInit(&CAN_FilterInitStructure);
-
- CAN_ITConfig(CAN1,CAN_IT_FMP0,ENABLE);//打通CAN1_FIFO0到NVIC的通道
- CAN_ITConfig(CAN2,CAN_IT_FMP1,ENABLE);//打通CAN2_FIFO1到NVIC的通道
-
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//选择NVIC分组2(2位抢占优先级，2位响应优先级)
-
- NVIC_InitTypeDef NVIC_InitStructure;
- NVIC_InitStructure.NVIC_IRQChannel=CAN1_RX0_IRQn;//选择CAN1_FIFO0接收中断通道
- NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;//使能中断通道
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=1;//抢占优先级为1
- NVIC_InitStructure.NVIC_IRQChannelSubPriority=1;//响应优先级为1
- NVIC_Init(&NVIC_InitStructure);//初始化CAN1_FIFO0的NVIC
- NVIC_InitStructure.NVIC_IRQChannel=CAN2_RX1_IRQn;//选择CAN2_FIFO1接收中断通道
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=0;//抢占优先级为1
- NVIC_InitStructure.NVIC_IRQChannelSubPriority=1;//响应优先级为1
- NVIC_Init(&NVIC_InitStructure);//初始化CAN2_FIFO1的NVIC
-}
-
-/*
- *函数简介:CAN1总线接收报文
- *参数说明:报文存储数组
- *返回类型:报文ID
- *备注:默认8字节标准数据帧
- *备注:没有接收到数据,直接退出,返回0
- */
-uint32_t CAN_CAN1Receive(uint8_t *Data)
-{
- CanRxMsg RxMessage;
- if(CAN_MessagePending(CAN1,CAN_FIFO0)==0)return 0;//没有接收到数据,直接退出
- CAN_Receive(CAN1,CAN_FIFO0,&RxMessage);//读取数据
- for(uint32_t i=0;i<8;i++)
- Data[i]=RxMessage.Data[i];//储存数据
- return RxMessage.StdId;//返回ID
-}
-
-/*
- *函数简介:CAN2总线接收报文
- *参数说明:报文存储数组
- *返回类型:报文ID
- *备注:默认8字节数据
- *备注:没有接收到数据,直接退出,返回0
- */
-uint32_t CAN_CAN2Receive(uint8_t *Data)
-{
- CanRxMsg RxMessage;
- if(CAN_MessagePending(CAN2,CAN_FIFO1)==0)return 0;//没有接收到数据,直接退出
- CAN_Receive(CAN2,CAN_FIFO1,&RxMessage);//读取数据
- for(uint32_t i=0;i<8;i++)
- Data[i]=RxMessage.Data[i];
- return RxMessage.StdId;
-}
-
-/*
- *函数简介:CAN1总线更改接收ID
- *参数说明:接收ID
- *返回类型:无
- *备注:无
- */
-void CAN_CAN1ChangeID(uint32_t ID)
-{
- CAN1->FMR |= 0x00000001;//配置CAN_FMR寄存器FINIT位进入初始化模式
- CAN1->sFilterRegister[0].FR1 = ((uint32_t)0xFFE3<<16) | (ID<<5);//配置CAN_F0R1寄存器更改ID低位
- CAN1->sFilterRegister[0].FR2 = ((uint32_t)0xFFE3<<16) | (ID<<5);//配置CAN_F0R2寄存器更改ID高位(16bits尺度下无高低位区别)
- CAN1->FMR &= ~(0x00000001);//配置CAN_FMR寄存器FINIT位回到工作模式
-}
-
-/*
- *函数简介:CAN2总线更改接收ID
- *参数说明:接收ID
- *返回类型:无
- *备注:无
- */
-void CAN_CAN2ChangeID(uint32_t ID)
-{
- CAN1->FMR |= 0x00000001;
- CAN1->sFilterRegister[15].FR1 = ((uint32_t)0xFFE3<<16) | (ID<<5);
- CAN1->sFilterRegister[15].FR2 = ((uint32_t)0xFFE3<<16) | (ID<<5);
- CAN1->FMR &= ~(0x00000001);
-}
-
-/*
- *函数简介:CAN接收ID列表复位
- *参数说明:无
- *返回类型:无
- *备注:复位CAN_IDSelect,重新从CAN1的1号设备开始接收
- */
-void CAN_CANIDReset(void)
-{
- CAN_IDSelect=0;
- CAN_CAN1ChangeID(CAN_CAN1IDList[0][1]);
- CAN_CAN2ChangeID(0x000);
-}
-
-/*
- *函数简介:CAN接收获取裁判系统状态
- *参数说明:无
- *返回类型:无
- *备注:跳转到接收底盘C板的回传数据,主要用于发射机构掉电时的CAN设备隔离
- */
-void CAN_CAN_GetRefereeSystemData(void)
-{
- CAN_IDSelect=5;
- CAN_CAN1ChangeID(0x000);
- CAN_CAN2ChangeID(CAN_CAN2IDList[1][1]);
-}
-
-/*
- *函数简介:CAN1_FIFO0接收中断函数
- *参数说明:无
- *返回类型:无
- *备注:进入中断时关闭连接检测计时,离开中断时重新打开连接检测计时
- *备注:某一设备掉线时,CAN_IDSelect会停留在当前设备在ID列表的索引
- *备注:从掉线到重新连接时会重启遥控器
- */
-void CAN1_RX0_IRQHandler(void)
-{
- if(CAN_GetITStatus(CAN1,CAN_IT_FMP0)==SET)//查询接收中断标志位
- {
- uint8_t Data[8];//接收数据
- uint32_t ID=CAN_CAN1Receive(Data);//接收数据帧的ID
-
- LinkCheck_OFF();//关闭连接检测定时
- if(LinkCheck_ErrorID>=0 && LinkCheck_ErrorID=0 && CAN_IDSelect=5000)//计次5000下等待发射机构设备启动
- {
- RefereeSystem_ShooterOpenCounter=0;
- RefereeSystem_ShooterOpenFlag=0;//发射机构离开上电期间
- CAN_CAN1DeviceNumber=4;//添加CAN设备
- CAN_DeviceNumber=6;
- }
- }
-
- LinkCheck_ON();//连接检测重新计时
- CAN_ClearITPendingBit(CAN1,CAN_IT_FMP0);//清除CAN1的FIFO0接收中断标志位
- }
-}
-
-/*
- *函数简介:CAN2_FIFO1接收中断函数
- *参数说明:无
- *返回类型:无
- *备注:进入中断时关闭连接检测计时,离开中断时重新打开连接检测计时
- *备注:某一设备掉线时,CAN_IDSelect会停留在当前设备在ID列表的索引
- */
-void CAN2_RX1_IRQHandler(void)
-{
- if(CAN_GetITStatus(CAN2,CAN_IT_FMP1)==SET)//查询接收中断标志位
- {
- uint8_t Data[8];//接收数据
- uint32_t ID=CAN_CAN2Receive(Data);//接收数据帧的ID
-
- LinkCheck_OFF();//关闭连接检测定时
- if(LinkCheck_ErrorID>=CAN_CAN1DeviceNumber && LinkCheck_ErrorID=0 && CAN_IDSelect=5000)//计次5000下等待发射机构设备启动
- {
- RefereeSystem_ShooterOpenCounter=0;
- RefereeSystem_ShooterOpenFlag=0;//发射机构离开上电期间
- CAN_CAN1DeviceNumber=4;//添加CAN设备
- CAN_DeviceNumber=6;
- }
- }
-
- LinkCheck_ON();//连接检测重新计时
- CAN_ClearITPendingBit(CAN2,CAN_IT_FMP1);//清除CAN2的FIFO1接收中断标志位
- }
-}
diff --git a/云台/云台-old/System/CAN.h b/云台/云台-old/System/CAN.h
deleted file mode 100644
index c140118..0000000
--- a/云台/云台-old/System/CAN.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef __CAN_H
-#define __CAN_H
-
-typedef enum
-{
- CAN_M3508=0,//M3508
- CAN_M2006,//M2006
- CAN_GM6020,//GM6020
- CAN_RoboMasterC,//C板
-}CAN_MotorModel;//CAN总线设备分类枚举
-
-extern uint8_t CAN_CAN1DeviceNumber;//CAN1总线上设备数量
-extern uint8_t CAN_CAN2DeviceNumber;//CAN2总线上设备数量
-extern uint8_t CAN_DeviceNumber;//CAN总线上设备数量
-extern int8_t CAN_IDSelect;//CAN总线上ID列表选择位
-
-void CAN_CANInit(void);//CAN总线初始化
-void CAN_CANIDReset(void);//CAN接收ID列表复位
-void CAN_CAN_GetRefereeSystemData(void);//CAN接收获取裁判系统状态
-
-#endif
diff --git a/云台/云台-old/System/Delay.c b/云台/云台-old/System/Delay.c
deleted file mode 100644
index 66245f1..0000000
--- a/云台/云台-old/System/Delay.c
+++ /dev/null
@@ -1,44 +0,0 @@
-#include "stm32f4xx.h" // Device header
-#include "stm32f4xx_conf.h"
-
-/*
- *函数简介:微秒级延时
- *参数说明:延时时长,单位us
- *返回类型:无
- *备注:参数范围:0~4294967295
- */
-void Delay_us(uint32_t us)
-{
- uint32_t temp;
- SysTick->LOAD=us*21; //时间加载，我们要延时n倍的us, 1us是一个fac_ua周期，所以总共要延时的周期值为二者相乘最后送到Load中。
- SysTick->VAL=0x00; //清空计数器
- SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; //开启使能位 开始倒数
- do temp=SysTick->CTRL;
- while((temp&0x01) && !(temp&(1<<16))); //用来判断 systick 定时器是否还处于开启状态，然后在等待时间到达，也就是数到0的时候,此时第十六位设置为1
- SysTick->CTRL&=~SysTick_CTRL_ENABLE_Msk; //关闭计数器使能位
- SysTick->VAL=0x00; //清空计数器
-}
-
-/*
- *函数简介:毫秒级延时
- *参数说明:延时时长,单位ms
- *返回类型:无
- *备注:参数范围:0~4294967295
- */
-void Delay_ms(uint32_t ms)
-{
- while(ms--)
- Delay_us(1000);
-}
-
-/*
- *函数简介:秒级延时
- *参数说明:延时时长,单位s
- *返回类型:无
- *备注:参数范围:0~4294967295
- */
-void Delay_s(uint32_t s)
-{
- while(s--)
- Delay_ms(1000);
-}
diff --git a/云台/云台-old/System/Delay.h b/云台/云台-old/System/Delay.h
deleted file mode 100644
index 2bd1c08..0000000
--- a/云台/云台-old/System/Delay.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef __DELAY_H
-#define __DELAY_H
-
-void Delay_us(uint32_t us);//微秒级延时
-void Delay_ms(uint32_t ms);//毫秒级延时
-void Delay_s(uint32_t s);//秒级延时
-
-#endif
diff --git a/云台/云台-old/System/MyI2C.c b/云台/云台-old/System/MyI2C.c
deleted file mode 100644
index d5ce21e..0000000
--- a/云台/云台-old/System/MyI2C.c
+++ /dev/null
@@ -1,440 +0,0 @@
-#include "stm32f4xx.h" // Device header
-#include "stm32f4xx_conf.h"
-#include "MyI2C.h"
-
-/*
- *函数简介:软件I2C专用us延时
- *参数说明:延时时长,单位1/21us
- *返回类型:无
- *备注:参数范围:0~4294967295
- */
-void MyI2C_Delay_us(uint32_t us)
-{
- uint32_t temp;
- SysTick->LOAD=us; //时间加载，我们要延时n倍的us, 1us是一个fac_ua周期，所以总共要延时的周期值为二者相乘最后送到Load中。
- SysTick->VAL=0x00; //清空计数器
- SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; //开启使能位 开始倒数
- do temp=SysTick->CTRL;
- while((temp&0x01) && !(temp&(1<<16))); //用来判断 systick 定时器是否还处于开启状态，然后在等待时间到达，也就是数到0的时候,此时第十六位设置为1
- SysTick->CTRL&=~SysTick_CTRL_ENABLE_Msk; //关闭计数器使能位
- SysTick->VAL=0x00; //清空计数器
-}
-
-/*
- *函数简介:软件I2C写SCL电平
- *参数说明:软件I2C配置结构体
- *参数说明:高低电平,0-低电平 1-高电平
- *返回类型:无
- *备注:使用前需要先定义结构体并初始化
- *备注:由于I2C速度较慢,在更改电平之后需要加入延时
- */
-void MyI2C_SCL(MyI2C_InitTypedef *MyI2C_InitStructure,uint8_t x)
-{
- GPIO_WriteBit(MyI2C_InitStructure->MyI2C_SCL_GPIOx,MyI2C_InitStructure->MyI2C_SCL_Pin,(BitAction)(x));
- MyI2C_Delay_us(1);//延时
-}
-
-/*
- *函数简介:软件I2C写SDA电平
- *参数说明:软件I2C配置结构体
- *参数说明:高低电平,0-低电平 1-高电平
- *返回类型:
- *备注:使用前需要先定义结构体并初始化
- *备注:由于I2C速度较慢,在更改电平之后需要加入延时
- */
-void MyI2C_SDA(MyI2C_InitTypedef *MyI2C_InitStructure,uint8_t x)
-{
- GPIO_WriteBit(MyI2C_InitStructure->MyI2C_SDA_GPIOx,MyI2C_InitStructure->MyI2C_SDA_Pin,(BitAction)(x));
- MyI2C_Delay_us(1);//延时
-}
-
-/*
- *函数简介:软件I2C读SDA电平
- *参数说明:软件I2C配置结构体
- *返回类型:高低电平,0-低电平 1-高电平
- *备注:使用前需要先定义结构体并初始化
- *备注:由于I2C速度较慢,在电平更改之后需要加入延时,读取时也可以不加
- */
-uint8_t MyI2C_Read_SDA(MyI2C_InitTypedef *MyI2C_InitStructure)
-{
- MyI2C_Delay_us(1);//延时
- uint8_t SDA_Status=GPIO_ReadInputDataBit(MyI2C_InitStructure->MyI2C_SDA_GPIOx,MyI2C_InitStructure->MyI2C_SDA_Pin);
- return SDA_Status;
-}
-
-/*
- *函数简介:软件I2C初始化
- *参数说明:软件I2C配置结构体
- *返回类型:无
- *备注:使用前需要先定义结构体并初始化
- */
-void MyI2C_Init(MyI2C_InitTypedef *MyI2C_InitStructure)
-{
- RCC_AHB1PeriphClockCmd(MyI2C_InitStructure->MyI2C_SCL_RCC,ENABLE);//开启SCL时钟
- RCC_AHB1PeriphClockCmd(MyI2C_InitStructure->MyI2C_SDA_RCC,ENABLE);//开启SDA时钟
-
- GPIO_InitTypeDef GPIO_InitStructure;
- GPIO_InitStructure.GPIO_Mode=GPIO_Mode_OUT;
- GPIO_InitStructure.GPIO_OType=GPIO_OType_OD;//开漏输出
- GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
- GPIO_InitStructure.GPIO_Pin=MyI2C_InitStructure->MyI2C_SCL_Pin;
- GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
- GPIO_Init(MyI2C_InitStructure->MyI2C_SCL_GPIOx,&GPIO_InitStructure);//配置SCL
- GPIO_InitStructure.GPIO_Pin=MyI2C_InitStructure->MyI2C_SDA_Pin;
- GPIO_Init(MyI2C_InitStructure->MyI2C_SDA_GPIOx,&GPIO_InitStructure);//配置SDA
-
- MyI2C_SCL(MyI2C_InitStructure,1);//初始化SCL
- MyI2C_SDA(MyI2C_InitStructure,1);//初始化SDA
-}
-
-/*
- *函数简介:软件I2C起始
- *参数说明:软件I2C配置结构体
- *返回类型:无
- *I2C协议:
- * SCL ~~~~/---\___
- * SDA ~~/---\_____
- */
-void MyI2C_Start(MyI2C_InitTypedef *MyI2C_InitStructure)
-{
- MyI2C_SDA(MyI2C_InitStructure,1);
- MyI2C_SCL(MyI2C_InitStructure,1);//复位SCL和SDA
- MyI2C_SDA(MyI2C_InitStructure,0);//起始
- MyI2C_SCL(MyI2C_InitStructure,0);//准备接收数据
-}
-
-/*
- *函数简介:软件I2C终止
- *参数说明:软件I2C配置结构体
- *返回类型:无
- *I2C协议:
- * SCL ____/-----
- * SDA ~~\___/---
- */
-void MyI2C_Stop(MyI2C_InitTypedef *MyI2C_InitStructure)
-{
- MyI2C_SDA(MyI2C_InitStructure,0);
- MyI2C_SCL(MyI2C_InitStructure,1);//准备接收停止信号
- MyI2C_SDA(MyI2C_InitStructure,1);//终止
-}
-
-/*
- *函数简介:软件I2C产生应答
- *参数说明:软件I2C配置结构体
- *参数说明:是否应答,0-NAck非应答 1-Ack应答
- *返回类型:无
- *I2C协议:
- * Ack:
- * SCL____/-\___
- * SDA~~\___/---
- * NAck:
- * SCL____/-\___
- * SDA~~/-------
- */
-void MyI2C_SendAck(MyI2C_InitTypedef *MyI2C_InitStructure,uint8_t AckBit)
-{
- MyI2C_SDA(MyI2C_InitStructure,!AckBit);//发送应答情况
- MyI2C_SCL(MyI2C_InitStructure,1);//产生时钟
- MyI2C_SCL(MyI2C_InitStructure,0);
- MyI2C_SDA(MyI2C_InitStructure,1);//释放总线
-}
-
-/*
- *函数简介:软件I2C接收应答
- *参数说明:软件I2C配置结构体
- *返回类型:是否应答,0-NAck非应答 1-Ack应答
- *I2C协议:
- * SCL ____/-\___
- * SDA ~~/-|==|~~
- * ( )从机
- */
-uint8_t MyI2C_ReceiveAck(MyI2C_InitTypedef *MyI2C_InitStructure)
-{
- uint8_t AckBit;//应答标志位
-
- MyI2C_SDA(MyI2C_InitStructure,1);//释放SDA总线
- MyI2C_SCL(MyI2C_InitStructure,1);//提示从机发送Ack
-
- AckBit=!MyI2C_Read_SDA(MyI2C_InitStructure);//接收应答
-
- MyI2C_SCL(MyI2C_InitStructure,0);//置SCL为0,准备下一轮发送
- return AckBit;//返回应答情况
-}
-
-/*
- *函数简介:软件I2C发送一个8bits数据
- *参数说明:软件I2C配置结构体
- *参数说明:8bits发送数据
- *返回类型:无
- *I2C协议:
- * SCL ____/-\___/-\___/-\___/-\___/-\___/-\___/-\___/-\___
- * SDA ~~x=====x=====x=====x=====x=====x=====x=====x=====~~
- */
-void MyI2C_Send8bits(MyI2C_InitTypedef *MyI2C_InitStructure,uint8_t Byte)
-{
- for(uint8_t i=0;i<8;i++)
- {
- MyI2C_SDA(MyI2C_InitStructure,Byte&(0x80>>i));//发送数据每一位,高位先行
- MyI2C_SCL(MyI2C_InitStructure,1);//产生时钟
- MyI2C_SCL(MyI2C_InitStructure,0);
- }
-
- MyI2C_SDA(MyI2C_InitStructure,1);//释放SDA总线
-}
-
-/*
- *函数简介:软件I2C读取一个8bits数据
- *参数说明:软件I2C配置结构体
- *返回类型:8bits接收数据
- *I2C协议:
- * SCL ____/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\___
- * SDA ~~/-|==============================|~~
- * ( )从机
- */
-uint8_t MyI2C_Receive8bits(MyI2C_InitTypedef *MyI2C_InitStructure)
-{
- uint8_t Byte=0x00;
- MyI2C_SDA(MyI2C_InitStructure,1);//释放SDA总线
-
- for(uint8_t i=0;i<8;i++)//读取数据每一位,高位先行
- {
- MyI2C_SCL(MyI2C_InitStructure,1);//产生时钟
- if(MyI2C_Read_SDA(MyI2C_InitStructure)){Byte|=(0x80>>i);}//读取SDA
- MyI2C_SCL(MyI2C_InitStructure,0);
- }
-
- return Byte;
-}
-
-/*
- *函数简介:软件I2C发送一个字节数据
- *参数说明:软件I2C配置结构体
- *参数说明:7bits从机地址
- *参数说明:8bits发送数据
- *返回类型:无
- *备注:无
- */
-void MyI2C_SendByte(MyI2C_InitTypedef *MyI2C_InitStructure,uint8_t Address,uint8_t Byte)
-{
- MyI2C_Start(MyI2C_InitStructure);//起始
-
- MyI2C_Send8bits(MyI2C_InitStructure,Address<<1);//发送设备地址(写)
- while(MyI2C_ReceiveAck(MyI2C_InitStructure)!=1);//等待Ack应答
-
- MyI2C_Send8bits(MyI2C_InitStructure,Byte);//发送数据
- while(MyI2C_ReceiveAck(MyI2C_InitStructure)!=1);//等待Ack应答
-
- MyI2C_Stop(MyI2C_InitStructure);//终止
-}
-
-/*
- *函数简介:软件I2C发送数据
- *参数说明:软件I2C配置结构体
- *参数说明:7bits从机地址
- *参数说明:发送数据数组
- *参数说明:发送数据数组长度
- *返回类型:无
- *备注:无
- */
-void MyI2C_SendData(MyI2C_InitTypedef *MyI2C_InitStructure,uint8_t Address,uint8_t *Data,uint16_t Length)
-{
- MyI2C_Start(MyI2C_InitStructure);//起始
-
- MyI2C_Send8bits(MyI2C_InitStructure,Address<<1);//发送设备地址(写)
- while(MyI2C_ReceiveAck(MyI2C_InitStructure)!=1);//等待Ack应答
-
- for(uint16_t i=0;i
-#include
-
-//重定向串口选择,选择哪个串口就把哪个取消注释
-//#define UART1_Redirect//选择UART1重定向
-#define UART2_Redirect//选择UART2重定向
-
-uint8_t UART1_RxData;//接收数据缓存区
-uint8_t UART1_RxFlag;//接收完成标志位
-
-uint8_t UART2_RxData;//接收数据缓存区
-uint8_t UART2_RxFlag;//接收完成标志位
-
-
-/*
- *函数简介:串口专用指数函数
- *参数说明:底数x
- *参数说明:指数y
- *返回类型:x^y
- *备注:x,y均为整数
- */
-uint32_t USART_Pow(uint32_t x,uint32_t y)
-{
- uint32_t Result=1;
- while(y--)
- Result*=x;
- return Result;
-}
-
-/*
- *函数简介:UART1串口发送初始化
- *参数说明:无
- *返回类型:无
- *备注:UART1为USART6,默认Tx引脚PG14
- */
-void UART1_SendInit(void)
-{
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6,ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOG,ENABLE);//开启时钟
-
- GPIO_InitTypeDef GPIO_InitStructure;
- GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//复用推挽
- GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
- GPIO_InitStructure.GPIO_Pin=GPIO_Pin_14;
- GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
- GPIO_Init(GPIOG,&GPIO_InitStructure);//初始化UART1-Tx(PG14)
-
- GPIO_PinAFConfig(GPIOG,GPIO_PinSource14,GPIO_AF_USART6);//开启PG14的USART6复用模式
-
- USART_InitTypeDef USART_InitStructure;
- USART_InitStructure.USART_BaudRate=115200;//配置波特率115200
- USART_InitStructure.USART_HardwareFlowControl=USART_HardwareFlowControl_None;//配置无硬件流控制
- USART_InitStructure.USART_Mode=USART_Mode_Tx;//配置为发送模式
- USART_InitStructure.USART_Parity=USART_Parity_No;//配置为无校验位
- USART_InitStructure.USART_StopBits=USART_StopBits_1;//配置停止位为1
- USART_InitStructure.USART_WordLength=USART_WordLength_8b;//配置字长8bit
- USART_Init(USART6,&USART_InitStructure);//初始化USART6
-
- USART_Cmd(USART6,ENABLE);//启动USART6
-}
-
-/*
- *函数简介:UART1串口接收初始化
- *参数说明:无
- *返回类型:无
- *备注:UART1为USART6,默认Rx引脚PG9
- */
-void UART1_ReceiveInit(void)
-{
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6,ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOG,ENABLE);//开启时钟
-
- GPIO_InitTypeDef GPIO_InitStructure;
- GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//复用推挽
- GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
- GPIO_InitStructure.GPIO_Pin=GPIO_Pin_9;
- GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
- GPIO_Init(GPIOG,&GPIO_InitStructure);//初始化UART1-Rx(PG9)
-
- GPIO_PinAFConfig(GPIOG,GPIO_PinSource9,GPIO_AF_USART6);//开启PG9的USART6复用模式
-
- USART_InitTypeDef USART_InitStructure;
- USART_InitStructure.USART_BaudRate=115200;//配置波特率115200
- USART_InitStructure.USART_HardwareFlowControl=USART_HardwareFlowControl_None;//配置无硬件流控制
- USART_InitStructure.USART_Mode=USART_Mode_Rx;//配置为接收模式
- USART_InitStructure.USART_Parity=USART_Parity_No;//配置为无校验位
- USART_InitStructure.USART_StopBits=USART_StopBits_1;//配置停止位为1
- USART_InitStructure.USART_WordLength=USART_WordLength_8b;//配置字长8bit
- USART_Init(USART6,&USART_InitStructure);//初始化USART6
-
- USART_ITConfig(USART6,USART_IT_RXNE,ENABLE);//打通USART6到NVIC的串口接收中断通道
-
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//选择NVIC分组2(2位抢占优先级，2位响应优先级)
-
- NVIC_InitTypeDef NVIC_InitStructure;
- NVIC_InitStructure.NVIC_IRQChannel=USART6_IRQn;//选择USART6中断通道
- NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;//使能中断通道
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=1;//抢占优先级为1
- NVIC_InitStructure.NVIC_IRQChannelSubPriority=1;//响应优先级为1
- NVIC_Init(&NVIC_InitStructure);//初始化USART6的NVIC
-
- USART_Cmd(USART6,ENABLE);//启动USART6
-}
-
-/*
- *函数简介:UART1串口初始化
- *参数说明:无
- *返回类型:无
- *备注:UART1为USART6,默认Tx引脚PG14,Rx引脚PG9
- */
-void UART1_Init(void)
-{
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6,ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOG,ENABLE);//开启时钟
-
- GPIO_InitTypeDef GPIO_InitStructure;
- GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//复用推挽
- GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
- GPIO_InitStructure.GPIO_Pin=GPIO_Pin_14 | GPIO_Pin_9;
- GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
- GPIO_Init(GPIOG,&GPIO_InitStructure);//初始化UART1-Tx(PG14),UART1-Rx(PG9)
-
- GPIO_PinAFConfig(GPIOG,GPIO_PinSource14,GPIO_AF_USART6);//开启PG14的USART6复用模式
- GPIO_PinAFConfig(GPIOG,GPIO_PinSource9,GPIO_AF_USART6);//开启PG9的USART6复用模式
-
- USART_InitTypeDef USART_InitStructure;
- USART_InitStructure.USART_BaudRate=115200;//配置波特率115200
- USART_InitStructure.USART_HardwareFlowControl=USART_HardwareFlowControl_None;//配置无硬件流控制
- USART_InitStructure.USART_Mode=USART_Mode_Tx | USART_Mode_Rx;//配置为接发模式
- USART_InitStructure.USART_Parity=USART_Parity_No;//配置为无校验位
- USART_InitStructure.USART_StopBits=USART_StopBits_1;//配置停止位为1
- USART_InitStructure.USART_WordLength=USART_WordLength_8b;//配置字长8bit
- USART_Init(USART6,&USART_InitStructure);//初始化USART6
-
- USART_ITConfig(USART6,USART_IT_RXNE,ENABLE);//打通USART6到NVIC的串口接收中断通道
-
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//选择NVIC分组2(2位抢占优先级，2位响应优先级)
-
- NVIC_InitTypeDef NVIC_InitStructure;
- NVIC_InitStructure.NVIC_IRQChannel=USART6_IRQn;//选择USART6中断通道
- NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;//使能中断通道
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=1;//抢占优先级为1
- NVIC_InitStructure.NVIC_IRQChannelSubPriority=1;//响应优先级为1
- NVIC_Init(&NVIC_InitStructure);//初始化USART6的NVIC
-
- USART_Cmd(USART6,ENABLE);//启动USART6
-}
-
-/*
- *函数简介:UART1发送一个字节
- *参数说明:8bits数据
- *返回类型:无
- *备注:无
- */
-void UART1_SendByte(uint8_t Byte)
-{
- USART_SendData(USART6,Byte);
- while(USART_GetFlagStatus(USART6,USART_FLAG_TXE)==RESET);//等待发送完成
-}
-
-/*
- *函数简介:UART1发送一个数组
- *参数说明:8bits数组
- *参数说明:数组长度
- *返回类型:无
- *备注:无
- */
-void UART1_SendArray(uint8_t *Array,uint16_t Length)
-{
- for(uint16_t i=0;i=Number位数)
- *返回类型:无
- *备注:无
- */
-void UART1_SendNumber(uint32_t Number,uint8_t Length)
-{
- for(uint8_t i=0;iDR=ch;
- while(!(USART6->SR&(1<<7))){}
- return ch;
- }
-
- /*
- *函数简介:重写fgetc函数(重定向scanf，即移植scanf)
- *参数说明:无
- *返回类型:无
- *备注:看不懂
- *备注:默认重定向UART1(即USART6),若想修改重定向串口,请更改最上方宏定义的注释
- */
- int fgetc(FILE *stream)
- {
- while(!(USART6->SR&1<<5)){}
- return USART6->DR;
- }
-#endif
-
-/*
- *函数简介:UART1的printf函数
- *参数说明:无
- *返回类型:无
- *备注:等价printf函数,支持多串口
- *备注:看不懂
- */
-void UART1_Printf(char *format,...)
-{
- char Strings[100];
- va_list arg;//定义参数列表变量arg
- va_start(arg,format);//从format位置接收参数，放在arg里
- vsprintf(Strings,format,arg);//将格式化字符串打印到Strings
- va_end(arg);//释放参数表arg
- UART1_SendString(Strings);//发送字符串Strings
-}
-
-/*
- *函数简介:UART1获取接收完成标志位
- *参数说明:无
- *返回类型:1-接收完成,0-接收未完成
- *备注:接收完成会软件清零标志位
- */
-uint8_t UART1_GetRxFlag(void)
-{
- if(UART1_RxFlag==1)
- {
- UART1_RxFlag=0;//复位
- return 1;
- }
- return 0;
-}
-
-/*
- *函数简介:UART2串口发送初始化
- *参数说明:无
- *返回类型:无
- *备注:UART2为USART1,默认Tx引脚PA9
- */
-void UART2_SendInit(void)
-{
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1,ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA,ENABLE);//开启时钟
-
- GPIO_InitTypeDef GPIO_InitStructure;
- GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//复用推挽
- GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
- GPIO_InitStructure.GPIO_Pin=GPIO_Pin_9;
- GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
- GPIO_Init(GPIOA,&GPIO_InitStructure);//初始化UART2-Tx(PA9)
-
- GPIO_PinAFConfig(GPIOA,GPIO_PinSource9,GPIO_AF_USART1);//开启PA9的USART1复用模式
-
- USART_InitTypeDef USART_InitStructure;
- USART_InitStructure.USART_BaudRate=115200;//配置波特率115200
- USART_InitStructure.USART_HardwareFlowControl=USART_HardwareFlowControl_None;//配置无硬件流控制
- USART_InitStructure.USART_Mode=USART_Mode_Tx;//配置为发送模式
- USART_InitStructure.USART_Parity=USART_Parity_No;//配置为无校验位
- USART_InitStructure.USART_StopBits=USART_StopBits_1;//配置停止位为1
- USART_InitStructure.USART_WordLength=USART_WordLength_8b;//配置字长8bit
- USART_Init(USART1,&USART_InitStructure);//初始化USART1
-
- USART_Cmd(USART1,ENABLE);//启动USART1
-}
-
-/*
- *函数简介:UART2串口接收初始化
- *参数说明:无
- *返回类型:无
- *备注:UART2为USART1,默认Rx引脚PB7
- */
-void UART2_ReceiveInit(void)
-{
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1,ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB,ENABLE);//开启时钟
-
- GPIO_InitTypeDef GPIO_InitStructure;
- GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//复用推挽
- GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
- GPIO_InitStructure.GPIO_Pin=GPIO_Pin_7;
- GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
- GPIO_Init(GPIOB,&GPIO_InitStructure);//初始化UART2-Rx(PB7)
-
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource7,GPIO_AF_USART1);//开启PB7的USART1复用模式
-
- USART_InitTypeDef USART_InitStructure;
- USART_InitStructure.USART_BaudRate=115200;//配置波特率115200
- USART_InitStructure.USART_HardwareFlowControl=USART_HardwareFlowControl_None;//配置无硬件流控制
- USART_InitStructure.USART_Mode=USART_Mode_Rx;//配置为接收模式
- USART_InitStructure.USART_Parity=USART_Parity_No;//配置为无校验位
- USART_InitStructure.USART_StopBits=USART_StopBits_1;//配置停止位为1
- USART_InitStructure.USART_WordLength=USART_WordLength_8b;//配置字长8bit
- USART_Init(USART1,&USART_InitStructure);//初始化USART1
-
- USART_ITConfig(USART1,USART_IT_RXNE,ENABLE);//打通USART1到NVIC的串口接收中断通道
-
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//选择NVIC分组2(2位抢占优先级，2位响应优先级)
-
- NVIC_InitTypeDef NVIC_InitStructure;
- NVIC_InitStructure.NVIC_IRQChannel=USART1_IRQn;//选择USART1中断通道
- NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;//使能中断通道
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=1;//抢占优先级为1
- NVIC_InitStructure.NVIC_IRQChannelSubPriority=1;//响应优先级为1
- NVIC_Init(&NVIC_InitStructure);//初始化USART1的NVIC
-
- USART_Cmd(USART1,ENABLE);//启动USART1
-}
-
-/*
- *函数简介:UART2串口初始化
- *参数说明:无
- *返回类型:无
- *备注:UART2为USART1,默认Tx引脚PA9,Rx引脚PB7
- */
-void UART2_Init(void)
-{
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1,ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA,ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB,ENABLE);//开启时钟
-
- GPIO_InitTypeDef GPIO_InitStructure;
- GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//复用推挽
- GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
- GPIO_InitStructure.GPIO_Pin=GPIO_Pin_9;
- GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
- GPIO_Init(GPIOA,&GPIO_InitStructure);//初始化UART2-Tx(PA9)
- GPIO_InitStructure.GPIO_Pin=GPIO_Pin_7;
- GPIO_Init(GPIOB,&GPIO_InitStructure);//初始化UART2-Rx(PB7)
-
- GPIO_PinAFConfig(GPIOA,GPIO_PinSource9,GPIO_AF_USART1);//开启PA9的USART1复用模式
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource7,GPIO_AF_USART1);//开启PB7的USART1复用模式
-
- USART_InitTypeDef USART_InitStructure;
- USART_InitStructure.USART_BaudRate=115200;//配置波特率115200
- USART_InitStructure.USART_HardwareFlowControl=USART_HardwareFlowControl_None;//配置无硬件流控制
- USART_InitStructure.USART_Mode=USART_Mode_Tx | USART_Mode_Rx;//配置为接发模式
- USART_InitStructure.USART_Parity=USART_Parity_No;//配置为无校验位
- USART_InitStructure.USART_StopBits=USART_StopBits_1;//配置停止位为1
- USART_InitStructure.USART_WordLength=USART_WordLength_8b;//配置字长8bit
- USART_Init(USART1,&USART_InitStructure);//初始化USART1
-
- USART_ITConfig(USART1,USART_IT_RXNE,ENABLE);//打通USART1到NVIC的串口接收中断通道
-
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//选择NVIC分组2(2位抢占优先级，2位响应优先级)
-
- NVIC_InitTypeDef NVIC_InitStructure;
- NVIC_InitStructure.NVIC_IRQChannel=USART1_IRQn;//选择USART1中断通道
- NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;//使能中断通道
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=1;//抢占优先级为1
- NVIC_InitStructure.NVIC_IRQChannelSubPriority=1;//响应优先级为1
- NVIC_Init(&NVIC_InitStructure);//初始化USART1的NVIC
-
- USART_Cmd(USART1,ENABLE);//启动USART1
-}
-
-/*
- *函数简介:UART2发送一个字节
- *参数说明:8bits数据
- *返回类型:无
- *备注:无
- */
-void UART2_SendByte(uint8_t Byte)
-{
- USART_SendData(USART1,Byte);
- while(USART_GetFlagStatus(USART1,USART_FLAG_TXE)==RESET);//等待发送完成
-}
-
-/*
- *函数简介:UART2发送一个数组
- *参数说明:8bits数组
- *参数说明:数组长度
- *返回类型:无
- *备注:无
- */
-void UART2_SendArray(uint8_t *Array,uint16_t Length)
-{
- for(uint16_t i=0;i=Number位数)
- *返回类型:无
- *备注:无
- */
-void UART2_SendNumber(uint32_t Number,uint8_t Length)
-{
- for(uint8_t i=0;iDR=ch;
- while(!(USART1->SR&(1<<7))){}
- return ch;
- }
-
- /*
- *函数简介:重写fgetc函数(重定向scanf，即移植scanf)
- *参数说明:无
- *返回类型:无
- *备注:看不懂
- *备注:默认重定向UART1(即USART6),若想修改重定向串口,请更改最上方宏定义的注释
- */
- int fgetc(FILE *stream)
- {
- while(!(USART1->SR&1<<5)){}
- return USART1->DR;
- }
-#endif
-
-/*
- *函数简介:UART2的printf函数
- *参数说明:无
- *返回类型:无
- *备注:等价printf函数,支持多串口
- *备注:看不懂
- */
-void UART2_Printf(char *format,...)
-{
- char Strings[100];
- va_list arg;//定义参数列表变量arg
- va_start(arg,format);//从format位置接收参数，放在arg里
- vsprintf(Strings,format,arg);//将格式化字符串打印到Strings
- va_end(arg);//释放参数表arg
- UART2_SendString(Strings);//发送字符串Strings
-}
-
-/*
- *函数简介:UART2获取接收完成标志位
- *参数说明:无
- *返回类型:1-接收完成,0-接收未完成
- *备注:接收完成会软件清零标志位
- */
-uint8_t UART2_GetRxFlag(void)
-{
- if(UART2_RxFlag==1)
- {
- UART2_RxFlag=0;//复位
- return 1;
- }
- return 0;
-}
-
-/*
- *函数简介:UART1普通串口中断函数
- *参数说明:无
- *返回类型:无
- *备注:接收完成置UART1_RxFlag为1,需软件清0
- */
-/**************************************************
-void USART6_IRQHandler(void)
-{
- if(USART_GetITStatus(USART6,USART_IT_RXNE)==SET)//查询接收中断标志位
- {
- UART1_RxData=USART_ReceiveData(USART6);//将数据存入缓存区
- //函数体
- UART1_RxFlag=1;//置接收完成标志位
- }
-
- USART_ClearITPendingBit(USART6,USART_IT_RXNE);//清除接收中断标志位
-}
-**************************************************/
-
-/*
- *函数简介:UART2普通串口中断函数
- *参数说明:无
- *返回类型:无
- *备注:接收完成置UART2_RxFlag为1,需软件清0
- */
-/**************************************************
-void USART1_IRQHandler(void)
-{
- if(USART_GetITStatus(USART1,USART_IT_RXNE)==SET)//查询接收中断标志位
- {
- UART2_RxData=USART_ReceiveData(USART1);//将数据存入缓存区
- //函数体
- UART2_RxFlag=1;//置接收完成标志位
- }
-
- USART_ClearITPendingBit(USART1,USART_IT_RXNE);//清除接收中断标志位
-}
-**************************************************/
diff --git a/云台/云台-old/System/UART.h b/云台/云台-old/System/UART.h
deleted file mode 100644
index b5c5ba4..0000000
--- a/云台/云台-old/System/UART.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef __UART_H
-#define __UART_H
-
-extern uint8_t UART1_RxData;//接收数据缓存区
-extern uint8_t UART1_RxFlag;//接收完成标志位
-extern uint8_t UART2_RxData;//接收数据缓存区
-extern uint8_t UART2_RxFlag;//接收完成标志位
-
-void UART1_SendInit(void);//UART1串口发送初始化
-void UART1_ReceiveInit(void);//UART1串口接收初始化
-void UART1_Init(void);//UART1串口初始化
-void UART1_SendByte(uint8_t Byte);//UART1发送一个字节
-void UART1_SendArray(uint8_t *Array,uint16_t Length);//UART1发送一个数组
-void UART1_SendString(char *String);//UART1发送一个字符串
-void UART1_SendNumber(uint32_t Number,uint8_t Length);//UART1以文本形式发送一个数字
-void UART1_Printf(char *format,...);//UART1的printf函数
-uint8_t UART1_GetRxFlag(void);//UART1获取接收完成标志位
-void UART2_SendInit(void);//UART2串口发送初始化
-void UART2_ReceiveInit(void);//UART2串口接收初始化
-void UART2_Init(void);//UART2串口初始化
-void UART2_SendByte(uint8_t Byte);//UART2发送一个字节
-void UART2_SendArray(uint8_t *Array,uint16_t Length);//UART2发送一个数组
-void UART2_SendString(char *String);//UART2发送一个字符串
-void UART2_SendNumber(uint32_t Number,uint8_t Length);//UART2以文本形式发送一个数字
-void UART2_Printf(char *format,...);//UART2的printf函数
-uint8_t UART2_GetRxFlag(void);//UART2获取接收完成标志位
-
-#endif
diff --git a/云台/云台-old/User/Parameter.h b/云台/云台-old/User/Parameter.h
deleted file mode 100644
index 97ba204..0000000
--- a/云台/云台-old/User/Parameter.h
+++ /dev/null
@@ -1,37 +0,0 @@
-#ifndef __PARAMETER_H
-#define __PARAMETER_H
-
-/*=============================================结构参数=============================================*/
-#define Yaw_GM6020PositionValue 4050//Yaw轴编码器值4050
-#define Pitch_GM6020PositionValue 3245//Pitch轴编码器值
-#define Pitch_GM6020PositionLowerLinit 3000//Pitch轴编码器值下限
-#define Pitch_GM6020PositionUpperLinit 2900//Pitch轴编码器值上限
-#define Pitch_GM6020AngleLowerLinit 15.0f//Pitch轴编码器值下限
-#define Pitch_GM6020AngleUpperLinit -10.0f//Pitch轴编码器值上限
-
-/*=============================================云台参数=============================================*/
-#define Gimbal_FrictionWheelSpeed 500//摩擦轮转速,弹速限制30m/s
-#define Gimbal_RammerSpeed -1500//拨弹盘转速,射频为7时大概冷却和热量相抵,5400是射频20的最低下限
-
-#define Gimbal_LeverSpeedMapRate 3.0f//云台俯仰拨杆速度映射比例
-#define Gimbal_YawPitchSpeedRate 2.0f//云台偏航俯仰速度比
-
-/*=============================================操作手参数=============================================*/
-#define PC_Go (Remote_RxData.Remote_Key_W)//前
-#define PC_Back (Remote_RxData.Remote_Key_S)//后
-#define PC_Left (Remote_RxData.Remote_Key_A)//左
-#define PC_Right (Remote_RxData.Remote_Key_D)//右
-
-#define PC_Spin (Remote_RxData.Remote_Mouse_RL)//视角水平移动
-#define PC_Pitch (Remote_RxData.Remote_Mouse_DU)//视角垂直移动
-#define PC_Mouse_RLSensitivity 3.0f//鼠标左右灵敏度
-#define PC_Mouse_DUSensitivity 8.0f//鼠标上下灵敏度
-
-#define PC_FrictionWheel (Remote_RxData.Remote_KeyPush_Q)//摩擦轮
-#define PC_Fire (Remote_RxData.Remote_Mouse_KeyL)//发射
-#define PC_Ejection (Remote_RxData.Remote_Key_E)//退弹
-
-#define PC_GyroScope (Remote_RxData.Remote_KeyPush_Ctrl)//小陀螺
-#define PC_SpeedUp (Remote_RxData.Remote_Key_Shift)//加速
-
-#endif
diff --git a/云台/云台-old/User/RM_C.h b/云台/云台-old/User/RM_C.h
deleted file mode 100644
index 6f90ca1..0000000
--- a/云台/云台-old/User/RM_C.h
+++ /dev/null
@@ -1,42 +0,0 @@
-#ifndef __RM_C_H
-#define __RM_C_H
-
-/*==========延时==========*/
-#include "Delay.h" //延时
-
-/*==========硬件驱动==========*/
-#include "TIM.h" //定时器
-#include "LED.h" //LED
-#include "Buzzer.h" //蜂鸣器
-#include "Remote.h" //遥控器
-#include "BMI088.h" //陀螺仪
-#include "IST8310.h" //磁力计
-#include "Laser.h" //激光
-#include "M3508.h" //M3508
-#include "GM6020.h" //GM6020
-#include "M2006.h" //M2006
-
-/*==========通讯协议==========*/
-#include "UART.h" //串口
-#include "MyI2C.h" //软件I2C
-#include "CAN.h" //CAN
-
-/*==========控制算法==========*/
-#include "PID.h" //PID
-
-/*==========功能==========*/
-#include "LinkCheck.h" //CAN连接检测
-#include "CloseLoopControl.h" //闭环控制
-#include "CToC.h" //板间通讯
-#include "IMUTemperatureControl.h" //陀螺仪恒温控制
-#include "AttitudeAlgorithms.h" //姿态解算
-#include "Warming.h" //报警
-
-/*==========车体=========*/
-#include "Parameter.h" //参数
-#include "Gimbal.h" //云台
-#include "Visual.h" //视觉
-#include "RefereeSystem.h" //裁判系统
-#include "Keyboard.h" //键盘
-
-#endif
diff --git a/云台/云台-old/User/main.c b/云台/云台-old/User/main.c
deleted file mode 100644
index 65613f0..0000000
--- a/云台/云台-old/User/main.c
+++ /dev/null
@@ -1,34 +0,0 @@
-#include "stm32f4xx.h" // Device header
-#include "stm32f4xx_conf.h"
-#include
-#include "RM_C.h"
-#include "AttitudeAlgorithms.h"
-#include "Gimbal.h"
-#include "visual.h"
-
-int main(void)
-{
- Warming_Init();//报警初始化
- LED_BON();//蓝灯点亮表示代码在运行
- AttitudeAlgorithms_Init();//姿态解算初始化
- Delay_s(1);//延时,等待校准和模块启动
- LinkCheck_Init();//连接检测初始化
- RefereeSystem_Init();//图传链路初始化
- Visual_Init();//视觉初始化
- CloseLoopControl_Init();//闭环控制初始化
- Remote_Init();//遥控器初始化
- UART2_SendInit();//串口2初始化
- //UART2_Init();
- while(1)
- {
- IWDG_ReloadCounter();//喂狗
-
- CToC_MasterSendControl();//CToC发送遥控器控制数据
- CToC_MasterSendData();//CToC发送遥控器摇杆数据
- //Debug();
- //UART2_Printf("%d\n",AttitudeAlgorithms_DegYaw);
- //Visual_SendData();
-
- Delay_us(1);//延时1usCToC周期1.5ms
- }
-}
diff --git a/云台/云台-old/User/stm32f4xx_conf.h b/云台/云台-old/User/stm32f4xx_conf.h
deleted file mode 100644
index 9540684..0000000
--- a/云台/云台-old/User/stm32f4xx_conf.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/**
- ******************************************************************************
- * @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_conf.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief Library configuration file.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_CONF_H
-#define __STM32F4xx_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment the line below to enable peripheral header file inclusion */
-#include "stm32f4xx_adc.h"
-#include "stm32f4xx_crc.h"
-#include "stm32f4xx_dbgmcu.h"
-#include "stm32f4xx_dma.h"
-#include "stm32f4xx_exti.h"
-#include "stm32f4xx_flash.h"
-#include "stm32f4xx_gpio.h"
-#include "stm32f4xx_i2c.h"
-#include "stm32f4xx_iwdg.h"
-#include "stm32f4xx_pwr.h"
-#include "stm32f4xx_rcc.h"
-#include "stm32f4xx_rtc.h"
-#include "stm32f4xx_sdio.h"
-#include "stm32f4xx_spi.h"
-#include "stm32f4xx_syscfg.h"
-#include "stm32f4xx_tim.h"
-#include "stm32f4xx_usart.h"
-#include "stm32f4xx_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-#if defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#include "stm32f4xx_cryp.h"
-#include "stm32f4xx_hash.h"
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_can.h"
-#include "stm32f4xx_dac.h"
-#include "stm32f4xx_dcmi.h"
-#include "stm32f4xx_dma2d.h"
-#include "stm32f4xx_fmc.h"
-#include "stm32f4xx_ltdc.h"
-#include "stm32f4xx_sai.h"
-#endif /* STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F427_437xx)
-#include "stm32f4xx_cryp.h"
-#include "stm32f4xx_hash.h"
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_can.h"
-#include "stm32f4xx_dac.h"
-#include "stm32f4xx_dcmi.h"
-#include "stm32f4xx_dma2d.h"
-#include "stm32f4xx_fmc.h"
-#include "stm32f4xx_sai.h"
-#endif /* STM32F427_437xx */
-
-#if defined(STM32F40_41xxx)
-#include "stm32f4xx_cryp.h"
-#include "stm32f4xx_hash.h"
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_can.h"
-#include "stm32f4xx_dac.h"
-#include "stm32f4xx_dcmi.h"
-#include "stm32f4xx_fsmc.h"
-#endif /* STM32F40_41xxx */
-
-#if defined(STM32F410xx)
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_dac.h"
-#endif /* STM32F410xx */
-
-#if defined(STM32F411xE)
-#include "stm32f4xx_flash_ramfunc.h"
-#endif /* STM32F411xE */
-
-#if defined(STM32F446xx) || defined(STM32F469_479xx)
-#include "stm32f4xx_qspi.h"
-#endif /* STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F410xx) || defined(STM32F446xx)
-#include "stm32f4xx_fmpi2c.h"
-#endif /* STM32F410xx || STM32F446xx */
-
-#if defined(STM32F446xx)
-#include "stm32f4xx_spdifrx.h"
-#include "stm32f4xx_cec.h"
-#endif /* STM32F446xx */
-
-#if defined(STM32F469_479xx)
-#include "stm32f4xx_dsi.h"
-#endif /* STM32F469_479xx */
-
-#if defined(STM32F410xx)
-#include "stm32f4xx_lptim.h"
-#endif /* STM32F410xx */
-
-#if defined(STM32F412xG)
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_can.h"
-#include "stm32f4xx_qspi.h"
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_fsmc.h"
-#include "stm32f4xx_dfsdm.h"
-#endif /* STM32F412xG */
-
-#if defined(STM32F413_423xx)
-#include "stm32f4xx_cryp.h"
-#include "stm32f4xx_fmpi2c.h"
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_can.h"
-#include "stm32f4xx_qspi.h"
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_fsmc.h"
-#include "stm32f4xx_dfsdm.h"
-#endif /* STM32F413_423xx */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* If an external clock source is used, then the value of the following define
- should be set to the value of the external clock source, else, if no external
- clock is used, keep this define commented */
-/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */
-
-
-/* Uncomment the line below to expanse the "assert_param" macro in the
- Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT 1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
-
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr: If expr is false, it calls assert_failed function
- * which reports the name of the source file and the source
- * line number of the call that failed.
- * If expr is true, it returns no value.
- * @retval None
- */
- #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
-#else
- #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F4xx_CONF_H */
-
diff --git a/云台/云台-old/User/stm32f4xx_it.c b/云台/云台-old/User/stm32f4xx_it.c
deleted file mode 100644
index 50a40d1..0000000
--- a/云台/云台-old/User/stm32f4xx_it.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/**
- ******************************************************************************
- * @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_it.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief Main Interrupt Service Routines.
- * This file provides template for all exceptions handler and
- * peripherals interrupt service routine.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_it.h"
-
-/** @addtogroup Template_Project
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/* Cortex-M4 Processor Exceptions Handlers */
-/******************************************************************************/
-
-/**
- * @brief This function handles NMI exception.
- * @param None
- * @retval None
- */
-void NMI_Handler(void)
-{
-}
-
-/**
- * @brief This function handles Hard Fault exception.
- * @param None
- * @retval None
- */
-void HardFault_Handler(void)
-{
- /* Go to infinite loop when Hard Fault exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles Memory Manage exception.
- * @param None
- * @retval None
- */
-void MemManage_Handler(void)
-{
- /* Go to infinite loop when Memory Manage exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles Bus Fault exception.
- * @param None
- * @retval None
- */
-void BusFault_Handler(void)
-{
- /* Go to infinite loop when Bus Fault exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles Usage Fault exception.
- * @param None
- * @retval None
- */
-void UsageFault_Handler(void)
-{
- /* Go to infinite loop when Usage Fault exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles SVCall exception.
- * @param None
- * @retval None
- */
-void SVC_Handler(void)
-{
-}
-
-/**
- * @brief This function handles Debug Monitor exception.
- * @param None
- * @retval None
- */
-void DebugMon_Handler(void)
-{
-}
-
-/**
- * @brief This function handles PendSVC exception.
- * @param None
- * @retval None
- */
-void PendSV_Handler(void)
-{
-}
-
-/**
- * @brief This function handles SysTick Handler.
- * @param None
- * @retval None
- */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/* STM32F4xx Peripherals Interrupt Handlers */
-/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
-/* available peripheral interrupt handler's name please refer to the startup */
-/* file (startup_stm32f4xx.s). */
-/******************************************************************************/
-
-/**
- * @brief This function handles PPP interrupt request.
- * @param None
- * @retval None
- */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
- * @}
- */
-
-
diff --git a/云台/云台-old/User/stm32f4xx_it.h b/云台/云台-old/User/stm32f4xx_it.h
deleted file mode 100644
index dd54f16..0000000
--- a/云台/云台-old/User/stm32f4xx_it.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/**
- ******************************************************************************
- * @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_it.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains the headers of the interrupt handlers.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_IT_H
-#define __STM32F4xx_IT_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_IT_H */
-
diff --git a/云台/云台-old/keilkill.bat b/云台/云台-old/keilkill.bat
deleted file mode 100644
index accc110..0000000
--- a/云台/云台-old/keilkill.bat
+++ /dev/null
@@ -1,27 +0,0 @@
-del *.bak /s
-del *.ddk /s
-del *.edk /s
-del *.lst /s
-del *.lnp /s
-del *.mpf /s
-del *.mpj /s
-del *.obj /s
-del *.omf /s
-::del *.opt /s ::ɾJLINK
-del *.plg /s
-del *.rpt /s
-del *.tmp /s
-del *.__i /s
-del *.crf /s
-del *.o /s
-del *.d /s
-del *.axf /s
-del *.tra /s
-del *.dep /s
-del JLinkLog.txt /s
-
-del *.iex /s
-del *.htm /s
-del *.sct /s
-del *.map /s
-exit
diff --git a/底盘/底盘-old/底盘/.vscode/c_cpp_properties.json b/底盘/底盘-old/底盘/.vscode/c_cpp_properties.json
deleted file mode 100644
index 46b2791..0000000
--- a/底盘/底盘-old/底盘/.vscode/c_cpp_properties.json
+++ /dev/null
@@ -1,195 +0,0 @@
-{
- "configurations": [
- {
- "name": "windows-cygwin-gcc-x64",
- "includePath": [
- "${workspaceFolder}/**",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Start",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Library",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\System",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Algorithm",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Hardware",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Motor",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Function",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Control",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\CarBody",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\User",
- "C:\\Keil_v5\\ARM\\ARMCC\\include"
- ],
- "defines": [
- "USE_STDPERIPH_DRIVER",
- "STM32F40_41xxx",
- "__CC_ARM",
- "__arm__",
- "__align(x)=",
- "__ALIGNOF__(x)=",
- "__alignof__(x)=",
- "__asm(x)=",
- "__forceinline=",
- "__restrict=",
- "__global_reg(n)=",
- "__inline=",
- "__int64=long long",
- "__INTADDR__(expr)=0",
- "__irq=",
- "__packed=",
- "__pure=",
- "__smc(n)=",
- "__svc(n)=",
- "__svc_indirect(n)=",
- "__svc_indirect_r7(n)=",
- "__value_in_regs=",
- "__weak=",
- "__writeonly=",
- "__declspec(x)=",
- "__attribute__(x)=",
- "__nonnull__(x)=",
- "__register=",
- "__breakpoint(x)=",
- "__cdp(x,y,z)=",
- "__clrex()=",
- "__clz(x)=0U",
- "__current_pc()=0U",
- "__current_sp()=0U",
- "__disable_fiq()=",
- "__disable_irq()=",
- "__dmb(x)=",
- "__dsb(x)=",
- "__enable_fiq()=",
- "__enable_irq()=",
- "__fabs(x)=0.0",
- "__fabsf(x)=0.0f",
- "__force_loads()=",
- "__force_stores()=",
- "__isb(x)=",
- "__ldrex(x)=0U",
- "__ldrexd(x)=0U",
- "__ldrt(x)=0U",
- "__memory_changed()=",
- "__nop()=",
- "__pld(...)=",
- "__pli(...)=",
- "__qadd(x,y)=0",
- "__qdbl(x)=0",
- "__qsub(x,y)=0",
- "__rbit(x)=0U",
- "__rev(x)=0U",
- "__return_address()=0U",
- "__ror(x,y)=0U",
- "__schedule_barrier()=",
- "__semihost(x,y)=0",
- "__sev()=",
- "__sqrt(x)=0.0",
- "__sqrtf(x)=0.0f",
- "__ssat(x,y)=0",
- "__strex(x,y)=0U",
- "__strexd(x,y)=0",
- "__strt(x,y)=",
- "__swp(x,y)=0U",
- "__usat(x,y)=0U",
- "__wfe()=",
- "__wfi()=",
- "__yield()=",
- "__vfp_status(x,y)=0"
- ],
- "intelliSenseMode": "linux-gcc-x64",
- "cStandard": "${default}",
- "cppStandard": "${default}",
- "compilerPath": "C:/cygwin64/bin/gcc.exe"
- },
- {
- "name": "Target 1",
- "includePath": [
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\new-infantry\\底盘\\底盘-old\\底盘\\Start",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\new-infantry\\底盘\\底盘-old\\底盘\\Library",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\new-infantry\\底盘\\底盘-old\\底盘\\System",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\new-infantry\\底盘\\底盘-old\\底盘\\Algorithm",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\new-infantry\\底盘\\底盘-old\\底盘\\Hardware",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\new-infantry\\底盘\\底盘-old\\底盘\\Motor",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\new-infantry\\底盘\\底盘-old\\底盘\\Function",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\new-infantry\\底盘\\底盘-old\\底盘\\Control",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\new-infantry\\底盘\\底盘-old\\底盘\\CarBody",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\new-infantry\\底盘\\底盘-old\\底盘\\User",
- "C:\\Keil_v5\\ARM\\ARMCC\\include"
- ],
- "defines": [
- "USE_STDPERIPH_DRIVER",
- "STM32F40_41xxx",
- "__CC_ARM",
- "__arm__",
- "__align(x)=",
- "__ALIGNOF__(x)=",
- "__alignof__(x)=",
- "__asm(x)=",
- "__forceinline=",
- "__restrict=",
- "__global_reg(n)=",
- "__inline=",
- "__int64=long long",
- "__INTADDR__(expr)=0",
- "__irq=",
- "__packed=",
- "__pure=",
- "__smc(n)=",
- "__svc(n)=",
- "__svc_indirect(n)=",
- "__svc_indirect_r7(n)=",
- "__value_in_regs=",
- "__weak=",
- "__writeonly=",
- "__declspec(x)=",
- "__attribute__(x)=",
- "__nonnull__(x)=",
- "__register=",
- "__breakpoint(x)=",
- "__cdp(x,y,z)=",
- "__clrex()=",
- "__clz(x)=0U",
- "__current_pc()=0U",
- "__current_sp()=0U",
- "__disable_fiq()=",
- "__disable_irq()=",
- "__dmb(x)=",
- "__dsb(x)=",
- "__enable_fiq()=",
- "__enable_irq()=",
- "__fabs(x)=0.0",
- "__fabsf(x)=0.0f",
- "__force_loads()=",
- "__force_stores()=",
- "__isb(x)=",
- "__ldrex(x)=0U",
- "__ldrexd(x)=0U",
- "__ldrt(x)=0U",
- "__memory_changed()=",
- "__nop()=",
- "__pld(...)=",
- "__pli(...)=",
- "__qadd(x,y)=0",
- "__qdbl(x)=0",
- "__qsub(x,y)=0",
- "__rbit(x)=0U",
- "__rev(x)=0U",
- "__return_address()=0U",
- "__ror(x,y)=0U",
- "__schedule_barrier()=",
- "__semihost(x,y)=0",
- "__sev()=",
- "__sqrt(x)=0.0",
- "__sqrtf(x)=0.0f",
- "__ssat(x,y)=0",
- "__strex(x,y)=0U",
- "__strexd(x,y)=0",
- "__strt(x,y)=",
- "__swp(x,y)=0U",
- "__usat(x,y)=0U",
- "__wfe()=",
- "__wfi()=",
- "__yield()=",
- "__vfp_status(x,y)=0"
- ],
- "intelliSenseMode": "${default}"
- }
- ],
- "version": 4
-}
\ No newline at end of file
diff --git a/底盘/底盘-old/底盘/.vscode/keil-assistant.log b/底盘/底盘-old/底盘/.vscode/keil-assistant.log
deleted file mode 100644
index fd2df44..0000000
--- a/底盘/底盘-old/底盘/.vscode/keil-assistant.log
+++ /dev/null
@@ -1,92 +0,0 @@
-[info] Log at : 2025/1/26|15:24:52|GMT+0800
-
-[info] Log at : 2025/1/26|15:33:07|GMT+0800
-
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-[info] Log at : 2025/3/28|09:33:15|GMT+0800
-
diff --git a/底盘/底盘-old/底盘/.vscode/launch.json b/底盘/底盘-old/底盘/.vscode/launch.json
deleted file mode 100644
index e8ed206..0000000
--- a/底盘/底盘-old/底盘/.vscode/launch.json
+++ /dev/null
@@ -1,24 +0,0 @@
-{
- "version": "0.2.0",
- "configurations": [
- {
- "name": "C/C++ Runner: Debug Session",
- "type": "cppdbg",
- "request": "launch",
- "args": [],
- "stopAtEntry": false,
- "externalConsole": true,
- "cwd": "f:/Mas_Infantry_Control-main/开源代码/V1.0/底盘/底盘/CarBody",
- "program": "f:/Mas_Infantry_Control-main/开源代码/V1.0/底盘/底盘/CarBody/build/Debug/outDebug",
- "MIMode": "gdb",
- "miDebuggerPath": "gdb",
- "setupCommands": [
- {
- "description": "Enable pretty-printing for gdb",
- "text": "-enable-pretty-printing",
- "ignoreFailures": true
- }
- ]
- }
- ]
-}
\ No newline at end of file
diff --git a/底盘/底盘-old/底盘/.vscode/settings.json b/底盘/底盘-old/底盘/.vscode/settings.json
deleted file mode 100644
index 86f068d..0000000
--- a/底盘/底盘-old/底盘/.vscode/settings.json
+++ /dev/null
@@ -1,71 +0,0 @@
-{
- "C_Cpp_Runner.cCompilerPath": "gcc",
- "C_Cpp_Runner.cppCompilerPath": "g++",
- "C_Cpp_Runner.debuggerPath": "gdb",
- "C_Cpp_Runner.cStandard": "",
- "C_Cpp_Runner.cppStandard": "",
- "C_Cpp_Runner.msvcBatchPath": "C:/Program Files/Microsoft Visual Studio/VR_NR/Community/VC/Auxiliary/Build/vcvarsall.bat",
- "C_Cpp_Runner.useMsvc": false,
- "C_Cpp_Runner.warnings": [
- "-Wall",
- "-Wextra",
- "-Wpedantic",
- "-Wshadow",
- "-Wformat=2",
- "-Wcast-align",
- "-Wconversion",
- "-Wsign-conversion",
- "-Wnull-dereference"
- ],
- "C_Cpp_Runner.msvcWarnings": [
- "/W4",
- "/permissive-",
- "/w14242",
- "/w14287",
- "/w14296",
- "/w14311",
- "/w14826",
- "/w44062",
- "/w44242",
- "/w14905",
- "/w14906",
- "/w14263",
- "/w44265",
- "/w14928"
- ],
- "C_Cpp_Runner.enableWarnings": true,
- "C_Cpp_Runner.warningsAsError": false,
- "C_Cpp_Runner.compilerArgs": [],
- "C_Cpp_Runner.linkerArgs": [],
- "C_Cpp_Runner.includePaths": [
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Start",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Library",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\System",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Algorithm",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Hardware",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Motor",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Function",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\Control",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\CarBody",
- "f:\\Mas_Infantry_Control-main\\开源代码\\V1.0\\底盘\\底盘\\User",
- "C:\\Keil_v5\\ARM\\ARMCC\\include"
- ],
- "C_Cpp_Runner.includeSearch": [
- "*",
- "**/*"
- ],
- "C_Cpp_Runner.excludeSearch": [
- "**/build",
- "**/build/**",
- "**/.*",
- "**/.*/**",
- "**/.vscode",
- "**/.vscode/**"
- ],
- "C_Cpp_Runner.useAddressSanitizer": false,
- "C_Cpp_Runner.useUndefinedSanitizer": false,
- "C_Cpp_Runner.useLeakSanitizer": false,
- "C_Cpp_Runner.showCompilationTime": false,
- "C_Cpp_Runner.useLinkTimeOptimization": false,
- "C_Cpp_Runner.msvcSecureNoWarnings": false
-}
\ No newline at end of file
diff --git a/底盘/底盘-old/底盘/.vscode/uv4.log b/底盘/底盘-old/底盘/.vscode/uv4.log
deleted file mode 100644
index dda0f7f..0000000
--- a/底盘/底盘-old/底盘/.vscode/uv4.log
+++ /dev/null
@@ -1,3 +0,0 @@
-Load "f:\\Mas_Infantry_Control-main\\Դ\\V1.0\\new-infantry\\\\\\Objects\\Project.axf"
-Erase Done.Programming Done.Verify OK.Application running ...
-Flash Load finished at 09:20:54
diff --git a/底盘/底盘-old/底盘/.vscode/uv4.log.lock b/底盘/底盘-old/底盘/.vscode/uv4.log.lock
deleted file mode 100644
index 47c1c0b..0000000
--- a/底盘/底盘-old/底盘/.vscode/uv4.log.lock
+++ /dev/null
@@ -1 +0,0 @@
-2025/3/28 9:20:55
\ No newline at end of file
diff --git a/底盘/底盘-old/底盘/CarBody/Mecanum.c b/底盘/底盘-old/底盘/CarBody/Mecanum.c
deleted file mode 100644
index 96742ac..0000000
--- a/底盘/底盘-old/底盘/CarBody/Mecanum.c
+++ /dev/null
@@ -1,356 +0,0 @@
-#include "stm32f4xx.h" // Device header
-#include "stm32f4xx_conf.h"
-#include
-#include "M3508.h"
-#include "GM6020.h"
-#include "Remote.h"
-#include "PID.h"
-#include "Parameter.h"
-#include "RefereeSystem.h"
-#include "Ultra_CAP.h"
-#include "Mecanum.h"
-#include "Delay.h"
-
-#define Mecanum_PowerControlSpeedNormalizationValue 3.0f//功率控制归一化速度标准值,范围[0,3]
-#define Mecanum_PowerControlGainCoefficientInitialValue 0.5f//功率控制增益系数初始值
-#define Mecanum_PowerControl_T 5.0f//功率控制周期(T=Mecanum_PowerControl_T*2ms)
-#define Mecanum_PowerControl_UseBuffer 30.0f//功率控制消耗的缓冲能量
-#define Mecanum_PowerControl_PowerMax 3.0f//功率控制功率上限与裁判系统功率上限比值上限
-#define Mecanum_PowerControl_UltraCAPPower 1.0f//使用超电增加功率
-
-//float Gear_ratio = 0.56666666666666666666666666666667f;//齿轮比17/30
-
-PID_PositionInitTypedef Mecanum_SpeedPID[4];//底盘四个电机的转速PID
-PID_PositionInitTypedef Mecanum_TrackPID;//底盘跟随PID
-float Mecanum_YawTheta;//底盘云台相对偏航角度
-uint8_t Mecanum_GyroScopeFlag;//底盘小陀螺标志位
-float Mecanum_Power;//底盘功率(软件计算值)
-float Mecanum_Current,Mecanum_PowerLimit,Mecanum_CurrentLimit=16384*4.0f;//底盘电流总和,功率控制功率上限,底盘电流限幅
-extern uint16_t RefereeSystem_Ref;
-
-/*
- *函数简介:麦轮初始化
- *参数说明:无
- *返回类型:无
- *备注:即四个转速PID的初始化
- *备注:四个电机的ID参照上方的宏定义,最好使用M3508电机的ID1~4,否则下方电机控制的代码需要修改
- */
-void Mecanum_Init(void)
-{
- PID_PositionStructureInit(&Mecanum_SpeedPID[0],0);//左前轮
- PID_PositionSetParameter(&Mecanum_SpeedPID[0],0.8,0,0);
- PID_PositionSetEkRange(&Mecanum_SpeedPID[0],-5,5);
- PID_PositionSetOUTRange(&Mecanum_SpeedPID[0],-15000,15000);
-
- PID_PositionStructureInit(&Mecanum_SpeedPID[1],0);//右前轮
- PID_PositionSetParameter(&Mecanum_SpeedPID[1],0.8,0,0);
- PID_PositionSetEkRange(&Mecanum_SpeedPID[1],-5,5);
- PID_PositionSetOUTRange(&Mecanum_SpeedPID[1],-15000,15000);
-
- PID_PositionStructureInit(&Mecanum_SpeedPID[2],0);//左后轮
- PID_PositionSetParameter(&Mecanum_SpeedPID[2],0.8,0,0);
- PID_PositionSetEkRange(&Mecanum_SpeedPID[2],-5,5);
- PID_PositionSetOUTRange(&Mecanum_SpeedPID[2],-15000,15000);
-
- PID_PositionStructureInit(&Mecanum_SpeedPID[3],0);//右后轮
- PID_PositionSetParameter(&Mecanum_SpeedPID[3],0.8,0,0);
- PID_PositionSetEkRange(&Mecanum_SpeedPID[3],-5,5);
- PID_PositionSetOUTRange(&Mecanum_SpeedPID[3],-15000,15000);
-
- PID_PositionStructureInit(&Mecanum_TrackPID,Yaw_GM6020PositionValue);//底盘跟随relative_angle
- //PID_PositionStructureInit(&Mecanum_TrackPID,Mecanum_YawTheta);
- //PID_PositionStructureInit(&Mecanum_TrackPID,GM6020_MotorStatus[0].Chassis_positive_direction);
- PID_PositionSetParameter(&Mecanum_TrackPID,0.001,0,0.01);
- PID_PositionSetEkRange(&Mecanum_TrackPID,-1,1);
- PID_PositionSetOUTRange(&Mecanum_TrackPID,-1,1);
-}
-
-/*
- *函数简介:麦轮PID清理
- *参数说明:无
- *返回类型:无
- *备注:清理四个转速位置式PID
- */
-void Mecanum_CleanPID(void)
-{
- PID_PositionClean(&Mecanum_SpeedPID[0]);//左前轮
- PID_PositionClean(&Mecanum_SpeedPID[1]);//右前轮
- PID_PositionClean(&Mecanum_SpeedPID[2]);//左后轮
- PID_PositionClean(&Mecanum_SpeedPID[3]);//右后轮
- PID_PositionClean(&Mecanum_TrackPID);//底盘跟随
-}
-
-/*
- *函数简介:麦轮速度控制
- *参数说明:左前轮速度
- *参数说明:右前轮速度
- *参数说明:左后轮速度
- *参数说明:右后轮速度
- *返回类型:无
- *备注:单独控制四个轮子的速度
- */
-void Mecanum_ControlSpeed(int16_t LeftFrontSpeed,int16_t RightFrontSpeed,int16_t LeftRearSpeed,int16_t RightRearSpeed)
-{
- //更改期望
- Mecanum_SpeedPID[0].Need_Value=LeftFrontSpeed;//左前轮
- Mecanum_SpeedPID[1].Need_Value=RightFrontSpeed;//右前轮;
- Mecanum_SpeedPID[2].Need_Value=LeftRearSpeed;//左后轮
- Mecanum_SpeedPID[3].Need_Value=RightRearSpeed;//右后轮
-
- //PID计算
- PID_PositionCalc(&Mecanum_SpeedPID[0],M3508_MotorStatus[Mecanum_LeftFrontWheel-0x201].RotorSpeed);//左前轮
- PID_PositionCalc(&Mecanum_SpeedPID[1],M3508_MotorStatus[Mecanum_RightFrontWheel-0x201].RotorSpeed);//右前轮
- PID_PositionCalc(&Mecanum_SpeedPID[2],M3508_MotorStatus[Mecanum_LeftRearWheel-0x201].RotorSpeed);//左后轮
- PID_PositionCalc(&Mecanum_SpeedPID[3],M3508_MotorStatus[Mecanum_RightRearWheel-0x201].RotorSpeed);//右后轮
-
- Mecanum_Current=0;
- for(uint8_t i=0;i<4;i++)
- Mecanum_Current+=fabs(Mecanum_SpeedPID[i].OUT);
- if(Mecanum_Current>Mecanum_CurrentLimit)
- {
- Mecanum_SpeedPID[0].OUT*=(Mecanum_CurrentLimit/Mecanum_Current);
- Mecanum_SpeedPID[1].OUT*=(Mecanum_CurrentLimit/Mecanum_Current);
- Mecanum_SpeedPID[2].OUT*=(Mecanum_CurrentLimit/Mecanum_Current);
- Mecanum_SpeedPID[3].OUT*=(Mecanum_CurrentLimit/Mecanum_Current);
- }
-
- M3508_CANSetLIDCurrent(Mecanum_SpeedPID[1].OUT,Mecanum_SpeedPID[0].OUT,Mecanum_SpeedPID[2].OUT,Mecanum_SpeedPID[3].OUT);//M3508控制
-}
-
-/*
- *函数简介:麦轮逆运动解算
- *参数说明:x轴速度,单位m/s(以前为正)
- *参数说明:y轴速度,单位m/s(以左为正)
- *参数说明:z轴转速,单位rad/s(以逆时针为正)
- *返回类型:无
- *备注:速度转速转换系数:
- * w'=v/R (rad/s)=v/(2Π×R) (r/s)=60×v/(2Π×R) (r/min)=1/19 w
- * ⇒ w=19×60×v/(2Π×R/100)=19×60×100×v/(2Π×R)=18143.663512×v/R,R单位cm
- *备注:麦轮半径参数在上方宏定义Mecanum_WheelRadius修改,默认7cm,转换参数2591.95
- *备注:底盘中心到轮子中心的距离由上方宏定义x轴分量Mecanum_rx和y轴分量Mecanum_ry决定
- */
-void Mecanum_InverseMotionControl(float v_x,float v_y,float w)
-{
- //逆运动解算
- int16_t LeftFrontSpeed=(int16_t)((-v_x-v_y-w*(Mecanum_rx+Mecanum_ry)/100.0f)/Mecanum_WheelRadius*18143.663512f);//左前轮
- int16_t RightFrontSpeed=(int16_t)((v_x-v_y-w*(Mecanum_rx+Mecanum_ry)/100.0f)/Mecanum_WheelRadius*18143.663512f);//右前轮
- int16_t LeftRearSpeed=(int16_t)((-v_x+v_y-w*(Mecanum_rx+Mecanum_ry)/100.0f)/Mecanum_WheelRadius*18143.663512f);//左后轮
- int16_t RightRearSpeed=(int16_t)((v_x+v_y-w*(Mecanum_rx+Mecanum_ry)/100.0f)/Mecanum_WheelRadius*18143.663512f);//右后轮
-
- Mecanum_ControlSpeed(LeftFrontSpeed,RightFrontSpeed,LeftRearSpeed,RightRearSpeed);//M3508速度控制
-}
-/*
-
- * @brief 设置底盘控制设定点，三个运动控制值由"chassis_behaviour_control_set".
- * @param[out] chassis_move_update: "chassis_move" valiable point
- * @retval
-
-void chassis_relative_angle(float relative_angle)
- {
- if(last_relative_angle!=99&&fabs(relative_angle-last_relative_angle)<5)
- {
- fake_relative_angle+=((relative_angle-last_relative_angle)/(30/17));
- }
- last_relative_angle=relative_angle;
- if(fake_relative_angle>3.141592653589793238462643383279f)fake_relative_angle=-3.141592653589793238462643383279f;
- if(fake_relative_angle<-3.141592653589793238462643383279f)fake_relative_angle=3.141592653589793238462643383279f;
- }
-*/
-/*
- *函数简介:麦轮功率控制
- *参数说明:无
- *返回类型:无
- *备注:麦轮是否开启可功率控制模式决定于上方宏定义Mecanum_PowerControl
- *备注:以Mecanum_PowerControl_T*2ms为控制周期,取底盘平均功率(通过M3508反馈数据计算),通过速度增益系数和速度归一化控制速度大小,速度增益系数在[0,2]范围内
- *备注:速度归一化的标准值在上方宏定义Mecanum_PowerControlSpeedNormalizationValue修改,范围[0,3]
- *备注:增益系数的初始值在上方宏定义Mecanum_PowerControlGainCoefficientInitialValue修改
- *备注:设定功率上限最高为150W限幅
- *备注:速度转速转换系数:
- * w'=v/R (rad/s)=v/(2Π×R) (r/s)=60×v/(2Π×R) (r/min)=1/19 w
- * ⇒ w=19×60×v/(2Π×R/100)=19×60×100×v/(2Π×R)=18143.663512×v/R,R单位cm
- *备注:底盘中心到轮子中心的距离由上方宏定义x轴分量Mecanum_rx和y轴分量Mecanum_ry决定
- */
-void Mecanum_PowerMoveControl(void)
-{
- static uint8_t Mecanum_GyroScopeCloseFlag=0;//小陀螺待关闭标志位
- static float GainCoefficient=1.0f;//速度增益系数
- static uint8_t Count=0;//计数器,以Mecanum_PowerControl_T*2ms为控制周期
-
- /*==========三轴速度获取==========*/
-
- float vx=1024-Remote_RxData.Remote_R_UD;
- float vy=1024-Remote_RxData.Remote_R_RL;
- float w=1024-Remote_RxData.Remote_L_RL;//获取三个轴的速度参量
- float sigma=sqrtf(vx*vx+vy*vy);//获取xy轴速度归一化系数
- if(sigma!=0)//x,y轴速度归一化(正交合成速度不变为标准值)
- {
- vx=vx/sigma*Mecanum_PowerControlSpeedNormalizationValue;
- vy=vy/sigma*Mecanum_PowerControlSpeedNormalizationValue;
- }
-
- int16_t Raw_Theta=Yaw_GM6020PositionValue-GM6020_MotorStatus[0].Angle;//获取底盘云台相对角度原始数据
- if(Raw_Theta<0)Raw_Theta+=8192;
- //Mecanum_YawTheta=Raw_Theta/8192.0f*2.0f*3.141592653589793238462643383279f;
- Mecanum_YawTheta=Raw_Theta*0.000766990393942820614859043794746f;//获取底盘云台相对角度*0.56666666666666666666666666666667f
-
- float vx_=vx,vy_=vy;
- vx=vx_*cosf(Mecanum_YawTheta)-vy_*sinf(Mecanum_YawTheta);
- vy=vx_*sinf(Mecanum_YawTheta)+vy_*cosf(Mecanum_YawTheta);//根据底盘云台相对角度修正xy轴速度
-
- /*==========小陀螺处理==========*/
- if(Yaw_GM6020PositionValue<4096)//正向小陀螺为逆时针
- {
- if((Remote_RxData.Remote_RS==2 ) || (Mecanum_GyroScopeFlag==1 && Mecanum_GyroScopeCloseFlag==1 && GM6020_MotorStatus[0].PositionYaw_GM6020PositionValue+100 || GM6020_MotorStatus[0].Angle2||GM6020_MotorStatus[0].Speed<-2)))//小陀螺关闭状态
- {
- PID_PositionSetOUTRange(&Mecanum_TrackPID,-2,2);
- PID_PositionCalc(&Mecanum_TrackPID,GM6020_MotorStatus[0].Position);//底盘跟云台GM6020_MotorStatus[0].Chassis_positive_direction
- //w = Mecanum_RGyroScopeAngularVelocity;
- w=-Mecanum_TrackPID.OUT;
- Mecanum_GyroScopeCloseFlag=0;//小陀螺未处于待关闭状态
- }
- else if(Remote_RxData.Remote_RS==1|| Remote_RxData.Remote_KeyPush_Ctrl==1)//反向小陀螺模式(仅检录使用)
- w=-Mecanum_LGyroScopeAngularVelocity;
- else
- {
- PID_PositionSetOUTRange(&Mecanum_TrackPID,-2,2);
- Mecanum_GyroScopeFlag=0;
- PID_PositionCalc(&Mecanum_TrackPID,GM6020_MotorStatus[0].Position);//底盘跟云台
- //w = Mecanum_RGyroScopeAngularVelocity;
- w=-Mecanum_TrackPID.OUT;
- }
- }
- else//正向小陀螺为顺时针
- {
- if((Remote_RxData.Remote_RS==2 || Remote_RxData.Remote_KeyPush_Ctrl==1) || (Mecanum_GyroScopeFlag==1 && Mecanum_GyroScopeCloseFlag==1 && GM6020_MotorStatus[0].Position>Yaw_GM6020PositionValue-500))//小陀螺模式
- {
- w=-Mecanum_LGyroScopeAngularVelocity;
- Mecanum_GyroScopeFlag=1;//处于小陀螺状态
- Mecanum_GyroScopeCloseFlag=1;//小陀螺处于待关闭状态
- }
- else if(Mecanum_GyroScopeFlag==1 && ((GM6020_MotorStatus[0].Angle>Yaw_GM6020PositionValue+5 || GM6020_MotorStatus[0].Angle1||GM6020_MotorStatus[0].Speed<-1)))//小陀螺关闭状态
- {
- PID_PositionSetOUTRange(&Mecanum_TrackPID,-2,2);
- PID_PositionCalc(&Mecanum_TrackPID,GM6020_MotorStatus[0].Position);//底盘跟云台
- //w = Mecanum_RGyroScopeAngularVelocity;
- w=-Mecanum_TrackPID.OUT;
- Mecanum_GyroScopeCloseFlag=0;//小陀螺未处于待关闭状态
- }
- else if(Remote_RxData.Remote_RS==1)//反向小陀螺模式(仅检录使用)
- w=Mecanum_LGyroScopeAngularVelocity;
- else
- {
- PID_PositionSetOUTRange(&Mecanum_TrackPID,-2,2);
- Mecanum_GyroScopeFlag=0;
- PID_PositionCalc(&Mecanum_TrackPID,GM6020_MotorStatus[0].Position);//底盘跟云台
- //w = Mecanum_RGyroScopeAngularVelocity;
- w=-Mecanum_TrackPID.OUT;
- }
- }
-
- /*==========功率上限处理==========*/
- /*由缓冲能量得到功率控制功率上限*/
- float Mecanum_PowerRef=1.0f/(60.0f-Mecanum_PowerControl_UseBuffer)*RefereeSystem_Buffer;//功率增益
- if(Mecanum_PowerRef>Mecanum_PowerControl_PowerMax)Mecanum_PowerRef=Mecanum_PowerControl_PowerMax;
- Mecanum_PowerLimit=Mecanum_PowerRef*RefereeSystem_Ref;
-
- /*由运动状态约束功率控制功率上限*/
- float Scale=sigma/660.0f;
- if(Scale<1 && Scale>0)Mecanum_PowerLimit*=Scale;//平移约束
- if(Mecanum_GyroScopeFlag==1)Mecanum_PowerLimit=Mecanum_PowerRef*RefereeSystem_Ref;//小陀螺约束
- if(Mecanum_PowerLimit>150.0f)Mecanum_PowerLimit=150.0f;//限幅约束
-
-
-
-
- /*由超电约束功率控制功率上限*/
- /*
- if(Remote_RxData.Remote_KeyPush_Shift==1)//开启超电
- {
- if(Mecanum_PowerLimit>0.0f)
- {
- if(Mecanum_PowerLimit2)GainCoefficient=2;//增益系数限上幅2
- }
- else if(Power_avg2)GainCoefficient=2;//增益系数限上幅2
- }
- else if(Power_avg>Mecanum_PowerLimit+5)
- {
- if(RefereeSystem_Buffer<60.0f-Mecanum_PowerControl_UseBuffer)GainCoefficient-=0.05f;//增益系数递增
- else GainCoefficient-=0.02f;//增益系数递增
- if(GainCoefficient10.0f)B=60.0f-Mecanum_PowerControl_UseBuffer-10.0f;
- else B=10.0f;
- if(RefereeSystem_Buffer>B)
- {
- float PowerScale=0;
- if(Mecanum_Power>C*Mecanum_PowerLimit)
- {
- if(Mecanum_Power>Mecanum_PowerLimit)PowerScale=0;
- else PowerScale=(Mecanum_PowerLimit-Mecanum_Power)/(Mecanum_PowerLimit-C*Mecanum_PowerLimit);
- }
- else PowerScale=1;
- Mecanum_CurrentLimit=Mecanum_BufferCurrent+Mecanum_PowerCurrent*PowerScale;
- }
- else
- {
- if(RefereeSystem_Buffer<5.0f)Mecanum_CurrentLimit=Mecanum_BufferCurrent*0.5f;
- else Mecanum_CurrentLimit=Mecanum_BufferCurrent*(RefereeSystem_Buffer+B-10.0f)/(2*B-10.0f);
- }
- if(Mecanum_CurrentLimit>16384*4)Mecanum_CurrentLimit=16384*4;
-
- /*==========运动控制==========*/
- vx*=GainCoefficient;vy*=GainCoefficient;
- if(Mecanum_GyroScopeFlag==1)w*=GainCoefficient;
- int16_t LeftFrontSpeed=(int16_t)((-vx-vy-w*(Mecanum_rx+Mecanum_ry)/100.0f)/Mecanum_WheelRadius*18143.663512f);//左前
- int16_t RightFrontSpeed=(int16_t)((vx-vy-w*(Mecanum_rx+Mecanum_ry)/100.0f)/Mecanum_WheelRadius*18143.663512f);//右前
- int16_t LeftRearSpeed=(int16_t)((-vx+vy-w*(Mecanum_rx+Mecanum_ry)/100.0f)/Mecanum_WheelRadius*18143.663512f);//左后
- int16_t RightRearSpeed=(int16_t)((vx+vy-w*(Mecanum_rx+Mecanum_ry)/100.0f)/Mecanum_WheelRadius*18143.663512f);//右后
-
- Mecanum_ControlSpeed(LeftFrontSpeed,RightFrontSpeed,LeftRearSpeed,RightRearSpeed);
-}
diff --git a/底盘/底盘-old/底盘/CarBody/Mecanum.h b/底盘/底盘-old/底盘/CarBody/Mecanum.h
deleted file mode 100644
index 4daec60..0000000
--- a/底盘/底盘-old/底盘/CarBody/Mecanum.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef __MECANUM_H
-#define __MECANUM_H
-
-#define Mecanum_LeftFrontWheel M3508_2//左前轮
-#define Mecanum_RightFrontWheel M3508_1//右前轮
-#define Mecanum_LeftRearWheel M3508_3//左后轮
-#define Mecanum_RightRearWheel M3508_4//右后轮
-
-extern float Mecanum_Power;//底盘功率(软件计算值)
-extern float Mecanum_YawTheta;//底盘云台相对偏航角度
-
-
-void Mecanum_Init(void);//麦轮初始化
-void Mecanum_CleanPID(void);//麦轮PID清理
-void Mecanum_ControlSpeed(int16_t LeftFrontSpeed,int16_t RightFrontSpeed,int16_t LeftRearSpeed,int16_t RightRearSpeed);//麦轮速度控制
-void Mecanum_InverseMotionControl(float v_x,float v_y,float w);//麦轮逆运动解算
-void Mecanum_PowerMoveControl(void);//麦轮功率控制
-
-#endif
diff --git a/底盘/底盘-old/底盘/CarBody/RefereeSystem.c b/底盘/底盘-old/底盘/CarBody/RefereeSystem.c
deleted file mode 100644
index 7368393..0000000
--- a/底盘/底盘-old/底盘/CarBody/RefereeSystem.c
+++ /dev/null
@@ -1,213 +0,0 @@
-#include "stm32f4xx.h" // Device header
-#include "stm32f4xx_conf.h"
-#include "RefereeSystem_CRCTable.h"
-#include "UART.h"
-
-/****************************************************************************************************
-
- 此处裁判系统只接收0x0201命令,获取机器人性能体系数据,主要获取发射机构是否上电
- 帧格式:
- 0xA5 0x0D 0x00 包序号 帧头CRC8校验 0x01 0x02 13ByteData 整包CRC16校验
- |___________________________________| |_______| |
- 帧头 命令码 数据
-
-****************************************************************************************************/
-
-/*接收数据缓冲区数组元素数=命令码对应数据段长度+9*/
-uint8_t RefereeSystem_RxHEXPacket1[22]={0xA5,0x0D,0x00,0x00,0x00,0x01,0x02,0};//裁判系统0x0201命令码接收数据缓冲区
-uint8_t RefereeSystem_RxHEXPacket2[25]={0xA5,0x10,0x00,0x00,0x00,0x02,0x02,0};//裁判系统0x0202命令码接收数据缓冲区
-
-uint8_t RefereeSystem_ShooterStatus=1;//发射机构状态,0-发射机构未上电,1-发射机构上电
-uint16_t RefereeSystem_Ref=80,RefereeSystem_Buffer=30.0f;//底盘功率上限,底盘功率缓冲能量(若无裁判系统,默认功率上限80W,缓冲能量30J)
-float RefereeSystem_Power;//底盘实时功率
-uint8_t RefereeSystem_RobotID=0;//机器人ID(无裁判系统时一直为0,4号步兵ID为4/104)
-
-/*
- *函数简介:裁判系统CRC8查表计算
- *参数说明:校验数据
- *参数说明:数据长度
- *参数说明:CRC初始值(默认给参数0xFF)
- *返回类型:无
- *备注:表格位于Referee System_CRCTable.h文件中CRC8_Table数组
- */
-uint8_t RefereeSystem_GetCRC8CheckSum(uint8_t *Data,uint16_t Length,uint8_t Initial)
-{
- uint8_t Minuend;
- while(Length--)
- {
- Minuend=Initial^(*Data);
- Data++;
- Initial=CRC8_Table[Minuend];
- }
- return Initial;
-}
-
-/*
- *函数简介:裁判系统CRC8校验
- *参数说明:校验数据(含尾端CRC校验码)
- *参数说明:数据长度
- *返回类型:校验正确返回1,否则返回0
- *备注:无
- */
-uint8_t RefereeSystem_VerifyCRC8CheckSum(uint8_t *Data,uint16_t Length)
-{
- uint8_t CRC8CheckSum=0;
- if((Data==0) || (Length<=2))return 0;//特殊情况处理
- CRC8CheckSum=RefereeSystem_GetCRC8CheckSum(Data,Length-1,CRC8_Initial);//获取CRC8计算值
- return CRC8CheckSum==Data[Length-1];//测量值与计算值相比较
-}
-
-/*
- *函数简介:裁判系统CRC16查表计算
- *参数说明:校验数据
- *参数说明:数据长度
- *参数说明:CRC初始值(默认给参数0xFFFF)
- *返回类型:无
- *备注:表格位于Referee System_CRCTable.h文件中CRC16_Table数组
- */
-uint16_t RefereeSystem_GetCRC16CheckSum(uint8_t *Data,uint32_t Length,uint16_t Initial)
-{
- uint8_t Minuend;
- while(Length--)
- {
- Minuend=*Data;
- Data++;
- Initial=((uint16_t)(Initial)>>8)^CRC16_Table[((uint16_t)(Initial)^(uint16_t)(Minuend))&0x00FF];
- }
- return Initial;
-}
-
-/*
- *函数简介:裁判系统CRC16校验
- *参数说明:校验数据(含尾端CRC校验码)
- *参数说明:数据长度
- *返回类型:校验正确返回1,否则返回0
- *备注:无
- */
-uint32_t RefereeSystem_VerifyCRC16CheckSum(uint8_t *Data, uint32_t Length)
-{
- uint16_t CRC16CheckSum=0;
- if((Data==0)||(Length<=2))return 0;//特殊情况处理
- CRC16CheckSum=RefereeSystem_GetCRC16CheckSum(Data,Length-2,CRC16_Initial);//获取CRC16计算值
- return ((CRC16CheckSum&0xFF)==Data[Length-2]&&((CRC16CheckSum>>8)&0xff)==Data[Length-1]);//测量值与计算值相比较
-}
-
-/*
- *函数简介:裁判系统接收初始化
- *参数说明:无
- *返回类型:无
- *备注:默认使用UART2(USART1)
- */
-void RefereeSystem_Init(void)
-{
- //UART2_Init();
- //while(RefereeSystem_RobotID==0);//等待裁判系统通讯建立
-}
-
-/*
- *函数简介:UART2串口中断接收裁判系统数据
- *参数说明:无
- *返回类型:无
- *备注:数据帧格式在最上方注释
- */
-
-// /*
-// void USART1_IRQHandler(void)
-// {
-
-// #define DataLength1 15//裁判系统0x0201命令码有效数据位数
-// #define DataLength2 18//裁判系统0x0202命令码有效数据位数
-
-// static int RxHEXState=0;//定义静态变量用于接收模式的选择
-// static int pRxHEXState=0;//定义静态变量用于充当计数器
-
-// uint8_t RefereeSystem_RxData;//裁判系统接收数据
-// int RefereeSystem_PowerRow;//底盘实时功率原始数据
-
-// if(USART_GetITStatus(USART1,USART_IT_RXNE)==SET)//查询接收中断标志位
-// {
-// USART_ClearITPendingBit(USART1,USART_IT_RXNE);//清除接收中断标志位
-
-// RefereeSystem_RxData=USART_ReceiveData(USART1);//将数据存入缓存区
-
-// /*=====检查帧头=====*/
-// if(RxHEXState==0){if(RefereeSystem_RxData==0xA5)RxHEXState=1;}
-
-// /*=====检查数据段长度,区分命令码=====*/
-// else if(RxHEXState==1)
-// {
-// if(RefereeSystem_RxData==0x0D)RxHEXState=2;//0x0201命令码
-// else if(RefereeSystem_RxData==0x10)RxHEXState=8;//0x0202命令码
-// else RxHEXState=0;//其他命令码直接跳过
-// }
-
-// /*=====0x0201命令码=====*/
-// /*=====检查帧头其他部分=====*/
-// else if(RxHEXState==2){if(RefereeSystem_RxData==0x00)RxHEXState=3;else RxHEXState=0;}
-// else if(RxHEXState==3){RefereeSystem_RxHEXPacket1[3]=RefereeSystem_RxData;RxHEXState=4;}
-// else if(RxHEXState==4)
-// {
-// RefereeSystem_RxHEXPacket1[4]=RefereeSystem_RxData;
-
-// if(RefereeSystem_VerifyCRC8CheckSum(RefereeSystem_RxHEXPacket1,5)==1)RxHEXState=5;//检查CRC8
-// else RxHEXState=0;
-// }
-
-// /*=====检查命令码=====*/
-// else if(RxHEXState==5){if(RefereeSystem_RxData==0x01)RxHEXState=6;else RxHEXState=0;}
-// else if(RxHEXState==6){if(RefereeSystem_RxData==0x02){RxHEXState=7;pRxHEXState=0;}else RxHEXState=0;}
-
-// /*=====接收有效数据=====*/
-// else if(RxHEXState==7)
-// {
-// RefereeSystem_RxHEXPacket1[pRxHEXState+7]=RefereeSystem_RxData;//接收数据
-// pRxHEXState++;
-
-// if(pRxHEXState>=DataLength1)
-// {
-// if(RefereeSystem_VerifyCRC16CheckSum(RefereeSystem_RxHEXPacket1,22)==1)//CRC校验
-// {
-// RefereeSystem_RobotID=RefereeSystem_RxHEXPacket1[7];//获取机器人ID
-// RefereeSystem_ShooterStatus=(RefereeSystem_RxHEXPacket1[19]&0x04)>>2;//获取发射机构状态
-// RefereeSystem_Ref=RefereeSystem_RxHEXPacket1[17]|((uint16_t)RefereeSystem_RxHEXPacket1[18]<<8);//获取功率上限
-// }
-// RxHEXState=0;
-// }
-// }
-
-
-// /*=====0x0202命令码=====*/
-// /*=====检查帧头其他部分=====*/
-// else if(RxHEXState==8){if(RefereeSystem_RxData==0x00)RxHEXState=9;else RxHEXState=0;}
-// else if(RxHEXState==9){RefereeSystem_RxHEXPacket2[3]=RefereeSystem_RxData;RxHEXState=10;}
-// else if(RxHEXState==10)
-// {
-// RefereeSystem_RxHEXPacket2[4]=RefereeSystem_RxData;
-// if(RefereeSystem_VerifyCRC8CheckSum(RefereeSystem_RxHEXPacket2,5)==1)RxHEXState=11;
-// else RxHEXState=0;
-// }
-
-// /*=====检查命令码=====*/
-// else if(RxHEXState==11){if(RefereeSystem_RxData==0x02)RxHEXState=12;else RxHEXState=0;}
-// else if(RxHEXState==12){if(RefereeSystem_RxData==0x02){RxHEXState=13;pRxHEXState=0;}else RxHEXState=0;}
-
-// /*=====接收有效数据=====*/
-// else if(RxHEXState==13)
-// {
-// RefereeSystem_RxHEXPacket2[pRxHEXState+7]=RefereeSystem_RxData;//接收数据
-// pRxHEXState++;
-
-// if(pRxHEXState>=DataLength2)
-// {
-// if(RefereeSystem_VerifyCRC16CheckSum(RefereeSystem_RxHEXPacket2,25)==1)//CRC校验
-// {
-// RefereeSystem_Buffer=RefereeSystem_RxHEXPacket2[15]|((uint16_t)RefereeSystem_RxHEXPacket2[16]<<8);//获取缓冲能量
-// RefereeSystem_PowerRow=(int32_t)((uint32_t)RefereeSystem_RxHEXPacket2[11]|((uint32_t)RefereeSystem_RxHEXPacket2[12]<<8)|((uint32_t)RefereeSystem_RxHEXPacket2[13]<<16)|((uint32_t)RefereeSystem_RxHEXPacket2[14]<<24));
-// RefereeSystem_Power=*((float *)(&RefereeSystem_PowerRow));//获取底盘实时功率
-// }
-// RxHEXState=0;
-// }
-// }
-// }
-// }
-// */
\ No newline at end of file
diff --git a/底盘/底盘-old/底盘/CarBody/RefereeSystem.h b/底盘/底盘-old/底盘/CarBody/RefereeSystem.h
deleted file mode 100644
index cef8d57..0000000
--- a/底盘/底盘-old/底盘/CarBody/RefereeSystem.h
+++ /dev/null
@@ -1,66 +0,0 @@
-#ifndef __REFEREESYSTEM_H
-#define __REFEREESYSTEM_H
-
-typedef struct
-{
- /**
- * @brief robot id
- * 0: robot none
- * 1: red hero
- * 2: red engineer
- * 3/4/5: red infantry
- * 6: red aerial
- * 7: red sentry
- * 8: red dart
- * 9: red radar station
- * 101: blue hero
- * 102: blue engineer
- * 103/104/105: blue infantry
- * 106: blue aerial
- * 107: blue sentry
- * 108: blue dart
- * 109: blue radar station
- */
- uint8_t robot_id;
- uint8_t robot_level;
- uint16_t current_HP;
- uint16_t maximum_HP;
-
- uint16_t shooter_barrel_cooling_value;
- uint16_t shooter_barrel_heat_limit;
- uint16_t chassis_power_limit;
-
- uint8_t mains_power_gimbal_output : 1;
- uint8_t mains_power_chassis_output : 1;
- uint8_t mains_power_shooter_output : 1;
-} robot_status_t;
-
-typedef struct
-{
- uint8_t Index;
- uint16_t DataLength;
- robot_status_t robot_status;
-
-}Referee_System_Info_TypeDef;
-
-
-typedef struct
-{
- uint8_t SOF; /*!< Data frame start byte, fixed value is 0xA5 */
- uint16_t Data_Length; /*!< the length of data in the data frame */
- uint8_t Seq; /*!< package serial number */
- uint8_t CRC8; /*!< Frame header CRC8 checksum */
-}FrameHeader_TypeDef;
-
-
-extern uint8_t RefereeSystem_ShooterStatus;//发射机构状态,0-发射机构未上电,1-发射机构上电
-extern uint16_t RefereeSystem_Ref,RefereeSystem_Buffer;//底盘功率上限,底盘功率缓冲能量
-extern float RefereeSystem_Power;//底盘实时功率
-extern uint8_t RefereeSystem_RobotID;//机器人ID
-
-uint8_t RefereeSystem_GetCRC8CheckSum(uint8_t *Data,uint16_t Length,uint8_t Initial);//裁判系统CRC8查表计算
-uint16_t RefereeSystem_GetCRC16CheckSum(uint8_t *Data,uint32_t Length,uint16_t Initial);//裁判系统CRC16查表计算
-void RefereeSystem_Init(void);//裁判系统接收初始化
-void HandPowercontrol();
-
-#endif
diff --git a/底盘/底盘-old/底盘/CarBody/RefereeSystem_CRCTable.c b/底盘/底盘-old/底盘/CarBody/RefereeSystem_CRCTable.c
deleted file mode 100644
index 877cfb3..0000000
--- a/底盘/底盘-old/底盘/CarBody/RefereeSystem_CRCTable.c
+++ /dev/null
@@ -1,46 +0,0 @@
-#include "stm32f4xx.h" // Device header
-#include "stm32f4xx_conf.h"
-
-//crc8 generator polynomial:G(x)=x8+x5+x4+1//CRC8-MAXIM
-uint8_t CRC8_Initial=0xFF;//CRC8初始值
-const uint8_t CRC8_Table[256]=
-{
- 0x00,0x5E,0xBC,0xE2,0x61,0x3F,0xDD,0x83,0xC2,0x9C,0x7E,0x20,0xA3,0xFD,0x1F,0x41,
- 0x9D,0xC3,0x21,0x7F,0xFC,0xA2,0x40,0x1E,0x5F,0x01,0xE3,0xBD,0x3E,0x60,0x82,0xDC,
- 0x23,0x7D,0x9F,0xC1,0x42,0x1C,0xFE,0xA0,0xE1,0xBF,0x5D,0x03,0x80,0xDE,0x3C,0x62,
- 0xBE,0xE0,0x02,0x5C,0xDF,0x81,0x63,0x3D,0x7C,0x22,0xC0,0x9E,0x1D,0x43,0xA1,0xFF,
- 0x46,0x18,0xFA,0xA4,0x27,0x79,0x9B,0xC5,0x84,0xDA,0x38,0x66,0xE5,0xBB,0x59,0x07,
- 0xDB,0x85,0x67,0x39,0xBA,0xE4,0x06,0x58,0x19,0x47,0xA5,0xFB,0x78,0x26,0xC4,0x9A,
- 0x65,0x3B,0xD9,0x87,0x04,0x5A,0xB8,0xE6,0xA7,0xF9,0x1B,0x45,0xC6,0x98,0x7A,0x24,
- 0xF8,0xA6,0x44,0x1A,0x99,0xC7,0x25,0x7B,0x3A,0x64,0x86,0xD8,0x5B,0x05,0xE7,0xB9,
- 0x8C,0xD2,0x30,0x6E,0xED,0xB3,0x51,0x0F,0x4E,0x10,0xF2,0xAC,0x2F,0x71,0x93,0xCD,
- 0x11,0x4F,0xAD,0xF3,0x70,0x2E,0xCC,0x92,0xD3,0x8D,0x6F,0x31,0xB2,0xEC,0x0E,0x50,
- 0xAF,0xF1,0x13,0x4D,0xCE,0x90,0x72,0x2C,0x6D,0x33,0xD1,0x8F,0x0C,0x52,0xB0,0xEE,
- 0x32,0x6C,0x8E,0xD0,0x53,0x0D,0xEF,0xB1,0xF0,0xAE,0x4C,0x12,0x91,0xCF,0x2D,0x73,
- 0xCA,0x94,0x76,0x28,0xAB,0xF5,0x17,0x49,0x08,0x56,0xB4,0xEA,0x69,0x37,0xD5,0x8B,
- 0x57,0x09,0xEB,0xB5,0x36,0x68,0x8A,0xD4,0x95,0xCB,0x29,0x77,0xF4,0xAA,0x48,0x16,
- 0xE9,0xB7,0x55,0x0B,0x88,0xD6,0x34,0x6A,0x2B,0x75,0x97,0xC9,0x4A,0x14,0xF6,0xA8,
- 0x74,0x2A,0xC8,0x96,0x15,0x4B,0xA9,0xF7,0xB6,0xE8,0x0A,0x54,0xD7,0x89,0x6B,0x35
-};
-
-//crc16 generator polynomial:G(x)=x16+x12+x5+1//CRC16-CCITT
-uint16_t CRC16_Initial=0xFFFF;//CRC16初始值
-const uint16_t CRC16_Table[256]=
-{
- 0x0000,0x1189,0x2312,0x329B,0x4624,0x57AD,0x6536,0x74BF,0x8C48,0x9DC1,0xAF5A,0xBED3,0xCA6C,0xDBE5,0xE97E,0xF8F7,
- 0x1081,0x0108,0x3393,0x221A,0x56A5,0x472C,0x75B7,0x643E,0x9CC9,0x8D40,0xBFDB,0xAE52,0xDAED,0xCB64,0xF9FF,0xE876,
- 0x2102,0x308B,0x0210,0x1399,0x6726,0x76AF,0x4434,0x55BD,0xAD4A,0xBCC3,0x8E58,0x9FD1,0xEB6E,0xFAE7,0xC87C,0xD9F5,
- 0x3183,0x200A,0x1291,0x0318,0x77A7,0x662E,0x54B5,0x453C,0xBDCB,0xAC42,0x9ED9,0x8F50,0xFBEF,0xEA66,0xD8FD,0xC974,
- 0x4204,0x538D,0x6116,0x709F,0x0420,0x15A9,0x2732,0x36BB,0xCE4C,0xDFC5,0xED5E,0xFCD7,0x8868,0x99E1,0xAB7A,0xBAF3,
- 0x5285,0x430C,0x7197,0x601E,0x14A1,0x0528,0x37B3,0x263A,0xDECD,0xCF44,0xFDDF,0xEC56,0x98E9,0x8960,0xBBFB,0xAA72,
- 0x6306,0x728F,0x4014,0x519D,0x2522,0x34AB,0x0630,0x17B9,0xEF4E,0xFEC7,0xCC5C,0xDDD5,0xA96A,0xB8E3,0x8A78,0x9BF1,
- 0x7387,0x620E,0x5095,0x411C,0x35A3,0x242A,0x16B1,0x0738,0xFFCF,0xEE46,0xDCDD,0xCD54,0xB9EB,0xA862,0x9AF9,0x8B70,
- 0x8408,0x9581,0xA71A,0xB693,0xC22C,0xD3A5,0xE13E,0xF0B7,0x0840,0x19C9,0x2B52,0x3ADB,0x4E64,0x5FED,0x6D76,0x7CFF,
- 0x9489,0x8500,0xB79B,0xA612,0xD2AD,0xC324,0xF1BF,0xE036,0x18C1,0x0948,0x3BD3,0x2A5A,0x5EE5,0x4F6C,0x7DF7,0x6C7E,
- 0xA50A,0xB483,0x8618,0x9791,0xE32E,0xF2A7,0xC03C,0xD1B5,0x2942,0x38CB,0x0A50,0x1BD9,0x6F66,0x7EEF,0x4C74,0x5DFD,
- 0xB58B,0xA402,0x9699,0x8710,0xF3AF,0xE226,0xD0BD,0xC134,0x39C3,0x284A,0x1AD1,0x0B58,0x7FE7,0x6E6E,0x5CF5,0x4D7C,
- 0xC60C,0xD785,0xE51E,0xF497,0x8028,0x91A1,0xA33A,0xB2B3,0x4A44,0x5BCD,0x6956,0x78DF,0x0C60,0x1DE9,0x2F72,0x3EFB,
- 0xD68D,0xC704,0xF59F,0xE416,0x90A9,0x8120,0xB3BB,0xA232,0x5AC5,0x4B4C,0x79D7,0x685E,0x1CE1,0x0D68,0x3FF3,0x2E7A,
- 0xE70E,0xF687,0xC41C,0xD595,0xA12A,0xB0A3,0x8238,0x93B1,0x6B46,0x7ACF,0x4854,0x59DD,0x2D62,0x3CEB,0x0E70,0x1FF9,
- 0xF78F,0xE606,0xD49D,0xC514,0xB1AB,0xA022,0x92B9,0x8330,0x7BC7,0x6A4E,0x58D5,0x495C,0x3DE3,0x2C6A,0x1EF1,0x0F78
-};
diff --git a/底盘/底盘-old/底盘/CarBody/RefereeSystem_CRCTable.h b/底盘/底盘-old/底盘/CarBody/RefereeSystem_CRCTable.h
deleted file mode 100644
index 69e1eb6..0000000
--- a/底盘/底盘-old/底盘/CarBody/RefereeSystem_CRCTable.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef __REFEREESYSTEM_CRCTABLE_H
-#define __REFEREESYSTEM_CRCTABLE_H
-
-//crc8 generator polynomial:G(x)=x8+x5+x4+1//CRC8-MAXIM
-extern uint8_t CRC8_Initial;//CRC8初始值
-extern const uint8_t CRC8_Table[256];
-
-//crc16 generator polynomial:G(x)=x16+x12+x5+1//CRC16-CCITT
-extern uint16_t CRC16_Initial;//CRC16初始值
-extern const uint16_t CRC16_Table[256];
-
-#endif
diff --git a/底盘/底盘-old/底盘/CarBody/UI.c b/底盘/底盘-old/底盘/CarBody/UI.c
deleted file mode 100644
index b34d023..0000000
--- a/底盘/底盘-old/底盘/CarBody/UI.c
+++ /dev/null
@@ -1,68 +0,0 @@
-#include "stm32f4xx.h" // Device header
-#include "stm32f4xx_conf.h"
-#include "UI_Library.h"
-#include "Remote.h"
-#include "CloseLoopControl.h"
-#include "Delay.h"
-#include "RefereeSystem.h"
-
-/*
- *函数简介:UI初始化
- *参数说明:无
- *返回类型:无
- *备注:无
- */
-void UI_Init(void)
-{
- _ui_init_default_Ungroup_1();
- Delay_ms(100);
- _ui_init_default_Ungroup_0();
- Delay_ms(100);
- _ui_init_default_Ungroup_2();
- Delay_ms(100);
- _ui_init_default_Ungroup_1();
- Delay_ms(100);
-}
-
-/*
- *函数简介:UI更新
- *参数说明:无
- *返回类型:无
- *备注:无
- */
-void UI_Updata(void)
-{
- static uint8_t Count=0;
- Count=(Count+1)%2;//每次更新一个,循环更新提高效率
-
- if(CloseLoopControl_ErrorFlag==1)//遥控器未连接,所有指示灯变绿
- {
- CloseLoopControl_ErrorFlag=0;
- _ui_update_default_Ungroup_2_NOCheck();
- }
- else
- {
- if(Count==0)//更新Shift
- {
- if(Remote_RxData.Remote_KeyPush_Shift==1)_ui_update_default_Ungroup_2_Shift_Open();
- else _ui_update_default_Ungroup_2_Shift_Close();
- }
- else//更新Ctrl
- {
- if(Remote_RxData.Remote_KeyPush_Ctrl==1)_ui_update_default_Ungroup_2_Ctrl_Open();
- else _ui_update_default_Ungroup_2_Ctrl_Close();
- }
- }
-}
-
-/*
- *函数简介:UI显示遥控器未连接
- *参数说明:无
- *返回类型:无
- *备注:所有指示灯变绿
- */
-void UI_RemoteNoCheck(void)
-{
- if(CloseLoopControl_ErrorFlag==1)CloseLoopControl_ErrorFlag=0;
- _ui_update_default_Ungroup_2_NOCheck();
-}
diff --git a/底盘/底盘-old/底盘/CarBody/UI.h b/底盘/底盘-old/底盘/CarBody/UI.h
deleted file mode 100644
index 6d79553..0000000
--- a/底盘/底盘-old/底盘/CarBody/UI.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef __UI_H
-#define __UI_H
-
-void UI_Init(void);//UI初始化
-void UI_Updata(void);//UI更新
-void UI_RemoteNoCheck(void);//UI显示遥控器未连接
-
-#endif
diff --git a/底盘/底盘-old/底盘/CarBody/UI_Base.c b/底盘/底盘-old/底盘/CarBody/UI_Base.c
deleted file mode 100644
index ee1cce4..0000000
--- a/底盘/底盘-old/底盘/CarBody/UI_Base.c
+++ /dev/null
@@ -1,41 +0,0 @@
-#include "stm32f4xx.h" // Device header
-#include "stm32f4xx_conf.h"
-#include "UI_Base.h"
-#include
-#include "RefereeSystem.h"
-#include "RefereeSystem_CRCTable.h"
-
-uint8_t UI_seq=0;
-
-#define DEFINE_FRAME_PROC(num,id) \
-void ui_proc_##num##_frame(ui_##num##_frame_t *msg) \
-{ \
- msg->header.SOF=0xA5; \
- msg->header.data_length=6+15*num; \
- msg->header.seq=UI_seq++; \
- msg->header.CRC8=RefereeSystem_GetCRC8CheckSum((uint8_t*)msg,4,CRC8_Initial); \
- msg->header.cmd_id=0x0301; \
- msg->header.dada_cmd_id=id; \
- msg->header.sender_id=RefereeSystem_RobotID; \
- msg->header.receiver_id=RefereeSystem_RobotID+256; \
- msg->CRC16=RefereeSystem_GetCRC16CheckSum((uint8_t*)msg,13+15*num,CRC16_Initial); \
-}
-
-DEFINE_FRAME_PROC(1,0x0101)
-DEFINE_FRAME_PROC(2,0x0102)
-DEFINE_FRAME_PROC(5,0x0103)
-DEFINE_FRAME_PROC(7,0x0104)
-
-void ui_proc_string_frame(ui_string_frame_t *msg)
-{
- msg->header.SOF=0xA5;
- msg->header.data_length=51;
- msg->header.seq=UI_seq++;
- msg->header.CRC8=RefereeSystem_GetCRC8CheckSum((uint8_t*)msg,4,CRC8_Initial);
- msg->header.cmd_id=0x0301;
- msg->header.dada_cmd_id=0x0110;
- msg->header.sender_id=RefereeSystem_RobotID;
- msg->header.receiver_id=RefereeSystem_RobotID+256;
- msg->option.str_length=strlen(msg->option.string);
- msg->CRC16=RefereeSystem_GetCRC16CheckSum((uint8_t *)msg,58,CRC16_Initial);
-}
diff --git a/底盘/底盘-old/底盘/CarBody/UI_Base.h b/底盘/底盘-old/底盘/CarBody/UI_Base.h
deleted file mode 100644
index 25f4390..0000000
--- a/底盘/底盘-old/底盘/CarBody/UI_Base.h
+++ /dev/null
@@ -1,103 +0,0 @@
-#ifndef __UI_BASE_H
-#define __UI_BASE_H
-
-#define PRIMITIVE_CAT(x, y) x##y
-#define MESSAGE_PACKED __attribute__((packed))
-
-#define DEFINE_MESSAGE(name,p_a,p_b,p_c,p_d,p_e) \
-typedef struct \
-{ \
-uint8_t figure_name[3]; \
-uint32_t operate_tpye:3; \
-uint32_t figure_tpye:3; \
-uint32_t layer:4; \
-uint32_t color:4; \
-uint32_t PRIMITIVE_CAT(details_,p_a):9; \
-uint32_t PRIMITIVE_CAT(details_,p_b):9; \
-uint32_t width:10; \
-uint32_t start_x:11; \
-uint32_t start_y:11; \
-uint32_t PRIMITIVE_CAT(details_,p_c):10; \
-uint32_t PRIMITIVE_CAT(details_,p_d):11; \
-uint32_t PRIMITIVE_CAT(details_,p_e):11; \
-}MESSAGE_PACKED ui_interface_##name##_t
-
-DEFINE_MESSAGE(figure,_a,_b,_c,_d,_e);
-DEFINE_MESSAGE(line,_a,_b,_c,end_x,end_y);
-DEFINE_MESSAGE(rect,_a,_b,_c,end_x,end_y);
-DEFINE_MESSAGE(round,_a,_b,r,_d,_e);
-DEFINE_MESSAGE(ellipse,_a,_b,_c,rx,ry);
-DEFINE_MESSAGE(arc,start_angle,end_angle,_c,rx,ry);
-
-typedef struct
-{
- uint8_t figure_name[3];
- uint32_t operate_tpye:3;
- uint32_t figure_tpye:3;
- uint32_t layer:4;
- uint32_t color:4;
- uint32_t font_size:9;
- uint32_t _b:9;
- uint32_t width:10;
- uint32_t start_x:11;
- uint32_t start_y:11;
- int32_t number;
-}MESSAGE_PACKED ui_interface_number_t;
-
-typedef struct
-{
- uint8_t figure_name[3];
- uint32_t operate_tpye:3;
- uint32_t figure_tpye:3;
- uint32_t layer:4;
- uint32_t color:4;
- uint32_t font_size:9;
- uint32_t str_length:9;
- uint32_t width:10;
- uint32_t start_x:11;
- uint32_t start_y:11;
- uint32_t _c:10;
- uint32_t _d:11;
- uint32_t _e:11;
- char string[30];
-}MESSAGE_PACKED ui_interface_string_t;
-
-typedef struct
-{
- uint8_t SOF;
- uint16_t data_length;
- uint8_t seq;
- uint8_t CRC8;
- uint16_t cmd_id;
- uint16_t dada_cmd_id;
- uint16_t sender_id;
- uint16_t receiver_id;
-}MESSAGE_PACKED ui_frame_header_t;
-
-#define DEFINE_FIGURE_MESSAGE(num) \
-typedef struct \
-{ \
- ui_frame_header_t header; \
- ui_interface_figure_t data[num]; \
- uint16_t CRC16; \
-}MESSAGE_PACKED ui_##num##_frame_t
-
-DEFINE_FIGURE_MESSAGE(1);
-DEFINE_FIGURE_MESSAGE(2);
-DEFINE_FIGURE_MESSAGE(5);
-DEFINE_FIGURE_MESSAGE(7);
-
-typedef struct
-{
- ui_frame_header_t header;
- ui_interface_string_t option;
- uint16_t CRC16;
-}MESSAGE_PACKED ui_string_frame_t;
-
-void ui_proc_1_frame(ui_1_frame_t *msg);
-void ui_proc_2_frame(ui_2_frame_t *msg);
-void ui_proc_5_frame(ui_5_frame_t *msg);
-void ui_proc_7_frame(ui_7_frame_t *msg);
-void ui_proc_string_frame(ui_string_frame_t *msg);
-
-#endif
diff --git a/底盘/底盘-old/底盘/CarBody/UI_Library.c b/底盘/底盘-old/底盘/CarBody/UI_Library.c
deleted file mode 100644
index 79e7e81..0000000
--- a/底盘/底盘-old/底盘/CarBody/UI_Library.c
+++ /dev/null
@@ -1,222 +0,0 @@
-#include "stm32f4xx.h" // Device header
-#include "stm32f4xx_conf.h"
-#include "UI_Base.h"
-#include
-#include "UART.h"
-
-/*==========Shift文本==========*/
-ui_string_frame_t ui_default_Ungroup_0;
-ui_interface_string_t* ui_default_Ungroup_Text_Shift=&ui_default_Ungroup_0.option;
-
-void _ui_init_default_Ungroup_0(void)
-{
- ui_default_Ungroup_0.option.figure_name[0]=0;
- ui_default_Ungroup_0.option.figure_name[1]=0;
- ui_default_Ungroup_0.option.figure_name[2]=0;
- ui_default_Ungroup_0.option.operate_tpye=1;
- ui_default_Ungroup_0.option.figure_tpye=7;
- ui_default_Ungroup_0.option.layer=0;
- ui_default_Ungroup_0.option.font_size=30;
- ui_default_Ungroup_0.option.start_x=75;
- ui_default_Ungroup_0.option.start_y=850;
- ui_default_Ungroup_0.option.color=2;
- ui_default_Ungroup_0.option.str_length=5;
- ui_default_Ungroup_0.option.width=6;
- strcpy(ui_default_Ungroup_Text_Shift->string, "Shift");
-
- ui_proc_string_frame(&ui_default_Ungroup_0);
- UART1_SendArray((uint8_t *)&ui_default_Ungroup_0,sizeof(ui_default_Ungroup_0));
-}
-
-void _ui_update_default_Ungroup_0(void)
-{
- ui_default_Ungroup_0.option.operate_tpye=2;
-
- ui_proc_string_frame(&ui_default_Ungroup_0);
- UART1_SendArray((uint8_t *)&ui_default_Ungroup_0,sizeof(ui_default_Ungroup_0));
-}
-
-void _ui_remove_default_Ungroup_0(void)
-{
- ui_default_Ungroup_0.option.operate_tpye=3;
-
- ui_proc_string_frame(&ui_default_Ungroup_0);
- UART1_SendArray((uint8_t *)&ui_default_Ungroup_0,sizeof(ui_default_Ungroup_0));
-}
-
-/*==========Ctrl文本==========*/
-ui_string_frame_t ui_default_Ungroup_1;
-ui_interface_string_t* ui_default_Ungroup_Text_Ctrl=&ui_default_Ungroup_1.option;
-
-void _ui_init_default_Ungroup_1(void)
-{
- ui_default_Ungroup_1.option.figure_name[0]=0;
- ui_default_Ungroup_1.option.figure_name[1]=0;
- ui_default_Ungroup_1.option.figure_name[2]=1;
- ui_default_Ungroup_1.option.operate_tpye=1;
- ui_default_Ungroup_1.option.figure_tpye=7;
- ui_default_Ungroup_1.option.layer=0;
- ui_default_Ungroup_1.option.font_size=30;
- ui_default_Ungroup_1.option.start_x=75;
- ui_default_Ungroup_1.option.start_y=750;
- ui_default_Ungroup_1.option.color=2;
- ui_default_Ungroup_1.option.str_length=4;
- ui_default_Ungroup_1.option.width=6;
- strcpy(ui_default_Ungroup_Text_Ctrl->string,"Ctrl");
-
- ui_proc_string_frame(&ui_default_Ungroup_1);
- UART1_SendArray((uint8_t *)&ui_default_Ungroup_1,sizeof(ui_default_Ungroup_1));
-}
-
-void _ui_update_default_Ungroup_1(void)
-{
- ui_default_Ungroup_1.option.operate_tpye=2;
-
- ui_proc_string_frame(&ui_default_Ungroup_1);
- UART2_SendArray((uint8_t *)&ui_default_Ungroup_1,sizeof(ui_default_Ungroup_1));
-}
-
-void _ui_remove_default_Ungroup_1(void)
-{
- ui_default_Ungroup_1.option.operate_tpye=3;
-
- ui_proc_string_frame(&ui_default_Ungroup_1);
- UART1_SendArray((uint8_t *)&ui_default_Ungroup_1,sizeof(ui_default_Ungroup_1));
-}
-
-/*==========指示灯==========*/
-ui_2_frame_t ui_default_Ungroup_2;
-ui_interface_round_t *ui_default_Ungroup_Round_Shift=(ui_interface_round_t *)&(ui_default_Ungroup_2.data[0]);
-ui_interface_round_t *ui_default_Ungroup_Round_Ctrl=(ui_interface_round_t *)&(ui_default_Ungroup_2.data[1]);
-
-void _ui_init_default_Ungroup_2(void)
-{
- for(int i=0;i<2;i++)
- {
- ui_default_Ungroup_2.data[i].figure_name[0]=0;
- ui_default_Ungroup_2.data[i].figure_name[1]=0;
- ui_default_Ungroup_2.data[i].figure_name[2]=i+2;
- ui_default_Ungroup_2.data[i].operate_tpye=1;
- }
-
- ui_default_Ungroup_Round_Shift->figure_tpye=2;
- ui_default_Ungroup_Round_Shift->layer=0;
- ui_default_Ungroup_Round_Shift->details_r=20;
- ui_default_Ungroup_Round_Shift->start_x=250;
- ui_default_Ungroup_Round_Shift->start_y=835;
- ui_default_Ungroup_Round_Shift->color=2;
- ui_default_Ungroup_Round_Shift->width=2;
-
- ui_default_Ungroup_Round_Ctrl->figure_tpye=2;
- ui_default_Ungroup_Round_Ctrl->layer=0;
- ui_default_Ungroup_Round_Ctrl->details_r=20;
- ui_default_Ungroup_Round_Ctrl->start_x=250;
- ui_default_Ungroup_Round_Ctrl->start_y=735;
- ui_default_Ungroup_Round_Ctrl->color=2;
- ui_default_Ungroup_Round_Ctrl->width=2;
-
- ui_proc_2_frame(&ui_default_Ungroup_2);
- UART1_SendArray((uint8_t *)&ui_default_Ungroup_2,sizeof(ui_default_Ungroup_2));
-}
-
-void _ui_update_default_Ungroup_2_ERROR(void)
-{
- ui_default_Ungroup_2.data[0].operate_tpye=2;
- ui_default_Ungroup_2.data[1].operate_tpye=2;
-
- ui_default_Ungroup_Round_Shift->details_r=10;
- ui_default_Ungroup_Round_Shift->start_x=240;
- ui_default_Ungroup_Round_Shift->start_y=825;
- ui_default_Ungroup_Round_Shift->color=0;
- ui_default_Ungroup_Round_Shift->width=20;
-
- ui_default_Ungroup_Round_Ctrl->details_r=10;
- ui_default_Ungroup_Round_Ctrl->start_x=240;
- ui_default_Ungroup_Round_Ctrl->start_y=725;
- ui_default_Ungroup_Round_Ctrl->color=0;
- ui_default_Ungroup_Round_Ctrl->width=20;
-
- ui_proc_2_frame(&ui_default_Ungroup_2);
- UART1_SendArray((uint8_t *)&ui_default_Ungroup_2,sizeof(ui_default_Ungroup_2));
-}
-
-void _ui_update_default_Ungroup_2_NOCheck(void)
-{
- ui_default_Ungroup_2.data[0].operate_tpye=2;
- ui_default_Ungroup_2.data[1].operate_tpye=2;
-
- ui_default_Ungroup_Round_Shift->details_r=20;
- ui_default_Ungroup_Round_Shift->start_x=250;
- ui_default_Ungroup_Round_Shift->start_y=835;
- ui_default_Ungroup_Round_Shift->color=2;
- ui_default_Ungroup_Round_Shift->width=2;
-
- ui_default_Ungroup_Round_Ctrl->details_r=20;
- ui_default_Ungroup_Round_Ctrl->start_x=250;
- ui_default_Ungroup_Round_Ctrl->start_y=735;
- ui_default_Ungroup_Round_Ctrl->color=2;
- ui_default_Ungroup_Round_Ctrl->width=2;
-
- ui_proc_2_frame(&ui_default_Ungroup_2);
- UART1_SendArray((uint8_t *)&ui_default_Ungroup_2,sizeof(ui_default_Ungroup_2));
-}
-
-void _ui_update_default_Ungroup_2_Shift_Open(void)
-{
- ui_default_Ungroup_2.data[0].operate_tpye=2;
- ui_default_Ungroup_2.data[1].operate_tpye=0;
-
- ui_default_Ungroup_Round_Shift->details_r=10;
- ui_default_Ungroup_Round_Shift->start_x=250;
- ui_default_Ungroup_Round_Shift->start_y=835;
- ui_default_Ungroup_Round_Shift->color=2;
- ui_default_Ungroup_Round_Shift->width=20;
-
- ui_proc_2_frame(&ui_default_Ungroup_2);
- UART1_SendArray((uint8_t *)&ui_default_Ungroup_2,sizeof(ui_default_Ungroup_2));
-}
-
-void _ui_update_default_Ungroup_2_Shift_Close(void)
-{
- ui_default_Ungroup_2.data[0].operate_tpye=2;
- ui_default_Ungroup_2.data[1].operate_tpye=0;
-
- ui_default_Ungroup_Round_Shift->details_r=20;
- ui_default_Ungroup_Round_Shift->start_x=250;
- ui_default_Ungroup_Round_Shift->start_y=835;
- ui_default_Ungroup_Round_Shift->color=2;
- ui_default_Ungroup_Round_Shift->width=2;
-
- ui_proc_2_frame(&ui_default_Ungroup_2);
- UART1_SendArray((uint8_t *)&ui_default_Ungroup_2,sizeof(ui_default_Ungroup_2));
-}
-
-void _ui_update_default_Ungroup_2_Ctrl_Open(void)
-{
- ui_default_Ungroup_2.data[0].operate_tpye=0;
- ui_default_Ungroup_2.data[1].operate_tpye=2;
-
- ui_default_Ungroup_Round_Ctrl->details_r=10;
- ui_default_Ungroup_Round_Ctrl->start_x=250;
- ui_default_Ungroup_Round_Ctrl->start_y=735;
- ui_default_Ungroup_Round_Ctrl->color=2;
- ui_default_Ungroup_Round_Ctrl->width=20;
-
- ui_proc_2_frame(&ui_default_Ungroup_2);
- UART1_SendArray((uint8_t *)&ui_default_Ungroup_2,sizeof(ui_default_Ungroup_2));
-}
-
-void _ui_update_default_Ungroup_2_Ctrl_Close(void)
-{
- ui_default_Ungroup_2.data[0].operate_tpye=0;
- ui_default_Ungroup_2.data[1].operate_tpye=2;
-
- ui_default_Ungroup_Round_Ctrl->details_r=20;
- ui_default_Ungroup_Round_Ctrl->start_x=250;
- ui_default_Ungroup_Round_Ctrl->start_y=735;
- ui_default_Ungroup_Round_Ctrl->color=2;
- ui_default_Ungroup_Round_Ctrl->width=2;
-
- ui_proc_2_frame(&ui_default_Ungroup_2);
- UART1_SendArray((uint8_t *)&ui_default_Ungroup_2,sizeof(ui_default_Ungroup_2));
-}
diff --git a/底盘/底盘-old/底盘/CarBody/UI_Library.h b/底盘/底盘-old/底盘/CarBody/UI_Library.h
deleted file mode 100644
index cdf2066..0000000
--- a/底盘/底盘-old/底盘/CarBody/UI_Library.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef __UI_LIBRARY_H
-#define __UI_LIBRARY_H
-
-/*==========Shift文本==========*/
-void _ui_init_default_Ungroup_0(void);
-void _ui_update_default_Ungroup_0(void);
-void _ui_remove_default_Ungroup_0(void);
-
-/*==========Ctrl文本==========*/
-void _ui_init_default_Ungroup_1(void);
-void _ui_update_default_Ungroup_1(void);
-void _ui_remove_default_Ungroup_1(void);
-
-/*==========指示灯==========*/
-void _ui_init_default_Ungroup_2(void);
-void _ui_update_default_Ungroup_2_ERROR(void);
-void _ui_update_default_Ungroup_2_NOCheck(void);
-void _ui_update_default_Ungroup_2_Shift_Open(void);
-void _ui_update_default_Ungroup_2_Shift_Close(void);
-void _ui_update_default_Ungroup_2_Ctrl_Open(void);
-void _ui_update_default_Ungroup_2_Ctrl_Close(void);
-
-#endif
diff --git a/底盘/底盘-old/底盘/CarBody/Ultra_CAP.c b/底盘/底盘-old/底盘/CarBody/Ultra_CAP.c
deleted file mode 100644
index f236656..0000000
--- a/底盘/底盘-old/底盘/CarBody/Ultra_CAP.c
+++ /dev/null
@@ -1,122 +0,0 @@
-#include "stm32f4xx.h" // Device header
-#include "stm32f4xx_conf.h"
-
-/*
- *函数简介:超电使能
- *参数说明:0-停机,1-运行(负载关),2-运行(负载开)
- *返回类型:1-发送成功,0-发送失败
- *备注:标识符0x600,数据长度4字节
- */
-uint8_t Ultra_CAP_Enable(uint8_t EnableFlag)
-{
- CanTxMsg TxMessage;
- TxMessage.StdId=0x600;//ID标准标识符0x600
- TxMessage.RTR=CAN_RTR_Data;//数据帧
- TxMessage.IDE=CAN_Id_Standard;//标准格式
- TxMessage.DLC=0x04;//4字节数据段
- TxMessage.Data[0]=0;
- TxMessage.Data[1]=EnableFlag;
- TxMessage.Data[2]=0;
- TxMessage.Data[3]=0;
-
- uint8_t mbox=CAN_Transmit(CAN1,&TxMessage);//发送数据并获取邮箱号
- uint16_t i=0;
- while((CAN_TransmitStatus(CAN1,mbox)==CAN_TxStatus_Failed)&&(i<0xFFF))i++;//等待发送结束
- if(i>=0xFFF)return 0;//发送失败
- return 1;//发送成功
-}
-
-/*
- *函数简介:超电设置电压上限
- *参数说明:电压
- *返回类型:1-发送成功,0-发送失败
- *备注:标识符0x602,数据长度4字节,默认存入EEPROM
- *备注:设定值=电压*100
- */
-uint8_t Ultra_CAP_SetVoltage(float Voltage)
-{
- uint16_t SetVoltage=(uint16_t)((int16_t)(Voltage*100.0f));
- CanTxMsg TxMessage;
- TxMessage.StdId=0x602;//ID标准标识符0x602
- TxMessage.RTR=CAN_RTR_Data;//数据帧
- TxMessage.IDE=CAN_Id_Standard;//标准格式
- TxMessage.DLC=0x04;//4字节数据段
- TxMessage.Data[0]=(uint8_t)(SetVoltage>>8);
- TxMessage.Data[1]=(uint8_t)(SetVoltage & 0x00FF);
- TxMessage.Data[2]=0;
- TxMessage.Data[3]=0x01;
-
- uint8_t mbox=CAN_Transmit(CAN1,&TxMessage);//发送数据并获取邮箱号
- uint16_t i=0;
- while((CAN_TransmitStatus(CAN1,mbox)==CAN_TxStatus_Failed)&&(i<0xFFF))i++;//等待发送结束
- if(i>=0xFFF)return 0;//发送失败
- return 1;//发送成功
-}
-
-/*
- *函数简介:超电设置电流上限
- *参数说明:无
- *返回类型:1-发送成功,0-发送失败
- *备注:标识符0x603,数据长度4字节,默认存入EEPROM
- *备注:设定值=电流*100
- */
-uint8_t Ultra_CAP_SetCurrent(float Current)
-{
- uint16_t SetCurrent=(uint16_t)((int16_t)(Current*100.0f));
- CanTxMsg TxMessage;
- TxMessage.StdId=0x603;//低位ID标准标识符0x603
- TxMessage.RTR=CAN_RTR_Data;//数据帧
- TxMessage.IDE=CAN_Id_Standard;//标准格式
- TxMessage.DLC=0x04;//4字节数据段
- TxMessage.Data[0]=(uint8_t)(SetCurrent>>8);
- TxMessage.Data[1]=(uint8_t)(SetCurrent & 0x00FF);
- TxMessage.Data[2]=0;
- TxMessage.Data[3]=0x01;
-
- uint8_t mbox=CAN_Transmit(CAN1,&TxMessage);//发送数据并获取邮箱号
- uint16_t i=0;
- while((CAN_TransmitStatus(CAN1,mbox)==CAN_TxStatus_Failed)&&(i<0xFFF))i++;//等待发送结束
- if(i>=0xFFF)return 0;//发送失败
- return 1;//发送成功
-}
-
-/*
- *函数简介:超电设置功率上限
- *参数说明:无
- *返回类型:1-发送成功,0-发送失败
- *备注:标识符0x601,数据长度4字节
- *备注:设定值=功率*100
- */
-uint8_t Ultra_CAP_SetPower(float PowerLimit)
-{
- uint16_t SetPower=(uint16_t)((int16_t)(PowerLimit*100.0f));
- CanTxMsg TxMessage;
- TxMessage.StdId=0x601;//低位ID标准标识符0x601
- TxMessage.RTR=CAN_RTR_Data;//数据帧
- TxMessage.IDE=CAN_Id_Standard;//标准格式
- TxMessage.DLC=0x04;//4字节数据段
- TxMessage.Data[0]=(uint8_t)(SetPower>>8);
- TxMessage.Data[1]=(uint8_t)(SetPower & 0x00FF);
- TxMessage.Data[2]=0;
- TxMessage.Data[3]=0;
-
- uint8_t mbox=CAN_Transmit(CAN1,&TxMessage);//发送数据并获取邮箱号
- uint16_t i=0;
- while((CAN_TransmitStatus(CAN1,mbox)==CAN_TxStatus_Failed)&&(i<0xFFF))i++;//等待发送结束
- if(i>=0xFFF)return 0;//发送失败
- return 1;//发送成功
-}
-
-/*
- *函数简介:超电初始化
- *参数说明:无
- *返回类型:无
- *备注:默认设定电压23V,电流8A,功率150W
- */
-void Ultra_CAP_Init(void)
-{
- Ultra_CAP_SetVoltage(23.0f);
- Ultra_CAP_SetCurrent(8.0f);
- Ultra_CAP_Enable(2);
- Ultra_CAP_SetPower(150.0f);
-}
diff --git a/底盘/底盘-old/底盘/CarBody/Ultra_CAP.h b/底盘/底盘-old/底盘/CarBody/Ultra_CAP.h
deleted file mode 100644
index 54b046b..0000000
--- a/底盘/底盘-old/底盘/CarBody/Ultra_CAP.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ULTRA_CAP_H
-#define __ULTRA_CAP_H
-
-void Ultra_CAP_Init(void);//超电初始化
-uint8_t Ultra_CAP_SetPower(float PowerLimit);//超电设置功率上限
-
-#endif
diff --git a/底盘/底盘-old/底盘/CarBody/sys.h b/底盘/底盘-old/底盘/CarBody/sys.h
deleted file mode 100644
index b54a536..0000000
--- a/底盘/底盘-old/底盘/CarBody/sys.h
+++ /dev/null
@@ -1,598 +0,0 @@
-/* USER CODE BEGIN Header */
-/**
- ******************************************************************************
- * @file : Referee_System.h
- * @brief : The header file of Referee_System.c
- * @author : GrassFan Wang
- * @date : 2025/01/22
- * @version : v1.0
- ******************************************************************************
- * @attention : None
- ******************************************************************************
- */
-/* USER CODE END Header */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef REFEREE_INFO_H
-#define REFEREE_INFO_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stdint.h"
-#include "stdbool.h"
-
-/* Exported defines ----------------------------------------------------------*/
-
-#define REFEREE_RXFRAME_LENGTH 136
-
-/**
- * @brief Referee Communication protocol format
- */
-#define FrameHeader_Length 5U /*!< the length of frame header */
-#define CMDID_Length 2U /*!< the length of CMD ID */
-#define CRC16_Length 2U /*!< the length of CRC ID */
-
-/**
- * @brief Cmd id
- */
-#define GAME_STATUS_ID 0x0001U /*!< game status data */
-#define GAME_RESULT_ID 0x0002U /*!< game result data */
-#define GAME_ROBOTHP_ID 0x0003U /*!< robot HP data */
-#define EVENE_DATA_ID 0x0101U /*!< site event data */
-#define SUPPLY_ACTION_ID 0x0102U /*!< supply station action data */
-#define REFEREE_WARNING_ID 0x0104U /*!< referee warning data */
-#define DART_INFO_ID 0x0105U /*!< dart shoot data */
-#define ROBOT_STATUS_ID 0x0201U /*!< robot status data */
-#define POWER_HEAT_ID 0x0202U /*!< real power heat data */
-#define ROBOT_POSITION_ID 0x0203U /*!< robot position data */
-#define ROBOT_BUFF_ID 0x0204U /*!< robot buff data */
-#define AIR_SUPPORT_ID 0x0205U /*!< aerial robot energy data */
-#define ROBOT_HURT_ID 0x0206U /*!< robot hurt data */
-#define SHOOT_DATA_ID 0x0207U /*!< real robo t shoot data */
-#define PROJECTILE_ALLOWANCE_ID 0x0208U /*!< bullet remain data */
-#define RFID_STATUS_ID 0x0209U /*!< RFID status data */
-#define DART_CLIENT_CMD_ID 0x020AU /*!< DART Client cmd data */
-#define GROUND_ROBOT_POSITION_ID 0x020BU /*!< ground robot position */
-#define RADAR_MARAKING_DATA_ID 0x020CU /*!< Radar marking progress*/
-#define SENTRY_INFO_ID 0X020DU /*!< SENTRY make autonomous decisions*/
-#define RADAR_INFO_ID 0X020EU /*!< RADAR make autonomous decisions*/
-
-#define INTERACTIVE_DATA_ID 0x0301U /*!< robot interactive data */
-#define CUSTOM_CONTROLLER_ID 0x0302U /*!< custom controller data */
-#define MINIMAP_INTERACTIVE_ID 0x0303U /*!< mini map interactive data */
-#define KEYMOUSE_INFO_ID 0x0304U /*!< key mouse data according the image transmission */
-#define MINIMAP_RECV_ID 0x0305U /*!< mini map receive data */
-#define CUSTOM_CONTROLLER_INTERACTIVE_ID 0x0306U /*!< mini map receive data */
-#define MAP_SENTRY_DATA_ID 0x0307U /*!< mini map sentry path */
-#define MAP_ROBOT_DATA_ID 0x0308U /*!< mini map robot path */
-/**
- * @brief Robot id
- */
-#define ROBOT_RED_HERO_ID 0x0001U
-#define ROBOT_RED_ENGINEER_ID 0x0002U
-#define ROBOT_RED_3_INFANTEY_ID 0x0003U
-#define ROBOT_RED_4_INFANTEY_ID 0x0004U
-#define ROBOT_RED_5_INFANTEY_ID 0x0005U
-#define ROBOT_RED_AERIAL_INFANTEY_ID 0x0006U
-#define ROBOT_RED_SENTEY_INFANTEY_ID 0x0007U
-#define ROBOT_RED_DART_INFANTEY_ID 0x0008U
-#define ROBOT_RED_RADAR_INFANTEY_ID 0x0009U
-#define ROBOT_RED_OUTPOST_INFANTEY_ID 0x0010U
-#define ROBOT_RED_BASE_INFANTEY_ID 0x0011U
-
-#define ROBOT_BLUE_HERO_ID 0x0101U
-#define ROBOT_BLUE_ENGINEER_ID 0x0102U
-#define ROBOT_BLUE_3_INFANTEY_ID 0x0103U
-#define ROBOT_BLUE_4_INFANTEY_ID 0x0104U
-#define ROBOT_BLUE_5_INFANTEY_ID 0x0105U
-#define ROBOT_BLUE_AERIAL_INFANTEY_ID 0x0106U
-#define ROBOT_BLUE_SENTEY_INFANTEY_ID 0x0107U
-#define ROBOT_BLUE_DART_INFANTEY_ID 0x0108U
-#define ROBOT_BLUE_RADAR_INFANTEY_ID 0x0109U
-#define ROBOT_BLUE_OUTPOST_INFANTEY_ID 0x0110U
-#define ROBOT_BLUE_BASE_INFANTEY_ID 0x0111U
-
-/**
- * @brief client id
- */
-#define CLIENT_RED_HERO_ID 0x0101U
-#define CLIENT_RED_ENGINEER_ID 0x0102U
-#define CLIENT_RED_3_INFANTEY_ID 0x0103U
-#define CLIENT_RED_4_INFANTEY_ID 0x0104U
-#define CLIENT_RED_5_INFANTEY_ID 0x0105U
-#define CLIENT_RED_AERIAL_INFANTEY_ID 0x0106U
-
-#define CLIENT_BLUE_HERO_ID 0x0165U
-#define CLIENT_BLUE_ENGINEER_ID 0x0166U
-#define CLIENT_BLUE_3_INFANTEY_ID 0x0167U
-#define CLIENT_BLUE_4_INFANTEY_ID 0x0168U
-#define CLIENT_BLUE_5_INFANTEY_ID 0x0169U
-#define CLIENT_BLUE_AERIAL_INFANTEY_ID 0x016AU
-
-/* Exported types ------------------------------------------------------------*/
-/* cancel byte alignment */
-#pragma pack(1)
-
-/**
- * @brief typedef structure that contains the information of frame header
- */
-typedef struct
-{
- uint8_t SOF; /*!< Data frame start byte, fixed value is 0xA5 */
- uint16_t Data_Length; /*!< the length of data in the data frame */
- uint8_t Seq; /*!< package serial number */
- uint8_t CRC8; /*!< Frame header CRC8 checksum */
-}FrameHeader_TypeDef;
-
-
-/**
- * @brief typedef structure that contains the information of game status, id: 0x0001U
- */
-typedef struct
-{
- /**
- * @brief the type of game,
- 1:RMUC,
- 2:RMUT,
- 3:RMUA,
- 4:RMUL,3v3,
- 5:RMUL,1v1,
- */
- uint8_t game_type : 4;
- uint8_t game_progress : 4; /*!< the progress of game */
- uint16_t stage_remain_time; /*!< remain time of real progress */
- uint64_t SyncTimeStamp; /*!< unix time */
-
-}game_status_t;
-
-/**
- * @brief typedef structure that contains the information of game result, id: 0x0002U
- */
-typedef struct
-{
- /**
- * @brief the result of game
- 0:draw
- 1:Red wins
- 2:Blue wins
- */
- uint8_t winner;
-}game_result_t;
-
-/**
- * @brief typedef structure that contains the information of robot HP data, id: 0x0003U
- */
-typedef struct
-{
- uint16_t red_1_robot_HP; /*!< Red Hero HP */
- uint16_t red_2_robot_HP; /*!< Red Engineer HP */
- uint16_t red_3_robot_HP; /*!< Red 3 Infantry HP */
- uint16_t red_4_robot_HP; /*!< Red 4 Infantry HP */
- uint16_t red_reserved;
- uint16_t red_7_robot_HP; /*!< Red Sentry HP */
- uint16_t red_outpost_HP; /*!< Red Outpost HP */
- uint16_t red_base_HP; /*!< Red Base HP */
-
- uint16_t blue_1_robot_HP; /*!< Blue Hero HP */
- uint16_t blue_2_robot_HP; /*!< Blue Engineer HP */
- uint16_t blue_3_robot_HP; /*!< Blue 3 Infantry HP */
- uint16_t blue_4_robot_HP; /*!< Blue 4 Infantry HP */
- uint16_t blue_reserved;
- uint16_t blue_7_robot_HP; /*!< Blue Sentry HP */
- uint16_t blue_outpost_HP; /*!< Blue Outpost HP */
- uint16_t blue_base_HP; /*!< Blue Base HP */
-} game_robot_HP_t;
-
-/**
- * @brief typedef structure that contains the information of site event data, id: 0x0101U
- */
-typedef union
-{
- /**
- * @brief the event of site
- bits 0-2:
- bit 0: Status of the supply zone that does not overlap with the exchange zone, 1 for occupied
- bit 1: Status of the supply zone that overlaps with the exchange zone, 1 for occupied
- bit 2: Status of the supply zone, 1 for occupied (applicable only to RMUL)
-
- bits 3-5: Status of the energy mechanism:
- bit 3: Status of the small energy mechanism, 1 for activated
- bit 4: Status of the large energy mechanism, 1 for activated
- bit 5-6: Status of the central highland, 1 for occupied by own side, 2 for occupied by the opponent
- bit 7-8: Status of the trapezoidal highland, 1 for occupied
- bit 9-17: Time of the opponent's last dart hit on the own side's outpost or base (0-420, default is 0 at the start)
- bit 18-20: Specific target of the opponent's last dart hit on the own side's outpost or base, default is 0 at the start,
- 1 for hitting the outpost, 2 for hitting the fixed target on the base, 3 for hitting the random fixed target on the base,
- 4 for hitting the random moving target on the base
- bit 21-22: Status of the central gain point, 0 for unoccupied, 1 for occupied by own side,
- 2 for occupied by the opponent, 3 for occupied by both sides (applicable only to RMUL)
- bit 23-31: Reserved
-
- */
- uint32_t event_data;
-}event_data_t;
-
-/**
- * @brief typedef structure that contains the warning of Referee , id: 0x0104U
- */
-typedef struct
-{
- /**
- * @brief the type of game,
- 1: Double Yellow Card,
- 2: Yellow Card,
- 3:RMUA,
- 4:RMUL,3v3,
- 5:RMUL,1v1,
- */
- uint8_t level;
- uint8_t offending_robot_id;
- uint8_t count;
-}referee_warning_t;
-
-/**
- * @brief typedef structure that contains the information of dart, id: 0x0105U
- */
-typedef struct
-{
-
- uint8_t dart_remaining_time;/* The remaining time for our side's dart launcher, in seconds.*/
-
- uint16_t dart_info;
- /**
- * @brief dart_info
- * bit 0-2 The most recent target hit by our side's dart is defaulted to 0 at the start,
- where 1 indicates hitting the outpost, 2 indicates hitting the base's fixed target,
- 3 indicates hitting the base's random fixed target, and 4 indicates hitting the base's random moving target.
- * bit 3-5 The cumulative hit count of the opponent's recently hit target (defaulting to 0 at the start, with a maximum of 4)
- * bit 6-7 The currently selected target for the dart (defaulting to 0 at the start or when not selected/selecting the outpost,
- 1 for selecting the base's fixed target, 2 for selecting the base's random fixed target, 3 for selecting the base's random moving target)
- * bit 8-15 Reserved
- */
-}dart_info_t;
-
-
-
-/**
- * @brief typedef structure that contains the information of robot status, id: 0x0201U
- */
-typedef struct
-{
- /**
- * @brief robot id
- * 0: robot none
- * 1: red hero
- * 2: red engineer
- * 3/4/5: red infantry
- * 6: red aerial
- * 7: red sentry
- * 8: red dart
- * 9: red radar station
- * 101: blue hero
- * 102: blue engineer
- * 103/104/105: blue infantry
- * 106: blue aerial
- * 107: blue sentry
- * 108: blue dart
- * 109: blue radar station
- */
- uint8_t robot_id;
- uint8_t robot_level;
- uint16_t current_HP;
- uint16_t maximum_HP;
-
- uint16_t shooter_barrel_cooling_value;
- uint16_t shooter_barrel_heat_limit;
- uint16_t chassis_power_limit;
-
- uint8_t mains_power_gimbal_output : 1;
- uint8_t mains_power_chassis_output : 1;
- uint8_t mains_power_shooter_output : 1;
-} robot_status_t;
-
-/**
- * @brief typedef structure that contains the information of power heat data, id: 0x0202U
- */
-typedef struct
-{
- uint16_t buffer_energy;
- uint16_t shooter_17mm_1_barrel_heat;
- uint16_t shooter_17mm_2_barrel_heat;
- uint16_t shooter_42mm_barrel_heat;
-} power_heat_data_t;
-
-/**
- * @brief typedef structure that contains the information of robot position data, id: 0x0203U
- */
-typedef struct
-{
- float x; /*!< position x coordinate, unit: m */
- float y; /*!< position y coordinate, unit: m */
- float angle; /*!< Position muzzle, unit: degrees */
-} robot_pos_t;
-
-/**
- * @brief typedef structure that contains the information of robot buff data, id: 0x0204U
- */
-typedef union
-{
- uint8_t recovery_buff;
- uint8_t cooling_buff;
- uint8_t defence_buff;
- uint8_t vulnerability_buff;
- uint16_t attack_buff;
- uint8_t remaining_energy;
-}buff_t;
-/**
- * @brief typedef structure that contains the information of robot hurt, id: 0x0206U
- */
-typedef struct
-{
- uint8_t armor_id : 4; /*!< hurt armor id */
- /**
- * @brief hurt type
- * 0: armor hurt
- * 1: module offline
- * 2: over fire rate
- * 3: over fire heat
- * 4: over chassis power
- * 5: armor bump
- */
- uint8_t HP_deduction_reason : 4;
-}hurt_data_t;
-
-/**
- * @brief typedef structure that contains the information of real shoot data, id: 0x0207U
- */
-typedef struct
-{
- uint8_t bullet_type;
- uint8_t shooter_number;
- uint8_t launching_frequency;
- float initial_speed;
-}shoot_data_t;
-
-/**
- * @brief typedef structure that contains the information of bullet remaining number, id: 0x0208U
- */
-typedef struct
-{
- uint16_t projectile_allowance_17mm;
- uint16_t projectile_allowance_42mm;
- uint16_t remaining_gold_coin;
-}projectile_allowance_t;;
-
-/**
- * @brief typedef structure that contains the information of RFID status, id: 0x0209U
- */
-typedef union
-{
- uint32_t rfid_status;
-}rfid_status_t;
-
-/**
- * @brief typedef structure that contains the information of dart client data, id: 0x020AU
- */
-typedef struct
-{
- uint8_t dart_launch_opening_status;
- uint8_t reserved;
- uint16_t target_change_time;
- uint16_t latest_launch_cmd_time;
-}dart_client_cmd_t;
-
-/**
- * @brief typedef structure that contains the information of robot position in mimi map, id: 0x020BU
- */
-typedef struct
-{
- float hero_x;
- float hero_y;
- float engineer_x;
- float engineer_y;
- float standard_3_x;
- float standard_3_y;
- float standard_4_x;
- float standard_4_y;
-}ground_robot_position_t;
-
-/**
- * @brief typedef structure that contains the information of robot mark, id: 0x020C
- */
-typedef struct
-{
- uint8_t mark_progress;
-}radar_mark_data_t;
-
-/**
- * @brief typedef structure that contains the information of robot mark, id: 0x020D
- */
-typedef struct
-{
- uint32_t sentry_info;
- uint16_t sentry_info_2;
-} sentry_info_t;
-
-/**
- * @brief typedef structure that contains the information of radar, id: 0x020E
- */
-typedef struct
-{
- uint8_t radar_info;
-}radar_info_t;
-/**
- * @brief typedef structure that contains the information of custom controller interactive, id: 0x0301U
- */
-typedef struct{
- uint16_t data_cmd_id;
- uint16_t sender_id;
- uint16_t receiver_id;
- uint8_t user_data[113];
-}robot_interaction_data_t;
-/**
- * @brief typedef structure that contains the information of custom controller interactive, id: 0x0302U
- */
-typedef struct
-{
- uint8_t data[30];
-} custom_robot_data_t;
-
-/**
- * @brief typedef structure that contains the information of client transmit data, id: 0x0303U
- */
-typedef struct
-{
- /**
- * @brief target position coordinate, is 0 when transmit target robot id
- */
- float target_position_x;
- float target_position_y;
- float target_position_z;
-
- uint8_t commd_keyboard;
- uint16_t target_robot_ID; /* is 0 when transmit position data */
-} ext_robot_command_t;
-
-/**
- * @brief typedef structure that contains the information of client receive data, id: 0x0305U
- */
-typedef struct
-{
- uint16_t target_robot_ID;
- float target_position_x;
- float target_position_y;
-} ext_client_map_command_t;
-
-/**
- * @brief typedef structure that contains the information of custom controller key mouse, id: 0x0306U
- */
-typedef struct
-{
- uint16_t key_value;
- uint16_t x_position:12;
- uint16_t mouse_left:4;
- uint16_t y_position:12;
- uint16_t mouse_right:4;
- uint16_t reserved;
-}custom_client_data_t;
-
-/**
- * @brief typedef structure that contains the information of sentry path, id: 0x0307U
- */
-typedef struct
-{
- /**
- * @brief sentry status
- * 1: attack on target point
- * 2: defend on target point
- * 3: move to target point
- */
- uint8_t intention;
- uint16_t start_position_x;
- uint16_t start_position_y;
- int8_t delta_x[49];
- int8_t delta_y[49];
-}map_sentry_data_t;
-
-/**
- * @brief typedef structure that contains the information of Referee
- */
-typedef struct
-{
- uint8_t Index;
- uint16_t DataLength;
-
-#ifdef GAME_STATUS_ID
- game_status_t game_status;
-#endif
-
-#ifdef GAME_RESULT_ID
- game_result_t game_result;
-#endif
-
-#ifdef GAME_ROBOTHP_ID
- game_robot_HP_t game_robot_HP;
-#endif
-
-#ifdef EVENE_DATA_ID
- event_data_t event_data;
-#endif
-
-#ifdef REFEREE_WARNING_ID
- referee_warning_t referee_warning;
-#endif
-
-#ifdef DART_INFO_ID
- dart_info_t dart_info;
-#endif
-
-#ifdef ROBOT_STATUS_ID
- robot_status_t robot_status;
-#endif
-
-#ifdef POWER_HEAT_ID
- power_heat_data_t power_heat_data;
-#endif
-
-#ifdef ROBOT_POSITION_ID
- robot_pos_t robot_pos;
-#endif
-
-#ifdef ROBOT_BUFF_ID
- buff_t buff;
-#endif
-
-#ifdef ROBOT_HURT_ID
- hurt_data_t hurt_data;
-#endif
-
-#ifdef SHOOT_DATA_ID
- shoot_data_t shoot_data;
-#endif
-
-#ifdef PROJECTILE_ALLOWANCE_ID
- projectile_allowance_t projectile_allowance;
-#endif
-#ifdef RFID_STATUS_ID
- rfid_status_t rfid_status;
-#endif
-
-#ifdef DART_CLIENT_CMD_ID
- dart_client_cmd_t dart_client_cmd;
-#endif
-
-#ifdef GROUND_ROBOT_POSITION_ID
- ground_robot_position_t ground_robot_position;
-#endif
-
-#ifdef RADAR_MARAKING_DATA_ID
- radar_mark_data_t radar_mark_data;
-#endif
-
-#ifdef SENTRY_INFO_ID
- sentry_info_t sentry_info;
-#endif
-
-#ifdef RADAR_INFO_ID
- radar_info_t radar_info;
-#endif
-}Referee_System_Info_TypeDef;
-
-/* restore byte alignment */
-#pragma pack()
-
-/* Exported variables ---------------------------------------------------------*/
-/**
- * @brief Referee_RxDMA MultiBuffer
- */
-extern uint8_t Referee_System_Info_MultiRx_Buf[2][REFEREE_RXFRAME_LENGTH];
-
-/**
- * @brief Referee structure variable
- */
-extern Referee_System_Info_TypeDef Referee_Info;
-
-
-/* Exported functions prototypes ---------------------------------------------*/
-extern void Referee_System_Frame_Update(uint8_t *Buff);
-
-#endif //REFEREE_INFO_H
diff --git a/底盘/底盘-old/底盘/Control/PID.c b/底盘/底盘-old/底盘/Control/PID.c
deleted file mode 100644
index 14becec..0000000
--- a/底盘/底盘-old/底盘/Control/PID.c
+++ /dev/null
@@ -1,202 +0,0 @@
-#include "stm32f4xx.h" // Device header
-#include "stm32f4xx_conf.h"
-#include "PID.h"
-
-/*
- *函数简介:位置式PID初始化结构体
- *参数说明:位置式PID参数结构体
- *参数说明:预期值
- *返回类型:无
- *备注:无
- */
-void PID_PositionStructureInit(PID_PositionInitTypedef* PID_InitStructure,float NeedValue)
-{
- PID_InitStructure->Need_Value=NeedValue;
- PID_InitStructure->Ek=0;
- PID_InitStructure->Sum_Ek=0;
- PID_InitStructure->Ek_low=0;
- PID_InitStructure->Ek_up=0;
- PID_InitStructure->Kp=0;
- PID_InitStructure->Ki=0;
- PID_InitStructure->Kd=0;
- PID_InitStructure->OUT_low=-1e10;
- PID_InitStructure->OUT_up=1e10;
-}
-
-/*
- *函数简介:位置式PID设置参数
- *参数说明:位置式PID参数结构体
- *参数说明:单精度浮点型Kp
- *参数说明:单精度浮点型Ki
- *参数说明:单精度浮点型Kd
- *返回类型:无
- *备注:无
- */
-void PID_PositionSetParameter(PID_PositionInitTypedef* PID_InitStructure,float kp,float ki,float kd)
-{
- PID_InitStructure->Kp=kp;
- PID_InitStructure->Ki=ki;
- PID_InitStructure->Kd=kd;
-}
-
-/*
- *函数简介:位置式PID设置误差为0阈值
- *参数说明:位置式PID参数结构体
- *参数说明:误差为0阈值下限
- *参数说明:误差为0阈值上限
- *返回类型:无
- *备注:无
- */
-void PID_PositionSetEkRange(PID_PositionInitTypedef* PID_InitStructure,float ek_low,float ek_up)
-{
- PID_InitStructure->Ek_low=ek_low;
- PID_InitStructure->Ek_up=ek_up;
-}
-
-/*
- *函数简介:位置式PID设置输出限幅
- *参数说明:位置式PID参数结构体
- *参数说明:输出限幅下限
- *参数说明:输出限幅上限
- *返回类型:无
- *备注:无
- */
-void PID_PositionSetOUTRange(PID_PositionInitTypedef* PID_InitStructure,float out_low,float out_up)
-{
- PID_InitStructure->OUT_low=out_low;
- PID_InitStructure->OUT_up=out_up;
-}
-
-/*
- *函数简介:位置式PID清理
- *参数说明:位置式PID参数结构体
- *返回类型:无
- *备注:使Ek和Sum为0
- */
-void PID_PositionClean(PID_PositionInitTypedef* PID_InitStructure)
-{
- PID_InitStructure->Ek=0;
- PID_InitStructure->Sum_Ek=0;
-}
-
-/*
- *函数简介:位置式PID计算
- *参数说明:位置式PID参数结构体
- *参数说明:当前值
- *返回类型:无
- *备注:OUT=POUT+IOUT+DOUT=Kp*Ek+Ki*ΣEk+Kd*(Ek-Ek_1)
- *备注:计算结果保存在位置式PID参数结构体中
- */
-void PID_PositionCalc(PID_PositionInitTypedef* PID_InitStructure,float NowValue)
-{
- PID_InitStructure->Now_Value=NowValue;
- PID_InitStructure->Ek_1=PID_InitStructure->Ek;
- PID_InitStructure->Ek=PID_InitStructure->Need_Value-PID_InitStructure->Now_Value;
- if(PID_InitStructure->Ek_lowEk&&PID_InitStructure->EkEk_up)//误差为0检测
- PID_InitStructure->Ek=0;
- PID_InitStructure->Sum_Ek+=PID_InitStructure->Ek;
- PID_InitStructure->Del_Ek=PID_InitStructure->Ek-PID_InitStructure->Ek_1;
-
- PID_InitStructure->P_OUT=PID_InitStructure->Kp*PID_InitStructure->Ek;
- PID_InitStructure->I_OUT=PID_InitStructure->Ki*PID_InitStructure->Sum_Ek;
- PID_InitStructure->D_OUT=PID_InitStructure->Kd*PID_InitStructure->Del_Ek;
- PID_InitStructure->OUT=PID_InitStructure->P_OUT+PID_InitStructure->I_OUT+PID_InitStructure->D_OUT;
-
- if(PID_InitStructure->OUTOUT_low)//输出限幅
- PID_InitStructure->OUT=PID_InitStructure->OUT_low;
- if(PID_InitStructure->OUT>PID_InitStructure->OUT_up)
- PID_InitStructure->OUT=PID_InitStructure->OUT_up;
-}
-
-/*
- *函数简介:增量式PID初始化结构体
- *参数说明:增量式PID参数结构体
- *参数说明:预期值
- *返回类型:无
- *备注:无
- */
-void PID_IncrementalStructureInit(PID_IncrementalInitTypedef* PID_InitStructure,float NeedValue)
-{
- PID_InitStructure->Need_Value=NeedValue;
- PID_InitStructure->Ek=0;
- PID_InitStructure->Ek_1=0;
- PID_InitStructure->Ek_low=0;
- PID_InitStructure->Ek_up=0;
- PID_InitStructure->Kp=0;
- PID_InitStructure->Ki=0;
- PID_InitStructure->Kd=0;
- PID_InitStructure->OUT_low=-1e10;
- PID_InitStructure->OUT_up=1e10;
-}
-
-/*
- *函数简介:增量式PID设置参数
- *参数说明:增量式PID参数结构体
- *参数说明:单精度浮点型Kp
- *参数说明:单精度浮点型Ki
- *参数说明:单精度浮点型Kd
- *返回类型:无
- *备注:无
- */
-void PID_IncrementalSetParameter(PID_IncrementalInitTypedef* PID_InitStructure,float kp,float ki,float kd)
-{
- PID_InitStructure->Kp=kp;
- PID_InitStructure->Ki=ki;
- PID_InitStructure->Kd=kd;
-}
-
-/*
- *函数简介:增量式PID设置误差为0阈值
- *参数说明:增量式PID参数结构体
- *参数说明:误差为0阈值下限
- *参数说明:误差为0阈值上限
- *返回类型:无
- *备注:无
- */
-void PID_IncrementalSetEkRange(PID_IncrementalInitTypedef* PID_InitStructure,float ek_low,float ek_up)
-{
- PID_InitStructure->Ek_low=ek_low;
- PID_InitStructure->Ek_up=ek_up;
-}
-
-/*
- *函数简介:增量式PID设置输出限幅
- *参数说明:增量式PID参数结构体
- *参数说明:输出限幅下限
- *参数说明:输出限幅上限
- *返回类型:无
- *备注:无
- */
-void PID_IncrementalSetOUTRange(PID_IncrementalInitTypedef* PID_InitStructure,float out_low,float out_up)
-{
- PID_InitStructure->OUT_low=out_low;
- PID_InitStructure->OUT_up=out_up;
-}
-
-/*
- *函数简介:增量式PID计算
- *参数说明:增量式PID参数结构体
- *参数说明:当前值
- *返回类型:无
- *备注:OUT=POUT+IOUT+DOUT=Kp*ΔEk+Ki*ΣΔEk+Kd*(ΔEk-ΔEk_1)=Kp*(Ek-Ek_1)+Ki*Ek+Kd*(Ek-2*Ek_1+Ek_2)
- *备注:计算结果保存在增量式PID参数结构体中
- */
-void PID_IncrementalCalc(PID_IncrementalInitTypedef* PID_InitStructure,float NowValue)
-{
- PID_InitStructure->Now_Value=NowValue;
- PID_InitStructure->Ek_2=PID_InitStructure->Ek_1;
- PID_InitStructure->Ek_1=PID_InitStructure->Ek;
- PID_InitStructure->Ek=PID_InitStructure->Need_Value-PID_InitStructure->Now_Value;
- if(PID_InitStructure->Ek_lowEk&&PID_InitStructure->EkEk_up)//误差为0检测
- PID_InitStructure->Ek=0;
-
- PID_InitStructure->P_OUT=PID_InitStructure->Kp*(PID_InitStructure->Ek-PID_InitStructure->Ek_1);
- PID_InitStructure->I_OUT=PID_InitStructure->Ki*PID_InitStructure->Ek;
- PID_InitStructure->D_OUT=PID_InitStructure->Kd*(PID_InitStructure->Ek-2*PID_InitStructure->Ek_1+PID_InitStructure->Ek_2);
- PID_InitStructure->OUT=PID_InitStructure->P_OUT+PID_InitStructure->I_OUT+PID_InitStructure->D_OUT;
-
- if(PID_InitStructure->OUTOUT_low)//输出限幅
- PID_InitStructure->OUT=PID_InitStructure->OUT_low;
- if(PID_InitStructure->OUT>PID_InitStructure->OUT_up)
- PID_InitStructure->OUT=PID_InitStructure->OUT_up;
-}
diff --git a/底盘/底盘-old/底盘/Control/PID.h b/底盘/底盘-old/底盘/Control/PID.h
deleted file mode 100644
index 7d37f58..0000000
--- a/底盘/底盘-old/底盘/Control/PID.h
+++ /dev/null
@@ -1,63 +0,0 @@
-#ifndef __PID_H__
-#define __PID_H__
-
-typedef struct
-{
- float Need_Value;//预期值
- float Now_Value;//当前值
-
- float Ek;//本次误差
- float Ek_1;//上一次误差
- float Sum_Ek;//误差积分
- float Del_Ek;//误差差分
- float Ek_low;//误差为0阈值下限
- float Ek_up;//误差为0阈值上限
-
- float Kp;//Kp
- float Ki;//Ki
- float Kd;//Kd
-
- float P_OUT;//比例输出
- float I_OUT;//积分输出
- float D_OUT;//微分输出
- float OUT;//总输出
- float OUT_low;//输出限幅下限
- float OUT_up;//输出限幅上限
-}PID_PositionInitTypedef;//位置式PID参数结构体
-
-typedef struct
-{
- float Need_Value;//预期值
- float Now_Value;//当前值
-
- float Ek;//本次误差
- float Ek_1;//上一次误差
- float Ek_2;//上两次误差
- float Ek_low;//误差为0阈值下限
- float Ek_up;//误差为0阈值上限
-
- float Kp;//Kp
- float Ki;//Ki
- float Kd;//Kd
-
- float P_OUT;//比例输出
- float I_OUT;//积分输出
- float D_OUT;//微分输出
- float OUT;//总输出
- float OUT_low;//输出限幅下限
- float OUT_up;//输出限幅上限
-}PID_IncrementalInitTypedef;//增量式PID参数结构体
-
-void PID_PositionStructureInit(PID_PositionInitTypedef* PID_InitStructure,float NeedValue);//位置式PID初始化结构体
-void PID_PositionSetParameter(PID_PositionInitTypedef* PID_InitStructure,float kp,float ki,float kd);//位置式PID设置参数
-void PID_PositionSetEkRange(PID_PositionInitTypedef* PID_InitStructure,float ek_low,float ek_up);//位置式PID设置误差为0阈值
-void PID_PositionSetOUTRange(PID_PositionInitTypedef* PID_InitStructure,float out_low,float out_up);//位置式PID设置输出限幅
-void PID_PositionClean(PID_PositionInitTypedef* PID_InitStructure);//位置式PID清理
-void PID_PositionCalc(PID_PositionInitTypedef* PID_InitStructure,float NowValue);//位置式PID计算
-void PID_IncrementalStructureInit(PID_IncrementalInitTypedef* PID_InitStructure,float NeedValue);//增量式PID初始化结构体
-void PID_IncrementalSetParameter(PID_IncrementalInitTypedef* PID_InitStructure,float kp,float ki,float kd);//增量式PID设置参数
-void PID_IncrementalSetEkRange(PID_IncrementalInitTypedef* PID_InitStructure,float ek_low,float ek_up);//增量式PID设置误差为0阈值
-void PID_IncrementalSetOUTRange(PID_IncrementalInitTypedef* PID_InitStructure,float out_low,float out_up);//增量式PID设置输出限幅
-void PID_IncrementalCalc(PID_IncrementalInitTypedef* PID_InitStructure,float NowValue);//增量式PID计算
-
-#endif
diff --git a/底盘/底盘-old/底盘/DebugConfig/Target_1_STM32F407IGHx.dbgconf b/底盘/底盘-old/底盘/DebugConfig/Target_1_STM32F407IGHx.dbgconf
deleted file mode 100644
index 1df0a1b..0000000
--- a/底盘/底盘-old/底盘/DebugConfig/Target_1_STM32F407IGHx.dbgconf
+++ /dev/null
@@ -1,48 +0,0 @@
-// File: STM32F405_415_407_417_427_437_429_439.dbgconf
-// Version: 1.0.0
-// Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
-// refer to STM32F40x STM32F41x datasheets
-// refer to STM32F42x STM32F43x datasheets
-
-// <<< Use Configuration Wizard in Context Menu >>>
-
-// Debug MCU configuration register (DBGMCU_CR)
-// DBG_STANDBY Debug Standby Mode
-// DBG_STOP Debug Stop Mode
-// DBG_SLEEP Debug Sleep Mode
-//
-DbgMCU_CR = 0x00000007;
-
-// Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
-// Reserved bits must be kept at reset value
-// DBG_CAN2_STOP CAN2 stopped when core is halted
-// DBG_CAN1_STOP CAN2 stopped when core is halted
-// DBG_I2C3_SMBUS_TIMEOUT I2C3 SMBUS timeout mode stopped when core is halted
-// DBG_I2C2_SMBUS_TIMEOUT I2C2 SMBUS timeout mode stopped when core is halted
-// DBG_I2C1_SMBUS_TIMEOUT I2C1 SMBUS timeout mode stopped when core is halted
-// DBG_IWDG_STOP Independent watchdog stopped when core is halted
-// DBG_WWDG_STOP Window watchdog stopped when core is halted
-// DBG_RTC_STOP RTC stopped when core is halted
-// DBG_TIM14_STOP TIM14 counter stopped when core is halted
-// DBG_TIM13_STOP TIM13 counter stopped when core is halted
-// DBG_TIM12_STOP TIM12 counter stopped when core is halted
-// DBG_TIM7_STOP TIM7 counter stopped when core is halted
-// DBG_TIM6_STOP TIM6 counter stopped when core is halted
-// DBG_TIM5_STOP TIM5 counter stopped when core is halted
-// DBG_TIM4_STOP TIM4 counter stopped when core is halted
-// DBG_TIM3_STOP TIM3 counter stopped when core is halted
-// DBG_TIM2_STOP TIM2 counter stopped when core is halted
-//
-DbgMCU_APB1_Fz = 0x00000000;
-
-// Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
-// Reserved bits must be kept at reset value
-// DBG_TIM11_STOP TIM11 counter stopped when core is halted
-// DBG_TIM10_STOP TIM10 counter stopped when core is halted
-// DBG_TIM9_STOP TIM9 counter stopped when core is halted
-// DBG_TIM8_STOP TIM8 counter stopped when core is halted
-// DBG_TIM1_STOP TIM1 counter stopped when core is halted
-//
-DbgMCU_APB2_Fz = 0x00000000;
-
-// <<< end of configuration section >>>
\ No newline at end of file
diff --git a/底盘/底盘-old/底盘/EventRecorderStub.scvd b/底盘/底盘-old/底盘/EventRecorderStub.scvd
deleted file mode 100644
index 2956b29..0000000
--- a/底盘/底盘-old/底盘/EventRecorderStub.scvd
+++ /dev/null
@@ -1,9 +0,0 @@
-
-
-
-
-
-
-
-
-
diff --git a/底盘/底盘-old/底盘/Function/CToC.c b/底盘/底盘-old/底盘/Function/CToC.c
deleted file mode 100644
index 5c256ca..0000000
--- a/底盘/底盘-old/底盘/Function/CToC.c
+++ /dev/null
@@ -1,141 +0,0 @@
-#include "stm32f4xx.h" // Device header
-#include "stm32f4xx_conf.h"
-#include "CToC.h"
-#include "Remote.h"
-#include "RefereeSystem.h"
-
-/*
- *函数简介:板间通讯从机初始化
- *参数说明:无
- *返回类型:无
- *备注:默认使用CAN2(CAN2-Tx为PB6,CAN2-Rx为PB5)
- *备注:CAN波特率1M,默认1Tq=1/14us≈0.07us
- *备注:使用CAN2需要在打开CAN2时钟之前打开CAN1时钟,且CAN2筛选器编号为15~27
- *备注:主机控制从机的标识符为149,从机回报的标识符为189
- */
-void CToC_SlaveInit(void)
-{
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1,ENABLE);
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2,ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB,ENABLE);//开启时钟
-
- GPIO_InitTypeDef GPIO_InitStructure;
- GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//复用推挽
- GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
- GPIO_InitStructure.GPIO_Pin=GPIO_Pin_5 | GPIO_Pin_6;
- GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
- GPIO_Init(GPIOB,&GPIO_InitStructure);//配置PB5(CAN2-Rx)和PB6(CAN2-Tx)
-
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource5,GPIO_AF_CAN2);//开启PB5的CAN2复用模式
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource6,GPIO_AF_CAN2);//开启PB6的CAN2复用模式
-
- CAN_InitTypeDef CAN_InitStructure;
- CAN_InitStructure.CAN_Mode=CAN_Mode_Normal;//正常模式
- CAN_InitStructure.CAN_Prescaler=3;//时钟分频,1Tq=Prescaler/T_PCLK=Prescaler/42M
- CAN_InitStructure.CAN_SJW=CAN_SJW_1tq;//SJW极限值
- CAN_InitStructure.CAN_BS1=CAN_BS1_10tq;//PBS1段长度
- CAN_InitStructure.CAN_BS2=CAN_BS2_3tq;//PBS2段长度,1/Baudrate=T_1bit=(1+BS1+BS2)Tq
- CAN_InitStructure.CAN_TTCM=DISABLE;//关闭时间触发功能
- CAN_InitStructure.CAN_ABOM=ENABLE;//开启自动离线管理功能
- CAN_InitStructure.CAN_AWUM=ENABLE;//开启自动唤醒功能
- CAN_InitStructure.CAN_NART=ENABLE;//禁止自动重传功能
- CAN_InitStructure.CAN_RFLM=DISABLE;//关闭锁定FIFO功能
- CAN_InitStructure.CAN_TXFP=DISABLE;//配置报文优先级判定为标识符决定
- CAN_Init(CAN2,&CAN_InitStructure);
-
- CAN_FilterInitTypeDef CAN_FilterInitStructure;
- CAN_FilterInitStructure.CAN_FilterNumber=15;//筛选器编号15(编号0~14属于CAN1,编号15~27属于CAN2)
- CAN_FilterInitStructure.CAN_FilterFIFOAssignment=CAN_Filter_FIFO1;//存入FIFO1
- CAN_FilterInitStructure.CAN_FilterMode=CAN_FilterMode_IdMask;//掩码模式
- CAN_FilterInitStructure.CAN_FilterScale=CAN_FilterScale_16bit;//筛选器尺度为16bits
- CAN_FilterInitStructure.CAN_FilterIdHigh=(CToC_SlaveID1<<5);//标识符=STID[15:5](189/0001 1000 1001)+RTR[4:4](0)+IDE[3:3](0)+EXID[2:0](000)
- CAN_FilterInitStructure.CAN_FilterIdLow=(CToC_SlaveID1<<5);
- CAN_FilterInitStructure.CAN_FilterMaskIdHigh=0xFFE3;//1111 1111 0000 0011
- CAN_FilterInitStructure.CAN_FilterMaskIdLow=0xFFE3;
- CAN_FilterInitStructure.CAN_FilterActivation=ENABLE;
- CAN_FilterInit(&CAN_FilterInitStructure);
-
- CAN_ITConfig(CAN2,CAN_IT_FMP1,ENABLE);//打通CAN2_FIFO1到NVIC的通道
-
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//选择NVIC分组2(2位抢占优先级，2位响应优先级)
-
- NVIC_InitTypeDef NVIC_InitStructure;
- NVIC_InitStructure.NVIC_IRQChannel=CAN2_RX1_IRQn;//选择CAN2_FIFO1接收中断通道
- NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;//使能中断通道
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=1;//抢占优先级为1
- NVIC_InitStructure.NVIC_IRQChannelSubPriority=1;//响应优先级为1
- NVIC_Init(&NVIC_InitStructure);//初始化CAN2_FIFO1的NVIC
-}
-
-/*
- *函数简介:板间通讯从机发送裁判系统数据
- *参数说明:无
- *返回类型:1-发送成功,0-发送失败
- *备注:默认标准格式数据帧,8字节数据段,主机ID为CToC_MasterID1
- *发送数据:Data[0]-发射机构状态
- */
-uint8_t CToC_SlaveSendRefereeSystemData(void)
-{
- CanTxMsg TxMessage;
- TxMessage.StdId=CToC_MasterID1;//主机ID
- TxMessage.RTR=CAN_RTR_Data;//数据帧
- TxMessage.IDE=CAN_Id_Standard;//标准格式
- TxMessage.DLC=0x08;//8字节数据段
- TxMessage.Data[0]=RefereeSystem_ShooterStatus;
- TxMessage.Data[1]=0;
- TxMessage.Data[2]=0;
- TxMessage.Data[3]=0;
- TxMessage.Data[4]=0;
- TxMessage.Data[5]=0;
- TxMessage.Data[6]=0;
- TxMessage.Data[7]=0;
-
- uint8_t mbox=CAN_Transmit(CAN2,&TxMessage);//发送数据并获取邮箱号
- uint16_t i=0;
- while((CAN_TransmitStatus(CAN2,mbox)==CAN_TxStatus_Failed)&&(i<0XFFF))i++;//等待发送结束
- if(i>=0xFFF)return 0;//发送失败
- return 1;//发送成功
-}
-
-/*
- *函数简介:板间通讯数据处理
- *参数说明:CAN数据帧ID号,详情见CToC.h的宏定义
- *参数说明:反馈数据(8字节)
- *返回类型:无
- *备注:无
- *接收数据:
- * CToC_SlaveID1
- * Data[0~1]-遥控器右摇杆左右
- * Data[2~3]-遥控器右摇杆上下
- * Data[4~5]-遥控器左摇杆左右
- * Data[6~7]-遥控器左摇杆上下
- * CToC_SlaveID2
- * Data[0]-遥控器连接状态
- * Data[1]-遥控器右侧拨动开关
- * Data[2]-键盘Ctrl状态(Remote_KeyPush_Ctrl)
- * Data[3]-键盘Shift状态(Remote_KeyPush_Shift)
- * Data[4]-遥控器启动标志位
- * Data[5]-遥控器左侧拨动开关
- */
-void CToC_CANDataProcess(uint32_t ID,uint8_t *Data)
-{
- if(ID==CToC_SlaveID1)//接收遥控器拨杆数据
- {
- Remote_RxData.Remote_R_RL=(uint16_t)((uint16_t)Data[0]<<8 | Data[1]);//右摇杆右左
- Remote_RxData.Remote_R_UD=(uint16_t)((uint16_t)Data[2]<<8 | Data[3]);//右摇杆上下
- Remote_RxData.Remote_L_RL=(uint16_t)((uint16_t)Data[4]<<8 | Data[5]);//左摇杆右左
- Remote_RxData.Remote_L_UD=(uint16_t)((uint16_t)Data[6]<<8 | Data[7]);//左摇杆上下
- }
- else if(ID==CToC_SlaveID2)//接收遥控器控制数据
- {
- Remote_Status=Data[0];//遥控器连接状态
- Remote_RxData.Remote_RS=Data[1];//遥控器右侧拨动开关
- Remote_RxData.Remote_KeyPush_Ctrl=Data[2];//键盘Ctrl状态
- Remote_RxData.Remote_KeyPush_Shift=Data[3];//键盘Shift状态
- Remote_StartFlag=Data[4];//遥控器启动标志位
- Remote_RxData.Remote_LS=Data[5];//遥控器左侧拨动开关
- Remote_RxData.Remote_Key_1=Data[6];
- Remote_RxData.Remote_Key_2=Data[7];
- }
-}
diff --git a/底盘/底盘-old/底盘/Function/CToC.h b/底盘/底盘-old/底盘/Function/CToC.h
deleted file mode 100644
index d1d3e41..0000000
--- a/底盘/底盘-old/底盘/Function/CToC.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __CTOC_H
-#define __CTOC_H
-
-#define CToC_MasterID1 0x019//主机ID1
-
-#define CToC_SlaveID1 0x149//从机ID1
-#define CToC_SlaveID2 0x189//从机ID2
-
-void CToC_SlaveInit(void);//板间通讯从机初始化
-uint8_t CToC_SlaveSendRefereeSystemData(void);//板间通讯从机发送裁判系统数据
-void CToC_CANDataProcess(uint32_t ID,uint8_t *Data);//板间通讯数据处理
-
-#endif
diff --git a/底盘/底盘-old/底盘/Function/CloseLoopControl.c b/底盘/底盘-old/底盘/Function/CloseLoopControl.c
deleted file mode 100644
index 4e220d5..0000000
--- a/底盘/底盘-old/底盘/Function/CloseLoopControl.c
+++ /dev/null
@@ -1,96 +0,0 @@
-#include "stm32f4xx.h" // Device header
-#include "stm32f4xx_conf.h"
-#include "Remote.h"
-#include "Mecanum.h"
-#include "Warming.h"
-#include "LinkCheck.h"
-#include "UI.h"
-
-uint8_t CloseLoopControl_ErrorFlag;//闭环控制CAN设备故障标志位
-
-/*
- *函数简介:闭环控制初始化
- *参数说明:无
- *返回类型:无
- *备注:使用定时器TIM6进行闭环,闭环周期2ms
- */
-void CloseLoopControl_Init(void)
-{
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM6,ENABLE);//开启时钟
-
- TIM_InternalClockConfig(TIM6);//选择时基单元的时钟(TIM6)
-
- TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure;//配置时基单元（配置参数）
- TIM_TimeBaseInitStructure.TIM_ClockDivision=TIM_CKD_DIV1;//配置时钟分频为1分频
- TIM_TimeBaseInitStructure.TIM_CounterMode=TIM_CounterMode_Up;//配置计数器模式为向上计数
- TIM_TimeBaseInitStructure.TIM_Period=500-1;//配置自动重装值ARR
- TIM_TimeBaseInitStructure.TIM_Prescaler=336-1;//配置分频值PSC,默认定时2ms
- TIM_TimeBaseInitStructure.TIM_RepetitionCounter=0;//配置重复计数单元的置为0
- TIM_TimeBaseInit(TIM6,&TIM_TimeBaseInitStructure);//初始化TIM7
-
- TIM_ClearFlag(TIM6,TIM_FLAG_Update);//清除配置时基单元产生的中断标志位
-
- TIM_ITConfig(TIM6,TIM_IT_Update,ENABLE);//使能更新中断
-
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//选择NVIC分组
-
- NVIC_InitTypeDef NVIC_InitStructure;//配置NVIC（配置参数）
- NVIC_InitStructure.NVIC_IRQChannel=TIM6_DAC_IRQn;//选择中断通道为TIM6
- NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;//使能中断通道
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=3;//TIM2的抢占优先级
- NVIC_InitStructure.NVIC_IRQChannelSubPriority=3;//TIM2的响应优先级
- NVIC_Init(&NVIC_InitStructure);//初始化NVIC
-
- TIM_Cmd(TIM6,ENABLE);//启动定时器
-
- Mecanum_Init();//麦轮初始化
-}
-
-/*
- *函数简介:TIM6定时器更新中断函数
- *参数说明:无
- *返回类型:无
- *备注:无
- */
-void TIM6_DAC_IRQHandler(void)
-{
- static uint8_t Remote_LastStatus,Remote_ThisStatus=0;
- static uint8_t Count=0;
- if(TIM_GetITStatus(TIM6,TIM_IT_Update)==SET)//检测TIM6更新
- {
- TIM_ClearITPendingBit(TIM6,TIM_IT_Update);//清除标志位
-
- /*===============麦轮闭环控制===============*/
- Remote_LastStatus=Remote_ThisStatus;//遥控器上一次连接状态
- Remote_ThisStatus=Remote_Status;//遥控器本次连接状态
- if(LinkCheck_Error==0)//CAN设备正常连接
- {
- if(Remote_Status==1)//遥控器处于连接状态
- {
- if(Remote_LastStatus==0 && Remote_ThisStatus==1)UI_Init();//遥控器连接瞬间,初始化UI界面
-
- Mecanum_PowerMoveControl();//底盘功率控制
-
- if(Count==50){Count=0;UI_Updata();}//每100ms更新一次UI界面
- else Count++;
- }
- else
- {
- Warming_MotorControl();//电机报警状态
-
- if(Count==50){Count=0;UI_RemoteNoCheck();}//每100ms更新一次UI界面,显示遥控器未连接
- else Count++;
- }
- }
- else//CAN设备异常连接
- {
- Warming_LinkError();//CAN设备连接错误报警
- Warming_MotorControl();//电机报警状态
-
- CloseLoopControl_ErrorFlag=1;//置闭环控制CAN设备故障标志位
-
- if(Count==50){Count=0;Warming_UIShow();}//每100ms更新一次UI界面,显示CAN设备异常连接
- else Count++;
- }
- }
-}
diff --git a/底盘/底盘-old/底盘/Function/CloseLoopControl.h b/底盘/底盘-old/底盘/Function/CloseLoopControl.h
deleted file mode 100644
index fb5d095..0000000
--- a/底盘/底盘-old/底盘/Function/CloseLoopControl.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef __CLOSELOOPCONTROL_H
-#define __CLOSELOOPCONTROL_H
-
-extern uint8_t CloseLoopControl_ErrorFlag;//闭环控制CAN设备故障标志位
-
-void CloseLoopControl_Init(void);//闭环控制初始化
-
-#endif
diff --git a/底盘/底盘-old/底盘/Function/LinkCheck.c b/底盘/底盘-old/底盘/Function/LinkCheck.c
deleted file mode 100644
index 1eae002..0000000
--- a/底盘/底盘-old/底盘/Function/LinkCheck.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
-
-连接检查初始化 --->定时器超时--->连接错误,关闭遥控器---
-开启定时器 --->等待CAN接收---| |
- ^ --->关闭定时器,更改ID<---等待恢复连接<--
- | |
- ---开启定时器-------
-
-*/
-
-#include "stm32f4xx.h" // Device header
-#include "stm32f4xx_conf.h"
-#include "TIM.h"
-#include "Remote.h"
-#include "CAN.h"
-
-uint8_t LinkCheck_Error=0;//连接错误标志位
-
-/*
- *函数简介:CAN设备连接检测初始化
- *参数说明:无
- *返回类型:无
- *备注:Freq=Sys_APB1TIM/(PSC+1)/(ARR+1)=84MHz/(PSC+1)/(ARR+1),T=1/Freq=(ARR+1)*(PSC+1)/84MHz
- *备注:默认定时2.5ms
- */
-void LinkCheck_Init(void)
-{
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM13,ENABLE);//开启时钟
-
- TIM_InternalClockConfig(TIM13);//选择时基单元的时钟
-
- TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure;//配置时基单元（配置参数）
- TIM_TimeBaseInitStructure.TIM_ClockDivision=TIM_CKD_DIV1;//配置时钟分频为1分频
- TIM_TimeBaseInitStructure.TIM_CounterMode=TIM_CounterMode_Up;//配置计数器模式为向上计数
- TIM_TimeBaseInitStructure.TIM_Period=210-1;//配置自动重装值ARR
- TIM_TimeBaseInitStructure.TIM_Prescaler=1000-1;//配置分频值PSC
- TIM_TimeBaseInitStructure.TIM_RepetitionCounter=0;//配置重复计数单元的置为0
- TIM_TimeBaseInit(TIM13,&TIM_TimeBaseInitStructure);//初始化TIM13
-
- TIM_ClearFlag(TIM13,TIM_FLAG_Update);//清除配置时基单元产生的中断标志位
-
- TIM_ITConfig(TIM13,TIM_IT_Update,ENABLE);//使能更新中断
-
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//选择NVIC分组
-
- NVIC_InitTypeDef NVIC_InitStructure;//配置NVIC（配置参数）
- NVIC_InitStructure.NVIC_IRQChannel=TIM8_UP_TIM13_IRQn;//选择中断通道为TIM13
- NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;//使能中断通道
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=1;//TIM13的抢占优先级
- NVIC_InitStructure.NVIC_IRQChannelSubPriority=2;//TIM13的响应优先级
- NVIC_Init(&NVIC_InitStructure);//初始化NVIC
-
- TIM_Cmd(TIM13,ENABLE);//启动定时器
-
- CAN_CANInit();//CAN通讯初始化
-}
-
-/*
- *函数简介:开启掉线检查
- *参数说明:无
- *返回类型:无
- *备注:无
- */
-void LinkCheck_ON(void)
-{
- TIM_SetCounter(TIM13,0);//复位计数器
- TIM_Cmd(TIM13,ENABLE);
-}
-
-/*
- *函数简介:关闭掉线检测
- *参数说明:无
- *返回类型:无
- *备注:无
- */
-void LinkCheck_OFF(void)
-{
- TIM_Cmd(TIM13,DISABLE);
-}
-
-/*
- *函数简介:TIM13定时器更新中断函数
- *参数说明:无
- *返回类型:无
- *备注:进入中断即发生CAN设备掉线
- */
-void TIM8_UP_TIM13_IRQHandler(void)
-{
- if(TIM_GetITStatus(TIM13,TIM_IT_Update)==SET)//检测TIM2更新
- {
- TIM_ClearITPendingBit(TIM13,TIM_IT_Update);//清除标志位
- LinkCheck_Error=1;//连接错误
- }
-}
diff --git a/底盘/底盘-old/底盘/Function/LinkCheck.h b/底盘/底盘-old/底盘/Function/LinkCheck.h
deleted file mode 100644
index 97e90ae..0000000
--- a/底盘/底盘-old/底盘/Function/LinkCheck.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __LINKCHECK_H
-#define __LINKCHECK_H
-
-extern uint8_t LinkCheck_Error;//连接错误标志位
-
-void LinkCheck_Init(void);//CAN设备连接检测初始化
-void LinkCheck_ON(void);//开启掉线检查
-void LinkCheck_OFF(void);//关闭掉线检测
-
-#endif
diff --git a/底盘/底盘-old/底盘/Function/Warming.c b/底盘/底盘-old/底盘/Function/Warming.c
deleted file mode 100644
index 93258aa..0000000
--- a/底盘/底盘-old/底盘/Function/Warming.c
+++ /dev/null
@@ -1,188 +0,0 @@
-#include "stm32f4xx.h" // Device header
-#include "stm32f4xx_conf.h"
-#include "LED.h"
-#include "Buzzer.h"
-#include "CAN.h"
-#include "Delay.h"
-#include "M3508.h"
-#include "UI_Library.h"
-
-/*==================== 报警列表 ====================
- 遥控器未连接 ················1s里红灯连闪两下
- 遥控器数据错误报警 ············红灯常亮
- CAN总线设备连接异常············2s内蜂鸣器以高音6响n下,n为CAN.c文件里ID列表的索引
- IST8310连接错误 ················绿灯以1s为周期闪烁
- BMI088连接错误 ················1s里绿灯连闪两下
- 陀螺仪温度过高报警 ············绿灯常亮
- 电机报警状态 ················电机静止
- 自定义UI显示警告 ············所有状态指示灯变成红或蓝
- ======================================================*/
-
-/*
- *函数简介:报警初始化
- *参数说明:无
- *返回类型:无
- *备注:报警功能用于各种错误的提示
- *备注:报警有两种方式-LED和蜂鸣器
- */
-void Warming_Init(void)
-{
- LED_Init();
- Buzzer_Init();
-}
-
-/*
- *函数简介:报警关闭
- *参数说明:无
- *返回类型:无
- *备注:无
- */
-void Warming_Stop(void)
-{
- TIM_SetCompare1(TIM10,0);
-}
-
-/*
- *函数简介:报警LED清理
- *参数说明:无
- *返回类型:无
- *备注:关闭所有灯
- */
-void Warming_LEDClean(void)
-{
- LED_BOFF();LED_GOFF();LED_ROFF();
-}
-
-/*
- *函数简介:报警蜂鸣器清理
- *参数说明:无
- *返回类型:无
- *备注:关闭所有蜂鸣器
- */
-void Warming_BuzzerClean(void)
-{
- Buzzer_ON(P);
-}
-
-/*
- *函数简介:遥控器未连接报警
- *参数说明:无
- *返回类型:无
- *备注:遥控器连接检测TIM7定时更新中断调用,定时25ms
- *报警现象:1s里红灯连闪两下
- */
-void Warming_RemoteNoCheck(void)
-{
- static uint8_t Counter=0;
- Counter++;
-
- if(Counter==1)LED_RON();
- else if(Counter==5)LED_ROFF();
- else if(Counter==13)LED_RON();
- else if(Counter==17)LED_ROFF();
- else if(Counter==40)Counter=0;
-}
-
-/*
- *函数简介:遥控器数据错误报警
- *参数说明:无
- *返回类型:无
- *报警现象:红灯常量
- */
-void Warming_RemoteDataERROR(void)
-{
- LED_RON();
-}
-
-/*
- *函数简介:CAN总线设备连接异常报警
- *参数说明:无
- *返回类型:无
-
- *备注:闭环控制TIM6定时更新中断调用,定时2ms
- *报警现象:2s内蜂鸣器以高音6响n下,n为连接异常的设备在ID列表的索引(CAN.h文件中CAN_IDSelect变量)
- */
-void Warming_LinkError(void)
-{
- static uint8_t i=0;
- static uint16_t Counter=0;
- Counter++;
-
- if(iDR);//外设地址(USART的DR数据接收寄存器)
- DMA_InitStructure.DMA_PeripheralBurst=DMA_PeripheralBurst_Single;//外设突发单次传输
- DMA_InitStructure.DMA_PeripheralDataSize=DMA_PeripheralDataSize_Byte;//外设数据长度为1字节(8bits)
- DMA_InitStructure.DMA_PeripheralInc=DMA_PeripheralInc_Disable;//外设地址不自增
- DMA_InitStructure.DMA_Memory0BaseAddr=(uint32_t)Remote_RxData0;//存储器地址(遥控器DMA数据存储器0)
- DMA_InitStructure.DMA_MemoryBurst=DMA_MemoryBurst_Single;//存储器突发单次传输
- DMA_InitStructure.DMA_MemoryDataSize=DMA_MemoryDataSize_Byte;//存储器数据长度为1字节(8bits)
- DMA_InitStructure.DMA_MemoryInc=DMA_MemoryInc_Enable;//存储器地址自增
- DMA_InitStructure.DMA_FIFOMode=DMA_FIFOMode_Disable;//不使用FIFO模式
- DMA_InitStructure.DMA_FIFOThreshold=DMA_FIFOStatus_1QuarterFull;//设置FIFO阈值为1/4(不使用FIFO模式时,此位无意义)
- DMA_Init(DMA1_Stream1,&DMA_InitStructure);//初始化数据流1
-
- DMA_DoubleBufferModeConfig(DMA1_Stream1,(uint32_t)Remote_RxData1,DMA_Memory_0);//设置双缓冲搬运从遥控器DMA数据存储器0开始
- DMA_DoubleBufferModeCmd(DMA1_Stream1,ENABLE);//使能DMA双缓冲功能
-
- /*===============配置定时器===============*/
- TIM_InternalClockConfig(TIM7);//选择时基单元的时钟(TIM7)
-
- TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure;//配置时基单元（配置参数）
- TIM_TimeBaseInitStructure.TIM_ClockDivision=TIM_CKD_DIV1;//配置时钟分频为1分频
- TIM_TimeBaseInitStructure.TIM_CounterMode=TIM_CounterMode_Up;//配置计数器模式为向上计数
- TIM_TimeBaseInitStructure.TIM_Period=2100-1;//配置自动重装值ARR
- TIM_TimeBaseInitStructure.TIM_Prescaler=1000-1;//配置分频值PSC,默认定时25ms
- TIM_TimeBaseInitStructure.TIM_RepetitionCounter=0;//配置重复计数单元的置为0
- TIM_TimeBaseInit(TIM7,&TIM_TimeBaseInitStructure);//初始化TIM7
-
- TIM_ClearFlag(TIM7,TIM_FLAG_Update);//清除配置时基单元产生的中断标志位
-
- /*===============配置接收中断和定时器中断===============*/
- USART_ITConfig(USART3,USART_IT_RXNE,ENABLE);//打通USART3到NVIC的串口接收中断通道
- TIM_ITConfig(TIM7,TIM_IT_Update,ENABLE);//使能TIM7更新中断
-
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//选择NVIC分组2(2位抢占优先级,2位响应优先级)
-
- NVIC_InitTypeDef NVIC_InitStructure;
- NVIC_InitStructure.NVIC_IRQChannel=USART3_IRQn;//选择USART3中断通道
- NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;//使能中断通道
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=1;//抢占优先级为1
- NVIC_InitStructure.NVIC_IRQChannelSubPriority=1;//响应优先级为1
- NVIC_Init(&NVIC_InitStructure);//初始化USART3的NVIC
- NVIC_InitStructure.NVIC_IRQChannel=TIM7_IRQn;//选择中断通道为TIM2
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=2;//TIM2的抢占优先级
- NVIC_InitStructure.NVIC_IRQChannelSubPriority=2;//TIM2的响应优先级
- NVIC_Init(&NVIC_InitStructure);//初始化NVIC
-
- /*===============使能===============*/
- DMA_Cmd(DMA1_Stream1,ENABLE);//使能DMA1的数据流1
- USART_DMACmd(USART3,USART_DMAReq_Rx,ENABLE);//使能串口USART3的DMA搬运
- USART_Cmd(USART3,ENABLE);//启动USART3
- TIM_Cmd(TIM7,ENABLE);//启动定时器
-
- /*===============配置IWDG===============*/
- IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
- IWDG_SetPrescaler(IWDG_Prescaler_8);//8分频
- IWDG_SetReload(0x0FFF);//设置重装载值
- IWDG_Enable();
-}
-
-/*
- *函数简介:遥控器开启
- *参数说明:无
- *返回类型:无
- *备注:默认开启串口USART3
- */
-void Remote_ON(void)
-{
- USART_Cmd(USART3,ENABLE);//启动USART3
-}
-
-/*
- *函数简介:遥控器关闭
- *参数说明:无
- *返回类型:无
- *备注:默认关闭串口USART3
- */
-void Remote_OFF(void)
-{
- USART_Cmd(USART3,DISABLE);//失能USART3
- Remote_Status=0;//遥控器连接状态变为未连接
-}
-
-/*
- *函数简介:遥控器DMA转运复位
- *参数说明:无
- *返回类型:无
- *备注:无
- */
-void Remote_TransferReset(void)
-{
- while(DMA_GetFlagStatus(DMA1_Stream1,DMA_FLAG_TCIF1)==RESET);//判断接收完成
- DMA_ClearFlag(DMA1_Stream1,DMA_FLAG_TCIF1);//清除接收完成标志位
- DMA_Cmd(DMA1_Stream1,DISABLE);//失能DMA1的数据流1
- while(DMA_GetCmdStatus(DMA1_Stream1)!=DISABLE);//检测DMA1的数据流1为可配置状态
- DMA_SetCurrDataCounter(DMA1_Stream1,18);//恢复传输计数器的值
- DMA_Cmd(DMA1_Stream1,ENABLE);//使能DMA1的数据流1
-}
-
-/*
- *函数简介:遥控器数据处理
- *参数说明:无
- *返回类型:无
- *备注:遥控器接收数据共18Bytes(144bits)
- */
-void Remote_DataProcess(void)
-{
- uint8_t *Data;//选择存储器
- if(DMA_GetCurrentMemoryTarget(DMA1_Stream1)==0)Data=Remote_RxData1;//若当前转运位于存储器0,则存储器1数据完整,采用存储器1进行数据处理
- else Data=Remote_RxData0;//若当前转运位于存储器1,则存储器0数据完整,采用存储器0进行数据处理
-
- Remote_RxData.Remote_R_RL=(((uint16_t)Data[1]<<8) | Data[0]) & 0x07FF;//B[0:10],11bits
- Remote_RxData.Remote_R_UD=(((uint16_t)Data[2]<<5) | (Data[1]>>3)) & 0x07FF;//B[11:21],11bits
- Remote_RxData.Remote_L_RL=(((uint16_t)Data[4]<<10) | (((uint16_t)Data[3]<<2) | (Data[2]>>6))) & 0x07FF;//B[22:32],11bits
- Remote_RxData.Remote_L_UD=(((uint16_t)Data[5]<<7) | (Data[4]>>1)) & 0x07FF;//B[33:43],11bits
-
- Remote_RxData.Remote_RS=(Data[5]>>4) & 0x03;//B[44:45],2bits
- Remote_RxData.Remote_LS=(Data[5]>>6) & 0x03;//B[46:47],2bits
-
- Remote_RxData.Remote_Mouse_RL=(int16_t)(((uint16_t)Data[7]<<8) | Data[6]);//B[48:63],16bits
- Remote_RxData.Remote_Mouse_DU=(int16_t)(((uint16_t)Data[9]<<8) | Data[8]);//B[64:79],16bits
- Remote_RxData.Remote_Mouse_Wheel=(int16_t)(((uint16_t)Data[11]<<8) | Data[10]);//B[80:95],16bits
- Remote_RxData.Remote_Mouse_KeyL=Data[12];//B[96:103],8bits
- Remote_RxData.Remote_Mouse_KeyR=Data[13];//B[104:111],8bits
-
- Remote_RxData.Remote_Key_W=Data[14] & 0x01;//B[112:112],1bits
- Remote_RxData.Remote_Key_S=(Data[14]>>1) & 0x01;//B[113:113],1bits
- Remote_RxData.Remote_Key_A=(Data[14]>>2) & 0x01;//B[114:114],1bits
- Remote_RxData.Remote_Key_D=(Data[14]>>3) & 0x01;//B[115:115],1bits
- Remote_RxData.Remote_Key_Shift=(Data[14]>>4) & 0x01;//B[116:116],1bits
- Remote_RxData.Remote_Key_Ctrl=(Data[14]>>5) & 0x01;//B[117:117],1bits
- Remote_RxData.Remote_Key_Q=(Data[14]>>6) & 0x01;//B[118:118],1bits
- Remote_RxData.Remote_Key_E=(Data[14]>>7) & 0x01;//B[119:119],1bits
-
- Remote_RxData.Remote_ThumbWheel=(int16_t)((uint16_t)Data[17]<<8) | Data[16];//B[120:135],16bits
-}
-
-/*
- *函数简介:遥控器接收中断
- *参数说明:无
- *返回类型:无
- *备注:USART的接收中断
- */
-void USART3_IRQHandler(void)
-{
- TIM_SetCounter(TIM7,0);
- TIM_Cmd(TIM7,DISABLE);//关闭定时器并重置计数值
- if(DMA_GetCurrDataCounter(DMA1_Stream1)==18)//转运一次完成,并交换了存储器
- {
- Remote_TransferReset();//复位DMA1的数据流1
- Remote_DataProcess();//数据处理
- if(Remote_StartFlag==1)//第一次接收数据
- {
- while(Remote_RxData.Remote_R_RL!=1024 || Remote_RxData.Remote_R_UD!=1024 || Remote_RxData.Remote_L_RL!=1024 || Remote_RxData.Remote_L_UD!=1024)//数据错误
- Warming_RemoteDataERROR();//数据错误报错,等待看门狗复位
- Remote_StartFlag=2;
- Warming_LEDClean();
- }
- Remote_Status=1;//遥控器已连接
- }
- TIM_Cmd(TIM7,ENABLE);//开启定时
-
- USART_ClearITPendingBit(USART3,USART_IT_RXNE);//清除接收中断标志位
-}
-
-/*
- *函数简介:TIM7定时器更新中断函数
- *参数说明:无
- *返回类型:无
- *备注:进入中断即遥控器未连接
- */
-void TIM7_IRQHandler(void)
-{
- if(TIM_GetITStatus(TIM7,TIM_IT_Update)==SET)//检测TIM2更新
- {
- TIM_ClearITPendingBit(TIM7,TIM_IT_Update);//清除标志位
- Warming_RemoteNoCheck();//遥控器未连接报警
- Remote_Status=0;//遥控器连接状态变为未连接
- Remote_StartFlag=1;//遥控器处于准备启动阶段
- }
-}
-
diff --git a/底盘/底盘-old/底盘/Hardware/Remote.h b/底盘/底盘-old/底盘/Hardware/Remote.h
deleted file mode 100644
index d77d54b..0000000
--- a/底盘/底盘-old/底盘/Hardware/Remote.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#ifndef __REMOTE_H
-#define __REMOTE_H
-
-typedef struct
-{
- uint16_t Remote_R_RL;//通道0-右摇杆左右(右为大),范围364(最左端)~1684(最右端),默认值1024(中间)
- uint16_t Remote_R_UD;//通道1-右摇杆上下(上为大),范围364(最下端)~1684(最上端),默认值1024(中间)
- uint16_t Remote_L_RL;//通道2-左摇杆左右(右为大),范围364(最左端)~1684(最右端),默认值1024(中间)
- uint16_t Remote_L_UD;//通道3-左摇杆上下(上为大),范围364(最下端)~1684(最上端),默认值1024(中间)
-
- uint8_t Remote_LS;//S1-左侧拨动开关,范围1~3,上为1,下为2,中间为3
- uint8_t Remote_RS;//S2-右侧拨动开关,范围1~3,上为1,下为2,中间为3
-
- int16_t Remote_Mouse_RL;//鼠标X轴-鼠标左右速度,范围-32768~32767,向右为正,向左为负,静止值为0
- int16_t Remote_Mouse_DU;//鼠标Y轴-鼠标前后速度,范围-32768~32767,向后为正,向前为负,静止值为0
- int16_t Remote_Mouse_Wheel;//鼠标Z轴-鼠标滚轮速度,范围-32768~32767,向前为正,向后为负,静止值为0
- uint8_t Remote_Mouse_KeyL;//鼠标左键,按下为1,未按下为0
- uint8_t Remote_Mouse_KeyR;//鼠标右键,按下为1,未按下为0
-
- uint8_t Remote_Key_1;//键盘1键,按下为1,未按下为0
- uint8_t Remote_Key_2;//键盘2键,按下为1,未按下为0
-
- uint8_t Remote_Key_W;//键盘W键,按下为1,未按下为0
- uint8_t Remote_Key_S;//键盘S键,按下为1,未按下为0
- uint8_t Remote_Key_A;//键盘A键,按下为1,未按下为0
- uint8_t Remote_Key_D;//键盘D键,按下为1,未按下为0
- uint8_t Remote_Key_Q;//键盘Q键,按下为1,未按下为0
- uint8_t Remote_Key_E;//键盘E键,按下为1,未按下为0
- uint8_t Remote_Key_Shift;//键盘Shift键,按下为1,未按下为0
- uint8_t Remote_Key_Ctrl;//键盘Ctrl键,按下为1,未按下为0
- uint8_t Remote_KeyLast_Shift;//上一次键盘Shift键
- uint8_t Remote_KeyLast_Ctrl;//上一次键盘Ctrl键
- uint8_t Remote_KeyPush_Ctrl;//按下键盘Ctrl键,按下时0,1切换
- uint8_t Remote_KeyPush_Shift;//按下键盘Shift键,按下时0,1切换
-
- int16_t Remote_ThumbWheel;//保留字段-遥控器拨轮,范围-3278(最上端)~1684(最下端),默认值1024
-}Remote_Data;//遥控器接收结构体
-
-extern Remote_Data Remote_RxData;//遥控器接收数据
-extern uint8_t Remote_Status;//遥控器连接状态,默认未连接(0)
-extern uint8_t Remote_StartFlag;//遥控器启动标志位,0-未在启动阶段,1-准备启动,2-第一次接收到数据
-
-void Remote_Init(void);//遥控器初始化
-void Remote_ON(void);//遥控器开启
-void Remote_OFF(void);//遥控器关闭
-
-#endif
diff --git a/底盘/底盘-old/底盘/Library/misc.c b/底盘/底盘-old/底盘/Library/misc.c
deleted file mode 100644
index 0bde31a..0000000
--- a/底盘/底盘-old/底盘/Library/misc.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/**
- ******************************************************************************
- * @file misc.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides all the miscellaneous firmware functions (add-on
- * to CMSIS functions).
- *
- * @verbatim
- *
- * ===================================================================
- * How to configure Interrupts using driver
- * ===================================================================
- *
- * This section provide functions allowing to configure the NVIC interrupts (IRQ).
- * The Cortex-M4 exceptions are managed by CMSIS functions.
- *
- * 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
- * function according to the following table.
-
- * The table below gives the allowed values of the pre-emption priority and subpriority according
- * to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
- * ==========================================================================================================================
- * NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
- * ==========================================================================================================================
- * NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
- * | | | 4 bits for subpriority
- * --------------------------------------------------------------------------------------------------------------------------
- * NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
- * | | | 3 bits for subpriority
- * --------------------------------------------------------------------------------------------------------------------------
- * NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
- * | | | 2 bits for subpriority
- * --------------------------------------------------------------------------------------------------------------------------
- * NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
- * | | | 1 bits for subpriority
- * --------------------------------------------------------------------------------------------------------------------------
- * NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
- * | | | 0 bits for subpriority
- * ==========================================================================================================================
- *
- * 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init()
- *
- * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
- * The pending IRQ priority will be managed only by the subpriority.
- *
- * @note IRQ priority order (sorted by highest to lowest priority):
- * - Lowest pre-emption priority
- * - Lowest subpriority
- * - Lowest hardware priority (IRQ number)
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "misc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup MISC
- * @brief MISC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup MISC_Private_Functions
- * @{
- */
-
-/**
- * @brief Configures the priority grouping: pre-emption priority and subpriority.
- * @param NVIC_PriorityGroup: specifies the priority grouping bits length.
- * This parameter can be one of the following values:
- * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
- * 4 bits for subpriority
- * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
- * 3 bits for subpriority
- * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
- * 2 bits for subpriority
- * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
- * 1 bits for subpriority
- * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
- * 0 bits for subpriority
- * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
- * The pending IRQ priority will be managed only by the subpriority.
- * @retval None
- */
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
-
- /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
- SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
-}
-
-/**
- * @brief Initializes the NVIC peripheral according to the specified
- * parameters in the NVIC_InitStruct.
- * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
- * function should be called before.
- * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
- * the configuration information for the specified NVIC peripheral.
- * @retval None
- */
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
-{
- uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
- assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
-
- if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
- {
- /* Compute the Corresponding IRQ Priority --------------------------------*/
- tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
- tmppre = (0x4 - tmppriority);
- tmpsub = tmpsub >> tmppriority;
-
- tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
- tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
-
- tmppriority = tmppriority << 0x04;
-
- NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
-
- /* Enable the Selected IRQ Channels --------------------------------------*/
- NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
- (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
- }
- else
- {
- /* Disable the Selected IRQ Channels -------------------------------------*/
- NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
- (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
- }
-}
-
-/**
- * @brief Sets the vector table location and Offset.
- * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
- * This parameter can be one of the following values:
- * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.
- * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.
- * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.
- * @retval None
- */
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
- assert_param(IS_NVIC_OFFSET(Offset));
-
- SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
-}
-
-/**
- * @brief Selects the condition for the system to enter low power mode.
- * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
- * This parameter can be one of the following values:
- * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
- * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
- * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
- * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_LP(LowPowerMode));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- SCB->SCR |= LowPowerMode;
- }
- else
- {
- SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
- }
-}
-
-/**
- * @brief Configures the SysTick clock source.
- * @param SysTick_CLKSource: specifies the SysTick clock source.
- * This parameter can be one of the following values:
- * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
- * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
- * @retval None
- */
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
-{
- /* Check the parameters */
- assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
- if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
- {
- SysTick->CTRL |= SysTick_CLKSource_HCLK;
- }
- else
- {
- SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/misc.h b/底盘/底盘-old/底盘/Library/misc.h
deleted file mode 100644
index e08161c..0000000
--- a/底盘/底盘-old/底盘/Library/misc.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/**
- ******************************************************************************
- * @file misc.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the miscellaneous
- * firmware library functions (add-on to CMSIS functions).
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __MISC_H
-#define __MISC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup MISC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief NVIC Init Structure definition
- */
-
-typedef struct
-{
- uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
- This parameter can be an enumerator of @ref IRQn_Type
- enumeration (For the complete STM32 Devices IRQ Channels
- list, please refer to stm32f4xx.h file) */
-
- uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
- specified in NVIC_IRQChannel. This parameter can be a value
- between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
- A lower priority value indicates a higher priority */
-
- uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
- in NVIC_IRQChannel. This parameter can be a value
- between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
- A lower priority value indicates a higher priority */
-
- FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
- will be enabled or disabled.
- This parameter can be set either to ENABLE or DISABLE */
-} NVIC_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup MISC_Exported_Constants
- * @{
- */
-
-/** @defgroup MISC_Vector_Table_Base
- * @{
- */
-
-#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
-#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
-#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
- ((VECTTAB) == NVIC_VectTab_FLASH))
-/**
- * @}
- */
-
-/** @defgroup MISC_System_Low_Power
- * @{
- */
-
-#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
-#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
-#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
-#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
- ((LP) == NVIC_LP_SLEEPDEEP) || \
- ((LP) == NVIC_LP_SLEEPONEXIT))
-/**
- * @}
- */
-
-/** @defgroup MISC_Preemption_Priority_Group
- * @{
- */
-
-#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
- 4 bits for subpriority */
-#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
- 3 bits for subpriority */
-#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
- 2 bits for subpriority */
-#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
- 1 bits for subpriority */
-#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
- 0 bits for subpriority */
-
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
- ((GROUP) == NVIC_PriorityGroup_1) || \
- ((GROUP) == NVIC_PriorityGroup_2) || \
- ((GROUP) == NVIC_PriorityGroup_3) || \
- ((GROUP) == NVIC_PriorityGroup_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
-
-#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
-
-/**
- * @}
- */
-
-/** @defgroup MISC_SysTick_clock_source
- * @{
- */
-
-#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
-#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
- ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __MISC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_adc.c b/底盘/底盘-old/底盘/Library/stm32f4xx_adc.c
deleted file mode 100644
index 3badce2..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_adc.c
+++ /dev/null
@@ -1,1737 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_adc.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC) peripheral:
- * + Initialization and Configuration (in addition to ADC multi mode
- * selection)
- * + Analog Watchdog configuration
- * + Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT
- * management
- * + Regular Channels Configuration
- * + Regular Channels DMA Configuration
- * + Injected channels Configuration
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable the ADC interface clock using
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE);
-
- (#) ADC pins configuration
- (++) Enable the clock for the ADC GPIOs using the following function:
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
- (++) Configure these ADC pins in analog mode using GPIO_Init();
-
- (#) Configure the ADC Prescaler, conversion resolution and data
- alignment using the ADC_Init() function.
- (#) Activate the ADC peripheral using ADC_Cmd() function.
-
- *** Regular channels group configuration ***
- ============================================
- [..]
- (+) To configure the ADC regular channels group features, use
- ADC_Init() and ADC_RegularChannelConfig() functions.
- (+) To activate the continuous mode, use the ADC_continuousModeCmd()
- function.
- (+) To configurate and activate the Discontinuous mode, use the
- ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.
- (+) To read the ADC converted values, use the ADC_GetConversionValue()
- function.
-
- *** Multi mode ADCs Regular channels configuration ***
- ======================================================
- [..]
- (+) Refer to "Regular channels group configuration" description to
- configure the ADC1, ADC2 and ADC3 regular channels.
- (+) Select the Multi mode ADC regular channels features (dual or
- triple mode) using ADC_CommonInit() function and configure
- the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd()
- functions.
- (+) Read the ADCs converted values using the
- ADC_GetMultiModeConversionValue() function.
-
- *** DMA for Regular channels group features configuration ***
- =============================================================
- [..]
- (+) To enable the DMA mode for regular channels group, use the
- ADC_DMACmd() function.
- (+) To enable the generation of DMA requests continuously at the end
- of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd()
- function.
-
- *** Injected channels group configuration ***
- =============================================
- [..]
- (+) To configure the ADC Injected channels group features, use
- ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig()
- functions.
- (+) To activate the continuous mode, use the ADC_continuousModeCmd()
- function.
- (+) To activate the Injected Discontinuous mode, use the
- ADC_InjectedDiscModeCmd() function.
- (+) To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd()
- function.
- (+) To read the ADC converted values, use the ADC_GetInjectedConversionValue()
- function.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_adc.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup ADC
- * @brief ADC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ADC DISCNUM mask */
-#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)
-
-/* ADC AWDCH mask */
-#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0)
-
-/* ADC Analog watchdog enable mode mask */
-#define CR1_AWDMode_RESET ((uint32_t)0xFF3FFDFF)
-
-/* CR1 register Mask */
-#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF)
-
-/* ADC EXTEN mask */
-#define CR2_EXTEN_RESET ((uint32_t)0xCFFFFFFF)
-
-/* ADC JEXTEN mask */
-#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF)
-
-/* ADC JEXTSEL mask */
-#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF)
-
-/* CR2 register Mask */
-#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD)
-
-/* ADC SQx mask */
-#define SQR3_SQ_SET ((uint32_t)0x0000001F)
-#define SQR2_SQ_SET ((uint32_t)0x0000001F)
-#define SQR1_SQ_SET ((uint32_t)0x0000001F)
-
-/* ADC L Mask */
-#define SQR1_L_RESET ((uint32_t)0xFF0FFFFF)
-
-/* ADC JSQx mask */
-#define JSQR_JSQ_SET ((uint32_t)0x0000001F)
-
-/* ADC JL mask */
-#define JSQR_JL_SET ((uint32_t)0x00300000)
-#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF)
-
-/* ADC SMPx mask */
-#define SMPR1_SMP_SET ((uint32_t)0x00000007)
-#define SMPR2_SMP_SET ((uint32_t)0x00000007)
-
-/* ADC JDRx registers offset */
-#define JDR_OFFSET ((uint8_t)0x28)
-
-/* ADC CDR register base address */
-#define CDR_ADDRESS ((uint32_t)0x40012308)
-
-/* ADC CCR register Mask */
-#define CR_CLEAR_MASK ((uint32_t)0xFFFC30E0)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Functions
- * @{
- */
-
-/** @defgroup ADC_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the ADC Prescaler
- (+) ADC Conversion Resolution (12bit..6bit)
- (+) Scan Conversion Mode (multichannel or one channel) for regular group
- (+) ADC Continuous Conversion Mode (Continuous or Single conversion) for
- regular group
- (+) External trigger Edge and source of regular group,
- (+) Converted data alignment (left or right)
- (+) The number of ADC conversions that will be done using the sequencer for
- regular channel group
- (+) Multi ADC mode selection
- (+) Direct memory access mode selection for multi ADC mode
- (+) Delay between 2 sampling phases (used in dual or triple interleaved modes)
- (+) Enable or disable the ADC peripheral
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes all ADCs peripherals registers to their default reset
- * values.
- * @param None
- * @retval None
- */
-void ADC_DeInit(void)
-{
- /* Enable all ADCs reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE);
-
- /* Release all ADCs from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE);
-}
-
-/**
- * @brief Initializes the ADCx peripheral according to the specified parameters
- * in the ADC_InitStruct.
- * @note This function is used to configure the global features of the ADC (
- * Resolution and Data Alignment), however, the rest of the configuration
- * parameters are specific to the regular channels group (scan mode
- * activation, continuous mode activation, External trigger source and
- * edge, number of conversion in the regular channels group sequencer).
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
- * the configuration information for the specified ADC peripheral.
- * @retval None
- */
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
-{
- uint32_t tmpreg1 = 0;
- uint8_t tmpreg2 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution));
- assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
- assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
- assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge));
- assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));
- assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
- assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion));
-
- /*---------------------------- ADCx CR1 Configuration -----------------*/
- /* Get the ADCx CR1 value */
- tmpreg1 = ADCx->CR1;
-
- /* Clear RES and SCAN bits */
- tmpreg1 &= CR1_CLEAR_MASK;
-
- /* Configure ADCx: scan conversion mode and resolution */
- /* Set SCAN bit according to ADC_ScanConvMode value */
- /* Set RES bit according to ADC_Resolution value */
- tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \
- ADC_InitStruct->ADC_Resolution);
- /* Write to ADCx CR1 */
- ADCx->CR1 = tmpreg1;
- /*---------------------------- ADCx CR2 Configuration -----------------*/
- /* Get the ADCx CR2 value */
- tmpreg1 = ADCx->CR2;
-
- /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */
- tmpreg1 &= CR2_CLEAR_MASK;
-
- /* Configure ADCx: external trigger event and edge, data alignment and
- continuous conversion mode */
- /* Set ALIGN bit according to ADC_DataAlign value */
- /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */
- /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
- /* Set CONT bit according to ADC_ContinuousConvMode value */
- tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \
- ADC_InitStruct->ADC_ExternalTrigConv |
- ADC_InitStruct->ADC_ExternalTrigConvEdge | \
- ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
-
- /* Write to ADCx CR2 */
- ADCx->CR2 = tmpreg1;
- /*---------------------------- ADCx SQR1 Configuration -----------------*/
- /* Get the ADCx SQR1 value */
- tmpreg1 = ADCx->SQR1;
-
- /* Clear L bits */
- tmpreg1 &= SQR1_L_RESET;
-
- /* Configure ADCx: regular channel sequence length */
- /* Set L bits according to ADC_NbrOfConversion value */
- tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1);
- tmpreg1 |= ((uint32_t)tmpreg2 << 20);
-
- /* Write to ADCx SQR1 */
- ADCx->SQR1 = tmpreg1;
-}
-
-/**
- * @brief Fills each ADC_InitStruct member with its default value.
- * @note This function is used to initialize the global features of the ADC (
- * Resolution and Data Alignment), however, the rest of the configuration
- * parameters are specific to the regular channels group (scan mode
- * activation, continuous mode activation, External trigger source and
- * edge, number of conversion in the regular channels group sequencer).
- * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
-{
- /* Initialize the ADC_Mode member */
- ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
-
- /* initialize the ADC_ScanConvMode member */
- ADC_InitStruct->ADC_ScanConvMode = DISABLE;
-
- /* Initialize the ADC_ContinuousConvMode member */
- ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
-
- /* Initialize the ADC_ExternalTrigConvEdge member */
- ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
-
- /* Initialize the ADC_ExternalTrigConv member */
- ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
-
- /* Initialize the ADC_DataAlign member */
- ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
-
- /* Initialize the ADC_NbrOfConversion member */
- ADC_InitStruct->ADC_NbrOfConversion = 1;
-}
-
-/**
- * @brief Initializes the ADCs peripherals according to the specified parameters
- * in the ADC_CommonInitStruct.
- * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
- * that contains the configuration information for All ADCs peripherals.
- * @retval None
- */
-void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
-{
- uint32_t tmpreg1 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode));
- assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler));
- assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode));
- assert_param(IS_ADC_SAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay));
- /*---------------------------- ADC CCR Configuration -----------------*/
- /* Get the ADC CCR value */
- tmpreg1 = ADC->CCR;
-
- /* Clear MULTI, DELAY, DMA and ADCPRE bits */
- tmpreg1 &= CR_CLEAR_MASK;
-
- /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler,
- and DMA access mode for multimode */
- /* Set MULTI bits according to ADC_Mode value */
- /* Set ADCPRE bits according to ADC_Prescaler value */
- /* Set DMA bits according to ADC_DMAAccessMode value */
- /* Set DELAY bits according to ADC_TwoSamplingDelay value */
- tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode |
- ADC_CommonInitStruct->ADC_Prescaler |
- ADC_CommonInitStruct->ADC_DMAAccessMode |
- ADC_CommonInitStruct->ADC_TwoSamplingDelay);
-
- /* Write to ADC CCR */
- ADC->CCR = tmpreg1;
-}
-
-/**
- * @brief Fills each ADC_CommonInitStruct member with its default value.
- * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
-{
- /* Initialize the ADC_Mode member */
- ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent;
-
- /* initialize the ADC_Prescaler member */
- ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2;
-
- /* Initialize the ADC_DMAAccessMode member */
- ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
-
- /* Initialize the ADC_TwoSamplingDelay member */
- ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
-}
-
-/**
- * @brief Enables or disables the specified ADC peripheral.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the ADCx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the ADON bit to wake up the ADC from power down mode */
- ADCx->CR2 |= (uint32_t)ADC_CR2_ADON;
- }
- else
- {
- /* Disable the selected ADC peripheral */
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON);
- }
-}
-/**
- * @}
- */
-
-/** @defgroup ADC_Group2 Analog Watchdog configuration functions
- * @brief Analog Watchdog configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Analog Watchdog configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the Analog Watchdog
- (AWD) feature in the ADC.
-
- [..] A typical configuration Analog Watchdog is done following these steps :
- (#) the ADC guarded channel(s) is (are) selected using the
- ADC_AnalogWatchdogSingleChannelConfig() function.
- (#) The Analog watchdog lower and higher threshold are configured using the
- ADC_AnalogWatchdogThresholdsConfig() function.
- (#) The Analog watchdog is enabled and configured to enable the check, on one
- or more channels, using the ADC_AnalogWatchdogCmd() function.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the analog watchdog on single/all regular or
- * injected channels
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.
- * This parameter can be one of the following values:
- * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
- * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
- * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
- * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
- * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
- * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
- * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
- * @retval None
- */
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
-
- /* Get the old register value */
- tmpreg = ADCx->CR1;
-
- /* Clear AWDEN, JAWDEN and AWDSGL bits */
- tmpreg &= CR1_AWDMode_RESET;
-
- /* Set the analog watchdog enable mode */
- tmpreg |= ADC_AnalogWatchdog;
-
- /* Store the new register value */
- ADCx->CR1 = tmpreg;
-}
-
-/**
- * @brief Configures the high and low thresholds of the analog watchdog.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param HighThreshold: the ADC analog watchdog High threshold value.
- * This parameter must be a 12-bit value.
- * @param LowThreshold: the ADC analog watchdog Low threshold value.
- * This parameter must be a 12-bit value.
- * @retval None
- */
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
- uint16_t LowThreshold)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_THRESHOLD(HighThreshold));
- assert_param(IS_ADC_THRESHOLD(LowThreshold));
-
- /* Set the ADCx high threshold */
- ADCx->HTR = HighThreshold;
-
- /* Set the ADCx low threshold */
- ADCx->LTR = LowThreshold;
-}
-
-/**
- * @brief Configures the analog watchdog guarded single channel
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_0: ADC Channel0 selected
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @arg ADC_Channel_18: ADC Channel18 selected
- * @retval None
- */
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
-
- /* Get the old register value */
- tmpreg = ADCx->CR1;
-
- /* Clear the Analog watchdog channel select bits */
- tmpreg &= CR1_AWDCH_RESET;
-
- /* Set the Analog watchdog channel */
- tmpreg |= ADC_Channel;
-
- /* Store the new register value */
- ADCx->CR1 = tmpreg;
-}
-/**
- * @}
- */
-
-/** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal)
- * and VBAT (Voltage BATtery) management functions
- * @brief Temperature Sensor, Vrefint and VBAT management functions
- *
-@verbatim
- ===============================================================================
- ##### Temperature Sensor, Vrefint and VBAT management functions #####
- ===============================================================================
- [..] This section provides functions allowing to enable/ disable the internal
- connections between the ADC and the Temperature Sensor, the Vrefint and
- the Vbat sources.
-
- [..] A typical configuration to get the Temperature sensor and Vrefint channels
- voltages is done following these steps :
- (#) Enable the internal connection of Temperature sensor and Vrefint sources
- with the ADC channels using ADC_TempSensorVrefintCmd() function.
- (#) Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using
- ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions
- (#) Get the voltage values, using ADC_GetConversionValue() or
- ADC_GetInjectedConversionValue().
-
- [..] A typical configuration to get the VBAT channel voltage is done following
- these steps :
- (#) Enable the internal connection of VBAT source with the ADC channel using
- ADC_VBATCmd() function.
- (#) Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or
- ADC_InjectedChannelConfig() functions
- (#) Get the voltage value, using ADC_GetConversionValue() or
- ADC_GetInjectedConversionValue().
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Enables or disables the temperature sensor and Vrefint channels.
- * @param NewState: new state of the temperature sensor and Vrefint channels.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_TempSensorVrefintCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the temperature sensor and Vrefint channel*/
- ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE;
- }
- else
- {
- /* Disable the temperature sensor and Vrefint channel*/
- ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE);
- }
-}
-
-/**
- * @brief Enables or disables the VBAT (Voltage Battery) channel.
- *
- * @note the Battery voltage measured is equal to VBAT/2 on STM32F40xx and
- * STM32F41xx devices and equal to VBAT/4 on STM32F42xx and STM32F43xx devices
- *
- * @param NewState: new state of the VBAT channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_VBATCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the VBAT channel*/
- ADC->CCR |= (uint32_t)ADC_CCR_VBATE;
- }
- else
- {
- /* Disable the VBAT channel*/
- ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Group4 Regular Channels Configuration functions
- * @brief Regular Channels Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Regular Channels Configuration functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to manage the ADC's regular channels,
- it is composed of 2 sub sections :
-
- (#) Configuration and management functions for regular channels: This subsection
- provides functions allowing to configure the ADC regular channels :
- (++) Configure the rank in the regular group sequencer for each channel
- (++) Configure the sampling time for each channel
- (++) select the conversion Trigger for regular channels
- (++) select the desired EOC event behavior configuration
- (++) Activate the continuous Mode (*)
- (++) Activate the Discontinuous Mode
- -@@- Please Note that the following features for regular channels
- are configured using the ADC_Init() function :
- (+@@) scan mode activation
- (+@@) continuous mode activation (**)
- (+@@) External trigger source
- (+@@) External trigger edge
- (+@@) number of conversion in the regular channels group sequencer.
-
- -@@- (*) and (**) are performing the same configuration
-
- (#) Get the conversion data: This subsection provides an important function in
- the ADC peripheral since it returns the converted data of the current
- regular channel. When the Conversion value is read, the EOC Flag is
- automatically cleared.
-
- -@- For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions
- results data (in the selected multi mode) can be returned in the same
- time using ADC_GetMultiModeConversionValue() function.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Configures for the selected ADC regular channel its corresponding
- * rank in the sequencer and its sample time.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_0: ADC Channel0 selected
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @arg ADC_Channel_18: ADC Channel18 selected
- * @param Rank: The rank in the regular group sequencer.
- * This parameter must be between 1 to 16.
- * @param ADC_SampleTime: The sample time value to be set for the selected channel.
- * This parameter can be one of the following values:
- * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
- * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
- * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
- * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles
- * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles
- * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles
- * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles
- * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles
- * @retval None
- */
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
-{
- uint32_t tmpreg1 = 0, tmpreg2 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- assert_param(IS_ADC_REGULAR_RANK(Rank));
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
-
- /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
- if (ADC_Channel > ADC_Channel_9)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR1;
-
- /* Calculate the mask to clear */
- tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10));
-
- /* Clear the old sample time */
- tmpreg1 &= ~tmpreg2;
-
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
-
- /* Set the new sample time */
- tmpreg1 |= tmpreg2;
-
- /* Store the new register value */
- ADCx->SMPR1 = tmpreg1;
- }
- else /* ADC_Channel include in ADC_Channel_[0..9] */
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR2;
-
- /* Calculate the mask to clear */
- tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);
-
- /* Clear the old sample time */
- tmpreg1 &= ~tmpreg2;
-
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
-
- /* Set the new sample time */
- tmpreg1 |= tmpreg2;
-
- /* Store the new register value */
- ADCx->SMPR2 = tmpreg1;
- }
- /* For Rank 1 to 6 */
- if (Rank < 7)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SQR3;
-
- /* Calculate the mask to clear */
- tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1));
-
- /* Clear the old SQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
-
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
-
- /* Set the SQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
-
- /* Store the new register value */
- ADCx->SQR3 = tmpreg1;
- }
- /* For Rank 7 to 12 */
- else if (Rank < 13)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SQR2;
-
- /* Calculate the mask to clear */
- tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7));
-
- /* Clear the old SQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
-
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
-
- /* Set the SQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
-
- /* Store the new register value */
- ADCx->SQR2 = tmpreg1;
- }
- /* For Rank 13 to 16 */
- else
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SQR1;
-
- /* Calculate the mask to clear */
- tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13));
-
- /* Clear the old SQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
-
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
-
- /* Set the SQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
-
- /* Store the new register value */
- ADCx->SQR1 = tmpreg1;
- }
-}
-
-/**
- * @brief Enables the selected ADC software start conversion of the regular channels.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval None
- */
-void ADC_SoftwareStartConv(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Enable the selected ADC conversion for regular group */
- ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART;
-}
-
-/**
- * @brief Gets the selected ADC Software start regular conversion Status.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval The new state of ADC software start conversion (SET or RESET).
- */
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Check the status of SWSTART bit */
- if ((ADCx->CR2 & ADC_CR2_SWSTART) != (uint32_t)RESET)
- {
- /* SWSTART bit is set */
- bitstatus = SET;
- }
- else
- {
- /* SWSTART bit is reset */
- bitstatus = RESET;
- }
-
- /* Return the SWSTART bit status */
- return bitstatus;
-}
-
-
-/**
- * @brief Enables or disables the EOC on each regular channel conversion
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC EOC flag rising
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC EOC rising on each regular channel conversion */
- ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS;
- }
- else
- {
- /* Disable the selected ADC EOC rising on each regular channel conversion */
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS);
- }
-}
-
-/**
- * @brief Enables or disables the ADC continuous conversion mode
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC continuous conversion mode
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC continuous conversion mode */
- ADCx->CR2 |= (uint32_t)ADC_CR2_CONT;
- }
- else
- {
- /* Disable the selected ADC continuous conversion mode */
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT);
- }
-}
-
-/**
- * @brief Configures the discontinuous mode for the selected ADC regular group
- * channel.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param Number: specifies the discontinuous mode regular channel count value.
- * This number must be between 1 and 8.
- * @retval None
- */
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
-{
- uint32_t tmpreg1 = 0;
- uint32_t tmpreg2 = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
-
- /* Get the old register value */
- tmpreg1 = ADCx->CR1;
-
- /* Clear the old discontinuous mode channel count */
- tmpreg1 &= CR1_DISCNUM_RESET;
-
- /* Set the discontinuous mode channel count */
- tmpreg2 = Number - 1;
- tmpreg1 |= tmpreg2 << 13;
-
- /* Store the new register value */
- ADCx->CR1 = tmpreg1;
-}
-
-/**
- * @brief Enables or disables the discontinuous mode on regular group channel
- * for the specified ADC
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC discontinuous mode on
- * regular group channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC regular discontinuous mode */
- ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN;
- }
- else
- {
- /* Disable the selected ADC regular discontinuous mode */
- ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN);
- }
-}
-
-/**
- * @brief Returns the last ADCx conversion result data for regular channel.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval The Data conversion value.
- */
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Return the selected ADC conversion value */
- return (uint16_t) ADCx->DR;
-}
-
-/**
- * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results
- * data in the selected multi mode.
- * @param None
- * @retval The Data conversion value.
- * @note In dual mode, the value returned by this function is as following
- * Data[15:0] : these bits contain the regular data of ADC1.
- * Data[31:16]: these bits contain the regular data of ADC2.
- * @note In triple mode, the value returned by this function is as following
- * Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2.
- * Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3.
- */
-uint32_t ADC_GetMultiModeConversionValue(void)
-{
- /* Return the multi mode conversion value */
- return (*(__IO uint32_t *) CDR_ADDRESS);
-}
-/**
- * @}
- */
-
-/** @defgroup ADC_Group5 Regular Channels DMA Configuration functions
- * @brief Regular Channels DMA Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Regular Channels DMA Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the DMA for ADC
- regular channels.
- Since converted regular channel values are stored into a unique data
- register, it is useful to use DMA for conversion of more than one regular
- channel. This avoids the loss of the data already stored in the ADC
- Data register.
- When the DMA mode is enabled (using the ADC_DMACmd() function), after each
- conversion of a regular channel, a DMA request is generated.
- [..] Depending on the "DMA disable selection for Independent ADC mode"
- configuration (using the ADC_DMARequestAfterLastTransferCmd() function),
- at the end of the last DMA transfer, two possibilities are allowed:
- (+) No new DMA request is issued to the DMA controller (feature DISABLED)
- (+) Requests can continue to be generated (feature ENABLED).
- [..] Depending on the "DMA disable selection for multi ADC mode" configuration
- (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function),
- at the end of the last DMA transfer, two possibilities are allowed:
- (+) No new DMA request is issued to the DMA controller (feature DISABLED)
- (+) Requests can continue to be generated (feature ENABLED).
-
-@endverbatim
- * @{
- */
-
- /**
- * @brief Enables or disables the specified ADC DMA request.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC DMA transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC DMA request */
- ADCx->CR2 |= (uint32_t)ADC_CR2_DMA;
- }
- else
- {
- /* Disable the selected ADC DMA request */
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA);
- }
-}
-
-/**
- * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode)
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC DMA request after last transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC DMA request after last transfer */
- ADCx->CR2 |= (uint32_t)ADC_CR2_DDS;
- }
- else
- {
- /* Disable the selected ADC DMA request after last transfer */
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS);
- }
-}
-
-/**
- * @brief Enables or disables the ADC DMA request after last transfer in multi ADC mode
- * @param NewState: new state of the selected ADC DMA request after last transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @note if Enabled, DMA requests are issued as long as data are converted and
- * DMA mode for multi ADC mode (selected using ADC_CommonInit() function
- * by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is
- * ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3.
- * @retval None
- */
-void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC DMA request after last transfer */
- ADC->CCR |= (uint32_t)ADC_CCR_DDS;
- }
- else
- {
- /* Disable the selected ADC DMA request after last transfer */
- ADC->CCR &= (uint32_t)(~ADC_CCR_DDS);
- }
-}
-/**
- * @}
- */
-
-/** @defgroup ADC_Group6 Injected channels Configuration functions
- * @brief Injected channels Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Injected channels Configuration functions #####
- ===============================================================================
-
- [..] This section provide functions allowing to configure the ADC Injected channels,
- it is composed of 2 sub sections :
-
- (#) Configuration functions for Injected channels: This subsection provides
- functions allowing to configure the ADC injected channels :
- (++) Configure the rank in the injected group sequencer for each channel
- (++) Configure the sampling time for each channel
- (++) Activate the Auto injected Mode
- (++) Activate the Discontinuous Mode
- (++) scan mode activation
- (++) External/software trigger source
- (++) External trigger edge
- (++) injected channels sequencer.
-
- (#) Get the Specified Injected channel conversion data: This subsection
- provides an important function in the ADC peripheral since it returns the
- converted data of the specific injected channel.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Configures for the selected ADC injected channel its corresponding
- * rank in the sequencer and its sample time.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_0: ADC Channel0 selected
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @arg ADC_Channel_18: ADC Channel18 selected
- * @param Rank: The rank in the injected group sequencer.
- * This parameter must be between 1 to 4.
- * @param ADC_SampleTime: The sample time value to be set for the selected channel.
- * This parameter can be one of the following values:
- * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
- * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
- * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
- * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles
- * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles
- * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles
- * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles
- * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles
- * @retval None
- */
-void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
-{
- uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- assert_param(IS_ADC_INJECTED_RANK(Rank));
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
- /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
- if (ADC_Channel > ADC_Channel_9)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR1;
- /* Calculate the mask to clear */
- tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10));
- /* Clear the old sample time */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
- /* Set the new sample time */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SMPR1 = tmpreg1;
- }
- else /* ADC_Channel include in ADC_Channel_[0..9] */
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR2;
- /* Calculate the mask to clear */
- tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);
- /* Clear the old sample time */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
- /* Set the new sample time */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SMPR2 = tmpreg1;
- }
- /* Rank configuration */
- /* Get the old register value */
- tmpreg1 = ADCx->JSQR;
- /* Get JL value: Number = JL+1 */
- tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20;
- /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
- tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
- /* Clear the old JSQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
- /* Set the JSQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->JSQR = tmpreg1;
-}
-
-/**
- * @brief Configures the sequencer length for injected channels
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param Length: The sequencer length.
- * This parameter must be a number between 1 to 4.
- * @retval None
- */
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
-{
- uint32_t tmpreg1 = 0;
- uint32_t tmpreg2 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_INJECTED_LENGTH(Length));
-
- /* Get the old register value */
- tmpreg1 = ADCx->JSQR;
-
- /* Clear the old injected sequence length JL bits */
- tmpreg1 &= JSQR_JL_RESET;
-
- /* Set the injected sequence length JL bits */
- tmpreg2 = Length - 1;
- tmpreg1 |= tmpreg2 << 20;
-
- /* Store the new register value */
- ADCx->JSQR = tmpreg1;
-}
-
-/**
- * @brief Set the injected channels conversion value offset
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_InjectedChannel: the ADC injected channel to set its offset.
- * This parameter can be one of the following values:
- * @arg ADC_InjectedChannel_1: Injected Channel1 selected
- * @arg ADC_InjectedChannel_2: Injected Channel2 selected
- * @arg ADC_InjectedChannel_3: Injected Channel3 selected
- * @arg ADC_InjectedChannel_4: Injected Channel4 selected
- * @param Offset: the offset value for the selected ADC injected channel
- * This parameter must be a 12bit value.
- * @retval None
- */
-void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
-{
- __IO uint32_t tmp = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
- assert_param(IS_ADC_OFFSET(Offset));
-
- tmp = (uint32_t)ADCx;
- tmp += ADC_InjectedChannel;
-
- /* Set the selected injected channel data offset */
- *(__IO uint32_t *) tmp = (uint32_t)Offset;
-}
-
- /**
- * @brief Configures the ADCx external trigger for injected channels conversion.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion.
- * This parameter can be one of the following values:
- * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected
- * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected
- * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected
- * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected
- * @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected
- * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected
- * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected
- * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected
- * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected
- * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected
- * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected
- * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected
- * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected
- * @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected
- * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected
- * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected
- * @retval None
- */
-void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
-
- /* Get the old register value */
- tmpreg = ADCx->CR2;
-
- /* Clear the old external event selection for injected group */
- tmpreg &= CR2_JEXTSEL_RESET;
-
- /* Set the external event selection for injected group */
- tmpreg |= ADC_ExternalTrigInjecConv;
-
- /* Store the new register value */
- ADCx->CR2 = tmpreg;
-}
-
-/**
- * @brief Configures the ADCx external trigger edge for injected channels conversion.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge
- * to start injected conversion.
- * This parameter can be one of the following values:
- * @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for
- * injected conversion
- * @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge
- * @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge
- * @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising
- * and falling edge
- * @retval None
- */
-void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge));
- /* Get the old register value */
- tmpreg = ADCx->CR2;
- /* Clear the old external trigger edge for injected group */
- tmpreg &= CR2_JEXTEN_RESET;
- /* Set the new external trigger edge for injected group */
- tmpreg |= ADC_ExternalTrigInjecConvEdge;
- /* Store the new register value */
- ADCx->CR2 = tmpreg;
-}
-
-/**
- * @brief Enables the selected ADC software start conversion of the injected channels.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval None
- */
-void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- /* Enable the selected ADC conversion for injected group */
- ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART;
-}
-
-/**
- * @brief Gets the selected ADC Software start injected conversion Status.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval The new state of ADC software start injected conversion (SET or RESET).
- */
-FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Check the status of JSWSTART bit */
- if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)
- {
- /* JSWSTART bit is set */
- bitstatus = SET;
- }
- else
- {
- /* JSWSTART bit is reset */
- bitstatus = RESET;
- }
- /* Return the JSWSTART bit status */
- return bitstatus;
-}
-
-/**
- * @brief Enables or disables the selected ADC automatic injected group
- * conversion after regular one.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC auto injected conversion
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC automatic injected group conversion */
- ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO;
- }
- else
- {
- /* Disable the selected ADC automatic injected group conversion */
- ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO);
- }
-}
-
-/**
- * @brief Enables or disables the discontinuous mode for injected group
- * channel for the specified ADC
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC discontinuous mode on injected
- * group channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC injected discontinuous mode */
- ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN;
- }
- else
- {
- /* Disable the selected ADC injected discontinuous mode */
- ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN);
- }
-}
-
-/**
- * @brief Returns the ADC injected channel conversion result
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_InjectedChannel: the converted ADC injected channel.
- * This parameter can be one of the following values:
- * @arg ADC_InjectedChannel_1: Injected Channel1 selected
- * @arg ADC_InjectedChannel_2: Injected Channel2 selected
- * @arg ADC_InjectedChannel_3: Injected Channel3 selected
- * @arg ADC_InjectedChannel_4: Injected Channel4 selected
- * @retval The Data conversion value.
- */
-uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
-
- tmp = (uint32_t)ADCx;
- tmp += ADC_InjectedChannel + JDR_OFFSET;
-
- /* Returns the selected injected channel conversion data value */
- return (uint16_t) (*(__IO uint32_t*) tmp);
-}
-/**
- * @}
- */
-
-/** @defgroup ADC_Group7 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure the ADC Interrupts
- and to get the status and clear flags and Interrupts pending bits.
-
- [..] Each ADC provides 4 Interrupts sources and 6 Flags which can be divided
- into 3 groups:
-
- *** Flags and Interrupts for ADC regular channels ***
- =====================================================
- [..]
- (+) Flags :
- (##) ADC_FLAG_OVR : Overrun detection when regular converted data are lost
-
- (##) ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate
- (depending on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() )
- the end of:
- (+++) a regular CHANNEL conversion
- (+++) sequence of regular GROUP conversions .
-
- (##) ADC_FLAG_STRT: Regular channel start ==> to indicate when regular
- CHANNEL conversion starts.
- [..]
- (+) Interrupts :
- (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection
- event.
- (##) ADC_IT_EOC : specifies the interrupt source for Regular channel end
- of conversion event.
-
-
- *** Flags and Interrupts for ADC Injected channels ***
- ======================================================
- [..]
- (+) Flags :
- (##) ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate
- at the end of injected GROUP conversion
-
- (##) ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when
- injected GROUP conversion starts.
- [..]
- (+) Interrupts :
- (##) ADC_IT_JEOC : specifies the interrupt source for Injected channel
- end of conversion event.
-
- *** General Flags and Interrupts for the ADC ***
- ================================================
- [..]
- (+)Flags :
- (##) ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage
- crosses the programmed thresholds values.
- [..]
- (+) Interrupts :
- (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog event.
-
-
- [..] The user should identify which mode will be used in his application to
- manage the ADC controller events: Polling mode or Interrupt mode.
-
- [..] In the Polling Mode it is advised to use the following functions:
- (+) ADC_GetFlagStatus() : to check if flags events occur.
- (+) ADC_ClearFlag() : to clear the flags events.
-
- [..] In the Interrupt Mode it is advised to use the following functions:
- (+) ADC_ITConfig() : to enable or disable the interrupt source.
- (+) ADC_GetITStatus() : to check if Interrupt occurs.
- (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit
- (corresponding Flag).
-@endverbatim
- * @{
- */
-/**
- * @brief Enables or disables the specified ADC interrupts.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg ADC_IT_EOC: End of conversion interrupt mask
- * @arg ADC_IT_AWD: Analog watchdog interrupt mask
- * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
- * @arg ADC_IT_OVR: Overrun interrupt enable
- * @param NewState: new state of the specified ADC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
-{
- uint32_t itmask = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_ADC_IT(ADC_IT));
-
- /* Get the ADC IT index */
- itmask = (uint8_t)ADC_IT;
- itmask = (uint32_t)0x01 << itmask;
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC interrupts */
- ADCx->CR1 |= itmask;
- }
- else
- {
- /* Disable the selected ADC interrupts */
- ADCx->CR1 &= (~(uint32_t)itmask);
- }
-}
-
-/**
- * @brief Checks whether the specified ADC flag is set or not.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg ADC_FLAG_AWD: Analog watchdog flag
- * @arg ADC_FLAG_EOC: End of conversion flag
- * @arg ADC_FLAG_JEOC: End of injected group conversion flag
- * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
- * @arg ADC_FLAG_STRT: Start of regular group conversion flag
- * @arg ADC_FLAG_OVR: Overrun flag
- * @retval The new state of ADC_FLAG (SET or RESET).
- */
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
-
- /* Check the status of the specified ADC flag */
- if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
- {
- /* ADC_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* ADC_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the ADC_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the ADCx's pending flags.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg ADC_FLAG_AWD: Analog watchdog flag
- * @arg ADC_FLAG_EOC: End of conversion flag
- * @arg ADC_FLAG_JEOC: End of injected group conversion flag
- * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
- * @arg ADC_FLAG_STRT: Start of regular group conversion flag
- * @arg ADC_FLAG_OVR: Overrun flag
- * @retval None
- */
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
-
- /* Clear the selected ADC flags */
- ADCx->SR = ~(uint32_t)ADC_FLAG;
-}
-
-/**
- * @brief Checks whether the specified ADC interrupt has occurred or not.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_IT: specifies the ADC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg ADC_IT_EOC: End of conversion interrupt mask
- * @arg ADC_IT_AWD: Analog watchdog interrupt mask
- * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
- * @arg ADC_IT_OVR: Overrun interrupt mask
- * @retval The new state of ADC_IT (SET or RESET).
- */
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t itmask = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_IT(ADC_IT));
-
- /* Get the ADC IT index */
- itmask = ADC_IT >> 8;
-
- /* Get the ADC_IT enable bit status */
- enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ;
-
- /* Check the status of the specified ADC interrupt */
- if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
- {
- /* ADC_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* ADC_IT is reset */
- bitstatus = RESET;
- }
- /* Return the ADC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the ADCx's interrupt pending bits.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_IT: specifies the ADC interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg ADC_IT_EOC: End of conversion interrupt mask
- * @arg ADC_IT_AWD: Analog watchdog interrupt mask
- * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
- * @arg ADC_IT_OVR: Overrun interrupt mask
- * @retval None
- */
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
-{
- uint8_t itmask = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_IT(ADC_IT));
- /* Get the ADC IT index */
- itmask = (uint8_t)(ADC_IT >> 8);
- /* Clear the selected ADC interrupt pending bits */
- ADCx->SR = ~(uint32_t)itmask;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_adc.h b/底盘/底盘-old/底盘/Library/stm32f4xx_adc.h
deleted file mode 100644
index ea75cb0..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_adc.h
+++ /dev/null
@@ -1,648 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_adc.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the ADC firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_ADC_H
-#define __STM32F4xx_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup ADC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief ADC Init structure definition
- */
-typedef struct
-{
- uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode.
- This parameter can be a value of @ref ADC_resolution */
- FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion
- is performed in Scan (multichannels)
- or Single (one channel) mode.
- This parameter can be set to ENABLE or DISABLE */
- FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion
- is performed in Continuous or Single mode.
- This parameter can be set to ENABLE or DISABLE. */
- uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and
- enable the trigger of a regular group.
- This parameter can be a value of
- @ref ADC_external_trigger_edge_for_regular_channels_conversion */
- uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger
- the start of conversion of a regular group.
- This parameter can be a value of
- @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */
- uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment
- is left or right. This parameter can be
- a value of @ref ADC_data_align */
- uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions
- that will be done using the sequencer for
- regular channel group.
- This parameter must range from 1 to 16. */
-}ADC_InitTypeDef;
-
-/**
- * @brief ADC Common Init structure definition
- */
-typedef struct
-{
- uint32_t ADC_Mode; /*!< Configures the ADC to operate in
- independent or multi mode.
- This parameter can be a value of @ref ADC_Common_mode */
- uint32_t ADC_Prescaler; /*!< Select the frequency of the clock
- to the ADC. The clock is common for all the ADCs.
- This parameter can be a value of @ref ADC_Prescaler */
- uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access
- mode for multi ADC mode.
- This parameter can be a value of
- @ref ADC_Direct_memory_access_mode_for_multi_mode */
- uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
- This parameter can be a value of
- @ref ADC_delay_between_2_sampling_phases */
-
-}ADC_CommonInitTypeDef;
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Constants
- * @{
- */
-#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
- ((PERIPH) == ADC2) || \
- ((PERIPH) == ADC3))
-
-/** @defgroup ADC_Common_mode
- * @{
- */
-#define ADC_Mode_Independent ((uint32_t)0x00000000)
-#define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001)
-#define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002)
-#define ADC_DualMode_InjecSimult ((uint32_t)0x00000005)
-#define ADC_DualMode_RegSimult ((uint32_t)0x00000006)
-#define ADC_DualMode_Interl ((uint32_t)0x00000007)
-#define ADC_DualMode_AlterTrig ((uint32_t)0x00000009)
-#define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011)
-#define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012)
-#define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015)
-#define ADC_TripleMode_RegSimult ((uint32_t)0x00000016)
-#define ADC_TripleMode_Interl ((uint32_t)0x00000017)
-#define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019)
-#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
- ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \
- ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \
- ((MODE) == ADC_DualMode_InjecSimult) || \
- ((MODE) == ADC_DualMode_RegSimult) || \
- ((MODE) == ADC_DualMode_Interl) || \
- ((MODE) == ADC_DualMode_AlterTrig) || \
- ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \
- ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \
- ((MODE) == ADC_TripleMode_InjecSimult) || \
- ((MODE) == ADC_TripleMode_RegSimult) || \
- ((MODE) == ADC_TripleMode_Interl) || \
- ((MODE) == ADC_TripleMode_AlterTrig))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_Prescaler
- * @{
- */
-#define ADC_Prescaler_Div2 ((uint32_t)0x00000000)
-#define ADC_Prescaler_Div4 ((uint32_t)0x00010000)
-#define ADC_Prescaler_Div6 ((uint32_t)0x00020000)
-#define ADC_Prescaler_Div8 ((uint32_t)0x00030000)
-#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \
- ((PRESCALER) == ADC_Prescaler_Div4) || \
- ((PRESCALER) == ADC_Prescaler_Div6) || \
- ((PRESCALER) == ADC_Prescaler_Div8))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode
- * @{
- */
-#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */
-#define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
-#define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
-#define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
-#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
- ((MODE) == ADC_DMAAccessMode_1) || \
- ((MODE) == ADC_DMAAccessMode_2) || \
- ((MODE) == ADC_DMAAccessMode_3))
-
-/**
- * @}
- */
-
-
-/** @defgroup ADC_delay_between_2_sampling_phases
- * @{
- */
-#define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000)
-#define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100)
-#define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200)
-#define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300)
-#define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400)
-#define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500)
-#define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600)
-#define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700)
-#define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800)
-#define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900)
-#define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00)
-#define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00)
-#define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00)
-#define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00)
-#define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00)
-#define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00)
-#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \
- ((DELAY) == ADC_TwoSamplingDelay_20Cycles))
-
-/**
- * @}
- */
-
-
-/** @defgroup ADC_resolution
- * @{
- */
-#define ADC_Resolution_12b ((uint32_t)0x00000000)
-#define ADC_Resolution_10b ((uint32_t)0x01000000)
-#define ADC_Resolution_8b ((uint32_t)0x02000000)
-#define ADC_Resolution_6b ((uint32_t)0x03000000)
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
- ((RESOLUTION) == ADC_Resolution_10b) || \
- ((RESOLUTION) == ADC_Resolution_8b) || \
- ((RESOLUTION) == ADC_Resolution_6b))
-
-/**
- * @}
- */
-
-
-/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
- * @{
- */
-#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)
-#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)
-#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)
-#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
-#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
- ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
- ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
- ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion
- * @{
- */
-#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
-#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000)
-#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000)
-#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)
-#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000)
-#define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000)
-#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)
-#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)
-#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000)
-#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000)
-#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000)
-#define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000)
-#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000)
-#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000)
-#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000)
-#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)
-#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
- ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
- ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_data_align
- * @{
- */
-#define ADC_DataAlign_Right ((uint32_t)0x00000000)
-#define ADC_DataAlign_Left ((uint32_t)0x00000800)
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
- ((ALIGN) == ADC_DataAlign_Left))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_channels
- * @{
- */
-#define ADC_Channel_0 ((uint8_t)0x00)
-#define ADC_Channel_1 ((uint8_t)0x01)
-#define ADC_Channel_2 ((uint8_t)0x02)
-#define ADC_Channel_3 ((uint8_t)0x03)
-#define ADC_Channel_4 ((uint8_t)0x04)
-#define ADC_Channel_5 ((uint8_t)0x05)
-#define ADC_Channel_6 ((uint8_t)0x06)
-#define ADC_Channel_7 ((uint8_t)0x07)
-#define ADC_Channel_8 ((uint8_t)0x08)
-#define ADC_Channel_9 ((uint8_t)0x09)
-#define ADC_Channel_10 ((uint8_t)0x0A)
-#define ADC_Channel_11 ((uint8_t)0x0B)
-#define ADC_Channel_12 ((uint8_t)0x0C)
-#define ADC_Channel_13 ((uint8_t)0x0D)
-#define ADC_Channel_14 ((uint8_t)0x0E)
-#define ADC_Channel_15 ((uint8_t)0x0F)
-#define ADC_Channel_16 ((uint8_t)0x10)
-#define ADC_Channel_17 ((uint8_t)0x11)
-#define ADC_Channel_18 ((uint8_t)0x12)
-
-#if defined (STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
-#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
-#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
-
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F410xx) || defined (STM32F411xE)
-#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_18)
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE */
-
-#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
-#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18)
-
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \
- ((CHANNEL) == ADC_Channel_1) || \
- ((CHANNEL) == ADC_Channel_2) || \
- ((CHANNEL) == ADC_Channel_3) || \
- ((CHANNEL) == ADC_Channel_4) || \
- ((CHANNEL) == ADC_Channel_5) || \
- ((CHANNEL) == ADC_Channel_6) || \
- ((CHANNEL) == ADC_Channel_7) || \
- ((CHANNEL) == ADC_Channel_8) || \
- ((CHANNEL) == ADC_Channel_9) || \
- ((CHANNEL) == ADC_Channel_10) || \
- ((CHANNEL) == ADC_Channel_11) || \
- ((CHANNEL) == ADC_Channel_12) || \
- ((CHANNEL) == ADC_Channel_13) || \
- ((CHANNEL) == ADC_Channel_14) || \
- ((CHANNEL) == ADC_Channel_15) || \
- ((CHANNEL) == ADC_Channel_16) || \
- ((CHANNEL) == ADC_Channel_17) || \
- ((CHANNEL) == ADC_Channel_18))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_sampling_times
- * @{
- */
-#define ADC_SampleTime_3Cycles ((uint8_t)0x00)
-#define ADC_SampleTime_15Cycles ((uint8_t)0x01)
-#define ADC_SampleTime_28Cycles ((uint8_t)0x02)
-#define ADC_SampleTime_56Cycles ((uint8_t)0x03)
-#define ADC_SampleTime_84Cycles ((uint8_t)0x04)
-#define ADC_SampleTime_112Cycles ((uint8_t)0x05)
-#define ADC_SampleTime_144Cycles ((uint8_t)0x06)
-#define ADC_SampleTime_480Cycles ((uint8_t)0x07)
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \
- ((TIME) == ADC_SampleTime_15Cycles) || \
- ((TIME) == ADC_SampleTime_28Cycles) || \
- ((TIME) == ADC_SampleTime_56Cycles) || \
- ((TIME) == ADC_SampleTime_84Cycles) || \
- ((TIME) == ADC_SampleTime_112Cycles) || \
- ((TIME) == ADC_SampleTime_144Cycles) || \
- ((TIME) == ADC_SampleTime_480Cycles))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion
- * @{
- */
-#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)
-#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)
-#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)
-#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
-#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
- ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
- ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
- ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
-
-/**
- * @}
- */
-
-
-/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion
- * @{
- */
-#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000)
-#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000)
-#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000)
-#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000)
-#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000)
-#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000)
-#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)
-#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)
-#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)
-#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000)
-#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000)
-#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000)
-#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000)
-#define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000)
-#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000)
-#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)
-#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_injected_channel_selection
- * @{
- */
-#define ADC_InjectedChannel_1 ((uint8_t)0x14)
-#define ADC_InjectedChannel_2 ((uint8_t)0x18)
-#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
-#define ADC_InjectedChannel_4 ((uint8_t)0x20)
-#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
- ((CHANNEL) == ADC_InjectedChannel_2) || \
- ((CHANNEL) == ADC_InjectedChannel_3) || \
- ((CHANNEL) == ADC_InjectedChannel_4))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_analog_watchdog_selection
- * @{
- */
-#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
-#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
-#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
-#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
-#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
-#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
-#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
-#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_None))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_interrupts_definition
- * @{
- */
-#define ADC_IT_EOC ((uint16_t)0x0205)
-#define ADC_IT_AWD ((uint16_t)0x0106)
-#define ADC_IT_JEOC ((uint16_t)0x0407)
-#define ADC_IT_OVR ((uint16_t)0x201A)
-#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
- ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_flags_definition
- * @{
- */
-#define ADC_FLAG_AWD ((uint8_t)0x01)
-#define ADC_FLAG_EOC ((uint8_t)0x02)
-#define ADC_FLAG_JEOC ((uint8_t)0x04)
-#define ADC_FLAG_JSTRT ((uint8_t)0x08)
-#define ADC_FLAG_STRT ((uint8_t)0x10)
-#define ADC_FLAG_OVR ((uint8_t)0x20)
-
-#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00))
-#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \
- ((FLAG) == ADC_FLAG_EOC) || \
- ((FLAG) == ADC_FLAG_JEOC) || \
- ((FLAG)== ADC_FLAG_JSTRT) || \
- ((FLAG) == ADC_FLAG_STRT) || \
- ((FLAG)== ADC_FLAG_OVR))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_thresholds
- * @{
- */
-#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
-/**
- * @}
- */
-
-
-/** @defgroup ADC_injected_offset
- * @{
- */
-#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
-/**
- * @}
- */
-
-
-/** @defgroup ADC_injected_length
- * @{
- */
-#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_injected_rank
- * @{
- */
-#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_regular_length
- * @{
- */
-#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_regular_rank
- * @{
- */
-#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_regular_discontinuous_mode_number
- * @{
- */
-#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the ADC configuration to the default reset state *****/
-void ADC_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
-void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
-void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-
-/* Analog Watchdog configuration functions ************************************/
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
-
-/* Temperature Sensor, Vrefint and VBAT management functions ******************/
-void ADC_TempSensorVrefintCmd(FunctionalState NewState);
-void ADC_VBATCmd(FunctionalState NewState);
-
-/* Regular Channels Configuration functions ***********************************/
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
-void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
-void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
-uint32_t ADC_GetMultiModeConversionValue(void);
-
-/* Regular Channels DMA Configuration functions *******************************/
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState);
-
-/* Injected channels Configuration functions **********************************/
-void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
-void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
-void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
-void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
-void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
-FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
-
-/* Interrupts and flags management functions **********************************/
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_ADC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_can.c b/底盘/底盘-old/底盘/Library/stm32f4xx_can.c
deleted file mode 100644
index 524c038..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_can.c
+++ /dev/null
@@ -1,1848 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_can.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Controller area network (CAN) peripheral:
- * + Initialization and Configuration
- * + CAN Frames Transmission
- * + CAN Frames Reception
- * + Operation modes switch
- * + Error management
- * + Interrupts and flags
- *
-@verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable the CAN controller interface clock using
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1
- and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2
- -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
-
- (#) CAN pins configuration
- (++) Enable the clock for the CAN GPIOs using the following function:
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
- (++) Connect the involved CAN pins to AF9 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx);
- (++) Configure these CAN pins in alternate function mode by calling
- the function GPIO_Init();
-
- (#) Initialize and configure the CAN using CAN_Init() and
- CAN_FilterInit() functions.
-
- (#) Transmit the desired CAN frame using CAN_Transmit() function.
-
- (#) Check the transmission of a CAN frame using CAN_TransmitStatus()
- function.
-
- (#) Cancel the transmission of a CAN frame using CAN_CancelTransmit()
- function.
-
- (#) Receive a CAN frame using CAN_Receive() function.
-
- (#) Release the receive FIFOs using CAN_FIFORelease() function.
-
- (#) Return the number of pending received frames using
- CAN_MessagePending() function.
-
- (#) To control CAN events you can use one of the following two methods:
- (++) Check on CAN flags using the CAN_GetFlagStatus() function.
- (++) Use CAN interrupts through the function CAN_ITConfig() at
- initialization phase and CAN_GetITStatus() function into
- interrupt routines to check if the event has occurred or not.
- After checking on a flag you should clear it using CAN_ClearFlag()
- function. And after checking on an interrupt event you should
- clear it using CAN_ClearITPendingBit() function.
-
-@endverbatim
-
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_can.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CAN
- * @brief CAN driver modules
- * @{
- */
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* CAN Master Control Register bits */
-#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */
-
-/* CAN Mailbox Transmit Request */
-#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */
-
-/* CAN Filter Master Register bits */
-#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */
-
-/* Time out for INAK bit */
-#define INAK_TIMEOUT ((uint32_t)0x0000FFFF)
-/* Time out for SLAK bit */
-#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF)
-
-/* Flags in TSR register */
-#define CAN_FLAGS_TSR ((uint32_t)0x08000000)
-/* Flags in RF1R register */
-#define CAN_FLAGS_RF1R ((uint32_t)0x04000000)
-/* Flags in RF0R register */
-#define CAN_FLAGS_RF0R ((uint32_t)0x02000000)
-/* Flags in MSR register */
-#define CAN_FLAGS_MSR ((uint32_t)0x01000000)
-/* Flags in ESR register */
-#define CAN_FLAGS_ESR ((uint32_t)0x00F00000)
-
-/* Mailboxes definition */
-#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
-#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
-#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
-
-#define CAN_MODE_MASK ((uint32_t) 0x00000003)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
-
-/** @defgroup CAN_Private_Functions
- * @{
- */
-
-/** @defgroup CAN_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to
- (+) Initialize the CAN peripherals : Prescaler, operating mode, the maximum
- number of time quanta to perform resynchronization, the number of time
- quanta in Bit Segment 1 and 2 and many other modes.
- Refer to @ref CAN_InitTypeDef for more details.
- (+) Configures the CAN reception filter.
- (+) Select the start bank filter for slave CAN.
- (+) Enables or disables the Debug Freeze mode for CAN
- (+)Enables or disables the CAN Time Trigger Operation communication mode
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the CAN peripheral registers to their default reset values.
- * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
- * @note CAN3 peripheral is available only for STM32F413_423xx devices
- * @retval None.
- */
-void CAN_DeInit(CAN_TypeDef* CANx)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- if (CANx == CAN1)
- {
- /* Enable CAN1 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);
- /* Release CAN1 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
- }
-#if defined(STM32F413_423xx)
- else if(CANx == CAN2)
- {
- /* Enable CAN2 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);
- /* Release CAN2 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);
- }
-
- else /* CAN3 available only for STM32F413_423xx */
- {
- /* Enable CAN3 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN3, ENABLE);
- /* Release CAN3 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN3, DISABLE);
- }
-#else
- else
- {
- /* Enable CAN2 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);
- /* Release CAN2 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);
- }
-#endif /* STM32F413_423xx */
-}
-
-/**
- * @brief Initializes the CAN peripheral according to the specified
- * parameters in the CAN_InitStruct.
- * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
- * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains
- * the configuration information for the CAN peripheral.
- * @note CAN3 peripheral is available only for STM32F413_423xx devices
- * @retval Constant indicates initialization succeed which will be
- * CAN_InitStatus_Failed or CAN_InitStatus_Success.
- */
-uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
-{
- uint8_t InitStatus = CAN_InitStatus_Failed;
- uint32_t wait_ack = 0x00000000;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
- assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
- assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
- assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
- assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
- assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
-
- /* Exit from sleep mode */
- CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
-
- /* Request initialisation */
- CANx->MCR |= CAN_MCR_INRQ ;
-
- /* Wait the acknowledge */
- while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
- {
- wait_ack++;
- }
-
- /* Check acknowledge */
- if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
- {
- InitStatus = CAN_InitStatus_Failed;
- }
- else
- {
- /* Set the time triggered communication mode */
- if (CAN_InitStruct->CAN_TTCM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_TTCM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
- }
-
- /* Set the automatic bus-off management */
- if (CAN_InitStruct->CAN_ABOM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_ABOM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
- }
-
- /* Set the automatic wake-up mode */
- if (CAN_InitStruct->CAN_AWUM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_AWUM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
- }
-
- /* Set the no automatic retransmission */
- if (CAN_InitStruct->CAN_NART == ENABLE)
- {
- CANx->MCR |= CAN_MCR_NART;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
- }
-
- /* Set the receive FIFO locked mode */
- if (CAN_InitStruct->CAN_RFLM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_RFLM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
- }
-
- /* Set the transmit FIFO priority */
- if (CAN_InitStruct->CAN_TXFP == ENABLE)
- {
- CANx->MCR |= CAN_MCR_TXFP;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
- }
-
- /* Set the bit timing register */
- CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
- ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
- ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
- ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
- ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
-
- /* Request leave initialisation */
- CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
-
- /* Wait the acknowledge */
- wait_ack = 0;
-
- while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
- {
- wait_ack++;
- }
-
- /* ...and check acknowledged */
- if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
- {
- InitStatus = CAN_InitStatus_Failed;
- }
- else
- {
- InitStatus = CAN_InitStatus_Success ;
- }
- }
-
- /* At this step, return the status of initialization */
- return InitStatus;
-}
-
-#if defined(STM32F413_423xx)
-/**
- * @brief Configures the CAN reception filter according to the specified
- * parameters in the CAN_FilterInitStruct.
- * @param CANx: where x can be 1 or 3 to select the CAN peripheral.
- * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that
- * contains the configuration information.
- * @retval None
- */
-void CAN_FilterInit(CAN_TypeDef* CANx, CAN_FilterInitTypeDef* CAN_FilterInitStruct)
-{
- uint32_t filter_number_bit_pos = 0;
- /* Check the parameters */
- assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
- assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
- assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
- assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
- assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
-
- filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
-
- /* Initialisation mode for the filter */
- CANx->FMR |= FMR_FINIT;
-
- /* Filter Deactivation */
- CANx->FA1R &= ~(uint32_t)filter_number_bit_pos;
-
- /* Filter Scale */
- if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
- {
- /* 16-bit scale for the filter */
- CANx->FS1R &= ~(uint32_t)filter_number_bit_pos;
-
- /* First 16-bit identifier and First 16-bit mask */
- /* Or First 16-bit identifier and Second 16-bit identifier */
- CANx->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
-
- /* Second 16-bit identifier and Second 16-bit mask */
- /* Or Third 16-bit identifier and Fourth 16-bit identifier */
- CANx->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
- }
-
- if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
- {
- /* 32-bit scale for the filter */
- CANx->FS1R |= filter_number_bit_pos;
- /* 32-bit identifier or First 32-bit identifier */
- CANx->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
- /* 32-bit mask or Second 32-bit identifier */
- CANx->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
- }
-
- /* Filter Mode */
- if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
- {
- /*Id/Mask mode for the filter*/
- CANx->FM1R &= ~(uint32_t)filter_number_bit_pos;
- }
- else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
- {
- /*Identifier list mode for the filter*/
- CANx->FM1R |= (uint32_t)filter_number_bit_pos;
- }
-
- /* Filter FIFO assignment */
- if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
- {
- /* FIFO 0 assignation for the filter */
- CANx->FFA1R &= ~(uint32_t)filter_number_bit_pos;
- }
-
- if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
- {
- /* FIFO 1 assignation for the filter */
- CANx->FFA1R |= (uint32_t)filter_number_bit_pos;
- }
-
- /* Filter activation */
- if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
- {
- CANx->FA1R |= filter_number_bit_pos;
- }
-
- /* Leave the initialisation mode for the filter */
- CANx->FMR &= ~FMR_FINIT;
-}
-#else
-/**
- * @brief Configures the CAN reception filter according to the specified
- * parameters in the CAN_FilterInitStruct.
- * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that
- * contains the configuration information.
- * @retval None
- */
-void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
-{
- uint32_t filter_number_bit_pos = 0;
- /* Check the parameters */
- assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
- assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
- assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
- assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
- assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
-
- filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
-
- /* Initialisation mode for the filter */
- CAN1->FMR |= FMR_FINIT;
-
- /* Filter Deactivation */
- CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;
-
- /* Filter Scale */
- if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
- {
- /* 16-bit scale for the filter */
- CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;
-
- /* First 16-bit identifier and First 16-bit mask */
- /* Or First 16-bit identifier and Second 16-bit identifier */
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
-
- /* Second 16-bit identifier and Second 16-bit mask */
- /* Or Third 16-bit identifier and Fourth 16-bit identifier */
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
- }
-
- if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
- {
- /* 32-bit scale for the filter */
- CAN1->FS1R |= filter_number_bit_pos;
- /* 32-bit identifier or First 32-bit identifier */
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
- /* 32-bit mask or Second 32-bit identifier */
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
- }
-
- /* Filter Mode */
- if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
- {
- /*Id/Mask mode for the filter*/
- CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;
- }
- else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
- {
- /*Identifier list mode for the filter*/
- CAN1->FM1R |= (uint32_t)filter_number_bit_pos;
- }
-
- /* Filter FIFO assignment */
- if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
- {
- /* FIFO 0 assignation for the filter */
- CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;
- }
-
- if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
- {
- /* FIFO 1 assignation for the filter */
- CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;
- }
-
- /* Filter activation */
- if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
- {
- CAN1->FA1R |= filter_number_bit_pos;
- }
-
- /* Leave the initialisation mode for the filter */
- CAN1->FMR &= ~FMR_FINIT;
-}
-#endif /* STM32F413_423xx */
-
-/**
- * @brief Fills each CAN_InitStruct member with its default value.
- * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized.
- * @retval None
- */
-void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
-{
- /* Reset CAN init structure parameters values */
-
- /* Initialize the time triggered communication mode */
- CAN_InitStruct->CAN_TTCM = DISABLE;
-
- /* Initialize the automatic bus-off management */
- CAN_InitStruct->CAN_ABOM = DISABLE;
-
- /* Initialize the automatic wake-up mode */
- CAN_InitStruct->CAN_AWUM = DISABLE;
-
- /* Initialize the no automatic retransmission */
- CAN_InitStruct->CAN_NART = DISABLE;
-
- /* Initialize the receive FIFO locked mode */
- CAN_InitStruct->CAN_RFLM = DISABLE;
-
- /* Initialize the transmit FIFO priority */
- CAN_InitStruct->CAN_TXFP = DISABLE;
-
- /* Initialize the CAN_Mode member */
- CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
-
- /* Initialize the CAN_SJW member */
- CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
-
- /* Initialize the CAN_BS1 member */
- CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
-
- /* Initialize the CAN_BS2 member */
- CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
-
- /* Initialize the CAN_Prescaler member */
- CAN_InitStruct->CAN_Prescaler = 1;
-}
-
-#if defined(STM32F413_423xx)
-/**
- * @brief Select the start bank filter for slave CAN.
- * @param CANx: where x can be 1 or 3 to select the CAN peripheral.
- * @param CAN_BankNumber: Select the start slave bank filter from 1..27.
- * @retval None
- */
-void CAN_SlaveStartBank(CAN_TypeDef* CANx, uint8_t CAN_BankNumber)
-{
- /* Check the parameters */
- assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
-
- /* Enter Initialisation mode for the filter */
- CANx->FMR |= FMR_FINIT;
-
- /* Select the start slave bank */
- CANx->FMR &= (uint32_t)0xFFFFC0F1 ;
- CANx->FMR |= (uint32_t)(CAN_BankNumber)<<8;
-
- /* Leave Initialisation mode for the filter */
- CANx->FMR &= ~FMR_FINIT;
-}
-#else
-/**
- * @brief Select the start bank filter for slave CAN.
- * @param CAN_BankNumber: Select the start slave bank filter from 1..27.
- * @retval None
- */
-void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
-{
- /* Check the parameters */
- assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
-
- /* Enter Initialisation mode for the filter */
- CAN1->FMR |= FMR_FINIT;
-
- /* Select the start slave bank */
- CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;
- CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;
-
- /* Leave Initialisation mode for the filter */
- CAN1->FMR &= ~FMR_FINIT;
-}
-#endif /* STM32F413_423xx */
-/**
- * @brief Enables or disables the DBG Freeze for CAN.
- * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
- * @param NewState: new state of the CAN peripheral.
- * This parameter can be: ENABLE (CAN reception/transmission is frozen
- * during debug. Reception FIFOs can still be accessed/controlled normally)
- * or DISABLE (CAN is working during debug).
- * @note CAN3 peripheral is available only for STM32F413_423xx devices
- * @retval None
- */
-void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Debug Freeze */
- CANx->MCR |= MCR_DBF;
- }
- else
- {
- /* Disable Debug Freeze */
- CANx->MCR &= ~MCR_DBF;
- }
-}
-
-
-/**
- * @brief Enables or disables the CAN Time TriggerOperation communication mode.
- * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be
- * sent over the CAN bus.
- * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
- * @param NewState: Mode new state. This parameter can be: ENABLE or DISABLE.
- * When enabled, Time stamp (TIME[15:0]) value is sent in the last two
- * data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8]
- * in data byte 7.
- * @note CAN3 peripheral is available only for STM32F413_423xx devices
- * @retval None
- */
-void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the TTCM mode */
- CANx->MCR |= CAN_MCR_TTCM;
-
- /* Set TGT bits */
- CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);
- CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);
- CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);
- }
- else
- {
- /* Disable the TTCM mode */
- CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM);
-
- /* Reset TGT bits */
- CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);
- CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);
- CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);
- }
-}
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Group2 CAN Frames Transmission functions
- * @brief CAN Frames Transmission functions
- *
-@verbatim
- ===============================================================================
- ##### CAN Frames Transmission functions #####
- ===============================================================================
- [..] This section provides functions allowing to
- (+) Initiate and transmit a CAN frame message (if there is an empty mailbox).
- (+) Check the transmission status of a CAN Frame
- (+) Cancel a transmit request
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initiates and transmits a CAN frame message.
- * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
- * @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data.
- * @note CAN3 peripheral is available only for STM32F413_423xx devices
- * @retval The number of the mailbox that is used for transmission or
- * CAN_TxStatus_NoMailBox if there is no empty mailbox.
- */
-uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
-{
- uint8_t transmit_mailbox = 0;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
- assert_param(IS_CAN_RTR(TxMessage->RTR));
- assert_param(IS_CAN_DLC(TxMessage->DLC));
-
- /* Select one empty transmit mailbox */
- if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
- {
- transmit_mailbox = 0;
- }
- else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
- {
- transmit_mailbox = 1;
- }
- else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
- {
- transmit_mailbox = 2;
- }
- else
- {
- transmit_mailbox = CAN_TxStatus_NoMailBox;
- }
-
- if (transmit_mailbox != CAN_TxStatus_NoMailBox)
- {
- /* Set up the Id */
- CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
- if (TxMessage->IDE == CAN_Id_Standard)
- {
- assert_param(IS_CAN_STDID(TxMessage->StdId));
- CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \
- TxMessage->RTR);
- }
- else
- {
- assert_param(IS_CAN_EXTID(TxMessage->ExtId));
- CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \
- TxMessage->IDE | \
- TxMessage->RTR);
- }
-
- /* Set up the DLC */
- TxMessage->DLC &= (uint8_t)0x0000000F;
- CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
- CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
-
- /* Set up the data field */
- CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) |
- ((uint32_t)TxMessage->Data[2] << 16) |
- ((uint32_t)TxMessage->Data[1] << 8) |
- ((uint32_t)TxMessage->Data[0]));
- CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) |
- ((uint32_t)TxMessage->Data[6] << 16) |
- ((uint32_t)TxMessage->Data[5] << 8) |
- ((uint32_t)TxMessage->Data[4]));
- /* Request transmission */
- CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
- }
- return transmit_mailbox;
-}
-
-/**
- * @brief Checks the transmission status of a CAN Frame.
- * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
- * @param TransmitMailbox: the number of the mailbox that is used for transmission.
- * @note CAN3 peripheral is available only for STM32F413_423xx devices
- * @retval CAN_TxStatus_Ok if the CAN driver transmits the message,
- * CAN_TxStatus_Failed in an other case.
- */
-uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
-{
- uint32_t state = 0;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
-
- switch (TransmitMailbox)
- {
- case (CAN_TXMAILBOX_0):
- state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0);
- break;
- case (CAN_TXMAILBOX_1):
- state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1);
- break;
- case (CAN_TXMAILBOX_2):
- state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2);
- break;
- default:
- state = CAN_TxStatus_Failed;
- break;
- }
- switch (state)
- {
- /* transmit pending */
- case (0x0): state = CAN_TxStatus_Pending;
- break;
- /* transmit failed */
- case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed;
- break;
- case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed;
- break;
- case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed;
- break;
- /* transmit succeeded */
- case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok;
- break;
- case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok;
- break;
- case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok;
- break;
- default: state = CAN_TxStatus_Failed;
- break;
- }
- return (uint8_t) state;
-}
-
-/**
- * @brief Cancels a transmit request.
- * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
- * @param Mailbox: Mailbox number.
- * @note CAN3 peripheral is available only for STM32F413_423xx devices
- * @retval None
- */
-void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
- /* abort transmission */
- switch (Mailbox)
- {
- case (CAN_TXMAILBOX_0): CANx->TSR = CAN_TSR_ABRQ0;
- break;
- case (CAN_TXMAILBOX_1): CANx->TSR = CAN_TSR_ABRQ1;
- break;
- case (CAN_TXMAILBOX_2): CANx->TSR = CAN_TSR_ABRQ2;
- break;
- default:
- break;
- }
-}
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Group3 CAN Frames Reception functions
- * @brief CAN Frames Reception functions
- *
-@verbatim
- ===============================================================================
- ##### CAN Frames Reception functions #####
- ===============================================================================
- [..] This section provides functions allowing to
- (+) Receive a correct CAN frame
- (+) Release a specified receive FIFO (2 FIFOs are available)
- (+) Return the number of the pending received CAN frames
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Receives a correct CAN frame.
- * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
- * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @param RxMessage: pointer to a structure receive frame which contains CAN Id,
- * CAN DLC, CAN data and FMI number.
- * @note CAN3 peripheral is available only for STM32F413_423xx devices
- * @retval None
- */
-void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_FIFO(FIFONumber));
- /* Get the Id */
- RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
- if (RxMessage->IDE == CAN_Id_Standard)
- {
- RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
- }
- else
- {
- RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
- }
-
- RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
- /* Get the DLC */
- RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
- /* Get the FMI */
- RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
- /* Get the data field */
- RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
- RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
- RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
- RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
- RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
- RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
- RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
- RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
- /* Release the FIFO */
- /* Release FIFO0 */
- if (FIFONumber == CAN_FIFO0)
- {
- CANx->RF0R = CAN_RF0R_RFOM0;
- }
- /* Release FIFO1 */
- else /* FIFONumber == CAN_FIFO1 */
- {
- CANx->RF1R = CAN_RF1R_RFOM1;
- }
-}
-
-/**
- * @brief Releases the specified receive FIFO.
- * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
- * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
- * @note CAN3 peripheral is available only for STM32F413_423xx devices
- * @retval None
- */
-void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_FIFO(FIFONumber));
- /* Release FIFO0 */
- if (FIFONumber == CAN_FIFO0)
- {
- CANx->RF0R = CAN_RF0R_RFOM0;
- }
- /* Release FIFO1 */
- else /* FIFONumber == CAN_FIFO1 */
- {
- CANx->RF1R = CAN_RF1R_RFOM1;
- }
-}
-
-/**
- * @brief Returns the number of pending received messages.
- * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
- * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @note CAN3 peripheral is available only for STM32F413_423xx devices
- * @retval NbMessage : which is the number of pending message.
- */
-uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
-{
- uint8_t message_pending=0;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_FIFO(FIFONumber));
- if (FIFONumber == CAN_FIFO0)
- {
- message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
- }
- else if (FIFONumber == CAN_FIFO1)
- {
- message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
- }
- else
- {
- message_pending = 0;
- }
- return message_pending;
-}
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Group4 CAN Operation modes functions
- * @brief CAN Operation modes functions
- *
-@verbatim
- ===============================================================================
- ##### CAN Operation modes functions #####
- ===============================================================================
- [..] This section provides functions allowing to select the CAN Operation modes
- (+) sleep mode
- (+) normal mode
- (+) initialization mode
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Selects the CAN Operation mode.
- * @param CAN_OperatingMode: CAN Operating Mode.
- * This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration.
- * @retval status of the requested mode which can be
- * - CAN_ModeStatus_Failed: CAN failed entering the specific mode
- * - CAN_ModeStatus_Success: CAN Succeed entering the specific mode
- */
-uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
-{
- uint8_t status = CAN_ModeStatus_Failed;
-
- /* Timeout for INAK or also for SLAK bits*/
- uint32_t timeout = INAK_TIMEOUT;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
-
- if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
- {
- /* Request initialisation */
- CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
-
- /* Wait the acknowledge */
- while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
- {
- timeout--;
- }
- if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
- {
- status = CAN_ModeStatus_Failed;
- }
- else
- {
- status = CAN_ModeStatus_Success;
- }
- }
- else if (CAN_OperatingMode == CAN_OperatingMode_Normal)
- {
- /* Request leave initialisation and sleep mode and enter Normal mode */
- CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
-
- /* Wait the acknowledge */
- while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
- {
- timeout--;
- }
- if ((CANx->MSR & CAN_MODE_MASK) != 0)
- {
- status = CAN_ModeStatus_Failed;
- }
- else
- {
- status = CAN_ModeStatus_Success;
- }
- }
- else if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
- {
- /* Request Sleep mode */
- CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
-
- /* Wait the acknowledge */
- while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
- {
- timeout--;
- }
- if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
- {
- status = CAN_ModeStatus_Failed;
- }
- else
- {
- status = CAN_ModeStatus_Success;
- }
- }
- else
- {
- status = CAN_ModeStatus_Failed;
- }
-
- return (uint8_t) status;
-}
-
-/**
- * @brief Enters the Sleep (low power) mode.
- * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
- * @note CAN3 peripheral is available only for STM32F413_423xx devices
- * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise.
- */
-uint8_t CAN_Sleep(CAN_TypeDef* CANx)
-{
- uint8_t sleepstatus = CAN_Sleep_Failed;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Request Sleep mode */
- CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
-
- /* Sleep mode status */
- if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
- {
- /* Sleep mode not entered */
- sleepstatus = CAN_Sleep_Ok;
- }
- /* return sleep mode status */
- return (uint8_t)sleepstatus;
-}
-
-/**
- * @brief Wakes up the CAN peripheral from sleep mode .
- * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
- * @note CAN3 peripheral is available only for STM32F413_423xx devices
- * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise.
- */
-uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
-{
- uint32_t wait_slak = SLAK_TIMEOUT;
- uint8_t wakeupstatus = CAN_WakeUp_Failed;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Wake up request */
- CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
-
- /* Sleep mode status */
- while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
- {
- wait_slak--;
- }
- if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
- {
- /* wake up done : Sleep mode exited */
- wakeupstatus = CAN_WakeUp_Ok;
- }
- /* return wakeup status */
- return (uint8_t)wakeupstatus;
-}
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Group5 CAN Bus Error management functions
- * @brief CAN Bus Error management functions
- *
-@verbatim
- ===============================================================================
- ##### CAN Bus Error management functions #####
- ===============================================================================
- [..] This section provides functions allowing to
- (+) Return the CANx's last error code (LEC)
- (+) Return the CANx Receive Error Counter (REC)
- (+) Return the LSB of the 9-bit CANx Transmit Error Counter(TEC).
-
- -@- If TEC is greater than 255, The CAN is in bus-off state.
- -@- if REC or TEC are greater than 96, an Error warning flag occurs.
- -@- if REC or TEC are greater than 127, an Error Passive Flag occurs.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the CANx's last error code (LEC).
- * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
- * @retval Error code:
- * - CAN_ERRORCODE_NoErr: No Error
- * - CAN_ERRORCODE_StuffErr: Stuff Error
- * - CAN_ERRORCODE_FormErr: Form Error
- * - CAN_ERRORCODE_ACKErr : Acknowledgment Error
- * - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error
- * - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error
- * - CAN_ERRORCODE_CRCErr: CRC Error
- * - CAN_ERRORCODE_SoftwareSetErr: Software Set Error
- */
-uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx)
-{
- uint8_t errorcode=0;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Get the error code*/
- errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC);
-
- /* Return the error code*/
- return errorcode;
-}
-
-/**
- * @brief Returns the CANx Receive Error Counter (REC).
- * @note In case of an error during reception, this counter is incremented
- * by 1 or by 8 depending on the error condition as defined by the CAN
- * standard. After every successful reception, the counter is
- * decremented by 1 or reset to 120 if its value was higher than 128.
- * When the counter value exceeds 127, the CAN controller enters the
- * error passive state.
- * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
- * @note CAN3 peripheral is available only for STM32F413_423xx devices
- * @retval CAN Receive Error Counter.
- */
-uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)
-{
- uint8_t counter=0;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Get the Receive Error Counter*/
- counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);
-
- /* Return the Receive Error Counter*/
- return counter;
-}
-
-
-/**
- * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
- * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
- * @note CAN3 peripheral is available only for STM32F413_423xx devices
- * @retval LSB of the 9-bit CAN Transmit Error Counter.
- */
-uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
-{
- uint8_t counter=0;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
- counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);
-
- /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
- return counter;
-}
-/**
- * @}
- */
-
-/** @defgroup CAN_Group6 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure the CAN Interrupts
- and to get the status and clear flags and Interrupts pending bits.
-
- The CAN provides 14 Interrupts sources and 15 Flags:
-
-
- *** Flags ***
- =============
- [..] The 15 flags can be divided on 4 groups:
-
- (+) Transmit Flags
- (++) CAN_FLAG_RQCP0,
- (++) CAN_FLAG_RQCP1,
- (++) CAN_FLAG_RQCP2 : Request completed MailBoxes 0, 1 and 2 Flags
- Set when the last request (transmit or abort)
- has been performed.
-
- (+) Receive Flags
-
-
- (++) CAN_FLAG_FMP0,
- (++) CAN_FLAG_FMP1 : FIFO 0 and 1 Message Pending Flags
- set to signal that messages are pending in the receive
- FIFO.
- These Flags are cleared only by hardware.
-
- (++) CAN_FLAG_FF0,
- (++) CAN_FLAG_FF1 : FIFO 0 and 1 Full Flags
- set when three messages are stored in the selected
- FIFO.
-
- (++) CAN_FLAG_FOV0
- (++) CAN_FLAG_FOV1 : FIFO 0 and 1 Overrun Flags
- set when a new message has been received and passed
- the filter while the FIFO was full.
-
- (+) Operating Mode Flags
-
- (++) CAN_FLAG_WKU : Wake up Flag
- set to signal that a SOF bit has been detected while
- the CAN hardware was in Sleep mode.
-
- (++) CAN_FLAG_SLAK : Sleep acknowledge Flag
- Set to signal that the CAN has entered Sleep Mode.
-
- (+) Error Flags
-
- (++) CAN_FLAG_EWG : Error Warning Flag
- Set when the warning limit has been reached (Receive
- Error Counter or Transmit Error Counter greater than 96).
- This Flag is cleared only by hardware.
-
- (++) CAN_FLAG_EPV : Error Passive Flag
- Set when the Error Passive limit has been reached
- (Receive Error Counter or Transmit Error Counter
- greater than 127).
- This Flag is cleared only by hardware.
-
- (++) CAN_FLAG_BOF : Bus-Off Flag
- set when CAN enters the bus-off state. The bus-off
- state is entered on TEC overflow, greater than 255.
- This Flag is cleared only by hardware.
-
- (++) CAN_FLAG_LEC : Last error code Flag
- set If a message has been transferred (reception or
- transmission) with error, and the error code is hold.
-
- *** Interrupts ***
- ==================
- [..] The 14 interrupts can be divided on 4 groups:
-
- (+) Transmit interrupt
-
- (++) CAN_IT_TME : Transmit mailbox empty Interrupt
- if enabled, this interrupt source is pending when
- no transmit request are pending for Tx mailboxes.
-
- (+) Receive Interrupts
-
- (++) CAN_IT_FMP0,
- (++) CAN_IT_FMP1 : FIFO 0 and FIFO1 message pending Interrupts
- if enabled, these interrupt sources are pending
- when messages are pending in the receive FIFO.
- The corresponding interrupt pending bits are cleared
- only by hardware.
-
- (++) CAN_IT_FF0,
- (++) CAN_IT_FF1 : FIFO 0 and FIFO1 full Interrupts
- if enabled, these interrupt sources are pending
- when three messages are stored in the selected FIFO.
-
- (++) CAN_IT_FOV0,
- (++) CAN_IT_FOV1 : FIFO 0 and FIFO1 overrun Interrupts
- if enabled, these interrupt sources are pending
- when a new message has been received and passed
- the filter while the FIFO was full.
-
- (+) Operating Mode Interrupts
-
- (++) CAN_IT_WKU : Wake-up Interrupt
- if enabled, this interrupt source is pending when
- a SOF bit has been detected while the CAN hardware
- was in Sleep mode.
-
- (++) CAN_IT_SLK : Sleep acknowledge Interrupt
- if enabled, this interrupt source is pending when
- the CAN has entered Sleep Mode.
-
- (+) Error Interrupts
-
- (++) CAN_IT_EWG : Error warning Interrupt
- if enabled, this interrupt source is pending when
- the warning limit has been reached (Receive Error
- Counter or Transmit Error Counter=96).
-
- (++) CAN_IT_EPV : Error passive Interrupt
- if enabled, this interrupt source is pending when
- the Error Passive limit has been reached (Receive
- Error Counter or Transmit Error Counter>127).
-
- (++) CAN_IT_BOF : Bus-off Interrupt
- if enabled, this interrupt source is pending when
- CAN enters the bus-off state. The bus-off state is
- entered on TEC overflow, greater than 255.
- This Flag is cleared only by hardware.
-
- (++) CAN_IT_LEC : Last error code Interrupt
- if enabled, this interrupt source is pending when
- a message has been transferred (reception or
- transmission) with error, and the error code is hold.
-
- (++) CAN_IT_ERR : Error Interrupt
- if enabled, this interrupt source is pending when
- an error condition is pending.
-
- [..] Managing the CAN controller events :
-
- The user should identify which mode will be used in his application to
- manage the CAN controller events: Polling mode or Interrupt mode.
-
- (#) In the Polling Mode it is advised to use the following functions:
- (++) CAN_GetFlagStatus() : to check if flags events occur.
- (++) CAN_ClearFlag() : to clear the flags events.
-
-
-
- (#) In the Interrupt Mode it is advised to use the following functions:
- (++) CAN_ITConfig() : to enable or disable the interrupt source.
- (++) CAN_GetITStatus() : to check if Interrupt occurs.
- (++) CAN_ClearITPendingBit() : to clear the Interrupt pending Bit
- (corresponding Flag).
- -@@- This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts
- pending bits since there are cleared only by hardware.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Enables or disables the specified CANx interrupts.
- * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
- * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg CAN_IT_TME: Transmit mailbox empty Interrupt
- * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt
- * @arg CAN_IT_FF0: FIFO 0 full Interrupt
- * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
- * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt
- * @arg CAN_IT_FF1: FIFO 1 full Interrupt
- * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
- * @arg CAN_IT_WKU: Wake-up Interrupt
- * @arg CAN_IT_SLK: Sleep acknowledge Interrupt
- * @arg CAN_IT_EWG: Error warning Interrupt
- * @arg CAN_IT_EPV: Error passive Interrupt
- * @arg CAN_IT_BOF: Bus-off Interrupt
- * @arg CAN_IT_LEC: Last error code Interrupt
- * @arg CAN_IT_ERR: Error Interrupt
- * @param NewState: new state of the CAN interrupts.
- * @note CAN3 peripheral is available only for STM32F413_423xx devices
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_IT(CAN_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected CANx interrupt */
- CANx->IER |= CAN_IT;
- }
- else
- {
- /* Disable the selected CANx interrupt */
- CANx->IER &= ~CAN_IT;
- }
-}
-/**
- * @brief Checks whether the specified CAN flag is set or not.
- * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
- * @param CAN_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
- * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
- * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
- * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
- * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
- * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKU: Wake up Flag
- * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
- * @arg CAN_FLAG_EWG: Error Warning Flag
- * @arg CAN_FLAG_EPV: Error Passive Flag
- * @arg CAN_FLAG_BOF: Bus-Off Flag
- * @arg CAN_FLAG_LEC: Last error code Flag
- * @note CAN3 peripheral is available only for STM32F413_423xx devices
- * @retval The new state of CAN_FLAG (SET or RESET).
- */
-FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
-
-
- if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */
- {
- /* Check the status of the specified CAN flag */
- if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- /* Return the CAN_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the CAN's pending flags.
- * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
- * @param CAN_FLAG: specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
- * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
- * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
- * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKU: Wake up Flag
- * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
- * @arg CAN_FLAG_LEC: Last error code Flag
- * @note CAN3 peripheral is available only for STM32F413_423xx devices
- * @retval None
- */
-void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
-{
- uint32_t flagtmp=0;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
-
- if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */
- {
- /* Clear the selected CAN flags */
- CANx->ESR = (uint32_t)RESET;
- }
- else /* MSR or TSR or RF0R or RF1R */
- {
- flagtmp = CAN_FLAG & 0x000FFFFF;
-
- if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
- {
- /* Receive Flags */
- CANx->RF0R = (uint32_t)(flagtmp);
- }
- else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)
- {
- /* Receive Flags */
- CANx->RF1R = (uint32_t)(flagtmp);
- }
- else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)
- {
- /* Transmit Flags */
- CANx->TSR = (uint32_t)(flagtmp);
- }
- else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */
- {
- /* Operating mode Flags */
- CANx->MSR = (uint32_t)(flagtmp);
- }
- }
-}
-
-/**
- * @brief Checks whether the specified CANx interrupt has occurred or not.
- * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
- * @param CAN_IT: specifies the CAN interrupt source to check.
- * This parameter can be one of the following values:
- * @arg CAN_IT_TME: Transmit mailbox empty Interrupt
- * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt
- * @arg CAN_IT_FF0: FIFO 0 full Interrupt
- * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
- * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt
- * @arg CAN_IT_FF1: FIFO 1 full Interrupt
- * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
- * @arg CAN_IT_WKU: Wake-up Interrupt
- * @arg CAN_IT_SLK: Sleep acknowledge Interrupt
- * @arg CAN_IT_EWG: Error warning Interrupt
- * @arg CAN_IT_EPV: Error passive Interrupt
- * @arg CAN_IT_BOF: Bus-off Interrupt
- * @arg CAN_IT_LEC: Last error code Interrupt
- * @arg CAN_IT_ERR: Error Interrupt
- * @note CAN3 peripheral is available only for STM32F413_423xx devices
- * @retval The current state of CAN_IT (SET or RESET).
- */
-ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
-{
- ITStatus itstatus = RESET;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_IT(CAN_IT));
-
- /* check the interrupt enable bit */
- if((CANx->IER & CAN_IT) != RESET)
- {
- /* in case the Interrupt is enabled, .... */
- switch (CAN_IT)
- {
- case CAN_IT_TME:
- /* Check CAN_TSR_RQCPx bits */
- itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2);
- break;
- case CAN_IT_FMP0:
- /* Check CAN_RF0R_FMP0 bit */
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);
- break;
- case CAN_IT_FF0:
- /* Check CAN_RF0R_FULL0 bit */
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);
- break;
- case CAN_IT_FOV0:
- /* Check CAN_RF0R_FOVR0 bit */
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);
- break;
- case CAN_IT_FMP1:
- /* Check CAN_RF1R_FMP1 bit */
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);
- break;
- case CAN_IT_FF1:
- /* Check CAN_RF1R_FULL1 bit */
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);
- break;
- case CAN_IT_FOV1:
- /* Check CAN_RF1R_FOVR1 bit */
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);
- break;
- case CAN_IT_WKU:
- /* Check CAN_MSR_WKUI bit */
- itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);
- break;
- case CAN_IT_SLK:
- /* Check CAN_MSR_SLAKI bit */
- itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);
- break;
- case CAN_IT_EWG:
- /* Check CAN_ESR_EWGF bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);
- break;
- case CAN_IT_EPV:
- /* Check CAN_ESR_EPVF bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);
- break;
- case CAN_IT_BOF:
- /* Check CAN_ESR_BOFF bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);
- break;
- case CAN_IT_LEC:
- /* Check CAN_ESR_LEC bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);
- break;
- case CAN_IT_ERR:
- /* Check CAN_MSR_ERRI bit */
- itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI);
- break;
- default:
- /* in case of error, return RESET */
- itstatus = RESET;
- break;
- }
- }
- else
- {
- /* in case the Interrupt is not enabled, return RESET */
- itstatus = RESET;
- }
-
- /* Return the CAN_IT status */
- return itstatus;
-}
-
-/**
- * @brief Clears the CANx's interrupt pending bits.
- * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
- * @param CAN_IT: specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg CAN_IT_TME: Transmit mailbox empty Interrupt
- * @arg CAN_IT_FF0: FIFO 0 full Interrupt
- * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
- * @arg CAN_IT_FF1: FIFO 1 full Interrupt
- * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
- * @arg CAN_IT_WKU: Wake-up Interrupt
- * @arg CAN_IT_SLK: Sleep acknowledge Interrupt
- * @arg CAN_IT_EWG: Error warning Interrupt
- * @arg CAN_IT_EPV: Error passive Interrupt
- * @arg CAN_IT_BOF: Bus-off Interrupt
- * @arg CAN_IT_LEC: Last error code Interrupt
- * @arg CAN_IT_ERR: Error Interrupt
- * @note CAN3 peripheral is available only for STM32F413_423xx devices
- * @retval None
- */
-void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_CLEAR_IT(CAN_IT));
-
- switch (CAN_IT)
- {
- case CAN_IT_TME:
- /* Clear CAN_TSR_RQCPx (rc_w1)*/
- CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2;
- break;
- case CAN_IT_FF0:
- /* Clear CAN_RF0R_FULL0 (rc_w1)*/
- CANx->RF0R = CAN_RF0R_FULL0;
- break;
- case CAN_IT_FOV0:
- /* Clear CAN_RF0R_FOVR0 (rc_w1)*/
- CANx->RF0R = CAN_RF0R_FOVR0;
- break;
- case CAN_IT_FF1:
- /* Clear CAN_RF1R_FULL1 (rc_w1)*/
- CANx->RF1R = CAN_RF1R_FULL1;
- break;
- case CAN_IT_FOV1:
- /* Clear CAN_RF1R_FOVR1 (rc_w1)*/
- CANx->RF1R = CAN_RF1R_FOVR1;
- break;
- case CAN_IT_WKU:
- /* Clear CAN_MSR_WKUI (rc_w1)*/
- CANx->MSR = CAN_MSR_WKUI;
- break;
- case CAN_IT_SLK:
- /* Clear CAN_MSR_SLAKI (rc_w1)*/
- CANx->MSR = CAN_MSR_SLAKI;
- break;
- case CAN_IT_EWG:
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
- break;
- case CAN_IT_EPV:
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
- break;
- case CAN_IT_BOF:
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
- break;
- case CAN_IT_LEC:
- /* Clear LEC bits */
- CANx->ESR = RESET;
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- break;
- case CAN_IT_ERR:
- /*Clear LEC bits */
- CANx->ESR = RESET;
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/
- break;
- default:
- break;
- }
-}
- /**
- * @}
- */
-
-/**
- * @brief Checks whether the CAN interrupt has occurred or not.
- * @param CAN_Reg: specifies the CAN interrupt register to check.
- * @param It_Bit: specifies the interrupt source bit to check.
- * @retval The new state of the CAN Interrupt (SET or RESET).
- */
-static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
-{
- ITStatus pendingbitstatus = RESET;
-
- if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
- {
- /* CAN_IT is set */
- pendingbitstatus = SET;
- }
- else
- {
- /* CAN_IT is reset */
- pendingbitstatus = RESET;
- }
- return pendingbitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_can.h b/底盘/底盘-old/底盘/Library/stm32f4xx_can.h
deleted file mode 100644
index b0ee3af..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_can.h
+++ /dev/null
@@ -1,649 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_can.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the CAN firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_CAN_H
-#define __STM32F4xx_CAN_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup CAN
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(STM32F413_423xx)
-#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
- ((PERIPH) == CAN2) || \
- ((PERIPH) == CAN3))
-#else
-#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
- ((PERIPH) == CAN2))
-#endif /* STM32F413_423xx */
-
-/**
- * @brief CAN init structure definition
- */
-typedef struct
-{
- uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
- It ranges from 1 to 1024. */
-
- uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
- This parameter can be a value of @ref CAN_operating_mode */
-
- uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
- the CAN hardware is allowed to lengthen or
- shorten a bit to perform resynchronization.
- This parameter can be a value of @ref CAN_synchronisation_jump_width */
-
- uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit
- Segment 1. This parameter can be a value of
- @ref CAN_time_quantum_in_bit_segment_1 */
-
- uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
-
- FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
- This parameter can be set either to ENABLE or DISABLE. */
-} CAN_InitTypeDef;
-
-/**
- * @brief CAN filter init structure definition
- */
-typedef struct
-{
- uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
- configuration, first one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
- configuration, second one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
- according to the mode (MSBs for a 32-bit configuration,
- first one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
- according to the mode (LSBs for a 32-bit configuration,
- second one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
- This parameter can be a value of @ref CAN_filter_FIFO */
-
- uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
-
- uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
- This parameter can be a value of @ref CAN_filter_mode */
-
- uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
- This parameter can be a value of @ref CAN_filter_scale */
-
- FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
- This parameter can be set either to ENABLE or DISABLE. */
-} CAN_FilterInitTypeDef;
-
-/**
- * @brief CAN Tx message structure definition
- */
-typedef struct
-{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter can be a value between 0 to 0x7FF. */
-
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter can be a value between 0 to 0x1FFFFFFF. */
-
- uint8_t IDE; /*!< Specifies the type of identifier for the message that
- will be transmitted. This parameter can be a value
- of @ref CAN_identifier_type */
-
- uint8_t RTR; /*!< Specifies the type of frame for the message that will
- be transmitted. This parameter can be a value of
- @ref CAN_remote_transmission_request */
-
- uint8_t DLC; /*!< Specifies the length of the frame that will be
- transmitted. This parameter can be a value between
- 0 to 8 */
-
- uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
- to 0xFF. */
-} CanTxMsg;
-
-/**
- * @brief CAN Rx message structure definition
- */
-typedef struct
-{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter can be a value between 0 to 0x7FF. */
-
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter can be a value between 0 to 0x1FFFFFFF. */
-
- uint8_t IDE; /*!< Specifies the type of identifier for the message that
- will be received. This parameter can be a value of
- @ref CAN_identifier_type */
-
- uint8_t RTR; /*!< Specifies the type of frame for the received message.
- This parameter can be a value of
- @ref CAN_remote_transmission_request */
-
- uint8_t DLC; /*!< Specifies the length of the frame that will be received.
- This parameter can be a value between 0 to 8 */
-
- uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
- 0xFF. */
-
- uint8_t FMI; /*!< Specifies the index of the filter the message stored in
- the mailbox passes through. This parameter can be a
- value between 0 to 0xFF */
-} CanRxMsg;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CAN_Exported_Constants
- * @{
- */
-
-/** @defgroup CAN_InitStatus
- * @{
- */
-
-#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
-#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */
-
-
-/* Legacy defines */
-#define CANINITFAILED CAN_InitStatus_Failed
-#define CANINITOK CAN_InitStatus_Success
-/**
- * @}
- */
-
-/** @defgroup CAN_operating_mode
- * @{
- */
-
-#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
-#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
-#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
-#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
-
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
- ((MODE) == CAN_Mode_LoopBack)|| \
- ((MODE) == CAN_Mode_Silent) || \
- ((MODE) == CAN_Mode_Silent_LoopBack))
-/**
- * @}
- */
-
-
- /**
- * @defgroup CAN_operating_mode
- * @{
- */
-#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */
-#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */
-#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */
-
-
-#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
- ((MODE) == CAN_OperatingMode_Normal)|| \
- ((MODE) == CAN_OperatingMode_Sleep))
-/**
- * @}
- */
-
-/**
- * @defgroup CAN_operating_mode_status
- * @{
- */
-
-#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
-#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */
-/**
- * @}
- */
-
-/** @defgroup CAN_synchronisation_jump_width
- * @{
- */
-#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
-#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
-#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
-#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
-
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
- ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
-/**
- * @}
- */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_1
- * @{
- */
-#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
-#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
-#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
-#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
-#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
-#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
-#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
-#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
-#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
-#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
-#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
-#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
-#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
-#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
-#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
-#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
-
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
-/**
- * @}
- */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_2
- * @{
- */
-#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
-#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
-#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
-#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
-#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
-#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
-#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
-#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
-
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
-/**
- * @}
- */
-
-/** @defgroup CAN_clock_prescaler
- * @{
- */
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_number
- * @{
- */
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_mode
- * @{
- */
-#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */
-#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
-
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
- ((MODE) == CAN_FilterMode_IdList))
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_scale
- * @{
- */
-#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
-#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
-
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
- ((SCALE) == CAN_FilterScale_32bit))
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_FIFO
- * @{
- */
-#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
- ((FIFO) == CAN_FilterFIFO1))
-
-/* Legacy defines */
-#define CAN_FilterFIFO0 CAN_Filter_FIFO0
-#define CAN_FilterFIFO1 CAN_Filter_FIFO1
-/**
- * @}
- */
-
-/** @defgroup CAN_Start_bank_filter_for_slave_CAN
- * @{
- */
-#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
-/**
- * @}
- */
-
-/** @defgroup CAN_Tx
- * @{
- */
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
-#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
-#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
-#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
-/**
- * @}
- */
-
-/** @defgroup CAN_identifier_type
- * @{
- */
-#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */
-#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */
-#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
- ((IDTYPE) == CAN_Id_Extended))
-
-/* Legacy defines */
-#define CAN_ID_STD CAN_Id_Standard
-#define CAN_ID_EXT CAN_Id_Extended
-/**
- * @}
- */
-
-/** @defgroup CAN_remote_transmission_request
- * @{
- */
-#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */
-#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
-
-/* Legacy defines */
-#define CAN_RTR_DATA CAN_RTR_Data
-#define CAN_RTR_REMOTE CAN_RTR_Remote
-/**
- * @}
- */
-
-/** @defgroup CAN_transmit_constants
- * @{
- */
-#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */
-#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
-#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
-#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide
- an empty mailbox */
-/* Legacy defines */
-#define CANTXFAILED CAN_TxStatus_Failed
-#define CANTXOK CAN_TxStatus_Ok
-#define CANTXPENDING CAN_TxStatus_Pending
-#define CAN_NO_MB CAN_TxStatus_NoMailBox
-/**
- * @}
- */
-
-/** @defgroup CAN_receive_FIFO_number_constants
- * @{
- */
-#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
-#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
-
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
-/**
- * @}
- */
-
-/** @defgroup CAN_sleep_constants
- * @{
- */
-#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
-#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
-
-/* Legacy defines */
-#define CANSLEEPFAILED CAN_Sleep_Failed
-#define CANSLEEPOK CAN_Sleep_Ok
-/**
- * @}
- */
-
-/** @defgroup CAN_wake_up_constants
- * @{
- */
-#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
-#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
-
-/* Legacy defines */
-#define CANWAKEUPFAILED CAN_WakeUp_Failed
-#define CANWAKEUPOK CAN_WakeUp_Ok
-/**
- * @}
- */
-
-/**
- * @defgroup CAN_Error_Code_constants
- * @{
- */
-#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */
-#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
-#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */
-#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
-#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
-#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
-#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
-#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */
-/**
- * @}
- */
-
-/** @defgroup CAN_flags
- * @{
- */
-/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
- and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with
- CAN_GetFlagStatus() function. */
-
-/* Transmit Flags */
-#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
-#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
-#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
-
-/* Receive Flags */
-#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
-#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */
-#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */
-#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
-#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */
-#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */
-
-/* Operating Mode Flags */
-#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
-#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
-/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
- In this case the SLAK bit can be polled.*/
-
-/* Error Flags */
-#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */
-#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */
-#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
-#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
-
-#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
- ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
- ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
- ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
- ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
- ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
- ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
- ((FLAG) == CAN_FLAG_SLAK ))
-
-#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
- ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
- ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
- ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
- ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
-/**
- * @}
- */
-
-
-/** @defgroup CAN_interrupts
- * @{
- */
-#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
-
-/* Receive Interrupts */
-#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
-#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
-#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
-#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
-#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
-#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
-
-/* Operating Mode Interrupts */
-#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
-#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
-
-/* Error Interrupts */
-#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
-#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
-#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
-#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
-#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
-
-/* Flags named as Interrupts : kept only for FW compatibility */
-#define CAN_IT_RQCP0 CAN_IT_TME
-#define CAN_IT_RQCP1 CAN_IT_TME
-#define CAN_IT_RQCP2 CAN_IT_TME
-
-
-#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
- ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
- ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
- ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
-
-#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
- ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
- ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the CAN configuration to the default reset state *****/
-void CAN_DeInit(CAN_TypeDef* CANx);
-
-/* Initialization and Configuration functions *********************************/
-uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
-#if defined(STM32F413_423xx)
-void CAN_FilterInit(CAN_TypeDef* CANx, CAN_FilterInitTypeDef* CAN_FilterInitStruct);
-#else
-void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
-#endif /* STM32F413_423xx */
-void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
-#if defined(STM32F413_423xx)
-void CAN_SlaveStartBank(CAN_TypeDef* CANx, uint8_t CAN_BankNumber);
-#else
-void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
-#endif /* STM32F413_423xx */
-void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
-void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
-
-/* CAN Frames Transmission functions ******************************************/
-uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
-uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
-void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
-
-/* CAN Frames Reception functions *********************************************/
-void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
-void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
-uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
-
-/* Operation modes functions **************************************************/
-uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
-uint8_t CAN_Sleep(CAN_TypeDef* CANx);
-uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
-
-/* CAN Bus Error management functions *****************************************/
-uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
-uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
-uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
-
-/* Interrupts and flags management functions **********************************/
-void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
-FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
-void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
-ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
-void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_CAN_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_cec.c b/底盘/底盘-old/底盘/Library/stm32f4xx_cec.c
deleted file mode 100644
index 70fe5fb..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_cec.c
+++ /dev/null
@@ -1,600 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_cec.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Consumer Electronics Control (CEC) peripheral
- * applicable only on STM32F446xx devices:
- * + Initialization and Configuration
- * + Data transfers functions
- * + Interrupts and flags management
- *
- * @verbatim
- ==============================================================================
- ##### CEC features #####
- ==============================================================================
- [..] This device provides some features:
- (#) Supports HDMI-CEC specification 1.4.
- (#) Supports two source clocks(HSI/244 or LSE).
- (#) Works in stop mode(without APB clock, but with CEC clock 32KHz).
- It can genarate an interrupt in the CEC clock domain that the CPU
- wakes up from the low power mode.
- (#) Configurable Signal Free Time before of transmission start. The
- number of nominal data bit periods waited before transmission can be
- ruled by Hardware or Software.
- (#) Configurable Peripheral Address (multi-addressing configuration).
- (#) Supports listen mode.The CEC Messages addressed to different destination
- can be received without interfering with CEC bus when Listen mode option is enabled.
- (#) Configurable Rx-Tolerance(Standard and Extended tolerance margin).
- (#) Error detection with configurable error bit generation.
- (#) Arbitration lost error in the case of two CEC devices starting at the same time.
-
- ##### How to use this driver #####
- ==============================================================================
- [..] This driver provides functions to configure and program the CEC device,
- follow steps below:
- (#) The source clock can be configured using:
- (++) RCC_CECCLKConfig(RCC_CECCLK_HSI_Div244) for HSI(Default)
- (++) RCC_CECCLKConfig(RCC_CECCLK_LSE) for LSE.
- (#) Enable CEC peripheral clock using RCC_APBPeriphClockCmd(RCC_APBPeriph_CEC, ENABLE).
- (#) Peripherals alternate function.
- (++) Connect the pin to the desired peripherals' Alternate Function (AF) using
- GPIO_PinAFConfig() function.
- (++) Configure the desired pin in alternate function by:
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
- (++) Select the type open-drain and output speed via GPIO_OType
- and GPIO_Speed members.
- (++) Call GPIO_Init() function.
- (#) Configure the Signal Free Time, Rx Tolerance, Stop reception generation
- and Bit error generation using the CEC_Init() function.
- The function CEC_Init() must be called when the CEC peripheral is disabled.
- (#) Configure the CEC own address by calling the fuction CEC_OwnAddressConfig().
- (#) Optionally, you can configure the Listen mode using the function CEC_ListenModeCmd().
- (#) Enable the NVIC and the corresponding interrupt using the function
- CEC_ITConfig() if you need to use interrupt mode.
- CEC_ITConfig() must be called before enabling the CEC peripheral.
- (#) Enable the CEC using the CEC_Cmd() function.
- (#) Charge the first data byte in the TXDR register using CEC_SendDataByte().
- (#) Enable the transmission of the Byte of a CEC message using CEC_StartOfMessage()
- (#) Transmit single data through the CEC peripheral using CEC_SendDataByte()
- and Receive the last transmitted byte using CEC_ReceiveDataByte().
- (#) Enable the CEC_EndOfMessage() in order to indicate the last byte of the message.
- [..]
- (@) If the listen mode is enabled, Stop reception generation and Bit error generation
- must be in reset state.
- (@) If the CEC message consists of only 1 byte, the function CEC_EndOfMessage()
- must be called before CEC_StartOfMessage().
-
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_cec.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CEC
- * @brief CEC driver modules
- * @{
- */
-#if defined(STM32F446xx)
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define BROADCAST_ADDRESS ((uint32_t)0x0000F)
-#define CFGR_CLEAR_MASK ((uint32_t)0x7000FE00) /* CFGR register Mask */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CEC_Private_Functions
- * @{
- */
-
-/** @defgroup CEC_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to initialize:
- (+) CEC own addresses
- (+) CEC Signal Free Time
- (+) CEC Rx Tolerance
- (+) CEC Stop Reception
- (+) CEC Bit Rising Error
- (+) CEC Long Bit Period Error
- [..] This section provides also a function to configure the CEC peripheral in Listen Mode.
- Messages addressed to different destination can be received when Listen mode is
- enabled without interfering with CEC bus.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the CEC peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void CEC_DeInit(void)
-{
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
-}
-
-/**
- * @brief Initializes the CEC peripheral according to the specified parameters
- * in the CEC_InitStruct.
- * @note The CEC parameters must be configured before enabling the CEC peripheral.
- * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that contains
- * the configuration information for the specified CEC peripheral.
- * @retval None
- */
-void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_CEC_SIGNAL_FREE_TIME(CEC_InitStruct->CEC_SignalFreeTime));
- assert_param(IS_CEC_RX_TOLERANCE(CEC_InitStruct->CEC_RxTolerance));
- assert_param(IS_CEC_STOP_RECEPTION(CEC_InitStruct->CEC_StopReception));
- assert_param(IS_CEC_BIT_RISING_ERROR(CEC_InitStruct->CEC_BitRisingError));
- assert_param(IS_CEC_LONG_BIT_PERIOD_ERROR(CEC_InitStruct->CEC_LongBitPeriodError));
- assert_param(IS_CEC_BDR_NO_GEN_ERROR(CEC_InitStruct->CEC_BRDNoGen));
- assert_param(IS_CEC_SFT_OPTION(CEC_InitStruct->CEC_SFTOption));
-
- /* Get the CEC CFGR value */
- tmpreg = CEC->CFGR;
-
- /* Clear CFGR bits */
- tmpreg &= CFGR_CLEAR_MASK;
-
- /* Configure the CEC peripheral */
- tmpreg |= (CEC_InitStruct->CEC_SignalFreeTime | CEC_InitStruct->CEC_RxTolerance |
- CEC_InitStruct->CEC_StopReception | CEC_InitStruct->CEC_BitRisingError |
- CEC_InitStruct->CEC_LongBitPeriodError| CEC_InitStruct->CEC_BRDNoGen |
- CEC_InitStruct->CEC_SFTOption);
-
- /* Write to CEC CFGR register */
- CEC->CFGR = tmpreg;
-}
-
-/**
- * @brief Fills each CEC_InitStruct member with its default value.
- * @param CEC_InitStruct: pointer to a CEC_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct)
-{
- CEC_InitStruct->CEC_SignalFreeTime = CEC_SignalFreeTime_Standard;
- CEC_InitStruct->CEC_RxTolerance = CEC_RxTolerance_Standard;
- CEC_InitStruct->CEC_StopReception = CEC_StopReception_Off;
- CEC_InitStruct->CEC_BitRisingError = CEC_BitRisingError_Off;
- CEC_InitStruct->CEC_LongBitPeriodError = CEC_LongBitPeriodError_Off;
- CEC_InitStruct->CEC_BRDNoGen = CEC_BRDNoGen_Off;
- CEC_InitStruct->CEC_SFTOption = CEC_SFTOption_Off;
-}
-
-/**
- * @brief Enables or disables the CEC peripheral.
- * @param NewState: new state of the CEC peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CEC_Cmd(FunctionalState NewState)
-{
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the CEC peripheral */
- CEC->CR |= CEC_CR_CECEN;
- }
- else
- {
- /* Disable the CEC peripheral */
- CEC->CR &= ~CEC_CR_CECEN;
- }
-}
-
-/**
- * @brief Enables or disables the CEC Listen Mode.
- * @param NewState: new state of the Listen Mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CEC_ListenModeCmd(FunctionalState NewState)
-{
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Listen Mode */
- CEC->CFGR |= CEC_CFGR_LSTN;
- }
- else
- {
- /* Disable the Listen Mode */
- CEC->CFGR &= ~CEC_CFGR_LSTN;
- }
-}
-
-/**
- * @brief Defines the Own Address of the CEC device.
- * @param CEC_OwnAddress: The CEC own address.
- * @retval None
- */
-void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
-{
- uint32_t tmp =0x00;
- /* Check the parameters */
- assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
- tmp = 1 <<(CEC_OwnAddress + 16);
- /* Set the CEC own address */
- CEC->CFGR |= tmp;
-}
-
-/**
- * @brief Clears the Own Address of the CEC device.
- * @param CEC_OwnAddress: The CEC own address.
- * @retval None
- */
-void CEC_OwnAddressClear(void)
-{
- /* Set the CEC own address */
- CEC->CFGR = 0x0;
-}
-
-/**
- * @}
- */
-
-/** @defgroup CEC_Group2 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers functions #####
- ===============================================================================
- [..] This section provides functions allowing the CEC data transfers.The read
- access of the CEC_RXDR register can be done using the CEC_ReceiveData()function
- and returns the Rx buffered value. Whereas a write access to the CEC_TXDR can be
- done using CEC_SendData() function.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmits single data through the CEC peripheral.
- * @param Data: the data to transmit.
- * @retval None
- */
-void CEC_SendData(uint8_t Data)
-{
- /* Transmit Data */
- CEC->TXDR = Data;
-}
-
-/**
- * @brief Returns the most recent received data by the CEC peripheral.
- * @param None
- * @retval The received data.
- */
-uint8_t CEC_ReceiveData(void)
-{
- /* Receive Data */
- return (uint8_t)(CEC->RXDR);
-}
-
-/**
- * @brief Starts a new message.
- * @param None
- * @retval None
- */
-void CEC_StartOfMessage(void)
-{
- /* Starts of new message */
- CEC->CR |= CEC_CR_TXSOM;
-}
-
-/**
- * @brief Transmits message with an EOM bit.
- * @param None
- * @retval None
- */
-void CEC_EndOfMessage(void)
-{
- /* The data byte will be transmitted with an EOM bit */
- CEC->CR |= CEC_CR_TXEOM;
-}
-
-/**
- * @}
- */
-
-/** @defgroup CEC_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
-*
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the CEC Interrupts
- sources and check or clear the flags or pending bits status.
- [..] The user should identify which mode will be used in his application to manage
- the communication: Polling mode or Interrupt mode.
-
- [..] In polling mode, the CEC can be managed by the following flags:
- (+) CEC_FLAG_TXACKE : to indicate a missing acknowledge in transmission mode.
- (+) CEC_FLAG_TXERR : to indicate an error occurs during transmission mode.
- The initiator detects low impedance in the CEC line.
- (+) CEC_FLAG_TXUDR : to indicate if an underrun error occurs in transmission mode.
- The transmission is enabled while the software has not yet
- loaded any value into the TXDR register.
- (+) CEC_FLAG_TXEND : to indicate the end of successful transmission.
- (+) CEC_FLAG_TXBR : to indicate the next transmission data has to be written to TXDR.
- (+) CEC_FLAG_ARBLST : to indicate arbitration lost in the case of two CEC devices
- starting at the same time.
- (+) CEC_FLAG_RXACKE : to indicate a missing acknowledge in receive mode.
- (+) CEC_FLAG_LBPE : to indicate a long bit period error generated during receive mode.
- (+) CEC_FLAG_SBPE : to indicate a short bit period error generated during receive mode.
- (+) CEC_FLAG_BRE : to indicate a bit rising error generated during receive mode.
- (+) CEC_FLAG_RXOVR : to indicate if an overrun error occur while receiving a CEC message.
- A byte is not yet received while a new byte is stored in the RXDR register.
- (+) CEC_FLAG_RXEND : to indicate the end Of reception
- (+) CEC_FLAG_RXBR : to indicate a new byte has been received from the CEC line and
- stored into the RXDR buffer.
- [..]
- (@)In this Mode, it is advised to use the following functions:
- FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG);
- void CEC_ClearFlag(uint16_t CEC_FLAG);
-
- [..] In Interrupt mode, the CEC can be managed by the following interrupt sources:
- (+) CEC_IT_TXACKE : to indicate a TX Missing acknowledge
- (+) CEC_IT_TXACKE : to indicate a missing acknowledge in transmission mode.
- (+) CEC_IT_TXERR : to indicate an error occurs during transmission mode.
- The initiator detects low impedance in the CEC line.
- (+) CEC_IT_TXUDR : to indicate if an underrun error occurs in transmission mode.
- The transmission is enabled while the software has not yet
- loaded any value into the TXDR register.
- (+) CEC_IT_TXEND : to indicate the end of successful transmission.
- (+) CEC_IT_TXBR : to indicate the next transmission data has to be written to TXDR register.
- (+) CEC_IT_ARBLST : to indicate arbitration lost in the case of two CEC devices
- starting at the same time.
- (+) CEC_IT_RXACKE : to indicate a missing acknowledge in receive mode.
- (+) CEC_IT_LBPE : to indicate a long bit period error generated during receive mode.
- (+) CEC_IT_SBPE : to indicate a short bit period error generated during receive mode.
- (+) CEC_IT_BRE : to indicate a bit rising error generated during receive mode.
- (+) CEC_IT_RXOVR : to indicate if an overrun error occur while receiving a CEC message.
- A byte is not yet received while a new byte is stored in the RXDR register.
- (+) CEC_IT_RXEND : to indicate the end Of reception
- (+) CEC_IT_RXBR : to indicate a new byte has been received from the CEC line and
- stored into the RXDR buffer.
- [..]
- (@)In this Mode it is advised to use the following functions:
- void CEC_ITConfig( uint16_t CEC_IT, FunctionalState NewState);
- ITStatus CEC_GetITStatus(uint16_t CEC_IT);
- void CEC_ClearITPendingBit(uint16_t CEC_IT);
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the selected CEC interrupts.
- * @param CEC_IT: specifies the CEC interrupt source to be enabled.
- * This parameter can be any combination of the following values:
- * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
- * @arg CEC_IT_TXERR: Tx Error.
- * @arg CEC_IT_TXUDR: Tx-Buffer Underrun.
- * @arg CEC_IT_TXEND: End of Transmission (successful transmission of the last byte).
- * @arg CEC_IT_TXBR: Tx-Byte Request.
- * @arg CEC_IT_ARBLST: Arbitration Lost
- * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge
- * @arg CEC_IT_LBPE: Rx Long period Error
- * @arg CEC_IT_SBPE: Rx Short period Error
- * @arg CEC_IT_BRE: Rx Bit Rising Error
- * @arg CEC_IT_RXOVR: Rx Overrun.
- * @arg CEC_IT_RXEND: End Of Reception
- * @arg CEC_IT_RXBR: Rx-Byte Received
- * @param NewState: new state of the selected CEC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState)
-{
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_CEC_IT(CEC_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected CEC interrupt */
- CEC->IER |= CEC_IT;
- }
- else
- {
- CEC_IT =~CEC_IT;
- /* Disable the selected CEC interrupt */
- CEC->IER &= CEC_IT;
- }
-}
-
-/**
- * @brief Gets the CEC flag status.
- * @param CEC_FLAG: specifies the CEC flag to check.
- * This parameter can be one of the following values:
- * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
- * @arg CEC_FLAG_TXERR: Tx Error.
- * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
- * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
- * @arg CEC_FLAG_TXBR: Tx-Byte Request.
- * @arg CEC_FLAG_ARBLST: Arbitration Lost
- * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
- * @arg CEC_FLAG_LBPE: Rx Long period Error
- * @arg CEC_FLAG_SBPE: Rx Short period Error
- * @arg CEC_FLAG_BRE: Rx Bit Rissing Error
- * @arg CEC_FLAG_RXOVR: Rx Overrun.
- * @arg CEC_FLAG_RXEND: End Of Reception.
- * @arg CEC_FLAG_RXBR: Rx-Byte Received.
- * @retval The new state of CEC_FLAG (SET or RESET)
- */
-FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
-
- /* Check the status of the specified CEC flag */
- if ((CEC->ISR & CEC_FLAG) != (uint16_t)RESET)
- {
- /* CEC flag is set */
- bitstatus = SET;
- }
- else
- {
- /* CEC flag is reset */
- bitstatus = RESET;
- }
-
- /* Return the CEC flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the CEC's pending flags.
- * @param CEC_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
- * @arg CEC_FLAG_TXERR: Tx Error
- * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun
- * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
- * @arg CEC_FLAG_TXBR: Tx-Byte Request
- * @arg CEC_FLAG_ARBLST: Arbitration Lost
- * @arg CEC_FLAG_RXACKE: Rx Missing Acknowledge
- * @arg CEC_FLAG_LBPE: Rx Long period Error
- * @arg CEC_FLAG_SBPE: Rx Short period Error
- * @arg CEC_FLAG_BRE: Rx Bit Rising Error
- * @arg CEC_FLAG_RXOVR: Rx Overrun
- * @arg CEC_FLAG_RXEND: End Of Reception
- * @arg CEC_FLAG_RXBR: Rx-Byte Received
- * @retval None
- */
-void CEC_ClearFlag(uint32_t CEC_FLAG)
-{
- assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
-
- /* Clear the selected CEC flag */
- CEC->ISR = CEC_FLAG;
-}
-
-/**
- * @brief Checks whether the specified CEC interrupt has occurred or not.
- * @param CEC_IT: specifies the CEC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
- * @arg CEC_IT_TXERR: Tx Error.
- * @arg CEC_IT_TXUDR: Tx-Buffer Underrun.
- * @arg CEC_IT_TXEND: End of transmission (successful transmission of the last byte).
- * @arg CEC_IT_TXBR: Tx-Byte Request.
- * @arg CEC_IT_ARBLST: Arbitration Lost.
- * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge.
- * @arg CEC_IT_LBPE: Rx Long period Error.
- * @arg CEC_IT_SBPE: Rx Short period Error.
- * @arg CEC_IT_BRE: Rx Bit Rising Error.
- * @arg CEC_IT_RXOVR: Rx Overrun.
- * @arg CEC_IT_RXEND: End Of Reception.
- * @arg CEC_IT_RXBR: Rx-Byte Received
- * @retval The new state of CEC_IT (SET or RESET).
- */
-ITStatus CEC_GetITStatus(uint16_t CEC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_CEC_GET_IT(CEC_IT));
-
- /* Get the CEC IT enable bit status */
- enablestatus = (CEC->IER & CEC_IT);
-
- /* Check the status of the specified CEC interrupt */
- if (((CEC->ISR & CEC_IT) != (uint32_t)RESET) && enablestatus)
- {
- /* CEC interrupt is set */
- bitstatus = SET;
- }
- else
- {
- /* CEC interrupt is reset */
- bitstatus = RESET;
- }
-
- /* Return the CEC interrupt status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the CEC's interrupt pending bits.
- * @param CEC_IT: specifies the CEC interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
- * @arg CEC_IT_TXERR: Tx Error
- * @arg CEC_IT_TXUDR: Tx-Buffer Underrun
- * @arg CEC_IT_TXEND: End of Transmission
- * @arg CEC_IT_TXBR: Tx-Byte Request
- * @arg CEC_IT_ARBLST: Arbitration Lost
- * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge
- * @arg CEC_IT_LBPE: Rx Long period Error
- * @arg CEC_IT_SBPE: Rx Short period Error
- * @arg CEC_IT_BRE: Rx Bit Rising Error
- * @arg CEC_IT_RXOVR: Rx Overrun
- * @arg CEC_IT_RXEND: End Of Reception
- * @arg CEC_IT_RXBR: Rx-Byte Received
- * @retval None
- */
-void CEC_ClearITPendingBit(uint16_t CEC_IT)
-{
- assert_param(IS_CEC_IT(CEC_IT));
-
- /* Clear the selected CEC interrupt pending bits */
- CEC->ISR = CEC_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* STM32F446xx */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_cec.h b/底盘/底盘-old/底盘/Library/stm32f4xx_cec.h
deleted file mode 100644
index dc7d69e..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_cec.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_cec.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the CEC firmware
- * library, applicable only for STM32F466xx devices.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4XX_CEC_H
-#define __STM32F4XX_CEC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup CEC
- * @{
- */
-#if defined(STM32F446xx)
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief CEC Init structure definition
- */
-typedef struct
-{
- uint32_t CEC_SignalFreeTime; /*!< Specifies the CEC Signal Free Time configuration.
- This parameter can be a value of @ref CEC_Signal_Free_Time */
- uint32_t CEC_RxTolerance; /*!< Specifies the CEC Reception Tolerance.
- This parameter can be a value of @ref CEC_RxTolerance */
- uint32_t CEC_StopReception; /*!< Specifies the CEC Stop Reception.
- This parameter can be a value of @ref CEC_Stop_Reception */
- uint32_t CEC_BitRisingError; /*!< Specifies the CEC Bit Rising Error generation.
- This parameter can be a value of @ref CEC_Bit_Rising_Error_Generation */
- uint32_t CEC_LongBitPeriodError; /*!< Specifies the CEC Long Bit Error generation.
- This parameter can be a value of @ref CEC_Long_Bit_Error_Generation */
- uint32_t CEC_BRDNoGen; /*!< Specifies the CEC Broadcast Error generation.
- This parameter can be a value of @ref CEC_BDR_No_Gen */
- uint32_t CEC_SFTOption; /*!< Specifies the CEC Signal Free Time option.
- This parameter can be a value of @ref CEC_SFT_Option */
-
-}CEC_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CEC_Exported_Constants
- * @{
- */
-
-/** @defgroup CEC_Signal_Free_Time
- * @{
- */
-#define CEC_SignalFreeTime_Standard ((uint32_t)0x00000000) /*!< CEC Signal Free Time Standard */
-#define CEC_SignalFreeTime_1T ((uint32_t)0x00000001) /*!< CEC 1.5 nominal data bit periods */
-#define CEC_SignalFreeTime_2T ((uint32_t)0x00000002) /*!< CEC 2.5 nominal data bit periods */
-#define CEC_SignalFreeTime_3T ((uint32_t)0x00000003) /*!< CEC 3.5 nominal data bit periods */
-#define CEC_SignalFreeTime_4T ((uint32_t)0x00000004) /*!< CEC 4.5 nominal data bit periods */
-#define CEC_SignalFreeTime_5T ((uint32_t)0x00000005) /*!< CEC 5.5 nominal data bit periods */
-#define CEC_SignalFreeTime_6T ((uint32_t)0x00000006) /*!< CEC 6.5 nominal data bit periods */
-#define CEC_SignalFreeTime_7T ((uint32_t)0x00000007) /*!< CEC 7.5 nominal data bit periods */
-
-#define IS_CEC_SIGNAL_FREE_TIME(TIME) (((TIME) == CEC_SignalFreeTime_Standard) || \
- ((TIME) == CEC_SignalFreeTime_1T)|| \
- ((TIME) == CEC_SignalFreeTime_2T)|| \
- ((TIME) == CEC_SignalFreeTime_3T)|| \
- ((TIME) == CEC_SignalFreeTime_4T)|| \
- ((TIME) == CEC_SignalFreeTime_5T)|| \
- ((TIME) == CEC_SignalFreeTime_6T)|| \
- ((TIME) == CEC_SignalFreeTime_7T))
-/**
- * @}
- */
-
-/** @defgroup CEC_RxTolerance
- * @{
- */
-#define CEC_RxTolerance_Standard ((uint32_t)0x00000000) /*!< Standard Tolerance Margin */
-#define CEC_RxTolerance_Extended CEC_CFGR_RXTOL /*!< Extended Tolerance Margin */
-
-#define IS_CEC_RX_TOLERANCE(TOLERANCE) (((TOLERANCE) == CEC_RxTolerance_Standard) || \
- ((TOLERANCE) == CEC_RxTolerance_Extended))
-/**
- * @}
- */
-
-/** @defgroup CEC_Stop_Reception
- * @{
- */
-#define CEC_StopReception_Off ((uint32_t)0x00000000) /*!< No RX Stop on bit Rising Error (BRE) */
-#define CEC_StopReception_On CEC_CFGR_BRESTP /*!< RX Stop on bit Rising Error (BRE) */
-
-#define IS_CEC_STOP_RECEPTION(RECEPTION) (((RECEPTION) == CEC_StopReception_On) || \
- ((RECEPTION) == CEC_StopReception_Off))
-/**
- * @}
- */
-
-/** @defgroup CEC_Bit_Rising_Error_Generation
- * @{
- */
-#define CEC_BitRisingError_Off ((uint32_t)0x00000000) /*!< Bit Rising Error generation turned Off */
-#define CEC_BitRisingError_On CEC_CFGR_BREGEN /*!< Bit Rising Error generation turned On */
-
-#define IS_CEC_BIT_RISING_ERROR(ERROR) (((ERROR) == CEC_BitRisingError_Off) || \
- ((ERROR) == CEC_BitRisingError_On))
-/**
- * @}
- */
-
-/** @defgroup CEC_Long_Bit_Error_Generation
- * @{
- */
-#define CEC_LongBitPeriodError_Off ((uint32_t)0x00000000) /*!< Long Bit Period Error generation turned Off */
-#define CEC_LongBitPeriodError_On CEC_CFGR_LREGEN /*!< Long Bit Period Error generation turned On */
-
-#define IS_CEC_LONG_BIT_PERIOD_ERROR(ERROR) (((ERROR) == CEC_LongBitPeriodError_Off) || \
- ((ERROR) == CEC_LongBitPeriodError_On))
-/**
- * @}
- */
-
-/** @defgroup CEC_BDR_No_Gen
- * @{
- */
-
-#define CEC_BRDNoGen_Off ((uint32_t)0x00000000) /*!< Broadcast Bit Rising Error generation turned Off */
-#define CEC_BRDNoGen_On CEC_CFGR_BRDNOGEN /*!< Broadcast Bit Rising Error generation turned On */
-
-#define IS_CEC_BDR_NO_GEN_ERROR(ERROR) (((ERROR) == CEC_BRDNoGen_Off) || \
- ((ERROR) == CEC_BRDNoGen_On))
-/**
- * @}
- */
-
-/** @defgroup CEC_SFT_Option
- * @{
- */
-#define CEC_SFTOption_Off ((uint32_t)0x00000000) /*!< SFT option turned Off */
-#define CEC_SFTOption_On CEC_CFGR_SFTOPT /*!< SFT option turned On */
-
-#define IS_CEC_SFT_OPTION(OPTION) (((OPTION) == CEC_SFTOption_Off) || \
- ((OPTION) == CEC_SFTOption_On))
-/**
- * @}
- */
-
-/** @defgroup CEC_Own_Address
- * @{
- */
-#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
-
-/**
- * @}
- */
-
-/** @defgroup CEC_Interrupt_Configuration_definition
- * @{
- */
-#define CEC_IT_TXACKE CEC_IER_TXACKEIE
-#define CEC_IT_TXERR CEC_IER_TXERRIE
-#define CEC_IT_TXUDR CEC_IER_TXUDRIE
-#define CEC_IT_TXEND CEC_IER_TXENDIE
-#define CEC_IT_TXBR CEC_IER_TXBRIE
-#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
-#define CEC_IT_RXACKE CEC_IER_RXACKEIE
-#define CEC_IT_LBPE CEC_IER_LBPEIE
-#define CEC_IT_SBPE CEC_IER_SBPEIE
-#define CEC_IT_BRE CEC_IER_BREIEIE
-#define CEC_IT_RXOVR CEC_IER_RXOVRIE
-#define CEC_IT_RXEND CEC_IER_RXENDIE
-#define CEC_IT_RXBR CEC_IER_RXBRIE
-
-#define IS_CEC_IT(IT) ((((IT) & (uint32_t)0xFFFFE000) == 0x00) && ((IT) != 0x00))
-
-#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TXACKE) || \
- ((IT) == CEC_IT_TXERR)|| \
- ((IT) == CEC_IT_TXUDR)|| \
- ((IT) == CEC_IT_TXEND)|| \
- ((IT) == CEC_IT_TXBR)|| \
- ((IT) == CEC_IT_ARBLST)|| \
- ((IT) == CEC_IT_RXACKE)|| \
- ((IT) == CEC_IT_LBPE)|| \
- ((IT) == CEC_IT_SBPE)|| \
- ((IT) == CEC_IT_BRE)|| \
- ((IT) == CEC_IT_RXOVR)|| \
- ((IT) == CEC_IT_RXEND)|| \
- ((IT) == CEC_IT_RXBR))
-/**
- * @}
- */
-
-/** @defgroup CEC_ISR_register_flags_definition
- * @{
- */
-#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
-#define CEC_FLAG_TXERR CEC_ISR_TXERR
-#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
-#define CEC_FLAG_TXEND CEC_ISR_TXEND
-#define CEC_FLAG_TXBR CEC_ISR_TXBR
-#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
-#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
-#define CEC_FLAG_LBPE CEC_ISR_LBPE
-#define CEC_FLAG_SBPE CEC_ISR_SBPE
-#define CEC_FLAG_BRE CEC_ISR_BRE
-#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
-#define CEC_FLAG_RXEND CEC_ISR_RXEND
-#define CEC_FLAG_RXBR CEC_ISR_RXBR
-
-#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE000) == 0x00) && ((FLAG) != 0x00))
-
-#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_TXACKE) || \
- ((FLAG) == CEC_FLAG_TXERR)|| \
- ((FLAG) == CEC_FLAG_TXUDR)|| \
- ((FLAG) == CEC_FLAG_TXEND)|| \
- ((FLAG) == CEC_FLAG_TXBR)|| \
- ((FLAG) == CEC_FLAG_ARBLST)|| \
- ((FLAG) == CEC_FLAG_RXACKE)|| \
- ((FLAG) == CEC_FLAG_LBPE)|| \
- ((FLAG) == CEC_FLAG_SBPE)|| \
- ((FLAG) == CEC_FLAG_BRE)|| \
- ((FLAG) == CEC_FLAG_RXOVR)|| \
- ((FLAG) == CEC_FLAG_RXEND)|| \
- ((FLAG) == CEC_FLAG_RXBR))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the CEC configuration to the default reset state *****/
-void CEC_DeInit(void);
-
-/* CEC_Initialization and Configuration functions *****************************/
-void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
-void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct);
-void CEC_Cmd(FunctionalState NewState);
-void CEC_ListenModeCmd(FunctionalState NewState);
-void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
-void CEC_OwnAddressClear(void);
-
-/* CEC_Data transfers functions ***********************************************/
-void CEC_SendData(uint8_t Data);
-uint8_t CEC_ReceiveData(void);
-void CEC_StartOfMessage(void);
-void CEC_EndOfMessage(void);
-
-/* CEC_Interrupts and flags management functions ******************************/
-void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState);
-FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG);
-void CEC_ClearFlag(uint32_t CEC_FLAG);
-ITStatus CEC_GetITStatus(uint16_t CEC_IT);
-void CEC_ClearITPendingBit(uint16_t CEC_IT);
-#endif /* STM32F446xx */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_CEC_H */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_crc.c b/底盘/底盘-old/底盘/Library/stm32f4xx_crc.c
deleted file mode 100644
index 3fa0c4a..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_crc.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_crc.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides all the CRC firmware functions.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_crc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CRC
- * @brief CRC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRC_Private_Functions
- * @{
- */
-
-/**
- * @brief Resets the CRC Data register (DR).
- * @param None
- * @retval None
- */
-void CRC_ResetDR(void)
-{
- /* Reset CRC generator */
- CRC->CR = CRC_CR_RESET;
-}
-
-/**
- * @brief Computes the 32-bit CRC of a given data word(32-bit).
- * @param Data: data word(32-bit) to compute its CRC
- * @retval 32-bit CRC
- */
-uint32_t CRC_CalcCRC(uint32_t Data)
-{
- CRC->DR = Data;
-
- return (CRC->DR);
-}
-
-/**
- * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
- * @param pBuffer: pointer to the buffer containing the data to be computed
- * @param BufferLength: length of the buffer to be computed
- * @retval 32-bit CRC
- */
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
-{
- uint32_t index = 0;
-
- for(index = 0; index < BufferLength; index++)
- {
- CRC->DR = pBuffer[index];
- }
- return (CRC->DR);
-}
-
-/**
- * @brief Returns the current CRC value.
- * @param None
- * @retval 32-bit CRC
- */
-uint32_t CRC_GetCRC(void)
-{
- return (CRC->DR);
-}
-
-/**
- * @brief Stores a 8-bit data in the Independent Data(ID) register.
- * @param IDValue: 8-bit value to be stored in the ID register
- * @retval None
- */
-void CRC_SetIDRegister(uint8_t IDValue)
-{
- CRC->IDR = IDValue;
-}
-
-/**
- * @brief Returns the 8-bit data stored in the Independent Data(ID) register
- * @param None
- * @retval 8-bit value of the ID register
- */
-uint8_t CRC_GetIDRegister(void)
-{
- return (CRC->IDR);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_crc.h b/底盘/底盘-old/底盘/Library/stm32f4xx_crc.h
deleted file mode 100644
index 7f9c021..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_crc.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_crc.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the CRC firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_CRC_H
-#define __STM32F4xx_CRC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup CRC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CRC_Exported_Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-void CRC_ResetDR(void);
-uint32_t CRC_CalcCRC(uint32_t Data);
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
-uint32_t CRC_GetCRC(void);
-void CRC_SetIDRegister(uint8_t IDValue);
-uint8_t CRC_GetIDRegister(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_CRC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_cryp.c b/底盘/底盘-old/底盘/Library/stm32f4xx_cryp.c
deleted file mode 100644
index c3a7f33..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_cryp.c
+++ /dev/null
@@ -1,926 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_cryp.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Cryptographic processor (CRYP) peripheral:
- * + Initialization and Configuration functions
- * + Data treatment functions
- * + Context swapping functions
- * + DMA interface function
- * + Interrupts and flags management
- *
-@verbatim
- ===================================================================
- ##### How to use this driver #####
- ===================================================================
- [..]
- (#) Enable the CRYP controller clock using
- RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
-
- (#) Initialize the CRYP using CRYP_Init(), CRYP_KeyInit() and if needed
- CRYP_IVInit().
-
- (#) Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function.
-
- (#) Enable the CRYP controller using the CRYP_Cmd() function.
-
- (#) If using DMA for Data input and output transfer, activate the needed DMA
- Requests using CRYP_DMACmd() function
-
- (#) If DMA is not used for data transfer, use CRYP_DataIn() and CRYP_DataOut()
- functions to enter data to IN FIFO and get result from OUT FIFO.
-
- (#) To control CRYP events you can use one of the following two methods:
- (++) Check on CRYP flags using the CRYP_GetFlagStatus() function.
- (++) Use CRYP interrupts through the function CRYP_ITConfig() at
- initialization phase and CRYP_GetITStatus() function into interrupt
- routines in processing phase.
-
- (#) Save and restore Cryptographic processor context using CRYP_SaveContext()
- and CRYP_RestoreContext() functions.
-
-
- *** Procedure to perform an encryption or a decryption ***
- ==========================================================
-
- *** Initialization ***
- ======================
- [..]
- (#) Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and CRYP_IVInit
- functions:
- (++) Configure the key size (128-, 192- or 256-bit, in the AES only)
- (++) Enter the symmetric key
- (++) Configure the data type
- (++) In case of decryption in AES-ECB or AES-CBC, you must prepare
- the key: configure the key preparation mode. Then Enable the CRYP
- peripheral using CRYP_Cmd() function: the BUSY flag is set.
- Wait until BUSY flag is reset : the key is prepared for decryption
- (++) Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the
- AES in ECB/CBC/CTR)
- (++) Configure the direction (encryption/decryption).
- (++) Write the initialization vectors (in CBC or CTR modes only)
-
- (#) Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function
-
-
- *** Basic Processing mode (polling mode) ***
- ============================================
- [..]
- (#) Enable the cryptographic processor using CRYP_Cmd() function.
-
- (#) Write the first blocks in the input FIFO (2 to 8 words) using
- CRYP_DataIn() function.
-
- (#) Repeat the following sequence until the complete message has been
- processed:
-
- (++) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus()
- function), then read the OUT-FIFO using CRYP_DataOut() function
- (1 block or until the FIFO is empty)
-
- (++) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus()
- function then write the IN FIFO using CRYP_DataIn() function
- (1 block or until the FIFO is full)
-
- (#) At the end of the processing, CRYP_FLAG_BUSY flag will be reset and
- both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is
- reset). You can disable the peripheral using CRYP_Cmd() function.
-
- *** Interrupts Processing mode ***
- ==================================
- [..] In this mode, Processing is done when the data are transferred by the
- CPU during interrupts.
-
- (#) Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using CRYP_ITConfig()
- function.
-
- (#) Enable the cryptographic processor using CRYP_Cmd() function.
-
- (#) In the CRYP_IT_INI interrupt handler : load the input message into the
- IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a
- time, or load data until the IN FIFO is full. When the last word of
- the message has been entered into the IN FIFO, disable the CRYP_IT_INI
- interrupt (using CRYP_ITConfig() function).
-
- (#) In the CRYP_IT_OUTI interrupt handler : read the output message from
- the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or
- 4 words) at a time or read data until the FIFO is empty.
- When the last word has been read, INIM=0, BUSY=0 and both FIFOs are
- empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset).
- You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig()
- function) and you can disable the peripheral using CRYP_Cmd() function.
-
- *** DMA Processing mode ***
- ===========================
- [..] In this mode, Processing is done when the DMA is used to transfer the
- data from/to the memory.
-
- (#) Configure the DMA controller to transfer the input data from the
- memory using DMA_Init() function.
- The transfer length is the length of the message.
- As message padding is not managed by the peripheral, the message
- length must be an entire number of blocks. The data are transferred
- in burst mode. The burst length is 4 words in the AES and 2 or 4
- words in the DES/TDES. The DMA should be configured to set an
- interrupt on transfer completion of the output data to indicate that
- the processing is finished.
- Refer to DMA peripheral driver for more details.
-
- (#) Enable the cryptographic processor using CRYP_Cmd() function.
- Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT
- using CRYP_DMACmd() function.
-
- (#) All the transfers and processing are managed by the DMA and the
- cryptographic processor. The DMA transfer complete interrupt indicates
- that the processing is complete. Both FIFOs are normally empty and
- CRYP_FLAG_BUSY flag is reset.
-
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_cryp.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CRYP
- * @brief CRYP driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define FLAG_MASK ((uint8_t)0x20)
-#define MAX_TIMEOUT ((uint16_t)0xFFFF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRYP_Private_Functions
- * @{
- */
-
-/** @defgroup CRYP_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to
- (+) Initialize the cryptographic Processor using CRYP_Init() function
- (++) Encrypt or Decrypt
- (++) mode : TDES-ECB, TDES-CBC,
- DES-ECB, DES-CBC,
- AES-ECB, AES-CBC, AES-CTR, AES-Key, AES-GCM, AES-CCM
- (++) DataType : 32-bit data, 16-bit data, bit data or bit-string
- (++) Key Size (only in AES modes)
- (+) Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function
- (+) Configure the Initialization Vectors(IV) for CBC and CTR modes using
- CRYP_IVInit() function.
- (+) Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function.
- (+) Enable or disable the CRYP Processor using CRYP_Cmd() function
-
-@endverbatim
- * @{
- */
-/**
- * @brief Deinitializes the CRYP peripheral registers to their default reset values
- * @param None
- * @retval None
- */
-void CRYP_DeInit(void)
-{
- /* Enable CRYP reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, ENABLE);
-
- /* Release CRYP from reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, DISABLE);
-}
-
-/**
- * @brief Initializes the CRYP peripheral according to the specified parameters
- * in the CRYP_InitStruct.
- * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure that contains
- * the configuration information for the CRYP peripheral.
- * @retval None
- */
-void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct)
-{
- /* Check the parameters */
- assert_param(IS_CRYP_ALGOMODE(CRYP_InitStruct->CRYP_AlgoMode));
- assert_param(IS_CRYP_DATATYPE(CRYP_InitStruct->CRYP_DataType));
- assert_param(IS_CRYP_ALGODIR(CRYP_InitStruct->CRYP_AlgoDir));
-
- /* Select Algorithm mode*/
- CRYP->CR &= ~CRYP_CR_ALGOMODE;
- CRYP->CR |= CRYP_InitStruct->CRYP_AlgoMode;
-
- /* Select dataType */
- CRYP->CR &= ~CRYP_CR_DATATYPE;
- CRYP->CR |= CRYP_InitStruct->CRYP_DataType;
-
- /* select Key size (used only with AES algorithm) */
- if ((CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_TDES_ECB) &&
- (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_TDES_CBC) &&
- (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_DES_ECB) &&
- (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_DES_CBC))
- {
- assert_param(IS_CRYP_KEYSIZE(CRYP_InitStruct->CRYP_KeySize));
- CRYP->CR &= ~CRYP_CR_KEYSIZE;
- CRYP->CR |= CRYP_InitStruct->CRYP_KeySize; /* Key size and value must be
- configured once the key has
- been prepared */
- }
-
- /* Select data Direction */
- CRYP->CR &= ~CRYP_CR_ALGODIR;
- CRYP->CR |= CRYP_InitStruct->CRYP_AlgoDir;
-}
-
-/**
- * @brief Fills each CRYP_InitStruct member with its default value.
- * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct)
-{
- /* Initialize the CRYP_AlgoDir member */
- CRYP_InitStruct->CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
-
- /* initialize the CRYP_AlgoMode member */
- CRYP_InitStruct->CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB;
-
- /* initialize the CRYP_DataType member */
- CRYP_InitStruct->CRYP_DataType = CRYP_DataType_32b;
-
- /* Initialize the CRYP_KeySize member */
- CRYP_InitStruct->CRYP_KeySize = CRYP_KeySize_128b;
-}
-
-/**
- * @brief Initializes the CRYP Keys according to the specified parameters in
- * the CRYP_KeyInitStruct.
- * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that
- * contains the configuration information for the CRYP Keys.
- * @retval None
- */
-void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
-{
- /* Key Initialisation */
- CRYP->K0LR = CRYP_KeyInitStruct->CRYP_Key0Left;
- CRYP->K0RR = CRYP_KeyInitStruct->CRYP_Key0Right;
- CRYP->K1LR = CRYP_KeyInitStruct->CRYP_Key1Left;
- CRYP->K1RR = CRYP_KeyInitStruct->CRYP_Key1Right;
- CRYP->K2LR = CRYP_KeyInitStruct->CRYP_Key2Left;
- CRYP->K2RR = CRYP_KeyInitStruct->CRYP_Key2Right;
- CRYP->K3LR = CRYP_KeyInitStruct->CRYP_Key3Left;
- CRYP->K3RR = CRYP_KeyInitStruct->CRYP_Key3Right;
-}
-
-/**
- * @brief Fills each CRYP_KeyInitStruct member with its default value.
- * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
-{
- CRYP_KeyInitStruct->CRYP_Key0Left = 0;
- CRYP_KeyInitStruct->CRYP_Key0Right = 0;
- CRYP_KeyInitStruct->CRYP_Key1Left = 0;
- CRYP_KeyInitStruct->CRYP_Key1Right = 0;
- CRYP_KeyInitStruct->CRYP_Key2Left = 0;
- CRYP_KeyInitStruct->CRYP_Key2Right = 0;
- CRYP_KeyInitStruct->CRYP_Key3Left = 0;
- CRYP_KeyInitStruct->CRYP_Key3Right = 0;
-}
-/**
- * @brief Initializes the CRYP Initialization Vectors(IV) according to the
- * specified parameters in the CRYP_IVInitStruct.
- * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef structure that contains
- * the configuration information for the CRYP Initialization Vectors(IV).
- * @retval None
- */
-void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct)
-{
- CRYP->IV0LR = CRYP_IVInitStruct->CRYP_IV0Left;
- CRYP->IV0RR = CRYP_IVInitStruct->CRYP_IV0Right;
- CRYP->IV1LR = CRYP_IVInitStruct->CRYP_IV1Left;
- CRYP->IV1RR = CRYP_IVInitStruct->CRYP_IV1Right;
-}
-
-/**
- * @brief Fills each CRYP_IVInitStruct member with its default value.
- * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef Initialization
- * Vectors(IV) structure which will be initialized.
- * @retval None
- */
-void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct)
-{
- CRYP_IVInitStruct->CRYP_IV0Left = 0;
- CRYP_IVInitStruct->CRYP_IV0Right = 0;
- CRYP_IVInitStruct->CRYP_IV1Left = 0;
- CRYP_IVInitStruct->CRYP_IV1Right = 0;
-}
-
-/**
- * @brief Configures the AES-CCM and AES-GCM phases
- * @note This function is used only with AES-CCM or AES-GCM Algorithms
- * @param CRYP_Phase: specifies the CRYP AES-CCM and AES-GCM phase to be configured.
- * This parameter can be one of the following values:
- * @arg CRYP_Phase_Init: Initialization phase
- * @arg CRYP_Phase_Header: Header phase
- * @arg CRYP_Phase_Payload: Payload phase
- * @arg CRYP_Phase_Final: Final phase
- * @retval None
- */
-void CRYP_PhaseConfig(uint32_t CRYP_Phase)
-{ uint32_t tempcr = 0;
-
- /* Check the parameter */
- assert_param(IS_CRYP_PHASE(CRYP_Phase));
-
- /* Get the CR register */
- tempcr = CRYP->CR;
-
- /* Reset the phase configuration bits: GCMP_CCMPH */
- tempcr &= (uint32_t)(~CRYP_CR_GCM_CCMPH);
- /* Set the selected phase */
- tempcr |= (uint32_t)CRYP_Phase;
-
- /* Set the CR register */
- CRYP->CR = tempcr;
-}
-
-/**
- * @brief Flushes the IN and OUT FIFOs (that is read and write pointers of the
- * FIFOs are reset)
- * @note The FIFOs must be flushed only when BUSY flag is reset.
- * @param None
- * @retval None
- */
-void CRYP_FIFOFlush(void)
-{
- /* Reset the read and write pointers of the FIFOs */
- CRYP->CR |= CRYP_CR_FFLUSH;
-}
-
-/**
- * @brief Enables or disables the CRYP peripheral.
- * @param NewState: new state of the CRYP peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CRYP_Cmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Cryptographic processor */
- CRYP->CR |= CRYP_CR_CRYPEN;
- }
- else
- {
- /* Disable the Cryptographic processor */
- CRYP->CR &= ~CRYP_CR_CRYPEN;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup CRYP_Group2 CRYP Data processing functions
- * @brief CRYP Data processing functions
- *
-@verbatim
- ===============================================================================
- ##### CRYP Data processing functions #####
- ===============================================================================
- [..] This section provides functions allowing the encryption and decryption
- operations:
- (+) Enter data to be treated in the IN FIFO : using CRYP_DataIn() function.
- (+) Get the data result from the OUT FIFO : using CRYP_DataOut() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Writes data in the Data Input register (DIN).
- * @note After the DIN register has been read once or several times,
- * the FIFO must be flushed (using CRYP_FIFOFlush() function).
- * @param Data: data to write in Data Input register
- * @retval None
- */
-void CRYP_DataIn(uint32_t Data)
-{
- CRYP->DR = Data;
-}
-
-/**
- * @brief Returns the last data entered into the output FIFO.
- * @param None
- * @retval Last data entered into the output FIFO.
- */
-uint32_t CRYP_DataOut(void)
-{
- return CRYP->DOUT;
-}
-/**
- * @}
- */
-
-/** @defgroup CRYP_Group3 Context swapping functions
- * @brief Context swapping functions
- *
-@verbatim
- ===============================================================================
- ##### Context swapping functions #####
- ===============================================================================
- [..] This section provides functions allowing to save and store CRYP Context
-
- [..] It is possible to interrupt an encryption/ decryption/ key generation process
- to perform another processing with a higher priority, and to complete the
- interrupted process later on, when the higher-priority task is complete. To do
- so, the context of the interrupted task must be saved from the CRYP registers
- to memory, and then be restored from memory to the CRYP registers.
-
- (#) To save the current context, use CRYP_SaveContext() function
- (#) To restore the saved context, use CRYP_RestoreContext() function
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Saves the CRYP peripheral Context.
- * @note This function stops DMA transfer before to save the context. After
- * restoring the context, you have to enable the DMA again (if the DMA
- * was previously used).
- * @param CRYP_ContextSave: pointer to a CRYP_Context structure that contains
- * the repository for current context.
- * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that
- * contains the configuration information for the CRYP Keys.
- * @retval None
- */
-ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,
- CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
-{
- __IO uint32_t timeout = 0;
- uint32_t ckeckmask = 0, bitstatus;
- ErrorStatus status = ERROR;
-
- /* Stop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR */
- CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DIEN;
-
- /* Wait until both the IN and OUT FIFOs are empty
- (IFEM=1 and OFNE=0 in the CRYP_SR register) and the
- BUSY bit is cleared. */
-
- if ((CRYP->CR & (uint32_t)(CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE_TDES_CBC)) != (uint32_t)0 )/* TDES */
- {
- ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY ;
- }
- else /* AES or DES */
- {
- ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY | CRYP_SR_OFNE;
- }
-
- do
- {
- bitstatus = CRYP->SR & ckeckmask;
- timeout++;
- }
- while ((timeout != MAX_TIMEOUT) && (bitstatus != CRYP_SR_IFEM));
-
- if ((CRYP->SR & ckeckmask) != CRYP_SR_IFEM)
- {
- status = ERROR;
- }
- else
- {
- /* Stop DMA transfers on the OUT FIFO by
- - writing the DOEN bit to 0 in the CRYP_DMACR register
- - and clear the CRYPEN bit. */
-
- CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DOEN;
- CRYP->CR &= ~(uint32_t)CRYP_CR_CRYPEN;
-
- /* Save the current configuration (bit 19, bit[17:16] and bits [9:2] in the CRYP_CR register) */
- CRYP_ContextSave->CR_CurrentConfig = CRYP->CR & (CRYP_CR_GCM_CCMPH |
- CRYP_CR_KEYSIZE |
- CRYP_CR_DATATYPE |
- CRYP_CR_ALGOMODE |
- CRYP_CR_ALGODIR);
-
- /* and, if not in ECB mode, the initialization vectors. */
- CRYP_ContextSave->CRYP_IV0LR = CRYP->IV0LR;
- CRYP_ContextSave->CRYP_IV0RR = CRYP->IV0RR;
- CRYP_ContextSave->CRYP_IV1LR = CRYP->IV1LR;
- CRYP_ContextSave->CRYP_IV1RR = CRYP->IV1RR;
-
- /* save The key value */
- CRYP_ContextSave->CRYP_K0LR = CRYP_KeyInitStruct->CRYP_Key0Left;
- CRYP_ContextSave->CRYP_K0RR = CRYP_KeyInitStruct->CRYP_Key0Right;
- CRYP_ContextSave->CRYP_K1LR = CRYP_KeyInitStruct->CRYP_Key1Left;
- CRYP_ContextSave->CRYP_K1RR = CRYP_KeyInitStruct->CRYP_Key1Right;
- CRYP_ContextSave->CRYP_K2LR = CRYP_KeyInitStruct->CRYP_Key2Left;
- CRYP_ContextSave->CRYP_K2RR = CRYP_KeyInitStruct->CRYP_Key2Right;
- CRYP_ContextSave->CRYP_K3LR = CRYP_KeyInitStruct->CRYP_Key3Left;
- CRYP_ContextSave->CRYP_K3RR = CRYP_KeyInitStruct->CRYP_Key3Right;
-
- /* Save the content of context swap registers */
- CRYP_ContextSave->CRYP_CSGCMCCMR[0] = CRYP->CSGCMCCM0R;
- CRYP_ContextSave->CRYP_CSGCMCCMR[1] = CRYP->CSGCMCCM1R;
- CRYP_ContextSave->CRYP_CSGCMCCMR[2] = CRYP->CSGCMCCM2R;
- CRYP_ContextSave->CRYP_CSGCMCCMR[3] = CRYP->CSGCMCCM3R;
- CRYP_ContextSave->CRYP_CSGCMCCMR[4] = CRYP->CSGCMCCM4R;
- CRYP_ContextSave->CRYP_CSGCMCCMR[5] = CRYP->CSGCMCCM5R;
- CRYP_ContextSave->CRYP_CSGCMCCMR[6] = CRYP->CSGCMCCM6R;
- CRYP_ContextSave->CRYP_CSGCMCCMR[7] = CRYP->CSGCMCCM7R;
-
- CRYP_ContextSave->CRYP_CSGCMR[0] = CRYP->CSGCM0R;
- CRYP_ContextSave->CRYP_CSGCMR[1] = CRYP->CSGCM1R;
- CRYP_ContextSave->CRYP_CSGCMR[2] = CRYP->CSGCM2R;
- CRYP_ContextSave->CRYP_CSGCMR[3] = CRYP->CSGCM3R;
- CRYP_ContextSave->CRYP_CSGCMR[4] = CRYP->CSGCM4R;
- CRYP_ContextSave->CRYP_CSGCMR[5] = CRYP->CSGCM5R;
- CRYP_ContextSave->CRYP_CSGCMR[6] = CRYP->CSGCM6R;
- CRYP_ContextSave->CRYP_CSGCMR[7] = CRYP->CSGCM7R;
-
- /* When needed, save the DMA status (pointers for IN and OUT messages,
- number of remaining bytes, etc.) */
-
- status = SUCCESS;
- }
-
- return status;
-}
-
-/**
- * @brief Restores the CRYP peripheral Context.
- * @note Since the DMA transfer is stopped in CRYP_SaveContext() function,
- * after restoring the context, you have to enable the DMA again (if the
- * DMA was previously used).
- * @param CRYP_ContextRestore: pointer to a CRYP_Context structure that contains
- * the repository for saved context.
- * @note The data that were saved during context saving must be rewritten into
- * the IN FIFO.
- * @retval None
- */
-void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore)
-{
-
- /* Configure the processor with the saved configuration */
- CRYP->CR = CRYP_ContextRestore->CR_CurrentConfig;
-
- /* restore The key value */
- CRYP->K0LR = CRYP_ContextRestore->CRYP_K0LR;
- CRYP->K0RR = CRYP_ContextRestore->CRYP_K0RR;
- CRYP->K1LR = CRYP_ContextRestore->CRYP_K1LR;
- CRYP->K1RR = CRYP_ContextRestore->CRYP_K1RR;
- CRYP->K2LR = CRYP_ContextRestore->CRYP_K2LR;
- CRYP->K2RR = CRYP_ContextRestore->CRYP_K2RR;
- CRYP->K3LR = CRYP_ContextRestore->CRYP_K3LR;
- CRYP->K3RR = CRYP_ContextRestore->CRYP_K3RR;
-
- /* and the initialization vectors. */
- CRYP->IV0LR = CRYP_ContextRestore->CRYP_IV0LR;
- CRYP->IV0RR = CRYP_ContextRestore->CRYP_IV0RR;
- CRYP->IV1LR = CRYP_ContextRestore->CRYP_IV1LR;
- CRYP->IV1RR = CRYP_ContextRestore->CRYP_IV1RR;
-
- /* Restore the content of context swap registers */
- CRYP->CSGCMCCM0R = CRYP_ContextRestore->CRYP_CSGCMCCMR[0];
- CRYP->CSGCMCCM1R = CRYP_ContextRestore->CRYP_CSGCMCCMR[1];
- CRYP->CSGCMCCM2R = CRYP_ContextRestore->CRYP_CSGCMCCMR[2];
- CRYP->CSGCMCCM3R = CRYP_ContextRestore->CRYP_CSGCMCCMR[3];
- CRYP->CSGCMCCM4R = CRYP_ContextRestore->CRYP_CSGCMCCMR[4];
- CRYP->CSGCMCCM5R = CRYP_ContextRestore->CRYP_CSGCMCCMR[5];
- CRYP->CSGCMCCM6R = CRYP_ContextRestore->CRYP_CSGCMCCMR[6];
- CRYP->CSGCMCCM7R = CRYP_ContextRestore->CRYP_CSGCMCCMR[7];
-
- CRYP->CSGCM0R = CRYP_ContextRestore->CRYP_CSGCMR[0];
- CRYP->CSGCM1R = CRYP_ContextRestore->CRYP_CSGCMR[1];
- CRYP->CSGCM2R = CRYP_ContextRestore->CRYP_CSGCMR[2];
- CRYP->CSGCM3R = CRYP_ContextRestore->CRYP_CSGCMR[3];
- CRYP->CSGCM4R = CRYP_ContextRestore->CRYP_CSGCMR[4];
- CRYP->CSGCM5R = CRYP_ContextRestore->CRYP_CSGCMR[5];
- CRYP->CSGCM6R = CRYP_ContextRestore->CRYP_CSGCMR[6];
- CRYP->CSGCM7R = CRYP_ContextRestore->CRYP_CSGCMR[7];
-
- /* Enable the cryptographic processor */
- CRYP->CR |= CRYP_CR_CRYPEN;
-}
-/**
- * @}
- */
-
-/** @defgroup CRYP_Group4 CRYP's DMA interface Configuration function
- * @brief CRYP's DMA interface Configuration function
- *
-@verbatim
- ===============================================================================
- ##### CRYP's DMA interface Configuration function #####
- ===============================================================================
- [..] This section provides functions allowing to configure the DMA interface for
- CRYP data input and output transfer.
-
- [..] When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be
- transferred:
- (+) From memory to the CRYP IN FIFO using the DMA peripheral by enabling
- the CRYP_DMAReq_DataIN request.
- (+) From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling
- the CRYP_DMAReq_DataOUT request.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the CRYP DMA interface.
- * @param CRYP_DMAReq: specifies the CRYP DMA transfer request to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg CRYP_DMAReq_DataOUT: DMA for outgoing(Tx) data transfer
- * @arg CRYP_DMAReq_DataIN: DMA for incoming(Rx) data transfer
- * @param NewState: new state of the selected CRYP DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CRYP_DMAREQ(CRYP_DMAReq));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected CRYP DMA request */
- CRYP->DMACR |= CRYP_DMAReq;
- }
- else
- {
- /* Disable the selected CRYP DMA request */
- CRYP->DMACR &= (uint8_t)~CRYP_DMAReq;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup CRYP_Group5 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure the CRYP Interrupts and
- to get the status and Interrupts pending bits.
-
- [..] The CRYP provides 2 Interrupts sources and 7 Flags:
-
- *** Flags : ***
- ===============
- [..]
- (#) CRYP_FLAG_IFEM : Set when Input FIFO is empty. This Flag is cleared only
- by hardware.
-
- (#) CRYP_FLAG_IFNF : Set when Input FIFO is not full. This Flag is cleared
- only by hardware.
-
-
- (#) CRYP_FLAG_INRIS : Set when Input FIFO Raw interrupt is pending it gives
- the raw interrupt state prior to masking of the input FIFO service interrupt.
- This Flag is cleared only by hardware.
-
- (#) CRYP_FLAG_OFNE : Set when Output FIFO not empty. This Flag is cleared
- only by hardware.
-
- (#) CRYP_FLAG_OFFU : Set when Output FIFO is full. This Flag is cleared only
- by hardware.
-
- (#) CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending it gives
- the raw interrupt state prior to masking of the output FIFO service interrupt.
- This Flag is cleared only by hardware.
-
- (#) CRYP_FLAG_BUSY : Set when the CRYP core is currently processing a block
- of data or a key preparation (for AES decryption). This Flag is cleared
- only by hardware. To clear it, the CRYP core must be disabled and the last
- processing has completed.
-
- *** Interrupts : ***
- ====================
- [..]
- (#) CRYP_IT_INI : The input FIFO service interrupt is asserted when there
- are less than 4 words in the input FIFO. This interrupt is associated to
- CRYP_FLAG_INRIS flag.
-
- -@- This interrupt is cleared by performing write operations to the input FIFO
- until it holds 4 or more words. The input FIFO service interrupt INMIS is
- enabled with the CRYP enable bit. Consequently, when CRYP is disabled, the
- INMIS signal is low even if the input FIFO is empty.
-
-
-
- (#) CRYP_IT_OUTI : The output FIFO service interrupt is asserted when there
- is one or more (32-bit word) data items in the output FIFO. This interrupt
- is associated to CRYP_FLAG_OUTRIS flag.
-
- -@- This interrupt is cleared by reading data from the output FIFO until there
- is no valid (32-bit) word left (that is, the interrupt follows the state
- of the OFNE (output FIFO not empty) flag).
-
- *** Managing the CRYP controller events : ***
- =============================================
- [..] The user should identify which mode will be used in his application to manage
- the CRYP controller events: Polling mode or Interrupt mode.
-
- (#) In the Polling Mode it is advised to use the following functions:
- (++) CRYP_GetFlagStatus() : to check if flags events occur.
-
- -@@- The CRYPT flags do not need to be cleared since they are cleared as
- soon as the associated event are reset.
-
-
- (#) In the Interrupt Mode it is advised to use the following functions:
- (++) CRYP_ITConfig() : to enable or disable the interrupt source.
- (++) CRYP_GetITStatus() : to check if Interrupt occurs.
-
- -@@- The CRYPT interrupts have no pending bits, the interrupt is cleared as
- soon as the associated event is reset.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified CRYP interrupts.
- * @param CRYP_IT: specifies the CRYP interrupt source to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg CRYP_IT_INI: Input FIFO interrupt
- * @arg CRYP_IT_OUTI: Output FIFO interrupt
- * @param NewState: new state of the specified CRYP interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CRYP_CONFIG_IT(CRYP_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected CRYP interrupt */
- CRYP->IMSCR |= CRYP_IT;
- }
- else
- {
- /* Disable the selected CRYP interrupt */
- CRYP->IMSCR &= (uint8_t)~CRYP_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified CRYP interrupt has occurred or not.
- * @note This function checks the status of the masked interrupt (i.e the
- * interrupt should be previously enabled).
- * @param CRYP_IT: specifies the CRYP (masked) interrupt source to check.
- * This parameter can be one of the following values:
- * @arg CRYP_IT_INI: Input FIFO interrupt
- * @arg CRYP_IT_OUTI: Output FIFO interrupt
- * @retval The new state of CRYP_IT (SET or RESET).
- */
-ITStatus CRYP_GetITStatus(uint8_t CRYP_IT)
-{
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_CRYP_GET_IT(CRYP_IT));
-
- /* Check the status of the specified CRYP interrupt */
- if ((CRYP->MISR & CRYP_IT) != (uint8_t)RESET)
- {
- /* CRYP_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* CRYP_IT is reset */
- bitstatus = RESET;
- }
- /* Return the CRYP_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Returns whether CRYP peripheral is enabled or disabled.
- * @param none.
- * @retval Current state of the CRYP peripheral (ENABLE or DISABLE).
- */
-FunctionalState CRYP_GetCmdStatus(void)
-{
- FunctionalState state = DISABLE;
-
- if ((CRYP->CR & CRYP_CR_CRYPEN) != 0)
- {
- /* CRYPEN bit is set */
- state = ENABLE;
- }
- else
- {
- /* CRYPEN bit is reset */
- state = DISABLE;
- }
- return state;
-}
-
-/**
- * @brief Checks whether the specified CRYP flag is set or not.
- * @param CRYP_FLAG: specifies the CRYP flag to check.
- * This parameter can be one of the following values:
- * @arg CRYP_FLAG_IFEM: Input FIFO Empty flag.
- * @arg CRYP_FLAG_IFNF: Input FIFO Not Full flag.
- * @arg CRYP_FLAG_OFNE: Output FIFO Not Empty flag.
- * @arg CRYP_FLAG_OFFU: Output FIFO Full flag.
- * @arg CRYP_FLAG_BUSY: Busy flag.
- * @arg CRYP_FLAG_OUTRIS: Output FIFO raw interrupt flag.
- * @arg CRYP_FLAG_INRIS: Input FIFO raw interrupt flag.
- * @retval The new state of CRYP_FLAG (SET or RESET).
- */
-FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t tempreg = 0;
-
- /* Check the parameters */
- assert_param(IS_CRYP_GET_FLAG(CRYP_FLAG));
-
- /* check if the FLAG is in RISR register */
- if ((CRYP_FLAG & FLAG_MASK) != 0x00)
- {
- tempreg = CRYP->RISR;
- }
- else /* The FLAG is in SR register */
- {
- tempreg = CRYP->SR;
- }
-
-
- /* Check the status of the specified CRYP flag */
- if ((tempreg & CRYP_FLAG ) != (uint8_t)RESET)
- {
- /* CRYP_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CRYP_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the CRYP_FLAG status */
- return bitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_cryp.h b/底盘/底盘-old/底盘/Library/stm32f4xx_cryp.h
deleted file mode 100644
index f9fbfb4..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_cryp.h
+++ /dev/null
@@ -1,376 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_cryp.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the Cryptographic
- * processor(CRYP) firmware library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_CRYP_H
-#define __STM32F4xx_CRYP_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup CRYP
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief CRYP Init structure definition
- */
-typedef struct
-{
- uint32_t CRYP_AlgoDir; /*!< Encrypt or Decrypt. This parameter can be a
- value of @ref CRYP_Algorithm_Direction */
- uint32_t CRYP_AlgoMode; /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB,
- AES-CBC, AES-CTR, AES-Key, AES-GCM and AES-CCM.
- This parameter can be a value of @ref CRYP_Algorithm_Mode */
- uint32_t CRYP_DataType; /*!< 32-bit data, 16-bit data, bit data or bit string.
- This parameter can be a value of @ref CRYP_Data_Type */
- uint32_t CRYP_KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit
- key length. This parameter can be a value of
- @ref CRYP_Key_Size_for_AES_only */
-}CRYP_InitTypeDef;
-
-/**
- * @brief CRYP Key(s) structure definition
- */
-typedef struct
-{
- uint32_t CRYP_Key0Left; /*!< Key 0 Left */
- uint32_t CRYP_Key0Right; /*!< Key 0 Right */
- uint32_t CRYP_Key1Left; /*!< Key 1 left */
- uint32_t CRYP_Key1Right; /*!< Key 1 Right */
- uint32_t CRYP_Key2Left; /*!< Key 2 left */
- uint32_t CRYP_Key2Right; /*!< Key 2 Right */
- uint32_t CRYP_Key3Left; /*!< Key 3 left */
- uint32_t CRYP_Key3Right; /*!< Key 3 Right */
-}CRYP_KeyInitTypeDef;
-/**
- * @brief CRYP Initialization Vectors (IV) structure definition
- */
-typedef struct
-{
- uint32_t CRYP_IV0Left; /*!< Init Vector 0 Left */
- uint32_t CRYP_IV0Right; /*!< Init Vector 0 Right */
- uint32_t CRYP_IV1Left; /*!< Init Vector 1 left */
- uint32_t CRYP_IV1Right; /*!< Init Vector 1 Right */
-}CRYP_IVInitTypeDef;
-
-/**
- * @brief CRYP context swapping structure definition
- */
-typedef struct
-{
- /*!< Current Configuration */
- uint32_t CR_CurrentConfig;
- /*!< IV */
- uint32_t CRYP_IV0LR;
- uint32_t CRYP_IV0RR;
- uint32_t CRYP_IV1LR;
- uint32_t CRYP_IV1RR;
- /*!< KEY */
- uint32_t CRYP_K0LR;
- uint32_t CRYP_K0RR;
- uint32_t CRYP_K1LR;
- uint32_t CRYP_K1RR;
- uint32_t CRYP_K2LR;
- uint32_t CRYP_K2RR;
- uint32_t CRYP_K3LR;
- uint32_t CRYP_K3RR;
- uint32_t CRYP_CSGCMCCMR[8];
- uint32_t CRYP_CSGCMR[8];
-}CRYP_Context;
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CRYP_Exported_Constants
- * @{
- */
-
-/** @defgroup CRYP_Algorithm_Direction
- * @{
- */
-#define CRYP_AlgoDir_Encrypt ((uint16_t)0x0000)
-#define CRYP_AlgoDir_Decrypt ((uint16_t)0x0004)
-#define IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) || \
- ((ALGODIR) == CRYP_AlgoDir_Decrypt))
-
-/**
- * @}
- */
-
-/** @defgroup CRYP_Algorithm_Mode
- * @{
- */
-
-/*!< TDES Modes */
-#define CRYP_AlgoMode_TDES_ECB ((uint32_t)0x00000000)
-#define CRYP_AlgoMode_TDES_CBC ((uint32_t)0x00000008)
-
-/*!< DES Modes */
-#define CRYP_AlgoMode_DES_ECB ((uint32_t)0x00000010)
-#define CRYP_AlgoMode_DES_CBC ((uint32_t)0x00000018)
-
-/*!< AES Modes */
-#define CRYP_AlgoMode_AES_ECB ((uint32_t)0x00000020)
-#define CRYP_AlgoMode_AES_CBC ((uint32_t)0x00000028)
-#define CRYP_AlgoMode_AES_CTR ((uint32_t)0x00000030)
-#define CRYP_AlgoMode_AES_Key ((uint32_t)0x00000038)
-#define CRYP_AlgoMode_AES_GCM ((uint32_t)0x00080000)
-#define CRYP_AlgoMode_AES_CCM ((uint32_t)0x00080008)
-
-#define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \
- ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \
- ((ALGOMODE) == CRYP_AlgoMode_DES_ECB) || \
- ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \
- ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \
- ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \
- ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \
- ((ALGOMODE) == CRYP_AlgoMode_AES_Key) || \
- ((ALGOMODE) == CRYP_AlgoMode_AES_GCM) || \
- ((ALGOMODE) == CRYP_AlgoMode_AES_CCM))
-/**
- * @}
- */
-
-/** @defgroup CRYP_Phase
- * @{
- */
-
-/*!< The phases are valid only for AES-GCM and AES-CCM modes */
-#define CRYP_Phase_Init ((uint32_t)0x00000000)
-#define CRYP_Phase_Header CRYP_CR_GCM_CCMPH_0
-#define CRYP_Phase_Payload CRYP_CR_GCM_CCMPH_1
-#define CRYP_Phase_Final CRYP_CR_GCM_CCMPH
-
-#define IS_CRYP_PHASE(PHASE) (((PHASE) == CRYP_Phase_Init) || \
- ((PHASE) == CRYP_Phase_Header) || \
- ((PHASE) == CRYP_Phase_Payload) || \
- ((PHASE) == CRYP_Phase_Final))
-
-/**
- * @}
- */
-
-/** @defgroup CRYP_Data_Type
- * @{
- */
-#define CRYP_DataType_32b ((uint16_t)0x0000)
-#define CRYP_DataType_16b ((uint16_t)0x0040)
-#define CRYP_DataType_8b ((uint16_t)0x0080)
-#define CRYP_DataType_1b ((uint16_t)0x00C0)
-#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) || \
- ((DATATYPE) == CRYP_DataType_16b)|| \
- ((DATATYPE) == CRYP_DataType_8b)|| \
- ((DATATYPE) == CRYP_DataType_1b))
-/**
- * @}
- */
-
-/** @defgroup CRYP_Key_Size_for_AES_only
- * @{
- */
-#define CRYP_KeySize_128b ((uint16_t)0x0000)
-#define CRYP_KeySize_192b ((uint16_t)0x0100)
-#define CRYP_KeySize_256b ((uint16_t)0x0200)
-#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)|| \
- ((KEYSIZE) == CRYP_KeySize_192b)|| \
- ((KEYSIZE) == CRYP_KeySize_256b))
-/**
- * @}
- */
-
-/** @defgroup CRYP_flags_definition
- * @{
- */
-#define CRYP_FLAG_BUSY ((uint8_t)0x10) /*!< The CRYP core is currently
- processing a block of data
- or a key preparation (for
- AES decryption). */
-#define CRYP_FLAG_IFEM ((uint8_t)0x01) /*!< Input Fifo Empty */
-#define CRYP_FLAG_IFNF ((uint8_t)0x02) /*!< Input Fifo is Not Full */
-#define CRYP_FLAG_INRIS ((uint8_t)0x22) /*!< Raw interrupt pending */
-#define CRYP_FLAG_OFNE ((uint8_t)0x04) /*!< Input Fifo service raw
- interrupt status */
-#define CRYP_FLAG_OFFU ((uint8_t)0x08) /*!< Output Fifo is Full */
-#define CRYP_FLAG_OUTRIS ((uint8_t)0x21) /*!< Output Fifo service raw
- interrupt status */
-
-#define IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM) || \
- ((FLAG) == CRYP_FLAG_IFNF) || \
- ((FLAG) == CRYP_FLAG_OFNE) || \
- ((FLAG) == CRYP_FLAG_OFFU) || \
- ((FLAG) == CRYP_FLAG_BUSY) || \
- ((FLAG) == CRYP_FLAG_OUTRIS)|| \
- ((FLAG) == CRYP_FLAG_INRIS))
-/**
- * @}
- */
-
-/** @defgroup CRYP_interrupts_definition
- * @{
- */
-#define CRYP_IT_INI ((uint8_t)0x01) /*!< IN Fifo Interrupt */
-#define CRYP_IT_OUTI ((uint8_t)0x02) /*!< OUT Fifo Interrupt */
-#define IS_CRYP_CONFIG_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00))
-#define IS_CRYP_GET_IT(IT) (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI))
-
-/**
- * @}
- */
-
-/** @defgroup CRYP_Encryption_Decryption_modes_definition
- * @{
- */
-#define MODE_ENCRYPT ((uint8_t)0x01)
-#define MODE_DECRYPT ((uint8_t)0x00)
-
-/**
- * @}
- */
-
-/** @defgroup CRYP_DMA_transfer_requests
- * @{
- */
-#define CRYP_DMAReq_DataIN ((uint8_t)0x01)
-#define CRYP_DMAReq_DataOUT ((uint8_t)0x02)
-#define IS_CRYP_DMAREQ(DMAREQ) ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the CRYP configuration to the default reset state ****/
-void CRYP_DeInit(void);
-
-/* CRYP Initialization and Configuration functions ****************************/
-void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct);
-void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct);
-void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
-void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
-void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);
-void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);
-void CRYP_Cmd(FunctionalState NewState);
-void CRYP_PhaseConfig(uint32_t CRYP_Phase);
-void CRYP_FIFOFlush(void);
-/* CRYP Data processing functions *********************************************/
-void CRYP_DataIn(uint32_t Data);
-uint32_t CRYP_DataOut(void);
-
-/* CRYP Context swapping functions ********************************************/
-ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,
- CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
-void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore);
-
-/* CRYP DMA interface function ************************************************/
-void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState);
-ITStatus CRYP_GetITStatus(uint8_t CRYP_IT);
-FunctionalState CRYP_GetCmdStatus(void);
-FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG);
-
-/* High Level AES functions **************************************************/
-ErrorStatus CRYP_AES_ECB(uint8_t Mode,
- uint8_t *Key, uint16_t Keysize,
- uint8_t *Input, uint32_t Ilength,
- uint8_t *Output);
-
-ErrorStatus CRYP_AES_CBC(uint8_t Mode,
- uint8_t InitVectors[16],
- uint8_t *Key, uint16_t Keysize,
- uint8_t *Input, uint32_t Ilength,
- uint8_t *Output);
-
-ErrorStatus CRYP_AES_CTR(uint8_t Mode,
- uint8_t InitVectors[16],
- uint8_t *Key, uint16_t Keysize,
- uint8_t *Input, uint32_t Ilength,
- uint8_t *Output);
-
-ErrorStatus CRYP_AES_GCM(uint8_t Mode, uint8_t InitVectors[16],
- uint8_t *Key, uint16_t Keysize,
- uint8_t *Input, uint32_t ILength,
- uint8_t *Header, uint32_t HLength,
- uint8_t *Output, uint8_t *AuthTAG);
-
-ErrorStatus CRYP_AES_CCM(uint8_t Mode,
- uint8_t* Nonce, uint32_t NonceSize,
- uint8_t* Key, uint16_t Keysize,
- uint8_t* Input, uint32_t ILength,
- uint8_t* Header, uint32_t HLength, uint8_t *HBuffer,
- uint8_t* Output,
- uint8_t* AuthTAG, uint32_t TAGSize);
-
-/* High Level TDES functions **************************************************/
-ErrorStatus CRYP_TDES_ECB(uint8_t Mode,
- uint8_t Key[24],
- uint8_t *Input, uint32_t Ilength,
- uint8_t *Output);
-
-ErrorStatus CRYP_TDES_CBC(uint8_t Mode,
- uint8_t Key[24],
- uint8_t InitVectors[8],
- uint8_t *Input, uint32_t Ilength,
- uint8_t *Output);
-
-/* High Level DES functions **************************************************/
-ErrorStatus CRYP_DES_ECB(uint8_t Mode,
- uint8_t Key[8],
- uint8_t *Input, uint32_t Ilength,
- uint8_t *Output);
-
-ErrorStatus CRYP_DES_CBC(uint8_t Mode,
- uint8_t Key[8],
- uint8_t InitVectors[8],
- uint8_t *Input,uint32_t Ilength,
- uint8_t *Output);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_CRYP_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_cryp_aes.c b/底盘/底盘-old/底盘/Library/stm32f4xx_cryp_aes.c
deleted file mode 100644
index c83d584..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_cryp_aes.c
+++ /dev/null
@@ -1,1699 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_cryp_aes.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides high level functions to encrypt and decrypt an
- * input message using AES in ECB/CBC/CTR/GCM/CCM modes.
- * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
- * peripheral.
- * AES-ECB/CBC/CTR/GCM/CCM modes are available on STM32F437x Devices.
- * For STM32F41xx Devices, only AES-ECB/CBC/CTR modes are available.
- *
-@verbatim
- ===================================================================
- ##### How to use this driver #####
- ===================================================================
- [..]
- (#) Enable The CRYP controller clock using
- RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
-
- (#) Encrypt and decrypt using AES in ECB Mode using CRYP_AES_ECB() function.
-
- (#) Encrypt and decrypt using AES in CBC Mode using CRYP_AES_CBC() function.
-
- (#) Encrypt and decrypt using AES in CTR Mode using CRYP_AES_CTR() function.
-
- (#) Encrypt and decrypt using AES in GCM Mode using CRYP_AES_GCM() function.
-
- (#) Encrypt and decrypt using AES in CCM Mode using CRYP_AES_CCM() function.
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_cryp.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CRYP
- * @brief CRYP driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define AESBUSY_TIMEOUT ((uint32_t) 0x00010000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRYP_Private_Functions
- * @{
- */
-
-/** @defgroup CRYP_Group6 High Level AES functions
- * @brief High Level AES functions
- *
-@verbatim
- ===============================================================================
- ##### High Level AES functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Encrypt and decrypt using AES in ECB Mode
- * @param Mode: encryption or decryption Mode.
- * This parameter can be one of the following values:
- * @arg MODE_ENCRYPT: Encryption
- * @arg MODE_DECRYPT: Decryption
- * @param Key: Key used for AES algorithm.
- * @param Keysize: length of the Key, must be a 128, 192 or 256.
- * @param Input: pointer to the Input buffer.
- * @param Ilength: length of the Input buffer, must be a multiple of 16.
- * @param Output: pointer to the returned buffer.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Operation done
- * - ERROR: Operation failed
- */
-ErrorStatus CRYP_AES_ECB(uint8_t Mode, uint8_t* Key, uint16_t Keysize,
- uint8_t* Input, uint32_t Ilength, uint8_t* Output)
-{
- CRYP_InitTypeDef AES_CRYP_InitStructure;
- CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
- __IO uint32_t counter = 0;
- uint32_t busystatus = 0;
- ErrorStatus status = SUCCESS;
- uint32_t keyaddr = (uint32_t)Key;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
- uint32_t i = 0;
-
- /* Crypto structures initialisation*/
- CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure);
-
- switch(Keysize)
- {
- case 128:
- AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
- AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
- break;
- case 192:
- AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b;
- AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
- break;
- case 256:
- AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b;
- AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
- break;
- default:
- break;
- }
-
- /*------------------ AES Decryption ------------------*/
- if(Mode == MODE_DECRYPT) /* AES decryption */
- {
- /* Flush IN/OUT FIFOs */
- CRYP_FIFOFlush();
-
- /* Crypto Init for Key preparation for decryption process */
- AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
- AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key;
- AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b;
- CRYP_Init(&AES_CRYP_InitStructure);
-
- /* Key Initialisation */
- CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- /* wait until the Busy flag is RESET */
- do
- {
- busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
- counter++;
- }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- else
- {
- /* Crypto Init for decryption process */
- AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
- }
- }
- /*------------------ AES Encryption ------------------*/
- else /* AES encryption */
- {
-
- CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
-
- /* Crypto Init for Encryption process */
- AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
- }
-
- AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_ECB;
- AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
- CRYP_Init(&AES_CRYP_InitStructure);
-
- /* Flush IN/OUT FIFOs */
- CRYP_FIFOFlush();
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- if(CRYP_GetCmdStatus() == DISABLE)
- {
- /* The CRYP peripheral clock is not enabled or the device doesn't embed
- the CRYP peripheral (please check the device sales type. */
- return(ERROR);
- }
-
- for(i=0; ((i>32));
- CRYP_DataIn(__REV(headerlength));
- CRYP_DataIn(__REV(inputlength>>32));
- CRYP_DataIn(__REV(inputlength));
- /* Wait until the OFNE flag is reset */
- while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET)
- {
- }
-
- tagaddr = (uint32_t)AuthTAG;
- /* Read the Auth TAG in the IN FIFO */
- *(uint32_t*)(tagaddr) = CRYP_DataOut();
- tagaddr+=4;
- *(uint32_t*)(tagaddr) = CRYP_DataOut();
- tagaddr+=4;
- *(uint32_t*)(tagaddr) = CRYP_DataOut();
- tagaddr+=4;
- *(uint32_t*)(tagaddr) = CRYP_DataOut();
- tagaddr+=4;
- }
- /*------------------ AES Decryption ------------------*/
- else /* AES decryption */
- {
- /* Flush IN/OUT FIFOs */
- CRYP_FIFOFlush();
-
- /* Key Initialisation */
- CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
-
- /* CRYP Initialization Vectors */
- CRYP_IVInit(&AES_CRYP_IVInitStructure);
-
- /* Crypto Init for Key preparation for decryption process */
- AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
- AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_GCM;
- AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
- CRYP_Init(&AES_CRYP_InitStructure);
-
- /***************************** Init phase *********************************/
- /* Select init phase */
- CRYP_PhaseConfig(CRYP_Phase_Init);
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- /* Wait for CRYPEN bit to be 0 */
- while(CRYP_GetCmdStatus() == ENABLE)
- {
- }
-
- /***************************** header phase *******************************/
- if(HLength != 0)
- {
- /* Select header phase */
- CRYP_PhaseConfig(CRYP_Phase_Header);
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- if(CRYP_GetCmdStatus() == DISABLE)
- {
- /* The CRYP peripheral clock is not enabled or the device doesn't embed
- the CRYP peripheral (please check the device sales type. */
- return(ERROR);
- }
-
- for(loopcounter = 0; (loopcounter < HLength); loopcounter+=16)
- {
- /* Wait until the IFEM flag is reset */
- while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET)
- {
- }
-
- /* Write the Input block in the IN FIFO */
- CRYP_DataIn(*(uint32_t*)(headeraddr));
- headeraddr+=4;
- CRYP_DataIn(*(uint32_t*)(headeraddr));
- headeraddr+=4;
- CRYP_DataIn(*(uint32_t*)(headeraddr));
- headeraddr+=4;
- CRYP_DataIn(*(uint32_t*)(headeraddr));
- headeraddr+=4;
- }
-
- /* Wait until the complete message has been processed */
- counter = 0;
- do
- {
- busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
- counter++;
- }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- }
-
- /**************************** payload phase *******************************/
- if(ILength != 0)
- {
- /* Select payload phase */
- CRYP_PhaseConfig(CRYP_Phase_Payload);
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- if(CRYP_GetCmdStatus() == DISABLE)
- {
- /* The CRYP peripheral clock is not enabled or the device doesn't embed
- the CRYP peripheral (please check the device sales type. */
- return(ERROR);
- }
-
- for(loopcounter = 0; ((loopcounter < ILength) && (status != ERROR)); loopcounter+=16)
- {
- /* Wait until the IFEM flag is reset */
- while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET)
- {
- }
- /* Write the Input block in the IN FIFO */
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
-
- /* Wait until the complete message has been processed */
- counter = 0;
- do
- {
- busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
- counter++;
- }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- else
- {
- /* Wait until the OFNE flag is reset */
- while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET)
- {
- }
-
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- }
- }
- }
-
- /***************************** final phase ********************************/
- /* Select final phase */
- CRYP_PhaseConfig(CRYP_Phase_Final);
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- if(CRYP_GetCmdStatus() == DISABLE)
- {
- /* The CRYP peripheral clock is not enabled or the device doesn't embed
- the CRYP peripheral (please check the device sales type. */
- return(ERROR);
- }
-
- /* Write number of bits concatenated with header in the IN FIFO */
- CRYP_DataIn(__REV(headerlength>>32));
- CRYP_DataIn(__REV(headerlength));
- CRYP_DataIn(__REV(inputlength>>32));
- CRYP_DataIn(__REV(inputlength));
- /* Wait until the OFNE flag is reset */
- while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET)
- {
- }
-
- tagaddr = (uint32_t)AuthTAG;
- /* Read the Auth TAG in the IN FIFO */
- *(uint32_t*)(tagaddr) = CRYP_DataOut();
- tagaddr+=4;
- *(uint32_t*)(tagaddr) = CRYP_DataOut();
- tagaddr+=4;
- *(uint32_t*)(tagaddr) = CRYP_DataOut();
- tagaddr+=4;
- *(uint32_t*)(tagaddr) = CRYP_DataOut();
- tagaddr+=4;
- }
- /* Disable Crypto */
- CRYP_Cmd(DISABLE);
-
- return status;
-}
-
-/**
- * @brief Encrypt and decrypt using AES in CCM Mode. The GCM and CCM modes
- * are available only on STM32F437x Devices.
- * @param Mode: encryption or decryption Mode.
- * This parameter can be one of the following values:
- * @arg MODE_ENCRYPT: Encryption
- * @arg MODE_DECRYPT: Decryption
- * @param Nonce: the nonce used for AES algorithm. It shall be unique for each processing.
- * @param Key: Key used for AES algorithm.
- * @param Keysize: length of the Key, must be a 128, 192 or 256.
- * @param Input: pointer to the Input buffer.
- * @param Ilength: length of the Input buffer in bytes, must be a multiple of 16.
- * @param Header: pointer to the header buffer.
- * @param Hlength: length of the header buffer in bytes.
- * @param HBuffer: pointer to temporary buffer used to append the header
- * HBuffer size must be equal to Hlength + 21
- * @param Output: pointer to the returned buffer.
- * @param AuthTAG: pointer to the authentication TAG buffer.
- * @param TAGSize: the size of the TAG (called also MAC).
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Operation done
- * - ERROR: Operation failed
- */
-ErrorStatus CRYP_AES_CCM(uint8_t Mode,
- uint8_t* Nonce, uint32_t NonceSize,
- uint8_t *Key, uint16_t Keysize,
- uint8_t *Input, uint32_t ILength,
- uint8_t *Header, uint32_t HLength, uint8_t *HBuffer,
- uint8_t *Output,
- uint8_t *AuthTAG, uint32_t TAGSize)
-{
- CRYP_InitTypeDef AES_CRYP_InitStructure;
- CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
- CRYP_IVInitTypeDef AES_CRYP_IVInitStructure;
- __IO uint32_t counter = 0;
- uint32_t busystatus = 0;
- ErrorStatus status = SUCCESS;
- uint32_t keyaddr = (uint32_t)Key;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
- uint32_t headeraddr = (uint32_t)Header;
- uint32_t tagaddr = (uint32_t)AuthTAG;
- uint32_t headersize = HLength;
- uint32_t loopcounter = 0;
- uint32_t bufferidx = 0;
- uint8_t blockb0[16] = {0};/* Block B0 */
- uint8_t ctr[16] = {0}; /* Counter */
- uint32_t temptag[4] = {0}; /* temporary TAG (MAC) */
- uint32_t ctraddr = (uint32_t)ctr;
- uint32_t b0addr = (uint32_t)blockb0;
-
- /************************ Formatting the header block ***********************/
- if(headersize != 0)
- {
- /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
- if(headersize < 65280)
- {
- HBuffer[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
- HBuffer[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
- headersize += 2;
- }
- else
- {
- /* header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
- HBuffer[bufferidx++] = 0xFF;
- HBuffer[bufferidx++] = 0xFE;
- HBuffer[bufferidx++] = headersize & 0xff000000;
- HBuffer[bufferidx++] = headersize & 0x00ff0000;
- HBuffer[bufferidx++] = headersize & 0x0000ff00;
- HBuffer[bufferidx++] = headersize & 0x000000ff;
- headersize += 6;
- }
- /* Copy the header buffer in internal buffer "HBuffer" */
- for(loopcounter = 0; loopcounter < headersize; loopcounter++)
- {
- HBuffer[bufferidx++] = Header[loopcounter];
- }
- /* Check if the header size is modulo 16 */
- if ((headersize % 16) != 0)
- {
- /* Padd the header buffer with 0s till the HBuffer length is modulo 16 */
- for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
- {
- HBuffer[loopcounter] = 0;
- }
- /* Set the header size to modulo 16 */
- headersize = ((headersize/16) + 1) * 16;
- }
- /* set the pointer headeraddr to HBuffer */
- headeraddr = (uint32_t)HBuffer;
- }
- /************************* Formatting the block B0 **************************/
- if(headersize != 0)
- {
- blockb0[0] = 0x40;
- }
- /* Flags byte */
- blockb0[0] |= 0u | (((( (uint8_t) TAGSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - NonceSize) - 1) & 0x07);
-
- for (loopcounter = 0; loopcounter < NonceSize; loopcounter++)
- {
- blockb0[loopcounter+1] = Nonce[loopcounter];
- }
- for ( ; loopcounter < 13; loopcounter++)
- {
- blockb0[loopcounter+1] = 0;
- }
-
- blockb0[14] = ((ILength >> 8) & 0xFF);
- blockb0[15] = (ILength & 0xFF);
-
- /************************* Formatting the initial counter *******************/
- /* Byte 0:
- Bits 7 and 6 are reserved and shall be set to 0
- Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter blocks
- are distinct from B0
- Bits 0, 1, and 2 contain the same encoding of q as in B0
- */
- ctr[0] = blockb0[0] & 0x07;
- /* byte 1 to NonceSize is the IV (Nonce) */
- for(loopcounter = 1; loopcounter < NonceSize + 1; loopcounter++)
- {
- ctr[loopcounter] = blockb0[loopcounter];
- }
- /* Set the LSB to 1 */
- ctr[15] |= 0x01;
-
- /* Crypto structures initialisation*/
- CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure);
-
- switch(Keysize)
- {
- case 128:
- AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
- AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
- break;
- case 192:
- AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b;
- AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
- break;
- case 256:
- AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b;
- AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
- break;
- default:
- break;
- }
-
- /* CRYP Initialization Vectors */
- AES_CRYP_IVInitStructure.CRYP_IV0Left = (__REV(*(uint32_t*)(ctraddr)));
- ctraddr+=4;
- AES_CRYP_IVInitStructure.CRYP_IV0Right= (__REV(*(uint32_t*)(ctraddr)));
- ctraddr+=4;
- AES_CRYP_IVInitStructure.CRYP_IV1Left = (__REV(*(uint32_t*)(ctraddr)));
- ctraddr+=4;
- AES_CRYP_IVInitStructure.CRYP_IV1Right= (__REV(*(uint32_t*)(ctraddr)));
-
- /*------------------ AES Encryption ------------------*/
- if(Mode == MODE_ENCRYPT) /* AES encryption */
- {
- /* Flush IN/OUT FIFOs */
- CRYP_FIFOFlush();
-
- /* Key Initialisation */
- CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
-
- /* CRYP Initialization Vectors */
- CRYP_IVInit(&AES_CRYP_IVInitStructure);
-
- /* Crypto Init for Key preparation for decryption process */
- AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
- AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CCM;
- AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
- CRYP_Init(&AES_CRYP_InitStructure);
-
- /***************************** Init phase *********************************/
- /* Select init phase */
- CRYP_PhaseConfig(CRYP_Phase_Init);
-
- b0addr = (uint32_t)blockb0;
- /* Write the blockb0 block in the IN FIFO */
- CRYP_DataIn((*(uint32_t*)(b0addr)));
- b0addr+=4;
- CRYP_DataIn((*(uint32_t*)(b0addr)));
- b0addr+=4;
- CRYP_DataIn((*(uint32_t*)(b0addr)));
- b0addr+=4;
- CRYP_DataIn((*(uint32_t*)(b0addr)));
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- /* Wait for CRYPEN bit to be 0 */
- while(CRYP_GetCmdStatus() == ENABLE)
- {
- }
- /***************************** header phase *******************************/
- if(headersize != 0)
- {
- /* Select header phase */
- CRYP_PhaseConfig(CRYP_Phase_Header);
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- if(CRYP_GetCmdStatus() == DISABLE)
- {
- /* The CRYP peripheral clock is not enabled or the device doesn't embed
- the CRYP peripheral (please check the device sales type. */
- return(ERROR);
- }
-
- for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
- {
- /* Wait until the IFEM flag is reset */
- while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET)
- {
- }
-
- /* Write the Input block in the IN FIFO */
- CRYP_DataIn(*(uint32_t*)(headeraddr));
- headeraddr+=4;
- CRYP_DataIn(*(uint32_t*)(headeraddr));
- headeraddr+=4;
- CRYP_DataIn(*(uint32_t*)(headeraddr));
- headeraddr+=4;
- CRYP_DataIn(*(uint32_t*)(headeraddr));
- headeraddr+=4;
- }
-
- /* Wait until the complete message has been processed */
- counter = 0;
- do
- {
- busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
- counter++;
- }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- }
-
- /**************************** payload phase *******************************/
- if(ILength != 0)
- {
- /* Select payload phase */
- CRYP_PhaseConfig(CRYP_Phase_Payload);
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- if(CRYP_GetCmdStatus() == DISABLE)
- {
- /* The CRYP peripheral clock is not enabled or the device doesn't embed
- the CRYP peripheral (please check the device sales type. */
- return(ERROR);
- }
-
- for(loopcounter = 0; ((loopcounter < ILength) && (status != ERROR)); loopcounter+=16)
- {
- /* Wait until the IFEM flag is reset */
- while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET)
- {
- }
-
- /* Write the Input block in the IN FIFO */
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
-
- /* Wait until the complete message has been processed */
- counter = 0;
- do
- {
- busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
- counter++;
- }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- else
- {
- /* Wait until the OFNE flag is reset */
- while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET)
- {
- }
-
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- }
- }
- }
-
- /***************************** final phase ********************************/
- /* Select final phase */
- CRYP_PhaseConfig(CRYP_Phase_Final);
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- if(CRYP_GetCmdStatus() == DISABLE)
- {
- /* The CRYP peripheral clock is not enabled or the device doesn't embed
- the CRYP peripheral (please check the device sales type. */
- return(ERROR);
- }
-
- ctraddr = (uint32_t)ctr;
- /* Write the counter block in the IN FIFO */
- CRYP_DataIn(*(uint32_t*)(ctraddr));
- ctraddr+=4;
- CRYP_DataIn(*(uint32_t*)(ctraddr));
- ctraddr+=4;
- CRYP_DataIn(*(uint32_t*)(ctraddr));
- ctraddr+=4;
- /* Reset bit 0 (after 8-bit swap) is equivalent to reset bit 24 (before 8-bit swap) */
- CRYP_DataIn(*(uint32_t*)(ctraddr) & 0xfeffffff);
-
- /* Wait until the OFNE flag is reset */
- while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET)
- {
- }
-
- /* Read the Auth TAG in the IN FIFO */
- temptag[0] = CRYP_DataOut();
- temptag[1] = CRYP_DataOut();
- temptag[2] = CRYP_DataOut();
- temptag[3] = CRYP_DataOut();
- }
- /*------------------ AES Decryption ------------------*/
- else /* AES decryption */
- {
- /* Flush IN/OUT FIFOs */
- CRYP_FIFOFlush();
-
- /* Key Initialisation */
- CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
-
- /* CRYP Initialization Vectors */
- CRYP_IVInit(&AES_CRYP_IVInitStructure);
-
- /* Crypto Init for Key preparation for decryption process */
- AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
- AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CCM;
- AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
- CRYP_Init(&AES_CRYP_InitStructure);
-
- /***************************** Init phase *********************************/
- /* Select init phase */
- CRYP_PhaseConfig(CRYP_Phase_Init);
-
- b0addr = (uint32_t)blockb0;
- /* Write the blockb0 block in the IN FIFO */
- CRYP_DataIn((*(uint32_t*)(b0addr)));
- b0addr+=4;
- CRYP_DataIn((*(uint32_t*)(b0addr)));
- b0addr+=4;
- CRYP_DataIn((*(uint32_t*)(b0addr)));
- b0addr+=4;
- CRYP_DataIn((*(uint32_t*)(b0addr)));
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- /* Wait for CRYPEN bit to be 0 */
- while(CRYP_GetCmdStatus() == ENABLE)
- {
- }
-
- /***************************** header phase *******************************/
- if(headersize != 0)
- {
- /* Select header phase */
- CRYP_PhaseConfig(CRYP_Phase_Header);
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- if(CRYP_GetCmdStatus() == DISABLE)
- {
- /* The CRYP peripheral clock is not enabled or the device doesn't embed
- the CRYP peripheral (please check the device sales type. */
- return(ERROR);
- }
-
- for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
- {
- /* Wait until the IFEM flag is reset */
- while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET)
- {
- }
-
- /* Write the Input block in the IN FIFO */
- CRYP_DataIn(*(uint32_t*)(headeraddr));
- headeraddr+=4;
- CRYP_DataIn(*(uint32_t*)(headeraddr));
- headeraddr+=4;
- CRYP_DataIn(*(uint32_t*)(headeraddr));
- headeraddr+=4;
- CRYP_DataIn(*(uint32_t*)(headeraddr));
- headeraddr+=4;
- }
-
- /* Wait until the complete message has been processed */
- counter = 0;
- do
- {
- busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
- counter++;
- }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- }
-
- /**************************** payload phase *******************************/
- if(ILength != 0)
- {
- /* Select payload phase */
- CRYP_PhaseConfig(CRYP_Phase_Payload);
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- if(CRYP_GetCmdStatus() == DISABLE)
- {
- /* The CRYP peripheral clock is not enabled or the device doesn't embed
- the CRYP peripheral (please check the device sales type. */
- return(ERROR);
- }
-
- for(loopcounter = 0; ((loopcounter < ILength) && (status != ERROR)); loopcounter+=16)
- {
- /* Wait until the IFEM flag is reset */
- while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET)
- {
- }
-
- /* Write the Input block in the IN FIFO */
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
- CRYP_DataIn(*(uint32_t*)(inputaddr));
- inputaddr+=4;
-
- /* Wait until the complete message has been processed */
- counter = 0;
- do
- {
- busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
- counter++;
- }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
-
- if (busystatus != RESET)
- {
- status = ERROR;
- }
- else
- {
- /* Wait until the OFNE flag is reset */
- while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET)
- {
- }
-
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = CRYP_DataOut();
- outputaddr+=4;
- }
- }
- }
-
- /***************************** final phase ********************************/
- /* Select final phase */
- CRYP_PhaseConfig(CRYP_Phase_Final);
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- if(CRYP_GetCmdStatus() == DISABLE)
- {
- /* The CRYP peripheral clock is not enabled or the device doesn't embed
- the CRYP peripheral (please check the device sales type. */
- return(ERROR);
- }
-
- ctraddr = (uint32_t)ctr;
- /* Write the counter block in the IN FIFO */
- CRYP_DataIn(*(uint32_t*)(ctraddr));
- ctraddr+=4;
- CRYP_DataIn(*(uint32_t*)(ctraddr));
- ctraddr+=4;
- CRYP_DataIn(*(uint32_t*)(ctraddr));
- ctraddr+=4;
- /* Reset bit 0 (after 8-bit swap) is equivalent to reset bit 24 (before 8-bit swap) */
- CRYP_DataIn(*(uint32_t*)(ctraddr) & 0xfeffffff);
-
- /* Wait until the OFNE flag is reset */
- while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET)
- {
- }
-
- /* Read the Authentification TAG (MAC) in the IN FIFO */
- temptag[0] = CRYP_DataOut();
- temptag[1] = CRYP_DataOut();
- temptag[2] = CRYP_DataOut();
- temptag[3] = CRYP_DataOut();
- }
-
- /* Copy temporary authentication TAG in user TAG buffer */
- for(loopcounter = 0; (loopcounter < TAGSize); loopcounter++)
- {
- /* Set the authentication TAG buffer */
- *((uint8_t*)tagaddr+loopcounter) = *((uint8_t*)temptag+loopcounter);
- }
-
- /* Disable Crypto */
- CRYP_Cmd(DISABLE);
-
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_cryp_des.c b/底盘/底盘-old/底盘/Library/stm32f4xx_cryp_des.c
deleted file mode 100644
index 685fd4d..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_cryp_des.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_cryp_des.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides high level functions to encrypt and decrypt an
- * input message using DES in ECB/CBC modes.
- * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
- * peripheral.
- *
-@verbatim
-
- ===================================================================
- ##### How to use this driver #####
- ===================================================================
- [..]
- (#) Enable The CRYP controller clock using
- RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
-
- (#) Encrypt and decrypt using DES in ECB Mode using CRYP_DES_ECB() function.
-
- (#) Encrypt and decrypt using DES in CBC Mode using CRYP_DES_CBC() function.
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_cryp.h"
-
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CRYP
- * @brief CRYP driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define DESBUSY_TIMEOUT ((uint32_t) 0x00010000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-
-/** @defgroup CRYP_Private_Functions
- * @{
- */
-
-/** @defgroup CRYP_Group8 High Level DES functions
- * @brief High Level DES functions
- *
-@verbatim
- ===============================================================================
- ##### High Level DES functions #####
- ===============================================================================
-@endverbatim
- * @{
- */
-
-/**
- * @brief Encrypt and decrypt using DES in ECB Mode
- * @param Mode: encryption or decryption Mode.
- * This parameter can be one of the following values:
- * @arg MODE_ENCRYPT: Encryption
- * @arg MODE_DECRYPT: Decryption
- * @param Key: Key used for DES algorithm.
- * @param Ilength: length of the Input buffer, must be a multiple of 8.
- * @param Input: pointer to the Input buffer.
- * @param Output: pointer to the returned buffer.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Operation done
- * - ERROR: Operation failed
- */
-ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input,
- uint32_t Ilength, uint8_t *Output)
-{
- CRYP_InitTypeDef DES_CRYP_InitStructure;
- CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure;
- __IO uint32_t counter = 0;
- uint32_t busystatus = 0;
- ErrorStatus status = SUCCESS;
- uint32_t keyaddr = (uint32_t)Key;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
- uint32_t i = 0;
-
- /* Crypto structures initialisation*/
- CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure);
-
- /* Crypto Init for Encryption process */
- if( Mode == MODE_ENCRYPT ) /* DES encryption */
- {
- DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
- }
- else/* if( Mode == MODE_DECRYPT )*/ /* DES decryption */
- {
- DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
- }
-
- DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_ECB;
- DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
- CRYP_Init(&DES_CRYP_InitStructure);
-
- /* Key Initialisation */
- DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
- CRYP_KeyInit(& DES_CRYP_KeyInitStructure);
-
- /* Flush IN/OUT FIFO */
- CRYP_FIFOFlush();
-
- /* Enable Crypto processor */
- CRYP_Cmd(ENABLE);
-
- if(CRYP_GetCmdStatus() == DISABLE)
- {
- /* The CRYP peripheral clock is not enabled or the device doesn't embed
- the CRYP peripheral (please check the device sales type. */
- status = ERROR;
- }
- else
- {
- for(i=0; ((iDAC_Trigger));
- assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
- assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
- assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
-
-/*---------------------------- DAC CR Configuration --------------------------*/
- /* Get the DAC CR value */
- tmpreg1 = DAC->CR;
- /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
- tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
- /* Configure for the selected DAC channel: buffer output, trigger,
- wave generation, mask/amplitude for wave generation */
- /* Set TSELx and TENx bits according to DAC_Trigger value */
- /* Set WAVEx bits according to DAC_WaveGeneration value */
- /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
- /* Set BOFFx bit according to DAC_OutputBuffer value */
- tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
- DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \
- DAC_InitStruct->DAC_OutputBuffer);
- /* Calculate CR register value depending on DAC_Channel */
- tmpreg1 |= tmpreg2 << DAC_Channel;
- /* Write to DAC CR */
- DAC->CR = tmpreg1;
-}
-
-/**
- * @brief Fills each DAC_InitStruct member with its default value.
- * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
-{
-/*--------------- Reset DAC init structure parameters values -----------------*/
- /* Initialize the DAC_Trigger member */
- DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
- /* Initialize the DAC_WaveGeneration member */
- DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
- /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
- DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
- /* Initialize the DAC_OutputBuffer member */
- DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
-}
-
-/**
- * @brief Enables or disables the specified DAC channel.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param NewState: new state of the DAC channel.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the DAC channel is enabled the trigger source can no more be modified.
- * @retval None
- */
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DAC channel */
- DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
- }
- else
- {
- /* Disable the selected DAC channel */
- DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));
- }
-}
-
-/**
- * @brief Enables or disables the selected DAC channel software trigger.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param NewState: new state of the selected DAC channel software trigger.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable software trigger for the selected DAC channel */
- DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
- }
- else
- {
- /* Disable software trigger for the selected DAC channel */
- DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
- }
-}
-
-/**
- * @brief Enables or disables simultaneously the two DAC channels software triggers.
- * @param NewState: new state of the DAC channels software triggers.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable software trigger for both DAC channels */
- DAC->SWTRIGR |= DUAL_SWTRIG_SET;
- }
- else
- {
- /* Disable software trigger for both DAC channels */
- DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
- }
-}
-
-/**
- * @brief Enables or disables the selected DAC channel wave generation.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_Wave: specifies the wave type to enable or disable.
- * This parameter can be one of the following values:
- * @arg DAC_Wave_Noise: noise wave generation
- * @arg DAC_Wave_Triangle: triangle wave generation
- * @param NewState: new state of the selected DAC channel wave generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_WAVE(DAC_Wave));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected wave generation for the selected DAC channel */
- DAC->CR |= DAC_Wave << DAC_Channel;
- }
- else
- {
- /* Disable the selected wave generation for the selected DAC channel */
- DAC->CR &= ~(DAC_Wave << DAC_Channel);
- }
-}
-
-/**
- * @brief Set the specified data holding register value for DAC channel1.
- * @param DAC_Align: Specifies the data alignment for DAC channel1.
- * This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: 8bit right data alignment selected
- * @arg DAC_Align_12b_L: 12bit left data alignment selected
- * @arg DAC_Align_12b_R: 12bit right data alignment selected
- * @param Data: Data to be loaded in the selected data holding register.
- * @retval None
- */
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALIGN(DAC_Align));
- assert_param(IS_DAC_DATA(Data));
-
- tmp = (uint32_t)DAC_BASE;
- tmp += DHR12R1_OFFSET + DAC_Align;
-
- /* Set the DAC channel1 selected data holding register */
- *(__IO uint32_t *) tmp = Data;
-}
-
-/**
- * @brief Set the specified data holding register value for DAC channel2.
- * @param DAC_Align: Specifies the data alignment for DAC channel2.
- * This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: 8bit right data alignment selected
- * @arg DAC_Align_12b_L: 12bit left data alignment selected
- * @arg DAC_Align_12b_R: 12bit right data alignment selected
- * @param Data: Data to be loaded in the selected data holding register.
- * @retval None
- */
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALIGN(DAC_Align));
- assert_param(IS_DAC_DATA(Data));
-
- tmp = (uint32_t)DAC_BASE;
- tmp += DHR12R2_OFFSET + DAC_Align;
-
- /* Set the DAC channel2 selected data holding register */
- *(__IO uint32_t *)tmp = Data;
-}
-
-/**
- * @brief Set the specified data holding register value for dual channel DAC.
- * @param DAC_Align: Specifies the data alignment for dual channel DAC.
- * This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: 8bit right data alignment selected
- * @arg DAC_Align_12b_L: 12bit left data alignment selected
- * @arg DAC_Align_12b_R: 12bit right data alignment selected
- * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register.
- * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register.
- * @note In dual mode, a unique register access is required to write in both
- * DAC channels at the same time.
- * @retval None
- */
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
-{
- uint32_t data = 0, tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALIGN(DAC_Align));
- assert_param(IS_DAC_DATA(Data1));
- assert_param(IS_DAC_DATA(Data2));
-
- /* Calculate and set dual DAC data holding register value */
- if (DAC_Align == DAC_Align_8b_R)
- {
- data = ((uint32_t)Data2 << 8) | Data1;
- }
- else
- {
- data = ((uint32_t)Data2 << 16) | Data1;
- }
-
- tmp = (uint32_t)DAC_BASE;
- tmp += DHR12RD_OFFSET + DAC_Align;
-
- /* Set the dual DAC selected data holding register */
- *(__IO uint32_t *)tmp = data;
-}
-
-/**
- * @brief Returns the last data output value of the selected DAC channel.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @retval The selected DAC channel data output value.
- */
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
-
- tmp = (uint32_t) DAC_BASE ;
- tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
-
- /* Returns the DAC channel data output register value */
- return (uint16_t) (*(__IO uint32_t*) tmp);
-}
-/**
- * @}
- */
-
-/** @defgroup DAC_Group2 DMA management functions
- * @brief DMA management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified DAC channel DMA request.
- * @note When enabled DMA1 is generated when an external trigger (EXTI Line9,
- * TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8 but not a software trigger) occurs.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param NewState: new state of the selected DAC channel DMA request.
- * This parameter can be: ENABLE or DISABLE.
- * @note The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be
- * already configured.
- * @note The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be
- * already configured.
- * @retval None
- */
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DAC channel DMA request */
- DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
- }
- else
- {
- /* Disable the selected DAC channel DMA request */
- DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
- }
-}
-/**
- * @}
- */
-
-/** @defgroup DAC_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified DAC interrupts.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
- * This parameter can be the following values:
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
- * @note The DMA underrun occurs when a second external trigger arrives before the
- * acknowledgement for the first external trigger is received (first request).
- * @param NewState: new state of the specified DAC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_DAC_IT(DAC_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DAC interrupts */
- DAC->CR |= (DAC_IT << DAC_Channel);
- }
- else
- {
- /* Disable the selected DAC interrupts */
- DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
- }
-}
-
-/**
- * @brief Checks whether the specified DAC flag is set or not.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_FLAG: specifies the flag to check.
- * This parameter can be only of the following value:
- * @arg DAC_FLAG_DMAUDR: DMA underrun flag
- * @note The DMA underrun occurs when a second external trigger arrives before the
- * acknowledgement for the first external trigger is received (first request).
- * @retval The new state of DAC_FLAG (SET or RESET).
- */
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_FLAG(DAC_FLAG));
-
- /* Check the status of the specified DAC flag */
- if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
- {
- /* DAC_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* DAC_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the DAC_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DAC channel's pending flags.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_FLAG: specifies the flag to clear.
- * This parameter can be of the following value:
- * @arg DAC_FLAG_DMAUDR: DMA underrun flag
- * @note The DMA underrun occurs when a second external trigger arrives before the
- * acknowledgement for the first external trigger is received (first request).
- * @retval None
- */
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_FLAG(DAC_FLAG));
-
- /* Clear the selected DAC flags */
- DAC->SR = (DAC_FLAG << DAC_Channel);
-}
-
-/**
- * @brief Checks whether the specified DAC interrupt has occurred or not.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_IT: specifies the DAC interrupt source to check.
- * This parameter can be the following values:
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
- * @note The DMA underrun occurs when a second external trigger arrives before the
- * acknowledgement for the first external trigger is received (first request).
- * @retval The new state of DAC_IT (SET or RESET).
- */
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_IT(DAC_IT));
-
- /* Get the DAC_IT enable bit status */
- enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
-
- /* Check the status of the specified DAC interrupt */
- if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
- {
- /* DAC_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* DAC_IT is reset */
- bitstatus = RESET;
- }
- /* Return the DAC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DAC channel's interrupt pending bits.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_IT: specifies the DAC interrupt pending bit to clear.
- * This parameter can be the following values:
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
- * @note The DMA underrun occurs when a second external trigger arrives before the
- * acknowledgement for the first external trigger is received (first request).
- * @retval None
- */
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_IT(DAC_IT));
-
- /* Clear the selected DAC interrupt pending bits */
- DAC->SR = (DAC_IT << DAC_Channel);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_dac.h b/底盘/底盘-old/底盘/Library/stm32f4xx_dac.h
deleted file mode 100644
index 4160732..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_dac.h
+++ /dev/null
@@ -1,296 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_dac.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the DAC firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_DAC_H
-#define __STM32F4xx_DAC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup DAC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief DAC Init structure definition
- */
-
-typedef struct
-{
- uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
- This parameter can be a value of @ref DAC_trigger_selection */
-
- uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
- are generated, or whether no wave is generated.
- This parameter can be a value of @ref DAC_wave_generation */
-
- uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
- the maximum amplitude triangle generation for the DAC channel.
- This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
-
- uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
- This parameter can be a value of @ref DAC_output_buffer */
-}DAC_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Constants
- * @{
- */
-
-/** @defgroup DAC_trigger_selection
- * @{
- */
-
-#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
- has been loaded, and not by external trigger */
-#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
-
-#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
- ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
- ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
- ((TRIGGER) == DAC_Trigger_Software))
-
-/**
- * @}
- */
-
-/** @defgroup DAC_wave_generation
- * @{
- */
-
-#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
-#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
-#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
-#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
- ((WAVE) == DAC_WaveGeneration_Noise) || \
- ((WAVE) == DAC_WaveGeneration_Triangle))
-/**
- * @}
- */
-
-/** @defgroup DAC_lfsrunmask_triangleamplitude
- * @{
- */
-
-#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
-#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
-#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
-#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
-#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
-#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
-#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
-#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
-#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
-#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
-
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
- ((VALUE) == DAC_TriangleAmplitude_1) || \
- ((VALUE) == DAC_TriangleAmplitude_3) || \
- ((VALUE) == DAC_TriangleAmplitude_7) || \
- ((VALUE) == DAC_TriangleAmplitude_15) || \
- ((VALUE) == DAC_TriangleAmplitude_31) || \
- ((VALUE) == DAC_TriangleAmplitude_63) || \
- ((VALUE) == DAC_TriangleAmplitude_127) || \
- ((VALUE) == DAC_TriangleAmplitude_255) || \
- ((VALUE) == DAC_TriangleAmplitude_511) || \
- ((VALUE) == DAC_TriangleAmplitude_1023) || \
- ((VALUE) == DAC_TriangleAmplitude_2047) || \
- ((VALUE) == DAC_TriangleAmplitude_4095))
-/**
- * @}
- */
-
-/** @defgroup DAC_output_buffer
- * @{
- */
-
-#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
-#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
- ((STATE) == DAC_OutputBuffer_Disable))
-/**
- * @}
- */
-
-/** @defgroup DAC_Channel_selection
- * @{
- */
-
-#define DAC_Channel_1 ((uint32_t)0x00000000)
-#define DAC_Channel_2 ((uint32_t)0x00000010)
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
- ((CHANNEL) == DAC_Channel_2))
-/**
- * @}
- */
-
-/** @defgroup DAC_data_alignement
- * @{
- */
-
-#define DAC_Align_12b_R ((uint32_t)0x00000000)
-#define DAC_Align_12b_L ((uint32_t)0x00000004)
-#define DAC_Align_8b_R ((uint32_t)0x00000008)
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
- ((ALIGN) == DAC_Align_12b_L) || \
- ((ALIGN) == DAC_Align_8b_R))
-/**
- * @}
- */
-
-/** @defgroup DAC_wave_generation
- * @{
- */
-
-#define DAC_Wave_Noise ((uint32_t)0x00000040)
-#define DAC_Wave_Triangle ((uint32_t)0x00000080)
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
- ((WAVE) == DAC_Wave_Triangle))
-/**
- * @}
- */
-
-/** @defgroup DAC_data
- * @{
- */
-
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
-/**
- * @}
- */
-
-/** @defgroup DAC_interrupts_definition
- * @{
- */
-#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
-#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
-
-/**
- * @}
- */
-
-/** @defgroup DAC_flags_definition
- * @{
- */
-
-#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
-#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the DAC configuration to the default reset state *****/
-void DAC_DeInit(void);
-
-/* DAC channels configuration: trigger, output buffer, data format functions */
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
-void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
-
-/* DMA management functions ***************************************************/
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_DAC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_dbgmcu.c b/底盘/底盘-old/底盘/Library/stm32f4xx_dbgmcu.c
deleted file mode 100644
index 3af6445..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_dbgmcu.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_dbgmcu.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides all the DBGMCU firmware functions.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_dbgmcu.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DBGMCU
- * @brief DBGMCU driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DBGMCU_Private_Functions
- * @{
- */
-
-/**
- * @brief Returns the device revision identifier.
- * @param None
- * @retval Device revision identifier
- */
-uint32_t DBGMCU_GetREVID(void)
-{
- return(DBGMCU->IDCODE >> 16);
-}
-
-/**
- * @brief Returns the device identifier.
- * @param None
- * @retval Device identifier
- */
-uint32_t DBGMCU_GetDEVID(void)
-{
- return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
-}
-
-/**
- * @brief Configures low power mode behavior when the MCU is in Debug mode.
- * @param DBGMCU_Periph: specifies the low power mode.
- * This parameter can be any combination of the following values:
- * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
- * @arg DBGMCU_STOP: Keep debugger connection during STOP mode
- * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
- * @param NewState: new state of the specified low power mode in Debug mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- DBGMCU->CR |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->CR &= ~DBGMCU_Periph;
- }
-}
-
-/**
- * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.
- * @param DBGMCU_Periph: specifies the APB1 peripheral.
- * This parameter can be any combination of the following values:
- * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
- * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
- * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
- * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
- * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
- * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
- * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
- * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
- * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
- * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped when Core is halted.
- * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
- * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
- * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
- * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
- * @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted
- * @arg DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted
- * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- DBGMCU->APB1FZ |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->APB1FZ &= ~DBGMCU_Periph;
- }
-}
-
-/**
- * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.
- * @param DBGMCU_Periph: specifies the APB2 peripheral.
- * This parameter can be any combination of the following values:
- * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
- * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
- * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
- * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
- * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
- * @param NewState: new state of the specified peripheral in Debug mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- DBGMCU->APB2FZ |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->APB2FZ &= ~DBGMCU_Periph;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_dbgmcu.h b/底盘/底盘-old/底盘/Library/stm32f4xx_dbgmcu.h
deleted file mode 100644
index e3dd3be..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_dbgmcu.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_dbgmcu.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the DBGMCU firmware library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_DBGMCU_H
-#define __STM32F4xx_DBGMCU_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup DBGMCU
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DBGMCU_Exported_Constants
- * @{
- */
-#define DBGMCU_SLEEP ((uint32_t)0x00000001)
-#define DBGMCU_STOP ((uint32_t)0x00000002)
-#define DBGMCU_STANDBY ((uint32_t)0x00000004)
-#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
-
-#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)
-#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)
-#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)
-#define DBGMCU_TIM5_STOP ((uint32_t)0x00000008)
-#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)
-#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)
-#define DBGMCU_TIM12_STOP ((uint32_t)0x00000040)
-#define DBGMCU_TIM13_STOP ((uint32_t)0x00000080)
-#define DBGMCU_TIM14_STOP ((uint32_t)0x00000100)
-#define DBGMCU_RTC_STOP ((uint32_t)0x00000400)
-#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)
-#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)
-#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
-#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
-#define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
-#define DBGMCU_CAN1_STOP ((uint32_t)0x02000000)
-#define DBGMCU_CAN2_STOP ((uint32_t)0x04000000)
-#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00))
-
-#define DBGMCU_TIM1_STOP ((uint32_t)0x00000001)
-#define DBGMCU_TIM8_STOP ((uint32_t)0x00000002)
-#define DBGMCU_TIM9_STOP ((uint32_t)0x00010000)
-#define DBGMCU_TIM10_STOP ((uint32_t)0x00020000)
-#define DBGMCU_TIM11_STOP ((uint32_t)0x00040000)
-#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00))
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-uint32_t DBGMCU_GetREVID(void);
-uint32_t DBGMCU_GetDEVID(void);
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
-void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
-void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_DBGMCU_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_dcmi.c b/底盘/底盘-old/底盘/Library/stm32f4xx_dcmi.c
deleted file mode 100644
index 9de6676..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_dcmi.c
+++ /dev/null
@@ -1,530 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_dcmi.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the DCMI peripheral:
- * + Initialization and Configuration
- * + Image capture functions
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The sequence below describes how to use this driver to capture image
- from a camera module connected to the DCMI Interface.
- This sequence does not take into account the configuration of the
- camera module, which should be made before to configure and enable
- the DCMI to capture images.
-
- (#) Enable the clock for the DCMI and associated GPIOs using the following
- functions:
- RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
-
- (#) DCMI pins configuration
- (++) Connect the involved DCMI pins to AF13 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI);
- (++) Configure these DCMI pins in alternate function mode by calling
- the function GPIO_Init();
-
- (#) Declare a DCMI_InitTypeDef structure, for example:
- DCMI_InitTypeDef DCMI_InitStructure;
- and fill the DCMI_InitStructure variable with the allowed values
- of the structure member.
-
- (#) Initialize the DCMI interface by calling the function
- DCMI_Init(&DCMI_InitStructure);
-
- (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR
- register to the destination memory buffer.
-
- (#) Enable DCMI interface using the function
- DCMI_Cmd(ENABLE);
-
- (#) Start the image capture using the function
- DCMI_CaptureCmd(ENABLE);
-
- (#) At this stage the DCMI interface waits for the first start of frame,
- then a DMA request is generated continuously/once (depending on the
- mode used, Continuous/Snapshot) to transfer the received data into
- the destination memory.
-
- -@- If you need to capture only a rectangular window from the received
- image, you have to use the DCMI_CROPConfig() function to configure
- the coordinates and size of the window to be captured, then enable
- the Crop feature using DCMI_CROPCmd(ENABLE);
- In this case, the Crop configuration should be made before to enable
- and start the DCMI interface.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_dcmi.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DCMI
- * @brief DCMI driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DCMI_Private_Functions
- * @{
- */
-
-/** @defgroup DCMI_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the DCMI registers to their default reset values.
- * @param None
- * @retval None
- */
-void DCMI_DeInit(void)
-{
- DCMI->CR = 0x0;
- DCMI->IER = 0x0;
- DCMI->ICR = 0x1F;
- DCMI->ESCR = 0x0;
- DCMI->ESUR = 0x0;
- DCMI->CWSTRTR = 0x0;
- DCMI->CWSIZER = 0x0;
-}
-
-/**
- * @brief Initializes the DCMI according to the specified parameters in the DCMI_InitStruct.
- * @param DCMI_InitStruct: pointer to a DCMI_InitTypeDef structure that contains
- * the configuration information for the DCMI.
- * @retval None
- */
-void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct)
-{
- uint32_t temp = 0x0;
-
- /* Check the parameters */
- assert_param(IS_DCMI_CAPTURE_MODE(DCMI_InitStruct->DCMI_CaptureMode));
- assert_param(IS_DCMI_SYNCHRO(DCMI_InitStruct->DCMI_SynchroMode));
- assert_param(IS_DCMI_PCKPOLARITY(DCMI_InitStruct->DCMI_PCKPolarity));
- assert_param(IS_DCMI_VSPOLARITY(DCMI_InitStruct->DCMI_VSPolarity));
- assert_param(IS_DCMI_HSPOLARITY(DCMI_InitStruct->DCMI_HSPolarity));
- assert_param(IS_DCMI_CAPTURE_RATE(DCMI_InitStruct->DCMI_CaptureRate));
- assert_param(IS_DCMI_EXTENDED_DATA(DCMI_InitStruct->DCMI_ExtendedDataMode));
-
- /* The DCMI configuration registers should be programmed correctly before
- enabling the CR_ENABLE Bit and the CR_CAPTURE Bit */
- DCMI->CR &= ~(DCMI_CR_ENABLE | DCMI_CR_CAPTURE);
-
- /* Reset the old DCMI configuration */
- temp = DCMI->CR;
-
- temp &= ~((uint32_t)DCMI_CR_CM | DCMI_CR_ESS | DCMI_CR_PCKPOL |
- DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_FCRC_0 |
- DCMI_CR_FCRC_1 | DCMI_CR_EDM_0 | DCMI_CR_EDM_1);
-
- /* Sets the new configuration of the DCMI peripheral */
- temp |= ((uint32_t)DCMI_InitStruct->DCMI_CaptureMode |
- DCMI_InitStruct->DCMI_SynchroMode |
- DCMI_InitStruct->DCMI_PCKPolarity |
- DCMI_InitStruct->DCMI_VSPolarity |
- DCMI_InitStruct->DCMI_HSPolarity |
- DCMI_InitStruct->DCMI_CaptureRate |
- DCMI_InitStruct->DCMI_ExtendedDataMode);
-
- DCMI->CR = temp;
-}
-
-/**
- * @brief Fills each DCMI_InitStruct member with its default value.
- * @param DCMI_InitStruct : pointer to a DCMI_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct)
-{
- /* Set the default configuration */
- DCMI_InitStruct->DCMI_CaptureMode = DCMI_CaptureMode_Continuous;
- DCMI_InitStruct->DCMI_SynchroMode = DCMI_SynchroMode_Hardware;
- DCMI_InitStruct->DCMI_PCKPolarity = DCMI_PCKPolarity_Falling;
- DCMI_InitStruct->DCMI_VSPolarity = DCMI_VSPolarity_Low;
- DCMI_InitStruct->DCMI_HSPolarity = DCMI_HSPolarity_Low;
- DCMI_InitStruct->DCMI_CaptureRate = DCMI_CaptureRate_All_Frame;
- DCMI_InitStruct->DCMI_ExtendedDataMode = DCMI_ExtendedDataMode_8b;
-}
-
-/**
- * @brief Initializes the DCMI peripheral CROP mode according to the specified
- * parameters in the DCMI_CROPInitStruct.
- * @note This function should be called before to enable and start the DCMI interface.
- * @param DCMI_CROPInitStruct: pointer to a DCMI_CROPInitTypeDef structure that
- * contains the configuration information for the DCMI peripheral CROP mode.
- * @retval None
- */
-void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct)
-{
- /* Sets the CROP window coordinates */
- DCMI->CWSTRTR = (uint32_t)((uint32_t)DCMI_CROPInitStruct->DCMI_HorizontalOffsetCount |
- ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalStartLine << 16));
-
- /* Sets the CROP window size */
- DCMI->CWSIZER = (uint32_t)(DCMI_CROPInitStruct->DCMI_CaptureCount |
- ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalLineCount << 16));
-}
-
-/**
- * @brief Enables or disables the DCMI Crop feature.
- * @note This function should be called before to enable and start the DCMI interface.
- * @param NewState: new state of the DCMI Crop feature.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DCMI_CROPCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DCMI Crop feature */
- DCMI->CR |= (uint32_t)DCMI_CR_CROP;
- }
- else
- {
- /* Disable the DCMI Crop feature */
- DCMI->CR &= ~(uint32_t)DCMI_CR_CROP;
- }
-}
-
-/**
- * @brief Sets the embedded synchronization codes
- * @param DCMI_CodesInitTypeDef: pointer to a DCMI_CodesInitTypeDef structure that
- * contains the embedded synchronization codes for the DCMI peripheral.
- * @retval None
- */
-void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct)
-{
- DCMI->ESCR = (uint32_t)(DCMI_CodesInitStruct->DCMI_FrameStartCode |
- ((uint32_t)DCMI_CodesInitStruct->DCMI_LineStartCode << 8)|
- ((uint32_t)DCMI_CodesInitStruct->DCMI_LineEndCode << 16)|
- ((uint32_t)DCMI_CodesInitStruct->DCMI_FrameEndCode << 24));
-}
-
-/**
- * @brief Enables or disables the DCMI JPEG format.
- * @note The Crop and Embedded Synchronization features cannot be used in this mode.
- * @param NewState: new state of the DCMI JPEG format.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DCMI_JPEGCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DCMI JPEG format */
- DCMI->CR |= (uint32_t)DCMI_CR_JPEG;
- }
- else
- {
- /* Disable the DCMI JPEG format */
- DCMI->CR &= ~(uint32_t)DCMI_CR_JPEG;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup DCMI_Group2 Image capture functions
- * @brief Image capture functions
- *
-@verbatim
- ===============================================================================
- ##### Image capture functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the DCMI interface.
- * @param NewState: new state of the DCMI interface.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DCMI_Cmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DCMI by setting ENABLE bit */
- DCMI->CR |= (uint32_t)DCMI_CR_ENABLE;
- }
- else
- {
- /* Disable the DCMI by clearing ENABLE bit */
- DCMI->CR &= ~(uint32_t)DCMI_CR_ENABLE;
- }
-}
-
-/**
- * @brief Enables or disables the DCMI Capture.
- * @param NewState: new state of the DCMI capture.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DCMI_CaptureCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DCMI Capture */
- DCMI->CR |= (uint32_t)DCMI_CR_CAPTURE;
- }
- else
- {
- /* Disable the DCMI Capture */
- DCMI->CR &= ~(uint32_t)DCMI_CR_CAPTURE;
- }
-}
-
-/**
- * @brief Reads the data stored in the DR register.
- * @param None
- * @retval Data register value
- */
-uint32_t DCMI_ReadData(void)
-{
- return DCMI->DR;
-}
-/**
- * @}
- */
-
-/** @defgroup DCMI_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the DCMI interface interrupts.
- * @param DCMI_IT: specifies the DCMI interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
- * @arg DCMI_IT_OVF: Overflow interrupt mask
- * @arg DCMI_IT_ERR: Synchronization error interrupt mask
- * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
- * @arg DCMI_IT_LINE: Line interrupt mask
- * @param NewState: new state of the specified DCMI interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DCMI_CONFIG_IT(DCMI_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Interrupt sources */
- DCMI->IER |= DCMI_IT;
- }
- else
- {
- /* Disable the Interrupt sources */
- DCMI->IER &= (uint16_t)(~DCMI_IT);
- }
-}
-
-/**
- * @brief Checks whether the DCMI interface flag is set or not.
- * @param DCMI_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask
- * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask
- * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask
- * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask
- * @arg DCMI_FLAG_LINERI: Line Raw flag mask
- * @arg DCMI_FLAG_FRAMEMI: Frame capture complete Masked flag mask
- * @arg DCMI_FLAG_OVFMI: Overflow Masked flag mask
- * @arg DCMI_FLAG_ERRMI: Synchronization error Masked flag mask
- * @arg DCMI_FLAG_VSYNCMI: VSYNC Masked flag mask
- * @arg DCMI_FLAG_LINEMI: Line Masked flag mask
- * @arg DCMI_FLAG_HSYNC: HSYNC flag mask
- * @arg DCMI_FLAG_VSYNC: VSYNC flag mask
- * @arg DCMI_FLAG_FNE: Fifo not empty flag mask
- * @retval The new state of DCMI_FLAG (SET or RESET).
- */
-FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t dcmireg, tempreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DCMI_GET_FLAG(DCMI_FLAG));
-
- /* Get the DCMI register index */
- dcmireg = (((uint16_t)DCMI_FLAG) >> 12);
-
- if (dcmireg == 0x00) /* The FLAG is in RISR register */
- {
- tempreg= DCMI->RISR;
- }
- else if (dcmireg == 0x02) /* The FLAG is in SR register */
- {
- tempreg = DCMI->SR;
- }
- else /* The FLAG is in MISR register */
- {
- tempreg = DCMI->MISR;
- }
-
- if ((tempreg & DCMI_FLAG) != (uint16_t)RESET )
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the DCMI_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DCMI's pending flags.
- * @param DCMI_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask
- * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask
- * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask
- * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask
- * @arg DCMI_FLAG_LINERI: Line Raw flag mask
- * @retval None
- */
-void DCMI_ClearFlag(uint16_t DCMI_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_DCMI_CLEAR_FLAG(DCMI_FLAG));
-
- /* Clear the flag by writing in the ICR register 1 in the corresponding
- Flag position*/
-
- DCMI->ICR = DCMI_FLAG;
-}
-
-/**
- * @brief Checks whether the DCMI interrupt has occurred or not.
- * @param DCMI_IT: specifies the DCMI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
- * @arg DCMI_IT_OVF: Overflow interrupt mask
- * @arg DCMI_IT_ERR: Synchronization error interrupt mask
- * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
- * @arg DCMI_IT_LINE: Line interrupt mask
- * @retval The new state of DCMI_IT (SET or RESET).
- */
-ITStatus DCMI_GetITStatus(uint16_t DCMI_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t itstatus = 0;
-
- /* Check the parameters */
- assert_param(IS_DCMI_GET_IT(DCMI_IT));
-
- itstatus = DCMI->MISR & DCMI_IT; /* Only masked interrupts are checked */
-
- if ((itstatus != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the DCMI's interrupt pending bits.
- * @param DCMI_IT: specifies the DCMI interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
- * @arg DCMI_IT_OVF: Overflow interrupt mask
- * @arg DCMI_IT_ERR: Synchronization error interrupt mask
- * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
- * @arg DCMI_IT_LINE: Line interrupt mask
- * @retval None
- */
-void DCMI_ClearITPendingBit(uint16_t DCMI_IT)
-{
- /* Clear the interrupt pending Bit by writing in the ICR register 1 in the
- corresponding pending Bit position*/
-
- DCMI->ICR = DCMI_IT;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_dcmi.h b/底盘/底盘-old/底盘/Library/stm32f4xx_dcmi.h
deleted file mode 100644
index 215d861..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_dcmi.h
+++ /dev/null
@@ -1,304 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_dcmi.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the DCMI firmware library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_DCMI_H
-#define __STM32F4xx_DCMI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup DCMI
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/**
- * @brief DCMI Init structure definition
- */
-typedef struct
-{
- uint16_t DCMI_CaptureMode; /*!< Specifies the Capture Mode: Continuous or Snapshot.
- This parameter can be a value of @ref DCMI_Capture_Mode */
-
- uint16_t DCMI_SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
- This parameter can be a value of @ref DCMI_Synchronization_Mode */
-
- uint16_t DCMI_PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
- This parameter can be a value of @ref DCMI_PIXCK_Polarity */
-
- uint16_t DCMI_VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
- This parameter can be a value of @ref DCMI_VSYNC_Polarity */
-
- uint16_t DCMI_HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
- This parameter can be a value of @ref DCMI_HSYNC_Polarity */
-
- uint16_t DCMI_CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
- This parameter can be a value of @ref DCMI_Capture_Rate */
-
- uint16_t DCMI_ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
- This parameter can be a value of @ref DCMI_Extended_Data_Mode */
-} DCMI_InitTypeDef;
-
-/**
- * @brief DCMI CROP Init structure definition
- */
-typedef struct
-{
- uint16_t DCMI_VerticalStartLine; /*!< Specifies the Vertical start line count from which the image capture
- will start. This parameter can be a value between 0x00 and 0x1FFF */
-
- uint16_t DCMI_HorizontalOffsetCount; /*!< Specifies the number of pixel clocks to count before starting a capture.
- This parameter can be a value between 0x00 and 0x3FFF */
-
- uint16_t DCMI_VerticalLineCount; /*!< Specifies the number of lines to be captured from the starting point.
- This parameter can be a value between 0x00 and 0x3FFF */
-
- uint16_t DCMI_CaptureCount; /*!< Specifies the number of pixel clocks to be captured from the starting
- point on the same line.
- This parameter can be a value between 0x00 and 0x3FFF */
-} DCMI_CROPInitTypeDef;
-
-/**
- * @brief DCMI Embedded Synchronisation CODE Init structure definition
- */
-typedef struct
-{
- uint8_t DCMI_FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
- uint8_t DCMI_LineStartCode; /*!< Specifies the code of the line start delimiter. */
- uint8_t DCMI_LineEndCode; /*!< Specifies the code of the line end delimiter. */
- uint8_t DCMI_FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
-} DCMI_CodesInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DCMI_Exported_Constants
- * @{
- */
-
-/** @defgroup DCMI_Capture_Mode
- * @{
- */
-#define DCMI_CaptureMode_Continuous ((uint16_t)0x0000) /*!< The received data are transferred continuously
- into the destination memory through the DMA */
-#define DCMI_CaptureMode_SnapShot ((uint16_t)0x0002) /*!< Once activated, the interface waits for the start of
- frame and then transfers a single frame through the DMA */
-#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) || \
- ((MODE) == DCMI_CaptureMode_SnapShot))
-/**
- * @}
- */
-
-
-/** @defgroup DCMI_Synchronization_Mode
- * @{
- */
-#define DCMI_SynchroMode_Hardware ((uint16_t)0x0000) /*!< Hardware synchronization data capture (frame/line start/stop)
- is synchronized with the HSYNC/VSYNC signals */
-#define DCMI_SynchroMode_Embedded ((uint16_t)0x0010) /*!< Embedded synchronization data capture is synchronized with
- synchronization codes embedded in the data flow */
-#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) || \
- ((MODE) == DCMI_SynchroMode_Embedded))
-/**
- * @}
- */
-
-
-/** @defgroup DCMI_PIXCK_Polarity
- * @{
- */
-#define DCMI_PCKPolarity_Falling ((uint16_t)0x0000) /*!< Pixel clock active on Falling edge */
-#define DCMI_PCKPolarity_Rising ((uint16_t)0x0020) /*!< Pixel clock active on Rising edge */
-#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) || \
- ((POLARITY) == DCMI_PCKPolarity_Rising))
-/**
- * @}
- */
-
-
-/** @defgroup DCMI_VSYNC_Polarity
- * @{
- */
-#define DCMI_VSPolarity_Low ((uint16_t)0x0000) /*!< Vertical synchronization active Low */
-#define DCMI_VSPolarity_High ((uint16_t)0x0080) /*!< Vertical synchronization active High */
-#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) || \
- ((POLARITY) == DCMI_VSPolarity_High))
-/**
- * @}
- */
-
-
-/** @defgroup DCMI_HSYNC_Polarity
- * @{
- */
-#define DCMI_HSPolarity_Low ((uint16_t)0x0000) /*!< Horizontal synchronization active Low */
-#define DCMI_HSPolarity_High ((uint16_t)0x0040) /*!< Horizontal synchronization active High */
-#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) || \
- ((POLARITY) == DCMI_HSPolarity_High))
-/**
- * @}
- */
-
-
-/** @defgroup DCMI_Capture_Rate
- * @{
- */
-#define DCMI_CaptureRate_All_Frame ((uint16_t)0x0000) /*!< All frames are captured */
-#define DCMI_CaptureRate_1of2_Frame ((uint16_t)0x0100) /*!< Every alternate frame captured */
-#define DCMI_CaptureRate_1of4_Frame ((uint16_t)0x0200) /*!< One frame in 4 frames captured */
-#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || \
- ((RATE) == DCMI_CaptureRate_1of2_Frame) ||\
- ((RATE) == DCMI_CaptureRate_1of4_Frame))
-/**
- * @}
- */
-
-
-/** @defgroup DCMI_Extended_Data_Mode
- * @{
- */
-#define DCMI_ExtendedDataMode_8b ((uint16_t)0x0000) /*!< Interface captures 8-bit data on every pixel clock */
-#define DCMI_ExtendedDataMode_10b ((uint16_t)0x0400) /*!< Interface captures 10-bit data on every pixel clock */
-#define DCMI_ExtendedDataMode_12b ((uint16_t)0x0800) /*!< Interface captures 12-bit data on every pixel clock */
-#define DCMI_ExtendedDataMode_14b ((uint16_t)0x0C00) /*!< Interface captures 14-bit data on every pixel clock */
-#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_ExtendedDataMode_8b) || \
- ((DATA) == DCMI_ExtendedDataMode_10b) ||\
- ((DATA) == DCMI_ExtendedDataMode_12b) ||\
- ((DATA) == DCMI_ExtendedDataMode_14b))
-/**
- * @}
- */
-
-
-/** @defgroup DCMI_interrupt_sources
- * @{
- */
-#define DCMI_IT_FRAME ((uint16_t)0x0001)
-#define DCMI_IT_OVF ((uint16_t)0x0002)
-#define DCMI_IT_ERR ((uint16_t)0x0004)
-#define DCMI_IT_VSYNC ((uint16_t)0x0008)
-#define DCMI_IT_LINE ((uint16_t)0x0010)
-#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000))
-#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \
- ((IT) == DCMI_IT_OVF) || \
- ((IT) == DCMI_IT_ERR) || \
- ((IT) == DCMI_IT_VSYNC) || \
- ((IT) == DCMI_IT_LINE))
-/**
- * @}
- */
-
-
-/** @defgroup DCMI_Flags
- * @{
- */
-/**
- * @brief DCMI SR register
- */
-#define DCMI_FLAG_HSYNC ((uint16_t)0x2001)
-#define DCMI_FLAG_VSYNC ((uint16_t)0x2002)
-#define DCMI_FLAG_FNE ((uint16_t)0x2004)
-/**
- * @brief DCMI RISR register
- */
-#define DCMI_FLAG_FRAMERI ((uint16_t)0x0001)
-#define DCMI_FLAG_OVFRI ((uint16_t)0x0002)
-#define DCMI_FLAG_ERRRI ((uint16_t)0x0004)
-#define DCMI_FLAG_VSYNCRI ((uint16_t)0x0008)
-#define DCMI_FLAG_LINERI ((uint16_t)0x0010)
-/**
- * @brief DCMI MISR register
- */
-#define DCMI_FLAG_FRAMEMI ((uint16_t)0x1001)
-#define DCMI_FLAG_OVFMI ((uint16_t)0x1002)
-#define DCMI_FLAG_ERRMI ((uint16_t)0x1004)
-#define DCMI_FLAG_VSYNCMI ((uint16_t)0x1008)
-#define DCMI_FLAG_LINEMI ((uint16_t)0x1010)
-#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \
- ((FLAG) == DCMI_FLAG_VSYNC) || \
- ((FLAG) == DCMI_FLAG_FNE) || \
- ((FLAG) == DCMI_FLAG_FRAMERI) || \
- ((FLAG) == DCMI_FLAG_OVFRI) || \
- ((FLAG) == DCMI_FLAG_ERRRI) || \
- ((FLAG) == DCMI_FLAG_VSYNCRI) || \
- ((FLAG) == DCMI_FLAG_LINERI) || \
- ((FLAG) == DCMI_FLAG_FRAMEMI) || \
- ((FLAG) == DCMI_FLAG_OVFMI) || \
- ((FLAG) == DCMI_FLAG_ERRMI) || \
- ((FLAG) == DCMI_FLAG_VSYNCMI) || \
- ((FLAG) == DCMI_FLAG_LINEMI))
-
-#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the DCMI configuration to the default reset state ****/
-void DCMI_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct);
-void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct);
-void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct);
-void DCMI_CROPCmd(FunctionalState NewState);
-void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct);
-void DCMI_JPEGCmd(FunctionalState NewState);
-
-/* Image capture functions ****************************************************/
-void DCMI_Cmd(FunctionalState NewState);
-void DCMI_CaptureCmd(FunctionalState NewState);
-uint32_t DCMI_ReadData(void);
-
-/* Interrupts and flags management functions **********************************/
-void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState);
-FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG);
-void DCMI_ClearFlag(uint16_t DCMI_FLAG);
-ITStatus DCMI_GetITStatus(uint16_t DCMI_IT);
-void DCMI_ClearITPendingBit(uint16_t DCMI_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_DCMI_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_dfsdm.c b/底盘/底盘-old/底盘/Library/stm32f4xx_dfsdm.c
deleted file mode 100644
index 2c0ef00..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_dfsdm.c
+++ /dev/null
@@ -1,2201 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_dfsdm.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of Digital Filter for Sigma Delta modulator
- * (DFSDM) peripheral:
- * + Initialization functions.
- * + Configuration functions.
- * + Interrupts and flags management functions.
- *
- * @verbatim
- *
-================================================================================
- ##### How to use this driver #####
-================================================================================
- [..]
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_dfsdm.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DFSDM
- * @brief DFSDM driver modules
- * @{
- */
-#if defined(STM32F412xG) || defined(STM32F413_423xx)
-
-/* External variables --------------------------------------------------------*/
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-
-#define CHCFGR_INIT_CLEAR_MASK (uint32_t) 0xFFFE0F10
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DFSDM_Private_Functions
- * @{
- */
-
-/** @defgroup DFSDM_Group1 Initialization functions
- * @brief Initialization functions
- *
-@verbatim
- ===============================================================================
- Initialization functions
- ===============================================================================
- This section provides functions allowing to:
- - Deinitialize the DFSDM
- - Initialize DFSDM serial channels transceiver
- - Initialize DFSDM filter
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the DFSDM peripheral registers to their default reset values.
- * @param None.
- * @retval None.
- *
- */
-void DFSDM_DeInit(void)
-{
- /* Enable LPTx reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_DFSDM1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_DFSDM1, DISABLE);
-#if defined(STM32F413_423xx)
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_DFSDM2, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_DFSDM2, DISABLE);
-#endif /* STM32F413_423xx */
-}
-
-/**
- * @brief Initializes the DFSDM serial channels transceiver according to the specified
- * parameters in the DFSDM_TransceiverInit.
- * @param DFSDM_Channelx: specifies the channel to be selected.
- * This parameter can be one of the following values :
- * @arg DFSDM1_Channel0 : DFSDM 1 Channel 0
- * @arg DFSDM1_Channel1 : DFSDM 1 Channel 1
- * @arg DFSDM1_Channel2 : DFSDM 1 Channel 2
- * @arg DFSDM1_Channel3 : DFSDM 1 Channel 3
- * @arg DFSDM2_Channel0 : DFSDM 2 Channel 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel1 : DFSDM 2 Channel 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel2 : DFSDM 2 Channel 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel3 : DFSDM 2 Channel 3 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel4 : DFSDM 2 Channel 4 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel5 : DFSDM 2 Channel 5 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel6 : DFSDM 2 Channel 6 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel7 : DFSDM 2 Channel 7 (available only for STM32F413_423xx devices)
- * @param DFSDM_TransceiverInitStruct: pointer to a DFSDM_TransceiverInitTypeDef structure
- * that contains the configuration information for the specified channel.
- * @retval None
- * @note It is mandatory to disable the selected channel to use this function.
- */
-void DFSDM_TransceiverInit(DFSDM_Channel_TypeDef* DFSDM_Channelx, DFSDM_TransceiverInitTypeDef* DFSDM_TransceiverInitStruct)
-{
- uint32_t tmpreg1 = 0;
- uint32_t tmpreg2 = 0;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_CHANNEL(DFSDM_Channelx));
- assert_param(IS_DFSDM_INTERFACE(DFSDM_TransceiverInitStruct->DFSDM_Interface));
- assert_param(IS_DFSDM_Input_MODE(DFSDM_TransceiverInitStruct->DFSDM_Input));
- assert_param(IS_DFSDM_Redirection_STATE(DFSDM_TransceiverInitStruct->DFSDM_Redirection));
- assert_param(IS_DFSDM_PACK_MODE(DFSDM_TransceiverInitStruct->DFSDM_PackingMode));
- assert_param(IS_DFSDM_CLOCK(DFSDM_TransceiverInitStruct->DFSDM_Clock));
- assert_param(IS_DFSDM_DATA_RIGHT_BIT_SHIFT(DFSDM_TransceiverInitStruct->DFSDM_DataRightShift));
- assert_param(IS_DFSDM_OFFSET(DFSDM_TransceiverInitStruct->DFSDM_Offset));
- assert_param(IS_DFSDM_CLK_DETECTOR_STATE(DFSDM_TransceiverInitStruct->DFSDM_CLKAbsenceDetector));
- assert_param(IS_DFSDM_SC_DETECTOR_STATE(DFSDM_TransceiverInitStruct->DFSDM_ShortCircuitDetector));
-
- /* Get the DFSDM Channelx CHCFGR1 value */
- tmpreg1 = DFSDM_Channelx->CHCFGR1;
-
- /* Clear SITP, CKABEN, SCDEN and SPICKSEL bits */
- tmpreg1 &= CHCFGR_INIT_CLEAR_MASK;
-
- /* Set or Reset SITP bits according to DFSDM_Interface value */
- /* Set or Reset SPICKSEL bits according to DFSDM_Clock value */
- /* Set or Reset DATMPX bits according to DFSDM_InputMode value */
- /* Set or Reset CHINSEL bits according to DFSDM_Redirection value */
- /* Set or Reset DATPACK bits according to DFSDM_PackingMode value */
- /* Set or Reset CKABEN bit according to DFSDM_CLKAbsenceDetector value */
- /* Set or Reset SCDEN bit according to DFSDM_ShortCircuitDetector value */
- tmpreg1 |= (DFSDM_TransceiverInitStruct->DFSDM_Interface |
- DFSDM_TransceiverInitStruct->DFSDM_Clock |
- DFSDM_TransceiverInitStruct->DFSDM_Input |
- DFSDM_TransceiverInitStruct->DFSDM_Redirection |
- DFSDM_TransceiverInitStruct->DFSDM_PackingMode |
- DFSDM_TransceiverInitStruct->DFSDM_CLKAbsenceDetector |
- DFSDM_TransceiverInitStruct->DFSDM_ShortCircuitDetector);
-
- /* Write to DFSDM Channelx CHCFGR1R */
- DFSDM_Channelx->CHCFGR1 = tmpreg1;
-
- /* Get the DFSDM Channelx CHCFGR2 value */
- tmpreg2 = DFSDM_Channelx->CHCFGR2;
-
- /* Clear DTRBS and OFFSET bits */
- tmpreg2 &= ~(DFSDM_CHCFGR2_DTRBS | DFSDM_CHCFGR2_OFFSET);
-
- /* Set or Reset DTRBS bits according to DFSDM_DataRightShift value */
- /* Set or Reset OFFSET bits according to DFSDM_Offset value */
- tmpreg2 |= (((DFSDM_TransceiverInitStruct->DFSDM_DataRightShift) <<3 ) |
- ((DFSDM_TransceiverInitStruct->DFSDM_Offset) <<8 ));
-
- /* Write to DFSDM Channelx CHCFGR1R */
- DFSDM_Channelx->CHCFGR2 = tmpreg2;
-}
-
-/**
- * @brief Fills each DFSDM_TransceiverInitStruct member with its default value.
- * @param DFSDM_TransceiverInitStruct : pointer to a DFSDM_TransceiverInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void DFSDM_TransceiverStructInit(DFSDM_TransceiverInitTypeDef* DFSDM_TransceiverInitStruct)
-{
- /* SPI with rising edge to strobe data is selected as default serial interface */
- DFSDM_TransceiverInitStruct->DFSDM_Interface = DFSDM_Interface_SPI_FallingEdge;
-
- /* Clock coming from internal DFSDM_CKOUT output is selected as default serial clock */
- DFSDM_TransceiverInitStruct->DFSDM_Clock = DFSDM_Clock_Internal;
-
- /* No data right bit-shift is selected as default data right bit-shift */
- DFSDM_TransceiverInitStruct->DFSDM_DataRightShift = 0x0;
-
- /* No offset is selected as default offset */
- DFSDM_TransceiverInitStruct->DFSDM_Offset = 0x0;
-
- /* Clock Absence Detector is Enabled as default state */
- DFSDM_TransceiverInitStruct->DFSDM_CLKAbsenceDetector = DFSDM_CLKAbsenceDetector_Enable;
-}
-
-/**
- * @brief Initializes the DFSDMx Filter according to the specified
- * parameters in the DFSDM_FilterInitStruct.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @param DFSDM_FilterInitStruct: pointer to a DFSDM_FilterInitTypeDef structure
- * that contains the configuration information for the specified filter.
- * @retval None
- *
- * @note It is mandatory to disable the selected filter to use this function.
- */
-void DFSDM_FilterInit(DFSDM_Filter_TypeDef* DFSDMx, DFSDM_FilterInitTypeDef* DFSDM_FilterInitStruct)
-{
- uint32_t tmpreg1 = 0;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
- assert_param(IS_DFSDM_SINC_ORDER(DFSDM_FilterInitStruct->DFSDM_SincOrder));
- assert_param(IS_DFSDM_SINC_OVRSMPL_RATIO(DFSDM_FilterInitStruct->DFSDM_FilterOversamplingRatio));
- assert_param(IS_DFSDM_INTG_OVRSMPL_RATIO(DFSDM_FilterInitStruct->DFSDM_IntegratorOversamplingRatio));
-
- /* Get the DFSDMx FCR value */
- tmpreg1 = DFSDMx->FLTFCR;
-
- /* Clear FORD, FOSR and IOSR bits */
- tmpreg1 &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);
-
- /* Set or Reset FORD bits according to DFSDM_SincOrder value */
- /* Set or Reset FOSR bits according to DFSDM_FilterOversamplingRatio value */
- /* Set or Reset IOSR bits according to DFSDM_IntegratorOversamplingRatio value */
- tmpreg1 |= (DFSDM_FilterInitStruct->DFSDM_SincOrder |
- ((DFSDM_FilterInitStruct->DFSDM_FilterOversamplingRatio -1) << 16) |
- (DFSDM_FilterInitStruct->DFSDM_IntegratorOversamplingRatio -1));
-
- /* Write to DFSDMx FCR */
- DFSDMx->FLTFCR = tmpreg1;
-}
-
-/**
- * @brief Fills each DFSDM_FilterInitStruct member with its default value.
- * @param DFSDM_FilterInitStruct: pointer to a DFSDM_FilterInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void DFSDM_FilterStructInit(DFSDM_FilterInitTypeDef* DFSDM_FilterInitStruct)
-{
- /* Order = 3 is selected as default sinc order */
- DFSDM_FilterInitStruct->DFSDM_SincOrder = DFSDM_SincOrder_Sinc3;
-
- /* Ratio = 64 is selected as default oversampling ratio */
- DFSDM_FilterInitStruct->DFSDM_FilterOversamplingRatio = 64 ;
-
- /* Ratio = 4 is selected as default integrator oversampling ratio */
- DFSDM_FilterInitStruct->DFSDM_IntegratorOversamplingRatio = 4;
-}
-
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Group2 Configuration functions
- * @brief Configuration functions
- *
-@verbatim
- ===============================================================================
- Configuration functions
- ===============================================================================
- This section provides functions allowing to configure DFSDM:
- - Enable/Disable (DFSDM peripheral, Channel, Filter)
- - Configure Clock output
- - Configure Injected/Regular channels for Conversion
- - Configure short circuit detector
- - Configure Analog watchdog filter
-
-@endverbatim
- * @{
- */
-
-#if defined(STM32F412xG)
-/**
- * @brief Enables or disables the DFSDM peripheral.
- * @param NewState: new state of the DFSDM interface.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DFSDM_Command(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the ENABLE bit */
- DFSDM1_Channel0 -> CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
- }
- else
- {
- /* Reset the ENABLE bit */
- DFSDM1_Channel0 -> CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
- }
-}
-#endif /* STM32F412xG */
-
-#if defined(STM32F413_423xx)
-/**
- * @brief Enables or disables the DFSDM peripheral.
- * @param Instance: select the instance of DFSDM
- * This parameter can be: 1 or 2.
- * @param NewState: new state of the DFSDM interface.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DFSDM_Cmd(uint32_t Instance, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(Instance == 1)
- {
- if (NewState != DISABLE)
- {
- /* Set the ENABLE bit */
- DFSDM1_Channel0 -> CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
- }
- else
- {
- /* Reset the ENABLE bit */
- DFSDM1_Channel0 -> CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
- }
- }
- else /* DFSDM2 */
- {
- if (NewState != DISABLE)
- {
- /* Set the ENABLE bit */
- DFSDM2_Channel0 -> CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
- }
- else
- {
- /* Reset the ENABLE bit */
- DFSDM2_Channel0 -> CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
- }
- }
-}
-#endif /* STM32F413_423xx */
-/**
- * @brief Enables or disables the specified DFSDM serial channelx.
- * @param DFSDM_Channelx: specifies the channel to be selected.
- * This parameter can be one of the following values :
- * @arg DFSDM1_Channel0 : DFSDM 1 Channel 0
- * @arg DFSDM1_Channel1 : DFSDM 1 Channel 1
- * @arg DFSDM1_Channel2 : DFSDM 1 Channel 2
- * @arg DFSDM1_Channel3 : DFSDM 1 Channel 3
- * @arg DFSDM2_Channel0 : DFSDM 2 Channel 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel1 : DFSDM 2 Channel 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel2 : DFSDM 2 Channel 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel3 : DFSDM 2 Channel 3 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel4 : DFSDM 2 Channel 4 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel5 : DFSDM 2 Channel 5 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel6 : DFSDM 2 Channel 6 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel7 : DFSDM 2 Channel 7 (available only for STM32F413_423xx devices)
- * @param NewState: new state of the DFSDM serial channelx .
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DFSDM_ChannelCmd(DFSDM_Channel_TypeDef* DFSDM_Channelx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_CHANNEL(DFSDM_Channelx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the ENABLE bit */
- DFSDM_Channelx->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
- }
- else
- {
- /* Reset the ENABLE bit */
- DFSDM_Channelx->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);
- }
-}
-
-/**
- * @brief Enables or disables the specified DFSDMx Filter.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @param NewState: new state of the selected DFSDM module.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DFSDM_FilterCmd(DFSDM_Filter_TypeDef* DFSDMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the ENABLE bit */
- DFSDMx->FLTCR1 |= DFSDM_FLTCR1_DFEN;
- }
- else
- {
- /* Reset the ENABLE bit */
- DFSDMx->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
- }
-}
-
-#if defined(STM32F412xG)
-/**
- * @brief Configures the Output serial clock divider.
- * @param DFSDM_ClkOutDivision: Defines the divider for the output serial clock
- * This parameter can be a value between 1 and 256.
- * @retval None
- * @note The output serial clock is stopped if the divider =1.
- * By default the serial output clock is stopped.
- */
-void DFSDM_ConfigClkOutputDivider(uint32_t DFSDM_ClkOutDivision)
-{
- uint32_t tmpreg1 = 0;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_CLOCK_OUT_DIVIDER(DFSDM_ClkOutDivision));
-
- /* Get the DFSDM_Channel0 CHCFGR1 value */
- tmpreg1 = DFSDM1_Channel0 -> CHCFGR1;
-
- /* Clear the CKOUTDIV bits */
- tmpreg1 &= (uint32_t)(~DFSDM_CHCFGR1_CKOUTDIV);
-
- /* Set or Reset the CKOUTDIV bits */
- tmpreg1 |= (uint32_t)((DFSDM_ClkOutDivision - 1) << 16);
-
- /* Write to DFSDM Channel0 CHCFGR1 */
- DFSDM1_Channel0 -> CHCFGR1 = tmpreg1;
-}
-
-/**
- * @brief Configures the Output serial clock source.
- * @param DFSDM_ClkOutSource: Defines the divider for the output serial clock
- * This parameter can be a value of:
- * @arg DFSDM_ClkOutSource_SysClock
- * @arg DFSDM_ClkOutSource_AudioClock
- * @retval None
- */
-void DFSDM_ConfigClkOutputSource(uint32_t DFSDM_ClkOutSource)
-{
- uint32_t tmpreg1 = 0;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_CLOCK_OUT_SOURCE(DFSDM_ClkOutSource));
-
- /* Get the DFSDM_Channel0 CHCFGR1 value */
- tmpreg1 = DFSDM1_Channel0 -> CHCFGR1;
-
- /* Clear the CKOUTSRC bit */
- tmpreg1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
-
- /* Set or Reset the CKOUTSRC bit */
- tmpreg1 |= DFSDM_ClkOutSource;
-
- /* Write to DFSDM Channel0 CHCFGR1 */
- DFSDM1_Channel0 -> CHCFGR1 = tmpreg1;
-}
-#endif /* STM32F412xG */
-#if defined(STM32F413_423xx)
-/**
- * @brief Configures the Output serial clock divider.
- * @param Instance: select the instance of DFSDM
- * This parameter can be: 1 or 2.
- * @param DFSDM_ClkOutDivision: Defines the divider for the output serial clock
- * This parameter can be a value between 1 and 256.
- * @retval None
- * @note The output serial clock is stopped if the divider =1.
- * By default the serial output clock is stopped.
- */
-void DFSDM_ConfigClkOutputDivider(uint32_t Instance, uint32_t DFSDM_ClkOutDivision)
-{
- uint32_t tmpreg1 = 0;
-
- if(Instance == 1)
- {
- /* Check the parameters */
- assert_param(IS_DFSDM_CLOCK_OUT_DIVIDER(DFSDM_ClkOutDivision));
-
- /* Get the DFSDM_Channel0 CHCFGR1 value */
- tmpreg1 = DFSDM1_Channel0 -> CHCFGR1;
-
- /* Clear the CKOUTDIV bits */
- tmpreg1 &= (uint32_t)(~DFSDM_CHCFGR1_CKOUTDIV);
-
- /* Set or Reset the CKOUTDIV bits */
- tmpreg1 |= (uint32_t)((DFSDM_ClkOutDivision - 1) << 16);
-
- /* Write to DFSDM Channel0 CHCFGR1 */
- DFSDM1_Channel0 -> CHCFGR1 = tmpreg1;
- }
- else /* DFSDM2 */
- {
- /* Check the parameters */
- assert_param(IS_DFSDM_CLOCK_OUT_DIVIDER(DFSDM_ClkOutDivision));
-
- /* Get the DFSDM_Channel0 CHCFGR1 value */
- tmpreg1 = DFSDM2_Channel0 -> CHCFGR1;
-
- /* Clear the CKOUTDIV bits */
- tmpreg1 &= (uint32_t)(~DFSDM_CHCFGR1_CKOUTDIV);
-
- /* Set or Reset the CKOUTDIV bits */
- tmpreg1 |= (uint32_t)((DFSDM_ClkOutDivision - 1) << 16);
-
- /* Write to DFSDM Channel0 CHCFGR1 */
- DFSDM2_Channel0 -> CHCFGR1 = tmpreg1;
- }
-}
-
-/**
- * @brief Configures the Output serial clock source.
- * @param Instance: select the instance of DFSDM
- * This parameter can be: 1 or 2.
- * @param DFSDM_ClkOutSource: Defines the divider for the output serial clock
- * This parameter can be a value of:
- * @arg DFSDM_ClkOutSource_SysClock
- * @arg DFSDM_ClkOutSource_AudioClock
- * @retval None
- */
-void DFSDM_ConfigClkOutputSource(uint32_t Instance, uint32_t DFSDM_ClkOutSource)
-{
- uint32_t tmpreg1 = 0;
-
- if(Instance == 1)
- {
- /* Check the parameters */
- assert_param(IS_DFSDM_CLOCK_OUT_SOURCE(DFSDM_ClkOutSource));
-
- /* Get the DFSDM_Channel0 CHCFGR1 value */
- tmpreg1 = DFSDM1_Channel0 -> CHCFGR1;
-
- /* Clear the CKOUTSRC bit */
- tmpreg1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
-
- /* Set or Reset the CKOUTSRC bit */
- tmpreg1 |= DFSDM_ClkOutSource;
-
- /* Write to DFSDM Channel0 CHCFGR1 */
- DFSDM1_Channel0 -> CHCFGR1 = tmpreg1;
- }
- else /* DFSDM2 */
- {
- /* Check the parameters */
- assert_param(IS_DFSDM_CLOCK_OUT_SOURCE(DFSDM_ClkOutSource));
-
- /* Get the DFSDM_Channel0 CHCFGR1 value */
- tmpreg1 = DFSDM2_Channel0 -> CHCFGR1;
-
- /* Clear the CKOUTSRC bit */
- tmpreg1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
-
- /* Set or Reset the CKOUTSRC bit */
- tmpreg1 |= DFSDM_ClkOutSource;
-
- /* Write to DFSDM Channel0 CHCFGR1 */
- DFSDM2_Channel0 -> CHCFGR1 = tmpreg1;
- }
-}
-#endif /* STM32F413_423xx */
-/**
- * @brief Enables or disables the specified Break_i siganl to the specified DFSDM_Channelx.
- * @param DFSDM_Channelx: specifies the channel to be selected.
- * This parameter can be one of the following values :
- * @arg DFSDM1_Channel0 : DFSDM 1 Channel 0
- * @arg DFSDM1_Channel1 : DFSDM 1 Channel 1
- * @arg DFSDM1_Channel2 : DFSDM 1 Channel 2
- * @arg DFSDM1_Channel3 : DFSDM 1 Channel 3
- * @arg DFSDM2_Channel0 : DFSDM 2 Channel 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel1 : DFSDM 2 Channel 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel2 : DFSDM 2 Channel 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel3 : DFSDM 2 Channel 3 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel4 : DFSDM 2 Channel 4 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel5 : DFSDM 2 Channel 5 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel6 : DFSDM 2 Channel 6 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel7 : DFSDM 2 Channel 7 (available only for STM32F413_423xx devices)
- * @param DFSDM_SCDBreak_i: where i can be a value from 0 to 3 to select the specified Break signal.
- * @param NewState: new state of the selected DFSDM_SCDBreak_i.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DFSDM_ConfigBRKAnalogWatchDog(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDBreak_i, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_CHANNEL(DFSDM_Channelx));
- assert_param(IS_DFSDM_SCD_BREAK_SIGNAL(DFSDM_SCDBreak_i));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the BKSCD[i] bit */
- DFSDM_Channelx -> CHAWSCDR |= DFSDM_SCDBreak_i;
- }
- else
- {
- /* Reset the BKSCD[i] bit */
- DFSDM_Channelx -> CHAWSCDR &= ~(DFSDM_SCDBreak_i);
- }
-}
-
-/**
- * @brief Enables or disables the specified Break_i siganl to the specified DFSDM_Channelx.
- * @param DFSDM_Channelx: specifies the channel to be selected.
- * This parameter can be one of the following values :
- * @arg DFSDM1_Channel0 : DFSDM 1 Channel 0
- * @arg DFSDM1_Channel1 : DFSDM 1 Channel 1
- * @arg DFSDM1_Channel2 : DFSDM 1 Channel 2
- * @arg DFSDM1_Channel3 : DFSDM 1 Channel 3
- * @arg DFSDM2_Channel0 : DFSDM 2 Channel 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel1 : DFSDM 2 Channel 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel2 : DFSDM 2 Channel 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel3 : DFSDM 2 Channel 3 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel4 : DFSDM 2 Channel 4 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel5 : DFSDM 2 Channel 5 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel6 : DFSDM 2 Channel 6 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel7 : DFSDM 2 Channel 7 (available only for STM32F413_423xx devices)
- * @param DFSDM_SCDBreak_i: where i can be a value from 0 to 3 to select the specified Break signal.
- * @param NewState: new state of the selected DFSDM_SCDBreak_i.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DFSDM_ConfigBRKShortCircuitDetector(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDBreak_i, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_CHANNEL(DFSDM_Channelx));
- assert_param(IS_DFSDM_SCD_BREAK_SIGNAL(DFSDM_SCDBreak_i));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the BKSCD[i] bit */
- DFSDM_Channelx -> CHAWSCDR |= DFSDM_SCDBreak_i;
- }
- else
- {
- /* Reset the BKSCD[i] bit */
- DFSDM_Channelx -> CHAWSCDR &= ~(DFSDM_SCDBreak_i);
- }
-}
-
-/**
- * @brief Defines the threshold counter for the short circuit detector for the selected DFSDM_Channelx.
- * @param DFSDM_Channelx: specifies the channel to be selected.
- * This parameter can be one of the following values :
- * @arg DFSDM1_Channel0 : DFSDM 1 Channel 0
- * @arg DFSDM1_Channel1 : DFSDM 1 Channel 1
- * @arg DFSDM1_Channel2 : DFSDM 1 Channel 2
- * @arg DFSDM1_Channel3 : DFSDM 1 Channel 3
- * @arg DFSDM2_Channel0 : DFSDM 2 Channel 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel1 : DFSDM 2 Channel 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel2 : DFSDM 2 Channel 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel3 : DFSDM 2 Channel 3 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel4 : DFSDM 2 Channel 4 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel5 : DFSDM 2 Channel 5 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel6 : DFSDM 2 Channel 6 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel7 : DFSDM 2 Channel 7 (available only for STM32F413_423xx devices)
- * @param DFSDM_SCDThreshold: The threshold counter, this parameter can be a value between 0 and 255.
- * @retval None
- */
-void DFSDM_ConfigShortCircuitThreshold(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDThreshold)
-{
- uint32_t tmpreg1 = 0;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_CHANNEL(DFSDM_Channelx));
- assert_param(IS_DFSDM_CSD_THRESHOLD_VALUE(DFSDM_SCDThreshold));
-
- /* Get the DFSDM_Channelx AWSCDR value */
- tmpreg1 = DFSDM_Channelx -> CHAWSCDR;
-
- /* Clear the SCDT bits */
- tmpreg1 &= ~(DFSDM_CHAWSCDR_SCDT);
-
- /* Set or Reset the SCDT bits */
- tmpreg1 |= DFSDM_SCDThreshold;
-
- /* Write to DFSDM Channelx AWSCDR */
- DFSDM_Channelx -> CHAWSCDR = tmpreg1;
-}
-
-/**
- * @brief Selects the channel to be guarded by the Analog watchdog for the selected DFSDMx,
- * and select if the fast analog watchdog is enabled or not.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @param DFSDM_AWDChannelx: where x can be a value from 0 to 7 to select the DFSDM Channel.
- * @param DFSDM_AWDFastMode: The analog watchdog fast mode.
- * This parameter can be a value of @ref DFSDM_AWD_Fast_Mode_Selection.
- * @retval None
- */
-void DFSDM_ConfigAnalogWatchdog(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint32_t DFSDM_AWDFastMode)
-{
- uint32_t tmpreg1 = 0;
- uint32_t tmpreg2 = 0;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
- assert_param(IS_DFSDM_AWD_CHANNEL(DFSDM_AWDChannelx));
- assert_param(IS_DFSDM_AWD_MODE(DFSDM_AWDFastMode));
-
- /* Get the DFSDMx CR2 value */
- tmpreg1 = DFSDMx -> FLTCR2;
-
- /* Clear the AWDCH bits */
- tmpreg1 &= ~(DFSDM_FLTCR2_AWDCH);
-
- /* Set or Reset the AWDCH bits */
- tmpreg1 |= DFSDM_AWDChannelx;
-
- /* Write to DFSDMx CR2 Register */
- DFSDMx -> FLTCR2 |= tmpreg1;
-
- /* Get the DFSDMx CR1 value */
- tmpreg2 = DFSDMx->FLTCR1;
-
- /* Clear the AWFSEL bit */
- tmpreg2 &= ~(DFSDM_FLTCR1_AWFSEL);
-
- /* Set or Reset the AWFSEL bit */
- tmpreg2 |= DFSDM_AWDFastMode;
-
- /* Write to DFSDMx CR1 Register */
- DFSDMx->FLTCR1 = tmpreg2;
-}
-
-/**
- * @brief Selects the channel to be guarded by the Analog watchdog of the selected DFSDMx, and the mode to be used.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @param DFSDM_ExtremChannelx: where x can be a value from 0 to 7 to select the Channel to be connected
- * to the Extremes detector.
- * @retval None
- */
-void DFSDM_SelectExtremesDetectorChannel(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_ExtremChannelx)
-{
- uint32_t tmpreg1 = 0;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
- assert_param(IS_DFSDM_EXTREM_CHANNEL(DFSDM_ExtremChannelx));
-
- /* Get the DFSDMx CR2 value */
- tmpreg1 = DFSDMx -> FLTCR2;
-
- /* Clear the EXCH bits */
- tmpreg1 &= ~(DFSDM_FLTCR2_EXCH);
-
- /* Set or Reset the AWDCH bits */
- tmpreg1 |= DFSDM_ExtremChannelx;
-
- /* Write to DFSDMx CR2 Register */
- DFSDMx -> FLTCR2 = tmpreg1;
-}
-
-/**
- * @brief Returns the regular conversion data by the DFSDMx.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @retval The converted regular data.
- * @note This function returns a signed value.
- */
-int32_t DFSDM_GetRegularConversionData(DFSDM_Filter_TypeDef* DFSDMx)
-{
- uint32_t reg = 0;
- int32_t value = 0;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
-
- /* Get value of data register for regular channel */
- reg = DFSDMx -> FLTRDATAR;
-
- /* Extract conversion value */
- value = (((reg & 0xFFFFFF00) >> 8));
-
- /* Return the conversion result */
- return value;
-}
-
-/**
- * @brief Returns the injected conversion data by the DFSDMx.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @retval The converted regular data.
- * @note This function returns a signed value.
- */
-int32_t DFSDM_GetInjectedConversionData(DFSDM_Filter_TypeDef* DFSDMx)
-{
- uint32_t reg = 0;
- int32_t value = 0;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
-
- /* Get value of data register for regular channel */
- reg = DFSDMx -> FLTJDATAR;
-
- /* Extract conversion value */
- value = ((reg & 0xFFFFFF00) >> 8);
-
- /* Return the conversion result */
- return value;
-}
-
-/**
- * @brief Returns the highest value converted by the DFSDMx.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @retval The highest converted value.
- * @note This function returns a signed value.
- */
-int32_t DFSDM_GetMaxValue(DFSDM_Filter_TypeDef* DFSDMx)
-{
- int32_t value = 0;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
-
- value = ((DFSDMx -> FLTEXMAX) >> 8);
- /* Return the highest converted value */
- return value;
-}
-
-/**
- * @brief Returns the lowest value converted by the DFSDMx.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @retval The lowest converted value.
- * @note This function returns a signed value.
- */
-int32_t DFSDM_GetMinValue(DFSDM_Filter_TypeDef* DFSDMx)
-{
- int32_t value = 0;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
-
- value = ((DFSDMx -> FLTEXMIN) >> 8);
- /* Return the lowest conversion value */
- return value;
-}
-
-/**
- * @brief Returns the number of channel on which is captured the highest converted data by the DFSDMx.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @retval The highest converted value.
- */
-int32_t DFSDM_GetMaxValueChannel(DFSDM_Filter_TypeDef* DFSDMx)
-{
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
-
- /* Return the highest converted value */
- return ((DFSDMx -> FLTEXMAX) & (~DFSDM_FLTEXMAX_EXMAXCH));
-}
-
-/**
- * @brief Returns the number of channel on which is captured the lowest converted data by the DFSDMx.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @retval The lowest converted value.
- */
-int32_t DFSDM_GetMinValueChannel(DFSDM_Filter_TypeDef* DFSDMx)
-{
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
-
- /* Return the lowest converted value */
- return ((DFSDMx -> FLTEXMIN) & (~DFSDM_FLTEXMIN_EXMINCH));
-}
-
-/**
- * @brief Returns the conversion time (in 28-bit timer unit) for DFSDMx.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @retval Conversion time.
- */
-uint32_t DFSDM_GetConversionTime(DFSDM_Filter_TypeDef* DFSDMx)
-{
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
-
- /* Return the lowest converted value */
- return ((DFSDMx -> FLTCNVTIMR >> 4) & 0x0FFFFFFF);
-}
-
-/**
- * @brief Configures Sinc Filter for the Analog watchdog by setting
- * the Sinc filter order and the Oversampling ratio for the specified DFSDM_Channelx.
- * @param DFSDM_Channelx: specifies the channel to be selected.
- * This parameter can be one of the following values :
- * @arg DFSDM1_Channel0 : DFSDM 1 Channel 0
- * @arg DFSDM1_Channel1 : DFSDM 1 Channel 1
- * @arg DFSDM1_Channel2 : DFSDM 1 Channel 2
- * @arg DFSDM1_Channel3 : DFSDM 1 Channel 3
- * @arg DFSDM2_Channel0 : DFSDM 2 Channel 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel1 : DFSDM 2 Channel 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel2 : DFSDM 2 Channel 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel3 : DFSDM 2 Channel 3 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel4 : DFSDM 2 Channel 4 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel5 : DFSDM 2 Channel 5 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel6 : DFSDM 2 Channel 6 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel7 : DFSDM 2 Channel 7 (available only for STM32F413_423xx devices)
- * @param DFSDM_AWDSincOrder: The Sinc Filter order this parameter can be a value of @ref DFSDM_AWD_Sinc_Order.
- * @param DFSDM_AWDSincOverSampleRatio: The Filter Oversampling ratio, this parameter can be a value between 1 and 32.
- * @retval None
- */
-void DFSDM_ConfigAWDFilter(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_AWDSincOrder, uint32_t DFSDM_AWDSincOverSampleRatio)
-{
- uint32_t tmpreg1 = 0;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_CHANNEL(DFSDM_Channelx));
- assert_param(IS_DFSDM_AWD_SINC_ORDER(DFSDM_AWDSincOrder));
- assert_param(IS_DFSDM_AWD_OVRSMPL_RATIO(DFSDM_AWDSincOverSampleRatio));
-
- /* Get the DFSDM_Channelx CHAWSCDR value */
- tmpreg1 = DFSDM_Channelx -> CHAWSCDR;
-
- /* Clear the FORD and FOSR bits */
- tmpreg1 &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
-
- /* Set or Reset the SCDT bits */
- tmpreg1 |= (DFSDM_AWDSincOrder | ((DFSDM_AWDSincOverSampleRatio -1) << 16)) ;
-
- /* Write to DFSDM Channelx CHAWSCDR */
- DFSDM_Channelx -> CHAWSCDR = tmpreg1;
-}
-
-/**
- * @brief Returns the last Analog Watchdog Filter conversion result data for channelx.
- * @param DFSDM_Channelx: specifies the channel to be selected.
- * This parameter can be one of the following values :
- * @arg DFSDM1_Channel0 : DFSDM 1 Channel 0
- * @arg DFSDM1_Channel1 : DFSDM 1 Channel 1
- * @arg DFSDM1_Channel2 : DFSDM 1 Channel 2
- * @arg DFSDM1_Channel3 : DFSDM 1 Channel 3
- * @arg DFSDM2_Channel0 : DFSDM 2 Channel 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel1 : DFSDM 2 Channel 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel2 : DFSDM 2 Channel 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel3 : DFSDM 2 Channel 3 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel4 : DFSDM 2 Channel 4 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel5 : DFSDM 2 Channel 5 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel6 : DFSDM 2 Channel 6 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_Channel7 : DFSDM 2 Channel 7 (available only for STM32F413_423xx devices)
- * @retval The Data conversion value.
- */
-uint32_t DFSDM_GetAWDConversionValue(DFSDM_Channel_TypeDef* DFSDM_Channelx)
-{
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_CHANNEL(DFSDM_Channelx));
-
- /* Return the last analog watchdog filter conversion value */
- return DFSDM_Channelx -> CHWDATAR;
-}
-
-
-/**
- * @brief Configures the High Threshold and the Low threshold for the Analog watchdog of the selected DFSDMx.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @param DFSDM_HighThreshold: High threshold value. This parameter can be value between 0 and 0xFFFFFF.
- * @param DFSDM_LowThreshold: Low threshold value. This parameter can be value between 0 and 0xFFFFFF.
- * @retval None.
- * @note In case of channels transceivers monitoring (Analog Watchdog fast mode Enabled)),
- * only the higher 16 bits define the 16-bit threshold compared with analog watchdog filter output.
- */
-
-void DFSDM_SetAWDThreshold(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_HighThreshold, uint32_t DFSDM_LowThreshold)
-{
- uint32_t tmpreg1 = 0;
- uint32_t tmpreg2 = 0;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_HIGH_THRESHOLD(DFSDM_HighThreshold));
- assert_param(IS_DFSDM_LOW_THRESHOLD(DFSDM_LowThreshold));
-
- /* Get the DFSDMx AWHTR value */
- tmpreg1 = DFSDMx -> FLTAWHTR;
-
- /* Clear the AWHT bits */
- tmpreg1 &= ~(DFSDM_FLTAWHTR_AWHT);
-
- /* Set or Reset the AWHT bits */
- tmpreg1 |= (DFSDM_HighThreshold << 8 );
-
- /* Write to DFSDMx AWHTR Register */
- DFSDMx -> FLTAWHTR = tmpreg1;
-
- /* Get the DFSDMx AWLTR value */
- tmpreg2 = DFSDMx -> FLTAWLTR;
-
- /* Clear the AWLTR bits */
- tmpreg2 &= ~(DFSDM_FLTAWLTR_AWLT);
-
- /* Set or Reset the AWLTR bits */
- tmpreg2 |= (DFSDM_LowThreshold << 8 );
-
- /* Write to DFSDMx AWLTR Register */
- DFSDMx -> FLTAWLTR = tmpreg2;
-}
-
-/**
- * @brief Selects the injected channel for the selected DFSDMx.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @param DFSDM_InjectedChannelx: where x can be a value from 0 to 7 to select the Channel to be configuraed as
- * injected channel.
- * @retval None
- * @note User can select up to 8 channels.
- */
-void DFSDM_SelectInjectedChannel(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_InjectedChannelx)
-{
- uint32_t tmpreg1 = 0;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
- assert_param(IS_DFSDM_INJECT_CHANNEL(DFSDM_InjectedChannelx));
-
- /* Get the DFSDMx JCHGR value */
- tmpreg1 = DFSDMx -> FLTJCHGR;
-
- /* Clear the JCHGR bits */
- tmpreg1 &= ~(DFSDM_FLTJCHGR_JCHG);
-
- /* Set or Reset the JCHGR bits */
- tmpreg1 |= DFSDM_InjectedChannelx;
-
- /* Write to DFSDMx JCHGR Register */
- DFSDMx -> FLTJCHGR |= tmpreg1;
-}
-
-/**
- * @brief Selects the regular channel for the selected DFSDMx.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @param DFSDM_RegularChannelx: where x can be a value from 0 to 7 to select the Channel to be configurated as
- * regular channel.
- * @retval None
- * @note User can select only one channel.
- */
-void DFSDM_SelectRegularChannel(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_RegularChannelx)
-{
- uint32_t tmpreg1 = 0;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
- assert_param(IS_DFSDM_REGULAR_CHANNEL(DFSDM_RegularChannelx));
-
- /* Get the DFSDMx CR1 value */
- tmpreg1 = DFSDMx -> FLTCR1;
-
- /* Clear the RCH bits */
- tmpreg1 &= ~(DFSDM_FLTCR1_RCH);
-
- /* Set or Reset the RCH bits */
- tmpreg1 |= DFSDM_RegularChannelx;
-
- /* Write to DFSDMx CR1 Register */
- DFSDMx -> FLTCR1 = tmpreg1;
-}
-
-/**
- * @brief Starts a software start for the injected group of channels of the selected DFSDMx.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @retval None
- */
-void DFSDM_StartSoftwareInjectedConversion(DFSDM_Filter_TypeDef* DFSDMx)
-{
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
-
- /* Write 1 to DFSDMx CR1 RSWSTAR bit */
- DFSDMx -> FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
-}
-
-/**
- * @brief Starts a software start of the regular channel of the selected DFSDMx.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @retval None
- */
-void DFSDM_StartSoftwareRegularConversion(DFSDM_Filter_TypeDef* DFSDMx)
-{
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
-
- /* Write 1 to DFSDMx CR1 RSWSTAR bit */
- DFSDMx -> FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
-}
-
-/**
- * @brief Selects the Trigger signal to launch the injected conversions of the selected DFSDMx.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @param DFSDM_InjectedTrigger: the trigger signal.
- * This parameter can be a value of: @ref DFSDM_Injected_Trigger_signal
- * @param DFSDM_TriggerEdge: the edge of the selected trigger
- * This parameter can be a value of: @ref DFSDM_Trigger_Edge_selection
- * @retval None.
- * @note This function can be used only when the filter is disabled, use DFSDM_FilterCmd()
- * to disable the filter.
- */
-void DFSDM_ConfigInjectedTrigger(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_Trigger, uint32_t DFSDM_TriggerEdge)
-{
- uint32_t tmpreg1 = 0;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
-
- if (DFSDMx == DFSDM0)
- {
- assert_param(IS_DFSDM0_INJ_TRIGGER(DFSDM_Trigger));
- }
- else
- {
- assert_param(IS_DFSDM1_INJ_TRIGGER(DFSDM_Trigger));
- }
-
- assert_param(IS_DFSDM_TRIGGER_EDGE(DFSDM_TriggerEdge));
-
- /* Get the DFSDMx CR1 value */
- tmpreg1 = DFSDMx -> FLTCR1;
-
- /* Clear the JEXTSEL & JEXTEN bits */
- tmpreg1 &= ~(DFSDM_FLTCR1_JEXTSEL | DFSDM_FLTCR1_JEXTEN);
-
- /* Set or Reset the JEXTSEL & JEXTEN bits */
- tmpreg1 |= (DFSDM_Trigger | DFSDM_TriggerEdge);
-
- /* Write to DFSDMx CR1 Register */
- DFSDMx -> FLTCR1 = tmpreg1;
-}
-
-/**
- * @brief Starts an injected conversion synchronously when in DFSDM0
- * an injected conversion started by software.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @retval None
- * @note This function can be used only when the filter is disabled, use DFSDM_FilterCmd()
- * to disable the filter.
- */
-void DFSDM_SynchronousFilter0InjectedStart(DFSDM_Filter_TypeDef* DFSDMx)
-{
- /* Check the parameters */
- assert_param(IS_DFSDM_SYNC_FILTER(DFSDMx));
-
- /* Write 1 to DFSDMx CR1 JSYNC bit */
- DFSDMx -> FLTCR1 |= DFSDM_FLTCR1_JSYNC;
-}
-
-/**
- * @brief Starts a regular conversion synchronously when in DFSDM0
- * a regular conversion started by software.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @retval None
- * @note This function can be used only when the filter is disabled, use DFSDM_FilterCmd()
- * to disable the filter.
- */
-void DFSDM_SynchronousFilter0RegularStart(DFSDM_Filter_TypeDef* DFSDMx)
-{
- /* Check the parameters */
- assert_param(IS_DFSDM_SYNC_FILTER(DFSDMx));
-
- /* Write 1 to DFSDMx CR1 RSYNC bit */
- DFSDMx -> FLTCR1 |= DFSDM_FLTCR1_RSYNC;
-}
-
-/**
- * @brief Enables or Disables the continue mode for Regular conversion for the selected filter DFSDMx.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @param NewState: new state of the Continuous mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DFSDM_RegularContinuousModeCmd(DFSDM_Filter_TypeDef* DFSDMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the RCONT bit */
- DFSDMx -> FLTCR1 |= DFSDM_FLTCR1_RCONT;
- }
- else
- {
- /* Disable the RCONT bit */
- DFSDMx -> FLTCR1 &= ~(DFSDM_FLTCR1_RCONT);
- }
-}
-
-/**
- * @brief Enables or Disables the Fast mode for the selected filter DFSDMx.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @param NewState: new state of the Fast mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- * @note If just a single channel is selected in continuous mode (either by executing a regular
- * conversion or by executing a injected conversion with only one channel selected),
- * the sampling rate can be increased several times by enabling the fast mode.
- * @note This function can be used only when the filter is disabled, use DFSDM_FilterCmd()
- * to disable the filter.
- */
-void DFSDM_FastModeCmd(DFSDM_Filter_TypeDef* DFSDMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the FAST bit */
- DFSDMx -> FLTCR1 |= DFSDM_FLTCR1_FAST;
- }
- else
- {
- /* Disable the FAST bit */
- DFSDMx -> FLTCR1 &= ~(DFSDM_FLTCR1_FAST);
- }
-}
-
-/**
- * @brief Selects the injected conversions mode for the selected DFSDMx.
- * Injected conversions can operates in Single mode or Scan mode.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @param DFSDM_InjectConvMode: The injected conversion mode, this parameter can be:
- * @arg DFSDM_InjectConvMode_Single
- * @arg DFSDM_InjectConvMode_Scan
- * @retval None.
- * @note This function can be used only when the filter is disabled, use DFSDM_FilterCmd()
- * to disable the filter.
- */
-void DFSDM_SelectInjectedConversionMode(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_InjectConvMode)
-{
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
- assert_param(IS_DFSDM_INJ_CONV_MODE(DFSDM_InjectConvMode));
-
- /* Clear the JSCAN bit */
- DFSDMx -> FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN);
-
- /* Write to DFSDMx CR1 Register */
- DFSDMx -> FLTCR1 |= DFSDM_InjectConvMode;
-}
-
-/**
- * @brief Enables or Disables the DMA to read data for the injected channel group of the selected filter DFSDMx.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @param DFSDM_DMAConversionMode: Selects the mode to be configured for DMA read .
- * @arg DFSDM_DMAConversionMode_Regular: DMA channel Enabled/Disabled to read data for the regular conversion
- * @arg DFSDM_DMAConversionMode_Injected: DMA channel Enabled/Disabled to read data for the Injected conversion
-* @param NewState: new state of the DMA channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- * @note This function can be used only when the filter is disabled, use DFSDM_FilterCmd()
- * to disable the filter.
- */
-void DFSDM_DMATransferConfig(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_DMAConversionMode, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
- assert_param(IS_DFSDM_CONVERSION_MODE(DFSDM_DMAConversionMode));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the JDMAEN or RDMAEN bit */
- DFSDMx -> FLTCR1 |= (DFSDM_FLTCR1_JDMAEN << DFSDM_DMAConversionMode) ;
- }
- else
- {
- /* Disable the JDMAEN or RDMAEN bit */
- DFSDMx -> FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN << DFSDM_DMAConversionMode);
- }
-}
-
-/** @defgroup DFSDM_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts and flags management functions
- ===============================================================================
- This section provides functions allowing to configure the DFSDM Interrupts, get
- the status and clear flags bits.
-
- The LPT provides 7 Flags and Interrupts sources (2 flags and Interrupt sources
- are available only on LPT peripherals equipped with encoder mode interface)
-
- Flags and Interrupts sources:
- =============================
- 1. End of injected conversion.
- 2. End of regular conversion.
- 3. Injected data overrun.
- 4. Regular data overrun.
- 5. Analog watchdog.
- 6. Short circuit detector.
- 7. Channel clock absence
-
- - To enable a specific interrupt source, use "DFSDM_ITConfig",
- "DFSDM_ITClockAbsenceCmd" and "DFSDM_ITShortCircuitDetectorCmd" functions.
- - To check if an interrupt was occurred, call "DFSDM_GetITStatus","DFSDM_GetClockAbsenceITStatusfunction"
- and "DFSDM_GetGetShortCircuitITStatus" functions and read returned values.
- - To get a flag status, call the "DFSDM_GetFlagStatus" ,"DFSDM_GetClockAbsenceFlagStatus" ,"DFSDM_GetShortCircuitFlagStatus"
- and "DFSDM_GetWatchdogFlagStatus" functions and read the returned value.
- - To clear a flag or an interrupt, use DFSDM_ClearFlag,DFSDM_ClearClockAbsenceFlag,
- DFSDM_ClearShortCircuitFlag,DFSDM_ClearAnalogWatchdogFlag functions with the
- corresponding flag (interrupt).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified DFSDMx interrupts.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @param DFSDM_IT: specifies the DFSDM interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg DFSDM_IT_JEOC: End of injected conversion Interrupt source
- * @arg DFSDM_IT_REOC: End of regular conversion Interrupt source
- * @arg DFSDM_IT_JOVR: Injected data overrun Interrupt source
- * @arg DFSDM_IT_ROVR: Regular data overrun Interrupt source
- * @arg DFSDM_IT_AWD : Analog watchdog Interrupt source
- * @param NewState: new state of the DFSDM interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DFSDM_ITConfig(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_IT, FunctionalState NewState)
- {
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
- assert_param(IS_DFSDM_IT(DFSDM_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Interrupt sources */
- DFSDMx->FLTCR2 |= DFSDM_IT;
- }
- else
- {
- /* Disable the Interrupt sources */
- DFSDMx->FLTCR2 &= ~(DFSDM_IT);
- }
-}
-
-#if defined(STM32F412xG)
-/**
- * @brief Enables or disables the Clock Absence Interrupt.
- * @param NewState: new state of the interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DFSDM_ITClockAbsenceCmd(FunctionalState NewState)
- {
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Interrupt source */
- DFSDM1_0->FLTCR2 |= DFSDM_IT_CKAB;
- }
- else
- {
- /* Disable the Interrupt source */
- DFSDM1_0->FLTCR2 &= ~(DFSDM_IT_CKAB);
- }
-}
-
-/**
- * @brief Enables or disables the Short Circuit Detector Interrupt.
- * @param NewState: new state of the interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DFSDM_ITShortCircuitDetectorCmd(FunctionalState NewState)
- {
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Interrupt source */
- DFSDM1_0->FLTCR2 |= DFSDM_IT_SCD;
- }
- else
- {
- /* Disable the Interrupt source */
- DFSDM1_0->FLTCR2 &= ~(DFSDM_IT_SCD);
- }
-}
-#endif /* STM32F412xG */
-
-#if defined(STM32F413_423xx)
-/**
- * @brief Enables or disables the Clock Absence Interrupt.
- * @param Instance: select the instance of DFSDM
- * This parameter can be: 1 or 2.
- * @param NewState: new state of the interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DFSDM_ITClockAbsenceCmd(uint32_t Instance, FunctionalState NewState)
- {
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if(Instance == 1)
- {
- if (NewState != DISABLE)
- {
- /* Enable the Interrupt source */
- DFSDM1_0->FLTCR2 |= DFSDM_IT_CKAB;
- }
- else
- {
- /* Disable the Interrupt source */
- DFSDM1_0->FLTCR2 &= ~(DFSDM_IT_CKAB);
- }
- }
- else /* DFSDM2 */
- {
- if (NewState != DISABLE)
- {
- /* Enable the Interrupt source */
- DFSDM2_0->FLTCR2 |= DFSDM_IT_CKAB;
- }
- else
- {
- /* Disable the Interrupt source */
- DFSDM2_0->FLTCR2 &= ~(DFSDM_IT_CKAB);
- }
- }
-}
-
-/**
- * @brief Enables or disables the Short Circuit Detector Interrupt.
- * @param Instance: select the instance of DFSDM
- * This parameter can be: 1 or 2.
- * @param NewState: new state of the interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DFSDM_ITShortCircuitDetectorCmd(uint32_t Instance, FunctionalState NewState)
- {
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(Instance == 1)
- {
- if (NewState != DISABLE)
- {
- /* Enable the Interrupt source */
- DFSDM1_0->FLTCR2 |= DFSDM_IT_SCD;
- }
- else
- {
- /* Disable the Interrupt source */
- DFSDM1_0->FLTCR2 &= ~(DFSDM_IT_SCD);
- }
- }
- else /* DFSDM2 */
- {
- if (NewState != DISABLE)
- {
- /* Enable the Interrupt source */
- DFSDM2_0->FLTCR2 |= DFSDM_IT_SCD;
- }
- else
- {
- /* Disable the Interrupt source */
- DFSDM2_0->FLTCR2 &= ~(DFSDM_IT_SCD);
- }
- }
-
-}
-#endif /* STM32F413_423xx */
-
-/**
- * @brief Checks whether the specified DFSDM flag is set or not.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @param LPT_FLAG: specifies the flag to check.
- * This parameter can be any combination of the following values:
- * @arg DFSDM_FLAG_JEOC: End of injected conversion Flag
- * @arg DFSDM_FLAG_REOC: End of regular conversion Flag
- * @arg DFSDM_FLAG_JOVR: Injected data overrun Flag
- * @arg DFSDM_FLAG_ROVR: Regular data overrun Flag
- * @arg DFSDM_FLAG_AWD: Analog watchdog Flag
- * @arg DFSDM_FLAG_JCIP: Injected conversion in progress status
- * @arg DFSDM_FLAG_RCIP: Regular conversion in progress status
- * @retval None
- */
-FlagStatus DFSDM_GetFlagStatus(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_FLAG)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
- assert_param(IS_DFSDM_FLAG(DFSDM_FLAG));
-
- if ((DFSDMx->FLTISR & DFSDM_FLAG) != RESET )
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-#if defined(STM32F412xG)
-/**
- * @brief Checks whether the specified Clock Absence Channel flag is set or not.
- * @param DFSDM_FLAG_CLKAbsence: specifies the flag to check.
- * This parameter can be a value of @ref DFSDM_Clock_Absence_Flag_Definition
- * @retval None
- */
-FlagStatus DFSDM_GetClockAbsenceFlagStatus(uint32_t DFSDM_FLAG_CLKAbsence)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_CLK_ABS_FLAG(DFSDM_FLAG_CLKAbsence));
-
- if((DFSDM1_0->FLTISR & DFSDM_FLAG_CLKAbsence) != RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Checks whether the specified Short Circuit Channel Detector flag is set or not.
- * @param DFSDM_FLAG_SCD: specifies the flag to check.
- * This parameter can be a value of @ref DFSDM_SCD_Flag_Definition
- * @retval None
- */
-FlagStatus DFSDM_GetShortCircuitFlagStatus(uint32_t DFSDM_FLAG_SCD)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_SCD_FLAG(DFSDM_FLAG_SCD));
-
- if ((DFSDM1_0->FLTISR & DFSDM_FLAG_SCD) != RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- return bitstatus;
-}
-#endif /* STM32F412xG */
-#if defined(STM32F413_423xx)
-/**
- * @brief Checks whether the specified Clock Absence Channel flag is set or not.
- * @param Instance: select the instance of DFSDM
- * This parameter can be: 1 or 2.
- * @param DFSDM_FLAG_CLKAbsence: specifies the flag to check.
- * This parameter can be a value of @ref DFSDM_Clock_Absence_Flag_Definition
- * @retval None
- */
-FlagStatus DFSDM_GetClockAbsenceFlagStatus(uint32_t Instance, uint32_t DFSDM_FLAG_CLKAbsence)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_CLK_ABS_FLAG(DFSDM_FLAG_CLKAbsence));
-
- if(Instance == 1)
- {
- if((DFSDM1_0->FLTISR & DFSDM_FLAG_CLKAbsence) != RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- }
- else /* DFSDM2 */
- {
- /* Check the parameters */
- assert_param(IS_DFSDM_CLK_ABS_FLAG(DFSDM_FLAG_CLKAbsence));
-
- if((DFSDM2_0->FLTISR & DFSDM_FLAG_CLKAbsence) != RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- }
- return bitstatus;
-}
-
-/**
- * @brief Checks whether the specified Short Circuit Channel Detector flag is set or not.
- * @param Instance: select the instance of DFSDM
- * This parameter can be: 1 or 2.
- * @param DFSDM_FLAG_SCD: specifies the flag to check.
- * This parameter can be a value of @ref DFSDM_SCD_Flag_Definition
- * @retval None
- */
-FlagStatus DFSDM_GetShortCircuitFlagStatus(uint32_t Instance, uint32_t DFSDM_FLAG_SCD)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_SCD_FLAG(DFSDM_FLAG_SCD));
-
- if(Instance == 1)
- {
- if ((DFSDM1_0->FLTISR & DFSDM_FLAG_SCD) != RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- }
- else /* DFSDM2 */
- {
- if ((DFSDM2_0->FLTISR & DFSDM_FLAG_SCD) != RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- }
- return bitstatus;
-}
-#endif /* STM32F413_423xx */
-/**
- * @brief Checks whether the specified Watchdog threshold flag is set or not.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @param DFSDM_AWDChannelx: where x can be a value from 0 to 7 to select the DFSDM Channel.
- * @param DFSDM_Threshold: specifies the Threshold.
- * This parameter can be a value of @ref DFSDM_Threshold_Selection.
- * @retval None
- */
-FlagStatus DFSDM_GetWatchdogFlagStatus(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint8_t DFSDM_Threshold)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
- assert_param(IS_DFSDM_Threshold(DFSDM_Threshold));
- assert_param(IS_DFSDM_AWD_CHANNEL(DFSDM_AWDChannelx));
-
- if ((DFSDMx->FLTAWSR & ((DFSDM_AWDChannelx >> 16) << DFSDM_Threshold) ) != RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the DFSDMx's pending flag.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @param DFSDM_CLEARF: specifies the pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg DFSDM_CLEARF_JOVR: Injected data overrun Clear Flag
- * @arg DFSDM_CLEARF_ROVR: Regular data overrun Clear Flag
- * @retval None
- */
-void DFSDM_ClearFlag(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_CLEARF)
-{
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
- assert_param(IS_DFSDM_CLEAR_FLAG(DFSDM_CLEARF));
-
- /* Clear the pending Flag Bit */
- DFSDMx->FLTICR |= DFSDM_CLEARF;
-}
-
-#if defined(STM32F412xG)
-/**
- * @brief Clears the DFSDMx's pending Clock Absence Channel flag.
- * @param DFSDM_CLEARF_CLKAbsence: specifies the pending bit to clear.
- * This parameter can be any combination of @ref DFSDM_Clear_ClockAbs_Flag_Definition
- * @retval None
- */
-void DFSDM_ClearClockAbsenceFlag(uint32_t DFSDM_CLEARF_CLKAbsence)
-{
- /* Check the parameters */
- assert_param(IS_DFSDM_CLK_ABS_CLEARF(DFSDM_CLEARF_CLKAbsence));
-
- /* Clear the IT pending Flag Bit */
- DFSDM1_0->FLTICR |= DFSDM_CLEARF_CLKAbsence;
-}
-
-/**
- * @brief Clears the DFSDMx's pending Short circuit Channel flag.
- * @param DFSDM_CLEARF_SCD: specifies the pending bit to clear.
- * This parameter can be any combination of @ref DFSDM_Clear_Short_Circuit_Flag_Definition
- * @retval None
- */
-void DFSDM_ClearShortCircuitFlag(uint32_t DFSDM_CLEARF_SCD)
-{
- /* Check the parameters */
- assert_param(IS_DFSDM_SCD_CHANNEL_FLAG(DFSDM_CLEARF_SCD));
-
- /* Clear the pending Flag Bit */
- DFSDM1_0->FLTICR |= DFSDM_CLEARF_SCD;
-}
-#endif /* STM32F412xG */
-
-#if defined(STM32F413_423xx)
-/**
- * @brief Clears the DFSDMx's pending Clock Absence Channel flag.
- * @param Instance: select the instance of DFSDM
- * This parameter can be: 1 or 2.
- * @param DFSDM_CLEARF_CLKAbsence: specifies the pending bit to clear.
- * This parameter can be any combination of @ref DFSDM_Clear_ClockAbs_Flag_Definition
- * @retval None
- */
-void DFSDM_ClearClockAbsenceFlag(uint32_t Instance, uint32_t DFSDM_CLEARF_CLKAbsence)
-{
- /* Check the parameters */
- assert_param(IS_DFSDM_CLK_ABS_CLEARF(DFSDM_CLEARF_CLKAbsence));
-
- if(Instance == 1)
- {
- /* Clear the IT pending Flag Bit */
- DFSDM1_0->FLTICR |= DFSDM_CLEARF_CLKAbsence;
- }
- else /* DFSDM2 */
- {
- /* Clear the IT pending Flag Bit */
- DFSDM2_0->FLTICR |= DFSDM_CLEARF_CLKAbsence;
- }
-}
-
-/**
- * @brief Clears the DFSDMx's pending Short circuit Channel flag.
- * @param Instance: select the instance of DFSDM
- * This parameter can be: 1 or 2.
- * @param DFSDM_CLEARF_SCD: specifies the pending bit to clear.
- * This parameter can be any combination of @ref DFSDM_Clear_Short_Circuit_Flag_Definition
- * @retval None
- */
-void DFSDM_ClearShortCircuitFlag(uint32_t Instance, uint32_t DFSDM_CLEARF_SCD)
-{
- /* Check the parameters */
- assert_param(IS_DFSDM_SCD_CHANNEL_FLAG(DFSDM_CLEARF_SCD));
-
- if(Instance == 1)
- {
- /* Clear the pending Flag Bit */
- DFSDM1_0->FLTICR |= DFSDM_CLEARF_SCD;
- }
- else
- {
- /* Clear the pending Flag Bit */
- DFSDM2_0->FLTICR |= DFSDM_CLEARF_SCD;
- }
-}
-#endif /* STM32F413_423xx */
-/**
- * @brief Clears the DFSDMx's pending Analog watchdog Channel flag.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @param DFSDM_AWDChannelx: where x can be a value from 0 to 7 to select the DFSDM Channel.
- * @param DFSDM_Threshold: specifies the Threshold.
- * This parameter can be a value of @ref DFSDM_Threshold_Selection.
- * @retval None
- */
-void DFSDM_ClearAnalogWatchdogFlag(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint8_t DFSDM_Threshold)
-{
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
- assert_param(IS_DFSDM_Threshold(DFSDM_Threshold));
- assert_param(IS_DFSDM_AWD_CHANNEL(DFSDM_AWDChannelx));
-
- if ((DFSDMx->FLTAWSR & ((DFSDM_AWDChannelx >> 16) << DFSDM_Threshold) ) != RESET)
- {
- /* Clear the pending Flag Bit */
- DFSDMx->FLTAWCFR |= (DFSDM_AWDChannelx >> 16) << DFSDM_Threshold;
- }
-}
-
-/**
- * @brief Check whether the specified DFSDM interrupt has occurred or not.
- * @param DFSDMx: specifies the filter to be selected :
- * This parameter can be one of the following values :
- * @arg DFSDM1_0 : DFSDM 1 Filter 0
- * @arg DFSDM1_1 : DFSDM 1 Filter 1
- * @arg DFSDM2_0 : DFSDM 2 Filter 0 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_1 : DFSDM 2 Filter 1 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_2 : DFSDM 2 Filter 2 (available only for STM32F413_423xx devices)
- * @arg DFSDM2_3 : DFSDM 2 Filter 3 (available only for STM32F413_423xx devices)
- * @param DFSDM_IT: specifies the DFSDM interrupt source to check.
- * @arg DFSDM_IT_JEOC: End of injected conversion Interrupt source
- * @arg DFSDM_IT_REOC: End of regular conversion Interrupt source
- * @arg DFSDM_IT_JOVR: Injected data overrun Interrupt source
- * @arg DFSDM_IT_ROVR: Regular data overrun Interrupt source
- * @arg DFSDM_IT_AWD : Analog watchdog Interrupt source
- * @retval The new state of DFSDM_IT (SET or RESET).
- */
-ITStatus DFSDM_GetITStatus(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t itstatus = 0x0, itenable = 0x0;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_ALL_FILTER(DFSDMx));
- assert_param(IS_DFSDM_IT(DFSDM_IT));
-
- /* Get the Interrupt Status bit value */
- itstatus = DFSDMx->FLTISR & DFSDM_IT;
-
- /* Check if the Interrupt is enabled */
- itenable = DFSDMx->FLTCR2 & DFSDM_IT;
-
- if ((itstatus != RESET) && (itenable != RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-#if defined(STM32F412xG)
-/**
- * @brief Check whether the specified Clock Absence channel interrupt has occurred or not.
- * @param DFSDM_IT_CLKAbsence: specifies on which channel check the interrupt source.
- * This parameter can be a value of @ref DFSDM_Clock_Absence_Interrupt_Definition.
- * @retval The new state of DFSDM_IT (SET or RESET).
- * @note Clock absence interrupt is handled only by DFSDM0.
- */
-ITStatus DFSDM_GetClockAbsenceITStatus(uint32_t DFSDM_IT_CLKAbsence)
-{
- ITStatus bitstatus = RESET;
- uint32_t itstatus = 0x0, itenable = 0x0;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_CLK_ABS_IT(DFSDM_IT_CLKAbsence));
-
- /* Get the Interrupt Status bit value */
- itstatus = DFSDM0->FLTISR & DFSDM_IT_CLKAbsence;
-
- /* Check if the Interrupt is enabled */
- itenable = DFSDM0->FLTCR2 & DFSDM_IT_CKAB;
-
- if ((itstatus != RESET) && (itenable != RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Check whether the specified Short Circuit channel interrupt has occurred or not.
- * @param DFSDM_IT_SCR: specifies on which channel check the interrupt source.
- * This parameter can be a value of @ref DFSDM_SCD_Interrupt_Definition.
- * @retval The new state of DFSDM_IT (SET or RESET).
- * @note Short circuit interrupt is handled only by DFSDM0.
- */
-ITStatus DFSDM_GetShortCircuitITStatus(uint32_t DFSDM_IT_SCR)
-{
- ITStatus bitstatus = RESET;
- uint32_t itstatus = 0x0, itenable = 0x0;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_SCD_IT(DFSDM_IT_SCR));
-
- /* Get the Interrupt Status bit value */
- itstatus = DFSDM0->FLTISR & DFSDM_IT_SCR;
-
- /* Check if the Interrupt is enabled */
- itenable = DFSDM0->FLTCR2 & DFSDM_IT_SCD;
-
- if ((itstatus != RESET) && (itenable != RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-#endif /* STM32F412xG */
-
-#if defined(STM32F413_423xx)
-/**
- * @brief Check whether the specified Clock Absence channel interrupt has occurred or not.
- * @param Instance: select the instance of DFSDM
- * This parameter can be: 1 or 2.
- * @param DFSDM_IT_CLKAbsence: specifies on which channel check the interrupt source.
- * This parameter can be a value of @ref DFSDM_Clock_Absence_Interrupt_Definition.
- * @retval The new state of DFSDM_IT (SET or RESET).
- * @note Clock absence interrupt is handled only by DFSDM0.
- */
-ITStatus DFSDM_GetClockAbsenceITStatus(uint32_t Instance, uint32_t DFSDM_IT_CLKAbsence)
-{
- ITStatus bitstatus = RESET;
- uint32_t itstatus = 0x0, itenable = 0x0;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_CLK_ABS_IT(DFSDM_IT_CLKAbsence));
-
- if(Instance == 1)
- {
- /* Get the Interrupt Status bit value */
- itstatus = DFSDM1_0->FLTISR & DFSDM_IT_CLKAbsence;
- /* Check if the Interrupt is enabled */
- itenable = DFSDM1_0->FLTCR2 & DFSDM_IT_CKAB;
- }
- else
- {
- /* Get the Interrupt Status bit value */
- itstatus = DFSDM2_0->FLTISR & DFSDM_IT_CLKAbsence;
- /* Check if the Interrupt is enabled */
- itenable = DFSDM1_0->FLTCR2 & DFSDM_IT_CKAB;
- }
-
- if ((itstatus != RESET) && (itenable != RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Check whether the specified Short Circuit channel interrupt has occurred or not.
- * @param Instance: select the instance of DFSDM
- * This parameter can be: 1 or 2.
- * @param DFSDM_IT_SCR: specifies on which channel check the interrupt source.
- * This parameter can be a value of @ref DFSDM_SCD_Interrupt_Definition.
- * @retval The new state of DFSDM_IT (SET or RESET).
- * @note Short circuit interrupt is handled only by Filter 0.
- */
-ITStatus DFSDM_GetShortCircuitITStatus(uint32_t Instance, uint32_t DFSDM_IT_SCR)
-{
- ITStatus bitstatus = RESET;
- uint32_t itstatus = 0x0, itenable = 0x0;
-
- /* Check the parameters */
- assert_param(IS_DFSDM_SCD_IT(DFSDM_IT_SCR));
-
- if(Instance == 1)
- {
- /* Get the Interrupt Status bit value */
- itstatus = DFSDM1_0->FLTISR & DFSDM_IT_SCR;
-
- /* Check if the Interrupt is enabled */
- itenable = DFSDM1_0->FLTCR2 & DFSDM_IT_SCD;
- }
- else /* DFSDM2 */
- {
- /* Get the Interrupt Status bit value */
- itstatus = DFSDM2_0->FLTISR & DFSDM_IT_SCR;
-
- /* Check if the Interrupt is enabled */
- itenable = DFSDM2_0->FLTCR2 & DFSDM_IT_SCD;
- }
-
- if ((itstatus != RESET) && (itenable != RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-#endif /* STM32F413_423xx */
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* STM32F412xG || STM32F413_423xx */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_dfsdm.h b/底盘/底盘-old/底盘/Library/stm32f4xx_dfsdm.h
deleted file mode 100644
index ba8e85b..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_dfsdm.h
+++ /dev/null
@@ -1,821 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_dfsdm.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the DFSDM
- * firmware library
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4XX_DFSDM_H
-#define __STM32F4XX_DFSDM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F412xG) || defined(STM32F413_423xx)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup DFSDM
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief DFSDM Transceiver init structure definition
- */
-typedef struct
-{
- uint32_t DFSDM_Interface; /*!< Selects the serial interface type and input clock phase.
- This parameter can be a value of @ref DFSDM_Interface_Selection */
-
- uint32_t DFSDM_Clock; /*!< Specifies the clock source for the serial interface transceiver.
- This parameter can be a value of @ref DFSDM_Clock_Selection */
-
- uint32_t DFSDM_Input; /*!< Specifies the Input mode for the serial interface transceiver.
- This parameter can be a value of @ref DFSDM_Input_Selection */
-
- uint32_t DFSDM_Redirection; /*!< Specifies if the channel input is redirected from channel channel (y+1).
- This parameter can be a value of @ref DFSDM_Redirection_Selection */
-
- uint32_t DFSDM_PackingMode; /*!< Specifies the packing mode for the serial interface transceiver.
- This parameter can be a value of @ref DFSDM_Pack_Selection */
-
- uint32_t DFSDM_DataRightShift; /*!< Defines the final data right bit shift.
- This parameter can be a value between 0 and 31 */
-
- uint32_t DFSDM_Offset; /*!< Sets the calibration offset.
- This parameter can be a value between 0 and 0xFFFFFF */
-
- uint32_t DFSDM_CLKAbsenceDetector; /*!< Enables or disables the Clock Absence Detector.
- This parameter can be a value of @ref DFSDM_Clock_Absence_Detector_state */
-
- uint32_t DFSDM_ShortCircuitDetector; /*!< Enables or disables the Short Circuit Detector.
- This parameter can be a value of @ref DFSDM_Short_Circuit_Detector_state */
-}DFSDM_TransceiverInitTypeDef;
-
-/**
- * @brief DFSDM filter analog parameters structure definition
- */
-typedef struct
-{
- uint32_t DFSDM_SincOrder; /*!< Sets the Sinc Filter Order .
- This parameter can be a value of @ref DFSDM_Sinc_Order */
-
- uint32_t DFSDM_FilterOversamplingRatio; /*!< Sets the Sinc Filter Oversampling Ratio.
- This parameter can be a value between 1 and 1024 */
-
- uint32_t DFSDM_IntegratorOversamplingRatio;/*!< Sets the Integrator Oversampling Ratio.
- This parameter can be a value between 1 and 256 */
-}DFSDM_FilterInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DFSDM_Interface_Selection
- * @{
- */
-#define DFSDM_Interface_SPI_RisingEdge ((uint32_t)0x00000000) /*!< DFSDM SPI interface with rising edge to strobe data */
-#define DFSDM_Interface_SPI_FallingEdge ((uint32_t)0x00000001) /*!< DFSDM SPI interface with falling edge to strobe data */
-#define DFSDM_Interface_Manchester1 ((uint32_t)0x00000002) /*!< DFSDM Manchester coded input, rising edge = logic 0, falling edge = logic 1 */
-#define DFSDM_Interface_Manchester2 ((uint32_t)0x00000003) /*!< DFSDM Manchester coded input, rising edge = logic 1, falling edge = logic 0 */
-
-#define IS_DFSDM_INTERFACE(INTERFACE) (((INTERFACE) == DFSDM_Interface_SPI_RisingEdge) || \
- ((INTERFACE) == DFSDM_Interface_SPI_FallingEdge) || \
- ((INTERFACE) == DFSDM_Interface_Manchester1) || \
- ((INTERFACE) == DFSDM_Interface_Manchester2))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Clock_Selection
- * @{
- */
-#define DFSDM_Clock_External ((uint32_t)0x00000000) /*!< DFSDM clock coming from external DFSDM_CKINy input */
-#define DFSDM_Clock_Internal ((uint32_t)0x00000004) /*!< DFSDM clock coming from internal DFSDM_CKOUT output */
-#define DFSDM_Clock_InternalDiv2_Mode1 ((uint32_t)0x00000008) /*!< DFSDM clock coming from internal DFSDM_CKOUT output divided by 2
- and clock change is on every rising edge of DFSDM_CKOUT output signal */
-#define DFSDM_Clock_InternalDiv2_Mode2 ((uint32_t)0x0000000C) /*!< DFSDM clock coming from internal DFSDM_CKOUT output divided by 2
- and clock change is on every falling edge of DFSDM_CKOUT output signal */
-
-#define IS_DFSDM_CLOCK(CLOCK) (((CLOCK) == DFSDM_Clock_External) || \
- ((CLOCK) == DFSDM_Clock_Internal) || \
- ((CLOCK) == DFSDM_Clock_InternalDiv2_Mode1) || \
- ((CLOCK) == DFSDM_Clock_InternalDiv2_Mode2))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Input_Selection
- * @{
- */
-#define DFSDM_Input_External ((uint32_t)0x00000000) /*!< DFSDM clock coming from external DFSDM_CKINy input */
-#define DFSDM_Input_ADC ((uint32_t)0x00001000) /*!< DFSDM clock coming from internal DFSDM_CKOUT output */
-#define DFSDM_Input_Internal ((uint32_t)0x00002000) /*!< DFSDM clock coming from internal DFSDM_CKOUT output divided by 2
- and clock change is on every rising edge of DFSDM_CKOUT output signal */
-
-#define IS_DFSDM_Input_MODE(INPUT) (((INPUT) == DFSDM_Input_External) || \
- ((INPUT) == DFSDM_Input_ADC) || \
- ((INPUT) == DFSDM_Input_Internal))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Redirection_Selection
- * @{
- */
-#define DFSDM_Redirection_Disabled ((uint32_t)0x00000000) /*!< DFSDM Channel serial inputs are taken from pins of the same channel y */
-#define DFSDM_Redirection_Enabled DFSDM_CHCFGR1_CHINSEL /*!< DFSDM Channel serial inputs are taken from pins of the channel (y+1) modulo 8 */
-
-#define IS_DFSDM_Redirection_STATE(STATE) (((STATE) == DFSDM_Redirection_Disabled) || \
- ((STATE) == DFSDM_Redirection_Enabled))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Pack_Selection
- * @{
- */
-#define DFSDM_PackingMode_Standard ((uint32_t)0x00000000) /*!< DFSDM Input data in DFSDM_CHDATINyR register are stored only in INDAT0[15:0] */
-#define DFSDM_PackingMode_Interleaved ((uint32_t)0x00004000) /*!< DFSDM Input data in DFSDM_CHDATINyR register are stored as two samples:
- - first sample in INDAT0[15:0] - assigned to channel y
- - second sample INDAT1[15:0] - assigned to channel y */
-#define DFSDM_PackingMode_Dual ((uint32_t)0x00008000) /*!< DFSDM Input data in DFSDM_CHDATINyR register are stored as two samples:
- - first sample INDAT0[15:0] - assigned to channel y
- - second sample INDAT1[15:0] - assigned to channel (y+1) */
-
-#define IS_DFSDM_PACK_MODE(MODE) (((MODE) == DFSDM_PackingMode_Standard) || \
- ((MODE) == DFSDM_PackingMode_Interleaved) || \
- ((MODE) == DFSDM_PackingMode_Dual))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Clock_Absence_Detector_state
- * @{
- */
-#define DFSDM_CLKAbsenceDetector_Enable DFSDM_CHCFGR1_CKABEN /*!< DFSDM Clock Absence Detector is Enabled */
-#define DFSDM_CLKAbsenceDetector_Disable ((uint32_t)0x00000000) /*!< DFSDM Clock Absence Detector is Disabled */
-
-#define IS_DFSDM_CLK_DETECTOR_STATE(STATE) (((STATE) == DFSDM_CLKAbsenceDetector_Enable) || \
- ((STATE) == DFSDM_CLKAbsenceDetector_Disable))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Short_Circuit_Detector_state
- * @{
- */
-#define DFSDM_ShortCircuitDetector_Enable DFSDM_CHCFGR1_SCDEN /*!< DFSDM Short Circuit Detector is Enabled */
-#define DFSDM_ShortCircuitDetector_Disable ((uint32_t)0x00000000) /*!< DFSDM Short Circuit Detector is Disabled */
-
-#define IS_DFSDM_SC_DETECTOR_STATE(STATE) (((STATE) == DFSDM_ShortCircuitDetector_Enable) || \
- ((STATE) == DFSDM_ShortCircuitDetector_Disable))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Sinc_Order
- * @{
- */
-#define DFSDM_SincOrder_FastSinc ((uint32_t)0x00000000) /*!< DFSDM Sinc filter order = Fast sinc */
-#define DFSDM_SincOrder_Sinc1 ((uint32_t)0x20000000) /*!< DFSDM Sinc filter order = 1 */
-#define DFSDM_SincOrder_Sinc2 ((uint32_t)0x40000000) /*!< DFSDM Sinc filter order = 2 */
-#define DFSDM_SincOrder_Sinc3 ((uint32_t)0x60000000) /*!< DFSDM Sinc filter order = 3 */
-#define DFSDM_SincOrder_Sinc4 ((uint32_t)0x80000000) /*!< DFSDM Sinc filter order = 4 */
-#define DFSDM_SincOrder_Sinc5 ((uint32_t)0xA0000000) /*!< DFSDM Sinc filter order = 5 */
-
-#define IS_DFSDM_SINC_ORDER(ORDER) (((ORDER) == DFSDM_SincOrder_FastSinc) || \
- ((ORDER) == DFSDM_SincOrder_Sinc1) || \
- ((ORDER) == DFSDM_SincOrder_Sinc2) || \
- ((ORDER) == DFSDM_SincOrder_Sinc3) || \
- ((ORDER) == DFSDM_SincOrder_Sinc4) || \
- ((ORDER) == DFSDM_SincOrder_Sinc5))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Break_Signal_Assignment
- * @{
- */
-#define DFSDM_SCDBreak_0 ((uint32_t)0x00001000) /*!< DFSDM Break 0 signal assigned to short circuit detector */
-#define DFSDM_SCDBreak_1 ((uint32_t)0x00002000) /*!< DFSDM Break 1 signal assigned to short circuit detector */
-#define DFSDM_SCDBreak_2 ((uint32_t)0x00004000) /*!< DFSDM Break 2 signal assigned to short circuit detector */
-#define DFSDM_SCDBreak_3 ((uint32_t)0x00008000) /*!< DFSDM Break 3 signal assigned to short circuit detector */
-
-#define IS_DFSDM_SCD_BREAK_SIGNAL(RANK) (((RANK) == DFSDM_SCDBreak_0) || \
- ((RANK) == DFSDM_SCDBreak_1) || \
- ((RANK) == DFSDM_SCDBreak_2) || \
- ((RANK) == DFSDM_SCDBreak_3))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_AWD_Sinc_Order
- * @{
- */
-#define DFSDM_AWDSincOrder_Fast ((uint32_t)0x00000000) /*!< DFSDM Fast sinc filter */
-#define DFSDM_AWDSincOrder_Sinc1 ((uint32_t)0x00400000) /*!< DFSDM sinc1 filter */
-#define DFSDM_AWDSincOrder_Sinc2 ((uint32_t)0x00800000) /*!< DFSDM sinc2 filter */
-#define DFSDM_AWDSincOrder_Sinc3 ((uint32_t)0x00C00000) /*!< DFSDM sinc3 filter */
-
-#define IS_DFSDM_AWD_SINC_ORDER(ORDER) (((ORDER) == DFSDM_AWDSincOrder_Fast) || \
- ((ORDER) == DFSDM_AWDSincOrder_Sinc1) || \
- ((ORDER) == DFSDM_AWDSincOrder_Sinc2) || \
- ((ORDER) == DFSDM_AWDSincOrder_Sinc3))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_AWD_CHANNEL
- * @{
- */
-#define DFSDM_AWDChannel0 ((uint32_t)0x00010000) /*!< DFSDM AWDx guard channel 0 */
-#define DFSDM_AWDChannel1 ((uint32_t)0x00020000) /*!< DFSDM AWDx guard channel 1 */
-#define DFSDM_AWDChannel2 ((uint32_t)0x00040000) /*!< DFSDM AWDx guard channel 2 */
-#define DFSDM_AWDChannel3 ((uint32_t)0x00080000) /*!< DFSDM AWDx guard channel 3 */
-#define DFSDM_AWDChannel4 ((uint32_t)0x00100000) /*!< DFSDM AWDx guard channel 4 */
-#define DFSDM_AWDChannel5 ((uint32_t)0x00200000) /*!< DFSDM AWDx guard channel 5 */
-#define DFSDM_AWDChannel6 ((uint32_t)0x00400000) /*!< DFSDM AWDx guard channel 6 */
-#define DFSDM_AWDChannel7 ((uint32_t)0x00800000) /*!< DFSDM AWDx guard channel 7 */
-
-#define IS_DFSDM_AWD_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_AWDChannel0) || \
- ((CHANNEL) == DFSDM_AWDChannel1) || \
- ((CHANNEL) == DFSDM_AWDChannel2) || \
- ((CHANNEL) == DFSDM_AWDChannel3) || \
- ((CHANNEL) == DFSDM_AWDChannel4) || \
- ((CHANNEL) == DFSDM_AWDChannel5) || \
- ((CHANNEL) == DFSDM_AWDChannel6) || \
- ((CHANNEL) == DFSDM_AWDChannel7))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Threshold_Selection
- * @{
- */
-#define DFSDM_Threshold_Low ((uint8_t)0x00) /*!< DFSDM Low threshold */
-#define DFSDM_Threshold_High ((uint8_t)0x08) /*!< DFSDM High threshold */
-
-#define IS_DFSDM_Threshold(THR) (((THR) == DFSDM_Threshold_Low) || \
- ((THR) == DFSDM_Threshold_High))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_AWD_Fast_Mode_Selection
- * @{
- */
-#define DFSDM_AWDFastMode_Disable ((uint32_t)0x00000000) /*!< DFSDM Fast mode for AWD is disabled */
-#define DFSDM_AWDFastMode_Enable ((uint32_t)0x40000000) /*!< DFSDM Fast mode for AWD is enabled */
-
-#define IS_DFSDM_AWD_MODE(MODE) (((MODE) == DFSDM_AWDFastMode_Disable) || \
- ((MODE) == DFSDM_AWDFastMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Clock_Output_Source_Selection
- * @{
- */
-#define DFSDM_ClkOutSource_SysClock ((uint32_t)0x00000000) /*!< DFSDM Source for output clock is comming from system clock */
-#define DFSDM_ClkOutSource_AudioClock DFSDM_CHCFGR1_CKOUTSRC /*!< DFSDM Source for output clock is comming from audio clock */
-
-#define IS_DFSDM_CLOCK_OUT_SOURCE(SRC) (((SRC) == DFSDM_ClkOutSource_SysClock) || \
- ((SRC) == DFSDM_ClkOutSource_AudioClock))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Conversion_Mode
- * @{
- */
-#define DFSDM_DMAConversionMode_Regular ((uint32_t)0x00000010) /*!< DFSDM Regular mode */
-#define DFSDM_DMAConversionMode_Injected ((uint32_t)0x00000000) /*!< DFSDM Injected mode */
-
-#define IS_DFSDM_CONVERSION_MODE(MODE) (((MODE) == DFSDM_DMAConversionMode_Regular) || \
- ((MODE) == DFSDM_DMAConversionMode_Injected))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Extremes_Channel_Selection
- * @{
- */
-#define DFSDM_ExtremChannel0 ((uint32_t)0x00000100) /*!< DFSDM Extreme detector guard channel 0 */
-#define DFSDM_ExtremChannel1 ((uint32_t)0x00000200) /*!< DFSDM Extreme detector guard channel 1 */
-#define DFSDM_ExtremChannel2 ((uint32_t)0x00000400) /*!< DFSDM Extreme detector guard channel 2 */
-#define DFSDM_ExtremChannel3 ((uint32_t)0x00000800) /*!< DFSDM Extreme detector guard channel 3 */
-#define DFSDM_ExtremChannel4 ((uint32_t)0x00001000) /*!< DFSDM Extreme detector guard channel 4 */
-#define DFSDM_ExtremChannel5 ((uint32_t)0x00002000) /*!< DFSDM Extreme detector guard channel 5 */
-#define DFSDM_ExtremChannel6 ((uint32_t)0x00004000) /*!< DFSDM Extreme detector guard channel 6 */
-#define DFSDM_ExtremChannel7 ((uint32_t)0x00008000) /*!< DFSDM Extreme detector guard channel 7 */
-
-#define IS_DFSDM_EXTREM_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_ExtremChannel0) || \
- ((CHANNEL) == DFSDM_ExtremChannel1) || \
- ((CHANNEL) == DFSDM_ExtremChannel2) || \
- ((CHANNEL) == DFSDM_ExtremChannel3) || \
- ((CHANNEL) == DFSDM_ExtremChannel4) || \
- ((CHANNEL) == DFSDM_ExtremChannel5) || \
- ((CHANNEL) == DFSDM_ExtremChannel6) || \
- ((CHANNEL) == DFSDM_ExtremChannel7))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Injected_Channel_Selection
- * @{
- */
-#define DFSDM_InjectedChannel0 ((uint32_t)0x00000001) /*!< DFSDM channel 0 is selected as injected channel */
-#define DFSDM_InjectedChannel1 ((uint32_t)0x00000002) /*!< DFSDM channel 1 is selected as injected channel */
-#define DFSDM_InjectedChannel2 ((uint32_t)0x00000004) /*!< DFSDM channel 2 is selected as injected channel */
-#define DFSDM_InjectedChannel3 ((uint32_t)0x00000008) /*!< DFSDM channel 3 is selected as injected channel */
-#define DFSDM_InjectedChannel4 ((uint32_t)0x00000010) /*!< DFSDM channel 4 is selected as injected channel */
-#define DFSDM_InjectedChannel5 ((uint32_t)0x00000020) /*!< DFSDM channel 5 is selected as injected channel */
-#define DFSDM_InjectedChannel6 ((uint32_t)0x00000040) /*!< DFSDM channel 6 is selected as injected channel */
-#define DFSDM_InjectedChannel7 ((uint32_t)0x00000080) /*!< DFSDM channel 7 is selected as injected channel */
-
-#define IS_DFSDM_INJECT_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_InjectedChannel0) || \
- ((CHANNEL) == DFSDM_InjectedChannel1) || \
- ((CHANNEL) == DFSDM_InjectedChannel2) || \
- ((CHANNEL) == DFSDM_InjectedChannel3) || \
- ((CHANNEL) == DFSDM_InjectedChannel4) || \
- ((CHANNEL) == DFSDM_InjectedChannel5) || \
- ((CHANNEL) == DFSDM_InjectedChannel6) || \
- ((CHANNEL) == DFSDM_InjectedChannel7))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Regular_Channel_Selection
- * @{
- */
-#define DFSDM_RegularChannel0 ((uint32_t)0x00000000) /*!< DFSDM channel 0 is selected as regular channel */
-#define DFSDM_RegularChannel1 ((uint32_t)0x01000000) /*!< DFSDM channel 1 is selected as regular channel */
-#define DFSDM_RegularChannel2 ((uint32_t)0x02000000) /*!< DFSDM channel 2 is selected as regular channel */
-#define DFSDM_RegularChannel3 ((uint32_t)0x03000000) /*!< DFSDM channel 3 is selected as regular channel */
-#define DFSDM_RegularChannel4 ((uint32_t)0x04000000) /*!< DFSDM channel 4 is selected as regular channel */
-#define DFSDM_RegularChannel5 ((uint32_t)0x05000000) /*!< DFSDM channel 5 is selected as regular channel */
-#define DFSDM_RegularChannel6 ((uint32_t)0x06000000) /*!< DFSDM channel 6 is selected as regular channel */
-#define DFSDM_RegularChannel7 ((uint32_t)0x07000000) /*!< DFSDM channel 7 is selected as regular channel */
-
-#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_RegularChannel0) || \
- ((CHANNEL) == DFSDM_RegularChannel1) || \
- ((CHANNEL) == DFSDM_RegularChannel2) || \
- ((CHANNEL) == DFSDM_RegularChannel3) || \
- ((CHANNEL) == DFSDM_RegularChannel4) || \
- ((CHANNEL) == DFSDM_RegularChannel5) || \
- ((CHANNEL) == DFSDM_RegularChannel6) || \
- ((CHANNEL) == DFSDM_RegularChannel7))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Injected_Trigger_signal
- * @{
- */
-#define DFSDM_Trigger_TIM1_TRGO ((uint32_t)0x00000000) /*!< DFSDM Internal trigger 0 */
-#define DFSDM_Trigger_TIM1_TRGO2 ((uint32_t)0x00000100) /*!< DFSDM Internal trigger 1 */
-#define DFSDM_Trigger_TIM8_TRGO ((uint32_t)0x00000200) /*!< DFSDM Internal trigger 2 */
-#define DFSDM_Trigger_TIM8_TRGO2 ((uint32_t)0x00000300) /*!< DFSDM Internal trigger 3 */
-#define DFSDM_Trigger_TIM3_TRGO ((uint32_t)0x00000300) /*!< DFSDM Internal trigger 4 */
-#define DFSDM_Trigger_TIM4_TRGO ((uint32_t)0x00000400) /*!< DFSDM Internal trigger 5 */
-#define DFSDM_Trigger_TIM16_OC1 ((uint32_t)0x00000400) /*!< DFSDM Internal trigger 6 */
-#define DFSDM_Trigger_TIM6_TRGO ((uint32_t)0x00000500) /*!< DFSDM Internal trigger 7 */
-#define DFSDM_Trigger_TIM7_TRGO ((uint32_t)0x00000500) /*!< DFSDM Internal trigger 8 */
-#define DFSDM_Trigger_EXTI11 ((uint32_t)0x00000600) /*!< DFSDM External trigger 0 */
-#define DFSDM_Trigger_EXTI15 ((uint32_t)0x00000700) /*!< DFSDM External trigger 1 */
-
-#define IS_DFSDM0_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_Trigger_TIM1_TRGO) || \
- ((TRIG) == DFSDM_Trigger_TIM1_TRGO2) || \
- ((TRIG) == DFSDM_Trigger_TIM8_TRGO) || \
- ((TRIG) == DFSDM_Trigger_TIM8_TRGO2) || \
- ((TRIG) == DFSDM_Trigger_TIM4_TRGO) || \
- ((TRIG) == DFSDM_Trigger_TIM6_TRGO) || \
- ((TRIG) == DFSDM_Trigger_TIM7_TRGO) || \
- ((TRIG) == DFSDM_Trigger_EXTI15) || \
- ((TRIG) == DFSDM_Trigger_TIM3_TRGO) || \
- ((TRIG) == DFSDM_Trigger_TIM16_OC1) || \
- ((TRIG) == DFSDM_Trigger_EXTI11))
-
-#define IS_DFSDM1_INJ_TRIGGER(TRIG) IS_DFSDM0_INJ_TRIGGER(TRIG)
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Trigger_Edge_selection
- * @{
- */
-#define DFSDM_TriggerEdge_Disabled ((uint32_t)0x00000000) /*!< DFSDM Trigger detection disabled */
-#define DFSDM_TriggerEdge_Rising ((uint32_t)0x00002000) /*!< DFSDM Each rising edge makes a request to launch an injected conversion */
-#define DFSDM_TriggerEdge_Falling ((uint32_t)0x00004000) /*!< DFSDM Each falling edge makes a request to launch an injected conversion */
-#define DFSDM_TriggerEdge_BothEdges ((uint32_t)0x00006000) /*!< DFSDM Both edges make a request to launch an injected conversion */
-
-#define IS_DFSDM_TRIGGER_EDGE(EDGE) (((EDGE) == DFSDM_TriggerEdge_Disabled) || \
- ((EDGE) == DFSDM_TriggerEdge_Rising) || \
- ((EDGE) == DFSDM_TriggerEdge_Falling) || \
- ((EDGE) == DFSDM_TriggerEdge_BothEdges))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Injected_Conversion_Mode_Selection
- * @{
- */
-#define DFSDM_InjectConvMode_Single ((uint32_t)0x00000000) /*!< DFSDM Trigger detection disabled */
-#define DFSDM_InjectConvMode_Scan ((uint32_t)0x00000010) /*!< DFSDM Each rising edge makes a request to launch an injected conversion */
-
-#define IS_DFSDM_INJ_CONV_MODE(MODE) (((MODE) == DFSDM_InjectConvMode_Single) || \
- ((MODE) == DFSDM_InjectConvMode_Scan))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Interrupts_Definition
- * @{
- */
-#define DFSDM_IT_JEOC DFSDM_FLTCR2_JEOCIE
-#define DFSDM_IT_REOC DFSDM_FLTCR2_REOCIE
-#define DFSDM_IT_JOVR DFSDM_FLTCR2_JOVRIE
-#define DFSDM_IT_ROVR DFSDM_FLTCR2_ROVRIE
-#define DFSDM_IT_AWD DFSDM_FLTCR2_AWDIE
-#define DFSDM_IT_SCD DFSDM_FLTCR2_SCDIE
-#define DFSDM_IT_CKAB DFSDM_FLTCR2_CKABIE
-
-#define IS_DFSDM_IT(IT) (((IT) == DFSDM_IT_JEOC) || \
- ((IT) == DFSDM_IT_REOC) || \
- ((IT) == DFSDM_IT_JOVR) || \
- ((IT) == DFSDM_IT_ROVR) || \
- ((IT) == DFSDM_IT_AWD) || \
- ((IT) == DFSDM_IT_SCD) || \
- ((IT) == DFSDM_IT_CKAB))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Flag_Definition
- * @{
- */
-#define DFSDM_FLAG_JEOC DFSDM_FLTISR_JEOCF
-#define DFSDM_FLAG_REOC DFSDM_FLTISR_REOCF
-#define DFSDM_FLAG_JOVR DFSDM_FLTISR_JOVRF
-#define DFSDM_FLAG_ROVR DFSDM_FLTISR_ROVRF
-#define DFSDM_FLAG_AWD DFSDM_FLTISR_AWDF
-#define DFSDM_FLAG_JCIP DFSDM_FLTISR_JCIP
-#define DFSDM_FLAG_RCIP DFSDM_FLTISR_RCIP
-
-#define IS_DFSDM_FLAG(FLAG) (((FLAG) == DFSDM_FLAG_JEOC) || \
- ((FLAG) == DFSDM_FLAG_REOC) || \
- ((FLAG) == DFSDM_FLAG_JOVR) || \
- ((FLAG) == DFSDM_FLAG_ROVR) || \
- ((FLAG) == DFSDM_FLAG_AWD) || \
- ((FLAG) == DFSDM_FLAG_JCIP) || \
- ((FLAG) == DFSDM_FLAG_RCIP))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Clock_Absence_Flag_Definition
- * @{
- */
-#define DFSDM_FLAG_CLKAbsence_Channel0 ((uint32_t)0x00010000)
-#define DFSDM_FLAG_CLKAbsence_Channel1 ((uint32_t)0x00020000)
-#define DFSDM_FLAG_CLKAbsence_Channel2 ((uint32_t)0x00040000)
-#define DFSDM_FLAG_CLKAbsence_Channel3 ((uint32_t)0x00080000)
-#define DFSDM_FLAG_CLKAbsence_Channel4 ((uint32_t)0x00100000)
-#define DFSDM_FLAG_CLKAbsence_Channel5 ((uint32_t)0x00200000)
-#define DFSDM_FLAG_CLKAbsence_Channel6 ((uint32_t)0x00400000)
-#define DFSDM_FLAG_CLKAbsence_Channel7 ((uint32_t)0x00800000)
-
-#define IS_DFSDM_CLK_ABS_FLAG(FLAG) (((FLAG) == DFSDM_FLAG_CLKAbsence_Channel0) || \
- ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel1) || \
- ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel2) || \
- ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel3) || \
- ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel4) || \
- ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel5) || \
- ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel6) || \
- ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel7))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_SCD_Flag_Definition
- * @{
- */
-#define DFSDM_FLAG_SCD_Channel0 ((uint32_t)0x01000000)
-#define DFSDM_FLAG_SCD_Channel1 ((uint32_t)0x02000000)
-#define DFSDM_FLAG_SCD_Channel2 ((uint32_t)0x04000000)
-#define DFSDM_FLAG_SCD_Channel3 ((uint32_t)0x08000000)
-#define DFSDM_FLAG_SCD_Channel4 ((uint32_t)0x10000000)
-#define DFSDM_FLAG_SCD_Channel5 ((uint32_t)0x20000000)
-#define DFSDM_FLAG_SCD_Channel6 ((uint32_t)0x40000000)
-#define DFSDM_FLAG_SCD_Channel7 ((uint32_t)0x80000000)
-
-#define IS_DFSDM_SCD_FLAG(FLAG) (((FLAG) == DFSDM_FLAG_SCD_Channel0) || \
- ((FLAG) == DFSDM_FLAG_SCD_Channel1) || \
- ((FLAG) == DFSDM_FLAG_SCD_Channel2) || \
- ((FLAG) == DFSDM_FLAG_SCD_Channel3) || \
- ((FLAG) == DFSDM_FLAG_SCD_Channel4) || \
- ((FLAG) == DFSDM_FLAG_SCD_Channel5) || \
- ((FLAG) == DFSDM_FLAG_SCD_Channel6) || \
- ((FLAG) == DFSDM_FLAG_SCD_Channel7))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Clear_Flag_Definition
- * @{
- */
-#define DFSDM_CLEARF_JOVR DFSDM_FLTICR_CLRJOVRF
-#define DFSDM_CLEARF_ROVR DFSDM_FLTICR_CLRROVRF
-
-#define IS_DFSDM_CLEAR_FLAG(FLAG) (((FLAG) == DFSDM_CLEARF_JOVR) || \
- ((FLAG) == DFSDM_CLEARF_ROVR))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Clear_ClockAbs_Flag_Definition
- * @{
- */
-#define DFSDM_CLEARF_CLKAbsence_Channel0 ((uint32_t)0x00010000)
-#define DFSDM_CLEARF_CLKAbsence_Channel1 ((uint32_t)0x00020000)
-#define DFSDM_CLEARF_CLKAbsence_Channel2 ((uint32_t)0x00040000)
-#define DFSDM_CLEARF_CLKAbsence_Channel3 ((uint32_t)0x00080000)
-#define DFSDM_CLEARF_CLKAbsence_Channel4 ((uint32_t)0x00100000)
-#define DFSDM_CLEARF_CLKAbsence_Channel5 ((uint32_t)0x00200000)
-#define DFSDM_CLEARF_CLKAbsence_Channel6 ((uint32_t)0x00400000)
-#define DFSDM_CLEARF_CLKAbsence_Channel7 ((uint32_t)0x00800000)
-
-#define IS_DFSDM_CLK_ABS_CLEARF(FLAG) (((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel0) || \
- ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel1) || \
- ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel2) || \
- ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel3) || \
- ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel4) || \
- ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel5) || \
- ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel6) || \
- ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel7))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Clear_Short_Circuit_Flag_Definition
- * @{
- */
-#define DFSDM_CLEARF_SCD_Channel0 ((uint32_t)0x01000000)
-#define DFSDM_CLEARF_SCD_Channel1 ((uint32_t)0x02000000)
-#define DFSDM_CLEARF_SCD_Channel2 ((uint32_t)0x04000000)
-#define DFSDM_CLEARF_SCD_Channel3 ((uint32_t)0x08000000)
-#define DFSDM_CLEARF_SCD_Channel4 ((uint32_t)0x10000000)
-#define DFSDM_CLEARF_SCD_Channel5 ((uint32_t)0x20000000)
-#define DFSDM_CLEARF_SCD_Channel6 ((uint32_t)0x40000000)
-#define DFSDM_CLEARF_SCD_Channel7 ((uint32_t)0x80000000)
-
-#define IS_DFSDM_SCD_CHANNEL_FLAG(FLAG) (((FLAG) == DFSDM_CLEARF_SCD_Channel0) || \
- ((FLAG) == DFSDM_CLEARF_SCD_Channel1) || \
- ((FLAG) == DFSDM_CLEARF_SCD_Channel2) || \
- ((FLAG) == DFSDM_CLEARF_SCD_Channel3) || \
- ((FLAG) == DFSDM_CLEARF_SCD_Channel4) || \
- ((FLAG) == DFSDM_CLEARF_SCD_Channel5) || \
- ((FLAG) == DFSDM_CLEARF_SCD_Channel6) || \
- ((FLAG) == DFSDM_CLEARF_SCD_Channel7))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Clock_Absence_Interrupt_Definition
- * @{
- */
-#define DFSDM_IT_CLKAbsence_Channel0 ((uint32_t)0x00010000)
-#define DFSDM_IT_CLKAbsence_Channel1 ((uint32_t)0x00020000)
-#define DFSDM_IT_CLKAbsence_Channel2 ((uint32_t)0x00040000)
-#define DFSDM_IT_CLKAbsence_Channel3 ((uint32_t)0x00080000)
-#define DFSDM_IT_CLKAbsence_Channel4 ((uint32_t)0x00100000)
-#define DFSDM_IT_CLKAbsence_Channel5 ((uint32_t)0x00200000)
-#define DFSDM_IT_CLKAbsence_Channel6 ((uint32_t)0x00400000)
-#define DFSDM_IT_CLKAbsence_Channel7 ((uint32_t)0x00800000)
-
-#define IS_DFSDM_CLK_ABS_IT(IT) (((IT) == DFSDM_IT_CLKAbsence_Channel0) || \
- ((IT) == DFSDM_IT_CLKAbsence_Channel1) || \
- ((IT) == DFSDM_IT_CLKAbsence_Channel2) || \
- ((IT) == DFSDM_IT_CLKAbsence_Channel3) || \
- ((IT) == DFSDM_IT_CLKAbsence_Channel4) || \
- ((IT) == DFSDM_IT_CLKAbsence_Channel5) || \
- ((IT) == DFSDM_IT_CLKAbsence_Channel6) || \
- ((IT) == DFSDM_IT_CLKAbsence_Channel7))
-/**
- * @}
- */
-
-/** @defgroup DFSDM_SCD_Interrupt_Definition
- * @{
- */
-#define DFSDM_IT_SCD_Channel0 ((uint32_t)0x01000000)
-#define DFSDM_IT_SCD_Channel1 ((uint32_t)0x02000000)
-#define DFSDM_IT_SCD_Channel2 ((uint32_t)0x04000000)
-#define DFSDM_IT_SCD_Channel3 ((uint32_t)0x08000000)
-#define DFSDM_IT_SCD_Channel4 ((uint32_t)0x10000000)
-#define DFSDM_IT_SCD_Channel5 ((uint32_t)0x20000000)
-#define DFSDM_IT_SCD_Channel6 ((uint32_t)0x40000000)
-#define DFSDM_IT_SCD_Channel7 ((uint32_t)0x80000000)
-
-#define IS_DFSDM_SCD_IT(IT) (((IT) == DFSDM_IT_SCD_Channel0) || \
- ((IT) == DFSDM_IT_SCD_Channel1) || \
- ((IT) == DFSDM_IT_SCD_Channel2) || \
- ((IT) == DFSDM_IT_SCD_Channel3) || \
- ((IT) == DFSDM_IT_SCD_Channel4) || \
- ((IT) == DFSDM_IT_SCD_Channel5) || \
- ((IT) == DFSDM_IT_SCD_Channel6) || \
- ((IT) == DFSDM_IT_SCD_Channel7))
-/**
- * @}
- */
-
-#define IS_DFSDM_DATA_RIGHT_BIT_SHIFT(SHIFT) ((SHIFT) < 0x20 )
-
-#define IS_DFSDM_OFFSET(OFFSET) ((OFFSET) < 0x01000000 )
-
-#if defined(STM32F413_423xx)
-#define IS_DFSDM_ALL_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM1_Channel0) || \
- ((CHANNEL) == DFSDM1_Channel1) || \
- ((CHANNEL) == DFSDM1_Channel2) || \
- ((CHANNEL) == DFSDM1_Channel3) || \
- ((CHANNEL) == DFSDM2_Channel0) || \
- ((CHANNEL) == DFSDM2_Channel1) || \
- ((CHANNEL) == DFSDM2_Channel2) || \
- ((CHANNEL) == DFSDM2_Channel3) || \
- ((CHANNEL) == DFSDM2_Channel4) || \
- ((CHANNEL) == DFSDM2_Channel5) || \
- ((CHANNEL) == DFSDM2_Channel6) || \
- ((CHANNEL) == DFSDM2_Channel7))
-
-#define IS_DFSDM_ALL_FILTER(FILTER) (((FILTER) == DFSDM1_0) || \
- ((FILTER) == DFSDM1_1) || \
- ((FILTER) == DFSDM2_0) || \
- ((FILTER) == DFSDM2_1) || \
- ((FILTER) == DFSDM2_2) || \
- ((FILTER) == DFSDM2_3))
-
-#define IS_DFSDM_SYNC_FILTER(FILTER) (((FILTER) == DFSDM1_0) || \
- ((FILTER) == DFSDM1_1) || \
- ((FILTER) == DFSDM2_0) || \
- ((FILTER) == DFSDM2_1) || \
- ((FILTER) == DFSDM2_2) || \
- ((FILTER) == DFSDM2_3))
-#else
-#define IS_DFSDM_ALL_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM1_Channel0) || \
- ((CHANNEL) == DFSDM1_Channel1) || \
- ((CHANNEL) == DFSDM1_Channel2) || \
- ((CHANNEL) == DFSDM1_Channel3))
-
-#define IS_DFSDM_ALL_FILTER(FILTER) (((FILTER) == DFSDM1_0) || \
- ((FILTER) == DFSDM1_1))
-
-#define IS_DFSDM_SYNC_FILTER(FILTER) (((FILTER) == DFSDM1_0) || \
- ((FILTER) == DFSDM1_1))
-#endif /* STM32F413_423xx */
-
-
-
-
-#define IS_DFSDM_SINC_OVRSMPL_RATIO(RATIO) (((RATIO) < 0x401) && ((RATIO) >= 0x001))
-
-#define IS_DFSDM_INTG_OVRSMPL_RATIO(RATIO) (((RATIO) < 0x101 ) && ((RATIO) >= 0x001))
-
-#define IS_DFSDM_CLOCK_OUT_DIVIDER(DIVIDER) ((DIVIDER) < 0x101 )
-
-#define IS_DFSDM_CSD_THRESHOLD_VALUE(VALUE) ((VALUE) < 256)
-
-#define IS_DFSDM_AWD_OVRSMPL_RATIO(RATIO) ((RATIO) < 33) && ((RATIO) >= 0x001)
-
-#define IS_DFSDM_HIGH_THRESHOLD(VALUE) ((VALUE) < 0x1000000)
-#define IS_DFSDM_LOW_THRESHOLD(VALUE) ((VALUE) < 0x1000000)
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Initialization functions ***************************************************/
-void DFSDM_DeInit(void);
-void DFSDM_TransceiverInit(DFSDM_Channel_TypeDef* DFSDM_Channelx, DFSDM_TransceiverInitTypeDef* DFSDM_TransceiverInitStruct);
-void DFSDM_TransceiverStructInit(DFSDM_TransceiverInitTypeDef* DFSDM_TransceiverInitStruct);
-void DFSDM_FilterInit(DFSDM_Filter_TypeDef* DFSDMx, DFSDM_FilterInitTypeDef* DFSDM_FilterInitStruct);
-void DFSDM_FilterStructInit(DFSDM_FilterInitTypeDef* DFSDM_FilterInitStruct);
-
-/* Configuration functions ****************************************************/
-#if defined(STM32F412xG)
-void DFSDM_Command(FunctionalState NewState);
-#else /* STM32F413_423xx */
-void DFSDM_Cmd(uint32_t Instance, FunctionalState NewState);
-#endif /* STM32F412xG */
-void DFSDM_ChannelCmd(DFSDM_Channel_TypeDef* DFSDM_Channelx, FunctionalState NewState);
-void DFSDM_FilterCmd(DFSDM_Filter_TypeDef* DFSDMx, FunctionalState NewState);
-#if defined(STM32F412xG)
-void DFSDM_ConfigClkOutputDivider(uint32_t DFSDM_ClkOutDivision);
-void DFSDM_ConfigClkOutputSource(uint32_t DFSDM_ClkOutSource);
-#else
-void DFSDM_ConfigClkOutputDivider(uint32_t Instance, uint32_t DFSDM_ClkOutDivision);
-void DFSDM_ConfigClkOutputSource(uint32_t Instance, uint32_t DFSDM_ClkOutSource);
-#endif /* STM32F412xG */
-void DFSDM_SelectInjectedConversionMode(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_InjectConvMode);
-void DFSDM_SelectInjectedChannel(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_InjectedChannelx);
-void DFSDM_SelectRegularChannel(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_RegularChannelx);
-void DFSDM_StartSoftwareInjectedConversion(DFSDM_Filter_TypeDef* DFSDMx);
-void DFSDM_StartSoftwareRegularConversion(DFSDM_Filter_TypeDef* DFSDMx);
-void DFSDM_SynchronousFilter0InjectedStart(DFSDM_Filter_TypeDef* DFSDMx);
-void DFSDM_SynchronousFilter0RegularStart(DFSDM_Filter_TypeDef* DFSDMx);
-void DFSDM_RegularContinuousModeCmd(DFSDM_Filter_TypeDef* DFSDMx, FunctionalState NewState);
-void DFSDM_InjectedContinuousModeCmd(DFSDM_Filter_TypeDef* DFSDMx, FunctionalState NewState);
-void DFSDM_FastModeCmd(DFSDM_Filter_TypeDef* DFSDMx, FunctionalState NewState);
-void DFSDM_ConfigInjectedTrigger(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_Trigger, uint32_t DFSDM_TriggerEdge);
-void DFSDM_ConfigBRKShortCircuitDetector(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDBreak_i, FunctionalState NewState);
-void DFSDM_ConfigBRKAnalogWatchDog(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDBreak_i, FunctionalState NewState);
-void DFSDM_ConfigShortCircuitThreshold(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDThreshold);
-void DFSDM_ConfigAnalogWatchdog(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint32_t DFSDM_AWDFastMode);
-void DFSDM_ConfigAWDFilter(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_AWDSincOrder, uint32_t DFSDM_AWDSincOverSampleRatio);
-uint32_t DFSDM_GetAWDConversionValue(DFSDM_Channel_TypeDef* DFSDM_Channelx);
-void DFSDM_SetAWDThreshold(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_HighThreshold, uint32_t DFSDM_LowThreshold);
-void DFSDM_SelectExtremesDetectorChannel(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_ExtremChannelx);
-int32_t DFSDM_GetRegularConversionData(DFSDM_Filter_TypeDef* DFSDMx);
-int32_t DFSDM_GetInjectedConversionData(DFSDM_Filter_TypeDef* DFSDMx);
-int32_t DFSDM_GetMaxValue(DFSDM_Filter_TypeDef* DFSDMx);
-int32_t DFSDM_GetMinValue(DFSDM_Filter_TypeDef* DFSDMx);
-int32_t DFSDM_GetMaxValueChannel(DFSDM_Filter_TypeDef* DFSDMx);
-int32_t DFSDM_GetMinValueChannel(DFSDM_Filter_TypeDef* DFSDMx);
-uint32_t DFSDM_GetConversionTime(DFSDM_Filter_TypeDef* DFSDMx);
-void DFSDM_DMATransferConfig(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_DMAConversionMode, FunctionalState NewState);
-/* Interrupts and flags management functions **********************************/
-void DFSDM_ITConfig(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_IT, FunctionalState NewState);
-#if defined(STM32F412xG)
-void DFSDM_ITClockAbsenceCmd(FunctionalState NewState);
-void DFSDM_ITShortCircuitDetectorCmd(FunctionalState NewState);
-#else /* STM32F413_423xx */
-void DFSDM_ITClockAbsenceCmd(uint32_t Instance, FunctionalState NewState);
-void DFSDM_ITShortCircuitDetectorCmd(uint32_t Instance, FunctionalState NewState);
-#endif /* STM32F412xG */
-
-FlagStatus DFSDM_GetFlagStatus(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_FLAG);
-#if defined(STM32F412xG)
-FlagStatus DFSDM_GetClockAbsenceFlagStatus(uint32_t DFSDM_FLAG_CLKAbsence);
-FlagStatus DFSDM_GetShortCircuitFlagStatus(uint32_t DFSDM_FLAG_SCD);
-#else /* STM32F413_423xx */
-FlagStatus DFSDM_GetClockAbsenceFlagStatus(uint32_t Instance, uint32_t DFSDM_FLAG_CLKAbsence);
-FlagStatus DFSDM_GetShortCircuitFlagStatus(uint32_t Instance, uint32_t DFSDM_FLAG_SCD);
-#endif /* STM32F412xG */
-FlagStatus DFSDM_GetWatchdogFlagStatus(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint8_t DFSDM_Threshold);
-
-void DFSDM_ClearFlag(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_CLEARF);
-#if defined(STM32F412xG)
-void DFSDM_ClearClockAbsenceFlag(uint32_t DFSDM_CLEARF_CLKAbsence);
-void DFSDM_ClearShortCircuitFlag(uint32_t DFSDM_CLEARF_SCD);
-#else /* STM32F413_423xx */
-void DFSDM_ClearClockAbsenceFlag(uint32_t Instance, uint32_t DFSDM_CLEARF_CLKAbsence);
-void DFSDM_ClearShortCircuitFlag(uint32_t Instance, uint32_t DFSDM_CLEARF_SCD);
-#endif /* STM32F412xG */
-void DFSDM_ClearAnalogWatchdogFlag(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint8_t DFSDM_Threshold);
-
-ITStatus DFSDM_GetITStatus(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_IT);
-#if defined(STM32F412xG)
-ITStatus DFSDM_GetClockAbsenceITStatus(uint32_t DFSDM_IT_CLKAbsence);
-ITStatus DFSDM_GetShortCircuitITStatus(uint32_t DFSDM_IT_SCR);
-#else /* STM32F413_423xx */
-ITStatus DFSDM_GetClockAbsenceITStatus(uint32_t Instance, uint32_t DFSDM_IT_CLKAbsence);
-ITStatus DFSDM_GetShortCircuitITStatus(uint32_t Instance, uint32_t DFSDM_IT_SCR);
-#endif /* STM32F412xG */
-
-#endif /* STM32F412xG || STM32F413_423xx */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4XX_DFSDM_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_dma.c b/底盘/底盘-old/底盘/Library/stm32f4xx_dma.c
deleted file mode 100644
index 258c23f..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_dma.c
+++ /dev/null
@@ -1,1293 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_dma.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Direct Memory Access controller (DMA):
- * + Initialization and Configuration
- * + Data Counter
- * + Double Buffer mode configuration and command
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE)
- function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE)
- function for DMA2.
-
- (#) Enable and configure the peripheral to be connected to the DMA Stream
- (except for internal SRAM / FLASH memories: no initialization is
- necessary).
-
- (#) For a given Stream, program the required configuration through following parameters:
- Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination
- data formats, Circular or Normal mode, Stream Priority level, Source and Destination
- Incrementation mode, FIFO mode and its Threshold (if needed), Burst
- mode for Source and/or Destination (if needed) using the DMA_Init() function.
- To avoid filling unnecessary fields, you can call DMA_StructInit() function
- to initialize a given structure with default values (reset values), the modify
- only necessary fields
- (ie. Source and Destination addresses, Transfer size and Data Formats).
-
- (#) Enable the NVIC and the corresponding interrupt(s) using the function
- DMA_ITConfig() if you need to use DMA interrupts.
-
- (#) Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring
- the second Memory address and the first Memory to be used through the function
- DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function
- DMA_DoubleBufferModeCmd(). These operations must be done before step 6.
-
- (#) Enable the DMA stream using the DMA_Cmd() function.
-
- (#) Activate the needed Stream Request using PPP_DMACmd() function for
- any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
- The function allowing this operation is provided in each PPP peripheral
- driver (ie. SPI_DMACmd for SPI peripheral).
- Once the Stream is enabled, it is not possible to modify its configuration
- unless the stream is stopped and disabled.
- After enabling the Stream, it is advised to monitor the EN bit status using
- the function DMA_GetCmdStatus(). In case of configuration errors or bus errors
- this bit will remain reset and all transfers on this Stream will remain on hold.
-
- (#) Optionally, you can configure the number of data to be transferred
- when the Stream is disabled (ie. after each Transfer Complete event
- or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
- And you can get the number of remaining data to be transferred using
- the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is
- enabled and running).
-
- (#) To control DMA events you can use one of the following two methods:
- (##) Check on DMA Stream flags using the function DMA_GetFlagStatus().
- (##) Use DMA interrupts through the function DMA_ITConfig() at initialization
- phase and DMA_GetITStatus() function into interrupt routines in
- communication phase.
- [..]
- After checking on a flag you should clear it using DMA_ClearFlag()
- function. And after checking on an interrupt event you should
- clear it using DMA_ClearITPendingBit() function.
-
- (#) Optionally, if Circular mode and Double Buffer mode are enabled, you can modify
- the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that
- the Memory Address to be modified is not the one currently in use by DMA Stream.
- This condition can be monitored using the function DMA_GetCurrentMemoryTarget().
-
- (#) Optionally, Pause-Resume operations may be performed:
- The DMA_Cmd() function may be used to perform Pause-Resume operation.
- When a transfer is ongoing, calling this function to disable the
- Stream will cause the transfer to be paused. All configuration registers
- and the number of remaining data will be preserved. When calling again
- this function to re-enable the Stream, the transfer will be resumed from
- the point where it was paused.
-
- -@- Memory-to-Memory transfer is possible by setting the address of the memory into
- the Peripheral registers. In this mode, Circular mode and Double Buffer mode
- are not allowed.
-
- -@- The FIFO is used mainly to reduce bus usage and to allow data
- packing/unpacking: it is possible to set different Data Sizes for
- the Peripheral and the Memory (ie. you can set Half-Word data size
- for the peripheral to access its data register and set Word data size
- for the Memory to gain in access time. Each two Half-words will be
- packed and written in a single access to a Word in the Memory).
-
- -@- When FIFO is disabled, it is not allowed to configure different
- Data Sizes for Source and Destination. In this case the Peripheral
- Data Size will be applied to both Source and Destination.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_dma.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DMA
- * @brief DMA driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* Masks Definition */
-#define TRANSFER_IT_ENABLE_MASK (uint32_t)(DMA_SxCR_TCIE | DMA_SxCR_HTIE | \
- DMA_SxCR_TEIE | DMA_SxCR_DMEIE)
-
-#define DMA_Stream0_IT_MASK (uint32_t)(DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 | \
- DMA_LISR_TEIF0 | DMA_LISR_HTIF0 | \
- DMA_LISR_TCIF0)
-
-#define DMA_Stream1_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 6)
-#define DMA_Stream2_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 16)
-#define DMA_Stream3_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 22)
-#define DMA_Stream4_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000)
-#define DMA_Stream5_IT_MASK (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000)
-#define DMA_Stream6_IT_MASK (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000)
-#define DMA_Stream7_IT_MASK (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000)
-#define TRANSFER_IT_MASK (uint32_t)0x0F3C0F3C
-#define HIGH_ISR_MASK (uint32_t)0x20000000
-#define RESERVED_MASK (uint32_t)0x0F7D0F7D
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-
-/** @defgroup DMA_Private_Functions
- * @{
- */
-
-/** @defgroup DMA_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to initialize the DMA Stream source
- and destination addresses, incrementation and data sizes, transfer direction,
- buffer size, circular/normal mode selection, memory-to-memory mode selection
- and Stream priority value.
- [..]
- The DMA_Init() function follows the DMA configuration procedures as described in
- reference manual (RM0090) except the first point: waiting on EN bit to be reset.
- This condition should be checked by user application using the function DMA_GetCmdStatus()
- before calling the DMA_Init() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitialize the DMAy Streamx registers to their default reset values.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @retval None
- */
-void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- /* Disable the selected DMAy Streamx */
- DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN);
-
- /* Reset DMAy Streamx control register */
- DMAy_Streamx->CR = 0;
-
- /* Reset DMAy Streamx Number of Data to Transfer register */
- DMAy_Streamx->NDTR = 0;
-
- /* Reset DMAy Streamx peripheral address register */
- DMAy_Streamx->PAR = 0;
-
- /* Reset DMAy Streamx memory 0 address register */
- DMAy_Streamx->M0AR = 0;
-
- /* Reset DMAy Streamx memory 1 address register */
- DMAy_Streamx->M1AR = 0;
-
- /* Reset DMAy Streamx FIFO control register */
- DMAy_Streamx->FCR = (uint32_t)0x00000021;
-
- /* Reset interrupt pending bits for the selected stream */
- if (DMAy_Streamx == DMA1_Stream0)
- {
- /* Reset interrupt pending bits for DMA1 Stream0 */
- DMA1->LIFCR = DMA_Stream0_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream1)
- {
- /* Reset interrupt pending bits for DMA1 Stream1 */
- DMA1->LIFCR = DMA_Stream1_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream2)
- {
- /* Reset interrupt pending bits for DMA1 Stream2 */
- DMA1->LIFCR = DMA_Stream2_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream3)
- {
- /* Reset interrupt pending bits for DMA1 Stream3 */
- DMA1->LIFCR = DMA_Stream3_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream4)
- {
- /* Reset interrupt pending bits for DMA1 Stream4 */
- DMA1->HIFCR = DMA_Stream4_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream5)
- {
- /* Reset interrupt pending bits for DMA1 Stream5 */
- DMA1->HIFCR = DMA_Stream5_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream6)
- {
- /* Reset interrupt pending bits for DMA1 Stream6 */
- DMA1->HIFCR = (uint32_t)DMA_Stream6_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream7)
- {
- /* Reset interrupt pending bits for DMA1 Stream7 */
- DMA1->HIFCR = DMA_Stream7_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream0)
- {
- /* Reset interrupt pending bits for DMA2 Stream0 */
- DMA2->LIFCR = DMA_Stream0_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream1)
- {
- /* Reset interrupt pending bits for DMA2 Stream1 */
- DMA2->LIFCR = DMA_Stream1_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream2)
- {
- /* Reset interrupt pending bits for DMA2 Stream2 */
- DMA2->LIFCR = DMA_Stream2_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream3)
- {
- /* Reset interrupt pending bits for DMA2 Stream3 */
- DMA2->LIFCR = DMA_Stream3_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream4)
- {
- /* Reset interrupt pending bits for DMA2 Stream4 */
- DMA2->HIFCR = DMA_Stream4_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream5)
- {
- /* Reset interrupt pending bits for DMA2 Stream5 */
- DMA2->HIFCR = DMA_Stream5_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream6)
- {
- /* Reset interrupt pending bits for DMA2 Stream6 */
- DMA2->HIFCR = DMA_Stream6_IT_MASK;
- }
- else
- {
- if (DMAy_Streamx == DMA2_Stream7)
- {
- /* Reset interrupt pending bits for DMA2 Stream7 */
- DMA2->HIFCR = DMA_Stream7_IT_MASK;
- }
- }
-}
-
-/**
- * @brief Initializes the DMAy Streamx according to the specified parameters in
- * the DMA_InitStruct structure.
- * @note Before calling this function, it is recommended to check that the Stream
- * is actually disabled using the function DMA_GetCmdStatus().
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval None
- */
-void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CHANNEL(DMA_InitStruct->DMA_Channel));
- assert_param(IS_DMA_DIRECTION(DMA_InitStruct->DMA_DIR));
- assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
- assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
- assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
- assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
- assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
- assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
- assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
- assert_param(IS_DMA_FIFO_MODE_STATE(DMA_InitStruct->DMA_FIFOMode));
- assert_param(IS_DMA_FIFO_THRESHOLD(DMA_InitStruct->DMA_FIFOThreshold));
- assert_param(IS_DMA_MEMORY_BURST(DMA_InitStruct->DMA_MemoryBurst));
- assert_param(IS_DMA_PERIPHERAL_BURST(DMA_InitStruct->DMA_PeripheralBurst));
-
- /*------------------------- DMAy Streamx CR Configuration ------------------*/
- /* Get the DMAy_Streamx CR value */
- tmpreg = DMAy_Streamx->CR;
-
- /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
- tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
- DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
- DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
- DMA_SxCR_DIR));
-
- /* Configure DMAy Streamx: */
- /* Set CHSEL bits according to DMA_CHSEL value */
- /* Set DIR bits according to DMA_DIR value */
- /* Set PINC bit according to DMA_PeripheralInc value */
- /* Set MINC bit according to DMA_MemoryInc value */
- /* Set PSIZE bits according to DMA_PeripheralDataSize value */
- /* Set MSIZE bits according to DMA_MemoryDataSize value */
- /* Set CIRC bit according to DMA_Mode value */
- /* Set PL bits according to DMA_Priority value */
- /* Set MBURST bits according to DMA_MemoryBurst value */
- /* Set PBURST bits according to DMA_PeripheralBurst value */
- tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR |
- DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
- DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
- DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority |
- DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst;
-
- /* Write to DMAy Streamx CR register */
- DMAy_Streamx->CR = tmpreg;
-
- /*------------------------- DMAy Streamx FCR Configuration -----------------*/
- /* Get the DMAy_Streamx FCR value */
- tmpreg = DMAy_Streamx->FCR;
-
- /* Clear DMDIS and FTH bits */
- tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
-
- /* Configure DMAy Streamx FIFO:
- Set DMDIS bits according to DMA_FIFOMode value
- Set FTH bits according to DMA_FIFOThreshold value */
- tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold;
-
- /* Write to DMAy Streamx CR */
- DMAy_Streamx->FCR = tmpreg;
-
- /*------------------------- DMAy Streamx NDTR Configuration ----------------*/
- /* Write to DMAy Streamx NDTR register */
- DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize;
-
- /*------------------------- DMAy Streamx PAR Configuration -----------------*/
- /* Write to DMAy Streamx PAR */
- DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
-
- /*------------------------- DMAy Streamx M0AR Configuration ----------------*/
- /* Write to DMAy Streamx M0AR */
- DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr;
-}
-
-/**
- * @brief Fills each DMA_InitStruct member with its default value.
- * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
-{
- /*-------------- Reset DMA init structure parameters values ----------------*/
- /* Initialize the DMA_Channel member */
- DMA_InitStruct->DMA_Channel = 0;
-
- /* Initialize the DMA_PeripheralBaseAddr member */
- DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
-
- /* Initialize the DMA_Memory0BaseAddr member */
- DMA_InitStruct->DMA_Memory0BaseAddr = 0;
-
- /* Initialize the DMA_DIR member */
- DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory;
-
- /* Initialize the DMA_BufferSize member */
- DMA_InitStruct->DMA_BufferSize = 0;
-
- /* Initialize the DMA_PeripheralInc member */
- DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-
- /* Initialize the DMA_MemoryInc member */
- DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
-
- /* Initialize the DMA_PeripheralDataSize member */
- DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
-
- /* Initialize the DMA_MemoryDataSize member */
- DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
-
- /* Initialize the DMA_Mode member */
- DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
-
- /* Initialize the DMA_Priority member */
- DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
-
- /* Initialize the DMA_FIFOMode member */
- DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable;
-
- /* Initialize the DMA_FIFOThreshold member */
- DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;
-
- /* Initialize the DMA_MemoryBurst member */
- DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single;
-
- /* Initialize the DMA_PeripheralBurst member */
- DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
-}
-
-/**
- * @brief Enables or disables the specified DMAy Streamx.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param NewState: new state of the DMAy Streamx.
- * This parameter can be: ENABLE or DISABLE.
- *
- * @note This function may be used to perform Pause-Resume operation. When a
- * transfer is ongoing, calling this function to disable the Stream will
- * cause the transfer to be paused. All configuration registers and the
- * number of remaining data will be preserved. When calling again this
- * function to re-enable the Stream, the transfer will be resumed from
- * the point where it was paused.
- *
- * @note After configuring the DMA Stream (DMA_Init() function) and enabling the
- * stream, it is recommended to check (or wait until) the DMA Stream is
- * effectively enabled. A Stream may remain disabled if a configuration
- * parameter is wrong.
- * After disabling a DMA Stream, it is also recommended to check (or wait
- * until) the DMA Stream is effectively disabled. If a Stream is disabled
- * while a data transfer is ongoing, the current data will be transferred
- * and the Stream will be effectively disabled only after the transfer of
- * this single data is finished.
- *
- * @retval None
- */
-void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DMAy Streamx by setting EN bit */
- DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN;
- }
- else
- {
- /* Disable the selected DMAy Streamx by clearing EN bit */
- DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN;
- }
-}
-
-/**
- * @brief Configures, when the PINC (Peripheral Increment address mode) bit is
- * set, if the peripheral address should be incremented with the data
- * size (configured with PSIZE bits) or by a fixed offset equal to 4
- * (32-bit aligned addresses).
- *
- * @note This function has no effect if the Peripheral Increment mode is disabled.
- *
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_Pincos: specifies the Peripheral increment offset size.
- * This parameter can be one of the following values:
- * @arg DMA_PINCOS_Psize: Peripheral address increment is done
- * accordingly to PSIZE parameter.
- * @arg DMA_PINCOS_WordAligned: Peripheral address increment offset is
- * fixed to 4 (32-bit aligned addresses).
- * @retval None
- */
-void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos));
-
- /* Check the needed Peripheral increment offset */
- if(DMA_Pincos != DMA_PINCOS_Psize)
- {
- /* Configure DMA_SxCR_PINCOS bit with the input parameter */
- DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS;
- }
- else
- {
- /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */
- DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS;
- }
-}
-
-/**
- * @brief Configures, when the DMAy Streamx is disabled, the flow controller for
- * the next transactions (Peripheral or Memory).
- *
- * @note Before enabling this feature, check if the used peripheral supports
- * the Flow Controller mode or not.
- *
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_FlowCtrl: specifies the DMA flow controller.
- * This parameter can be one of the following values:
- * @arg DMA_FlowCtrl_Memory: DMAy_Streamx transactions flow controller is
- * the DMA controller.
- * @arg DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller
- * is the peripheral.
- * @retval None
- */
-void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl));
-
- /* Check the needed flow controller */
- if(DMA_FlowCtrl != DMA_FlowCtrl_Memory)
- {
- /* Configure DMA_SxCR_PFCTRL bit with the input parameter */
- DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL;
- }
- else
- {
- /* Clear the PFCTRL bit: Memory is the flow controller */
- DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup DMA_Group2 Data Counter functions
- * @brief Data Counter functions
- *
-@verbatim
- ===============================================================================
- ##### Data Counter functions #####
- ===============================================================================
- [..]
- This subsection provides function allowing to configure and read the buffer size
- (number of data to be transferred).
- [..]
- The DMA data counter can be written only when the DMA Stream is disabled
- (ie. after transfer complete event).
- [..]
- The following function can be used to write the Stream data counter value:
- (+) void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
- -@- It is advised to use this function rather than DMA_Init() in situations
- where only the Data buffer needs to be reloaded.
- -@- If the Source and Destination Data Sizes are different, then the value
- written in data counter, expressing the number of transfers, is relative
- to the number of transfers from the Peripheral point of view.
- ie. If Memory data size is Word, Peripheral data size is Half-Words,
- then the value to be configured in the data counter is the number
- of Half-Words to be transferred from/to the peripheral.
- [..]
- The DMA data counter can be read to indicate the number of remaining transfers for
- the relative DMA Stream. This counter is decremented at the end of each data
- transfer and when the transfer is complete:
- (+) If Normal mode is selected: the counter is set to 0.
- (+) If Circular mode is selected: the counter is reloaded with the initial value
- (configured before enabling the DMA Stream)
- [..]
- The following function can be used to read the Stream data counter value:
- (+) uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Writes the number of data units to be transferred on the DMAy Streamx.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param Counter: Number of data units to be transferred (from 0 to 65535)
- * Number of data items depends only on the Peripheral data format.
- *
- * @note If Peripheral data format is Bytes: number of data units is equal
- * to total number of bytes to be transferred.
- *
- * @note If Peripheral data format is Half-Word: number of data units is
- * equal to total number of bytes to be transferred / 2.
- *
- * @note If Peripheral data format is Word: number of data units is equal
- * to total number of bytes to be transferred / 4.
- *
- * @note In Memory-to-Memory transfer mode, the memory buffer pointed by
- * DMAy_SxPAR register is considered as Peripheral.
- *
- * @retval The number of remaining data units in the current DMAy Streamx transfer.
- */
-void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- /* Write the number of data units to be transferred */
- DMAy_Streamx->NDTR = (uint16_t)Counter;
-}
-
-/**
- * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @retval The number of remaining data units in the current DMAy Streamx transfer.
- */
-uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- /* Return the number of remaining data units for DMAy Streamx */
- return ((uint16_t)(DMAy_Streamx->NDTR));
-}
-/**
- * @}
- */
-
-/** @defgroup DMA_Group3 Double Buffer mode functions
- * @brief Double Buffer mode functions
- *
-@verbatim
- ===============================================================================
- ##### Double Buffer mode functions #####
- ===============================================================================
- [..]
- This subsection provides function allowing to configure and control the double
- buffer mode parameters.
-
- [..]
- The Double Buffer mode can be used only when Circular mode is enabled.
- The Double Buffer mode cannot be used when transferring data from Memory to Memory.
-
- [..]
- The Double Buffer mode allows to set two different Memory addresses from/to which
- the DMA controller will access alternatively (after completing transfer to/from
- target memory 0, it will start transfer to/from target memory 1).
- This allows to reduce software overhead for double buffering and reduce the CPU
- access time.
-
- [..]
- Two functions must be called before calling the DMA_Init() function:
- (+) void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx,
- uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory);
- (+) void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
-
- [..]
- DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address
- and the first Memory target from/to which the transfer will start after
- enabling the DMA Stream. Then DMA_DoubleBufferModeCmd() must be called
- to enable the Double Buffer mode (or disable it when it should not be used).
-
- [..]
- Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is
- stopped) to modify on of the target Memories addresses or to check which Memory target is currently
- used:
- (+) void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx,
- uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget);
- (+) uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
-
- [..]
- DMA_MemoryTargetConfig() can be called to modify the base address of one of
- the two target Memories.
- The Memory of which the base address will be modified must not be currently
- be used by the DMA Stream (ie. if the DMA Stream is currently transferring
- from Memory 1 then you can only modify base address of target Memory 0 and vice versa).
- To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which
- returns the index of the Memory target currently in use by the DMA Stream.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures, when the DMAy Streamx is disabled, the double buffer mode
- * and the current memory target.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param Memory1BaseAddr: the base address of the second buffer (Memory 1)
- * @param DMA_CurrentMemory: specifies which memory will be first buffer for
- * the transactions when the Stream will be enabled.
- * This parameter can be one of the following values:
- * @arg DMA_Memory_0: Memory 0 is the current buffer.
- * @arg DMA_Memory_1: Memory 1 is the current buffer.
- *
- * @note Memory0BaseAddr is set by the DMA structure configuration in DMA_Init().
- *
- * @retval None
- */
-void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
- uint32_t DMA_CurrentMemory)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory));
-
- if (DMA_CurrentMemory != DMA_Memory_0)
- {
- /* Set Memory 1 as current memory address */
- DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT);
- }
- else
- {
- /* Set Memory 0 as current memory address */
- DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT);
- }
-
- /* Write to DMAy Streamx M1AR */
- DMAy_Streamx->M1AR = Memory1BaseAddr;
-}
-
-/**
- * @brief Enables or disables the double buffer mode for the selected DMA stream.
- * @note This function can be called only when the DMA Stream is disabled.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param NewState: new state of the DMAy Streamx double buffer mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Configure the Double Buffer mode */
- if (NewState != DISABLE)
- {
- /* Enable the Double buffer mode */
- DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM;
- }
- else
- {
- /* Disable the Double buffer mode */
- DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM;
- }
-}
-
-/**
- * @brief Configures the Memory address for the next buffer transfer in double
- * buffer mode (for dynamic use). This function can be called when the
- * DMA Stream is enabled and when the transfer is ongoing.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param MemoryBaseAddr: The base address of the target memory buffer
- * @param DMA_MemoryTarget: Next memory target to be used.
- * This parameter can be one of the following values:
- * @arg DMA_Memory_0: To use the memory address 0
- * @arg DMA_Memory_1: To use the memory address 1
- *
- * @note It is not allowed to modify the Base Address of a target Memory when
- * this target is involved in the current transfer. ie. If the DMA Stream
- * is currently transferring to/from Memory 1, then it not possible to
- * modify Base address of Memory 1, but it is possible to modify Base
- * address of Memory 0.
- * To know which Memory is currently used, you can use the function
- * DMA_GetCurrentMemoryTarget().
- *
- * @retval None
- */
-void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
- uint32_t DMA_MemoryTarget)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget));
-
- /* Check the Memory target to be configured */
- if (DMA_MemoryTarget != DMA_Memory_0)
- {
- /* Write to DMAy Streamx M1AR */
- DMAy_Streamx->M1AR = MemoryBaseAddr;
- }
- else
- {
- /* Write to DMAy Streamx M0AR */
- DMAy_Streamx->M0AR = MemoryBaseAddr;
- }
-}
-
-/**
- * @brief Returns the current memory target used by double buffer transfer.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @retval The memory target number: 0 for Memory0 or 1 for Memory1.
- */
-uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- /* Get the current memory target */
- if ((DMAy_Streamx->CR & DMA_SxCR_CT) != 0)
- {
- /* Current memory buffer used is Memory 1 */
- tmp = 1;
- }
- else
- {
- /* Current memory buffer used is Memory 0 */
- tmp = 0;
- }
- return tmp;
-}
-/**
- * @}
- */
-
-/** @defgroup DMA_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Check the DMA enable status
- (+) Check the FIFO status
- (+) Configure the DMA Interrupts sources and check or clear the flags or
- pending bits status.
-
- [..]
- (#) DMA Enable status:
- After configuring the DMA Stream (DMA_Init() function) and enabling
- the stream, it is recommended to check (or wait until) the DMA Stream
- is effectively enabled. A Stream may remain disabled if a configuration
- parameter is wrong. After disabling a DMA Stream, it is also recommended
- to check (or wait until) the DMA Stream is effectively disabled.
- If a Stream is disabled while a data transfer is ongoing, the current
- data will be transferred and the Stream will be effectively disabled
- only after this data transfer completion.
- To monitor this state it is possible to use the following function:
- (++) FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);
-
- (#) FIFO Status:
- It is possible to monitor the FIFO status when a transfer is ongoing
- using the following function:
- (++) uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);
-
- (#) DMA Interrupts and Flags:
- The user should identify which mode will be used in his application
- to manage the DMA controller events: Polling mode or Interrupt mode.
-
- *** Polling Mode ***
- ====================
- [..]
- Each DMA stream can be managed through 4 event Flags:
- (x : DMA Stream number )
- (#) DMA_FLAG_FEIFx : to indicate that a FIFO Mode Transfer Error event occurred.
- (#) DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred.
- (#) DMA_FLAG_TEIFx : to indicate that a Transfer Error event occurred.
- (#) DMA_FLAG_HTIFx : to indicate that a Half-Transfer Complete event occurred.
- (#) DMA_FLAG_TCIFx : to indicate that a Transfer Complete event occurred .
- [..]
- In this Mode it is advised to use the following functions:
- (+) FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
- (+) void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
-
- *** Interrupt Mode ***
- ======================
- [..]
- Each DMA Stream can be managed through 4 Interrupts:
-
- *** Interrupt Source ***
- ========================
- [..]
- (#) DMA_IT_FEIFx : specifies the interrupt source for the FIFO Mode Transfer Error event.
- (#) DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event.
- (#) DMA_IT_TEIFx : specifies the interrupt source for the Transfer Error event.
- (#) DMA_IT_HTIFx : specifies the interrupt source for the Half-Transfer Complete event.
- (#) DMA_IT_TCIFx : specifies the interrupt source for the a Transfer Complete event.
- [..]
- In this Mode it is advised to use the following functions:
- (+) void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
- (+) ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
- (+) void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the status of EN bit for the specified DMAy Streamx.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- *
- * @note After configuring the DMA Stream (DMA_Init() function) and enabling
- * the stream, it is recommended to check (or wait until) the DMA Stream
- * is effectively enabled. A Stream may remain disabled if a configuration
- * parameter is wrong.
- * After disabling a DMA Stream, it is also recommended to check (or wait
- * until) the DMA Stream is effectively disabled. If a Stream is disabled
- * while a data transfer is ongoing, the current data will be transferred
- * and the Stream will be effectively disabled only after the transfer
- * of this single data is finished.
- *
- * @retval Current state of the DMAy Streamx (ENABLE or DISABLE).
- */
-FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx)
-{
- FunctionalState state = DISABLE;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN) != 0)
- {
- /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */
- state = ENABLE;
- }
- else
- {
- /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and
- all transfers are complete) */
- state = DISABLE;
- }
- return state;
-}
-
-/**
- * @brief Returns the current DMAy Streamx FIFO filled level.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @retval The FIFO filling state.
- * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
- * and not empty.
- * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
- * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
- * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
- * - DMA_FIFOStatus_Empty: when FIFO is empty
- * - DMA_FIFOStatus_Full: when FIFO is full
- */
-uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- /* Get the FIFO level bits */
- tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS));
-
- return tmpreg;
-}
-
-/**
- * @brief Checks whether the specified DMAy Streamx flag is set or not.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag
- * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag
- * @arg DMA_FLAG_TEIFx: Streamx transfer error flag
- * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag
- * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag
- * Where x can be 0 to 7 to select the DMA Stream.
- * @retval The new state of DMA_FLAG (SET or RESET).
- */
-FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
-{
- FlagStatus bitstatus = RESET;
- DMA_TypeDef* DMAy;
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
-
- /* Determine the DMA to which belongs the stream */
- if (DMAy_Streamx < DMA2_Stream0)
- {
- /* DMAy_Streamx belongs to DMA1 */
- DMAy = DMA1;
- }
- else
- {
- /* DMAy_Streamx belongs to DMA2 */
- DMAy = DMA2;
- }
-
- /* Check if the flag is in HISR or LISR */
- if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
- {
- /* Get DMAy HISR register value */
- tmpreg = DMAy->HISR;
- }
- else
- {
- /* Get DMAy LISR register value */
- tmpreg = DMAy->LISR;
- }
-
- /* Mask the reserved bits */
- tmpreg &= (uint32_t)RESERVED_MASK;
-
- /* Check the status of the specified DMA flag */
- if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
- {
- /* DMA_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* DMA_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the DMA_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DMAy Streamx's pending flags.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag
- * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag
- * @arg DMA_FLAG_TEIFx: Streamx transfer error flag
- * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag
- * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag
- * Where x can be 0 to 7 to select the DMA Stream.
- * @retval None
- */
-void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
-{
- DMA_TypeDef* DMAy;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
-
- /* Determine the DMA to which belongs the stream */
- if (DMAy_Streamx < DMA2_Stream0)
- {
- /* DMAy_Streamx belongs to DMA1 */
- DMAy = DMA1;
- }
- else
- {
- /* DMAy_Streamx belongs to DMA2 */
- DMAy = DMA2;
- }
-
- /* Check if LIFCR or HIFCR register is targeted */
- if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
- {
- /* Set DMAy HIFCR register clear flag bits */
- DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
- }
- else
- {
- /* Set DMAy LIFCR register clear flag bits */
- DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
- }
-}
-
-/**
- * @brief Enables or disables the specified DMAy Streamx interrupts.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_IT: specifies the DMA interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask
- * @arg DMA_IT_HT: Half transfer complete interrupt mask
- * @arg DMA_IT_TE: Transfer error interrupt mask
- * @arg DMA_IT_FE: FIFO error interrupt mask
- * @param NewState: new state of the specified DMA interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CONFIG_IT(DMA_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Check if the DMA_IT parameter contains a FIFO interrupt */
- if ((DMA_IT & DMA_IT_FE) != 0)
- {
- if (NewState != DISABLE)
- {
- /* Enable the selected DMA FIFO interrupts */
- DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE;
- }
- else
- {
- /* Disable the selected DMA FIFO interrupts */
- DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE;
- }
- }
-
- /* Check if the DMA_IT parameter contains a Transfer interrupt */
- if (DMA_IT != DMA_IT_FE)
- {
- if (NewState != DISABLE)
- {
- /* Enable the selected DMA transfer interrupts */
- DMAy_Streamx->CR |= (uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK);
- }
- else
- {
- /* Disable the selected DMA transfer interrupts */
- DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK);
- }
- }
-}
-
-/**
- * @brief Checks whether the specified DMAy Streamx interrupt has occurred or not.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_IT: specifies the DMA interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt
- * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt
- * @arg DMA_IT_TEIFx: Streamx transfer error interrupt
- * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt
- * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt
- * Where x can be 0 to 7 to select the DMA Stream.
- * @retval The new state of DMA_IT (SET or RESET).
- */
-ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
-{
- ITStatus bitstatus = RESET;
- DMA_TypeDef* DMAy;
- uint32_t tmpreg = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_GET_IT(DMA_IT));
-
- /* Determine the DMA to which belongs the stream */
- if (DMAy_Streamx < DMA2_Stream0)
- {
- /* DMAy_Streamx belongs to DMA1 */
- DMAy = DMA1;
- }
- else
- {
- /* DMAy_Streamx belongs to DMA2 */
- DMAy = DMA2;
- }
-
- /* Check if the interrupt enable bit is in the CR or FCR register */
- if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET)
- {
- /* Get the interrupt enable position mask in CR register */
- tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK);
-
- /* Check the enable bit in CR register */
- enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg);
- }
- else
- {
- /* Check the enable bit in FCR register */
- enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE);
- }
-
- /* Check if the interrupt pending flag is in LISR or HISR */
- if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
- {
- /* Get DMAy HISR register value */
- tmpreg = DMAy->HISR ;
- }
- else
- {
- /* Get DMAy LISR register value */
- tmpreg = DMAy->LISR ;
- }
-
- /* mask all reserved bits */
- tmpreg &= (uint32_t)RESERVED_MASK;
-
- /* Check the status of the specified DMA interrupt */
- if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
- {
- /* DMA_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* DMA_IT is reset */
- bitstatus = RESET;
- }
-
- /* Return the DMA_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DMAy Streamx's interrupt pending bits.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_IT: specifies the DMA interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt
- * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt
- * @arg DMA_IT_TEIFx: Streamx transfer error interrupt
- * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt
- * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt
- * Where x can be 0 to 7 to select the DMA Stream.
- * @retval None
- */
-void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
-{
- DMA_TypeDef* DMAy;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CLEAR_IT(DMA_IT));
-
- /* Determine the DMA to which belongs the stream */
- if (DMAy_Streamx < DMA2_Stream0)
- {
- /* DMAy_Streamx belongs to DMA1 */
- DMAy = DMA1;
- }
- else
- {
- /* DMAy_Streamx belongs to DMA2 */
- DMAy = DMA2;
- }
-
- /* Check if LIFCR or HIFCR register is targeted */
- if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
- {
- /* Set DMAy HIFCR register clear interrupt bits */
- DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
- }
- else
- {
- /* Set DMAy LIFCR register clear interrupt bits */
- DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_dma.h b/底盘/底盘-old/底盘/Library/stm32f4xx_dma.h
deleted file mode 100644
index c8ca9c5..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_dma.h
+++ /dev/null
@@ -1,601 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_dma.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the DMA firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_DMA_H
-#define __STM32F4xx_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup DMA
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief DMA Init structure definition
- */
-
-typedef struct
-{
- uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream.
- This parameter can be a value of @ref DMA_channel */
-
- uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */
-
- uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx.
- This memory is the default memory used when double buffer mode is
- not enabled. */
-
- uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral,
- from memory to memory or from peripheral to memory.
- This parameter can be a value of @ref DMA_data_transfer_direction */
-
- uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream.
- The data unit is equal to the configuration set in DMA_PeripheralDataSize
- or DMA_MemoryDataSize members depending in the transfer direction. */
-
- uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
- This parameter can be a value of @ref DMA_peripheral_incremented_mode */
-
- uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not.
- This parameter can be a value of @ref DMA_memory_incremented_mode */
-
- uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
- This parameter can be a value of @ref DMA_peripheral_data_size */
-
- uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
- This parameter can be a value of @ref DMA_memory_data_size */
-
- uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx.
- This parameter can be a value of @ref DMA_circular_normal_mode
- @note The circular buffer mode cannot be used if the memory-to-memory
- data transfer is configured on the selected Stream */
-
- uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx.
- This parameter can be a value of @ref DMA_priority_level */
-
- uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream.
- This parameter can be a value of @ref DMA_fifo_direct_mode
- @note The Direct mode (FIFO mode disabled) cannot be used if the
- memory-to-memory data transfer is configured on the selected Stream */
-
- uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level.
- This parameter can be a value of @ref DMA_fifo_threshold_level */
-
- uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
- It specifies the amount of data to be transferred in a single non interruptable
- transaction. This parameter can be a value of @ref DMA_memory_burst
- @note The burst mode is possible only if the address Increment mode is enabled. */
-
- uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
- It specifies the amount of data to be transferred in a single non interruptable
- transaction. This parameter can be a value of @ref DMA_peripheral_burst
- @note The burst mode is possible only if the address Increment mode is enabled. */
-}DMA_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants
- * @{
- */
-
-#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \
- ((PERIPH) == DMA1_Stream1) || \
- ((PERIPH) == DMA1_Stream2) || \
- ((PERIPH) == DMA1_Stream3) || \
- ((PERIPH) == DMA1_Stream4) || \
- ((PERIPH) == DMA1_Stream5) || \
- ((PERIPH) == DMA1_Stream6) || \
- ((PERIPH) == DMA1_Stream7) || \
- ((PERIPH) == DMA2_Stream0) || \
- ((PERIPH) == DMA2_Stream1) || \
- ((PERIPH) == DMA2_Stream2) || \
- ((PERIPH) == DMA2_Stream3) || \
- ((PERIPH) == DMA2_Stream4) || \
- ((PERIPH) == DMA2_Stream5) || \
- ((PERIPH) == DMA2_Stream6) || \
- ((PERIPH) == DMA2_Stream7))
-
-#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \
- ((CONTROLLER) == DMA2))
-
-/** @defgroup DMA_channel
- * @{
- */
-#define DMA_Channel_0 ((uint32_t)0x00000000)
-#define DMA_Channel_1 ((uint32_t)0x02000000)
-#define DMA_Channel_2 ((uint32_t)0x04000000)
-#define DMA_Channel_3 ((uint32_t)0x06000000)
-#define DMA_Channel_4 ((uint32_t)0x08000000)
-#define DMA_Channel_5 ((uint32_t)0x0A000000)
-#define DMA_Channel_6 ((uint32_t)0x0C000000)
-#define DMA_Channel_7 ((uint32_t)0x0E000000)
-
-#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \
- ((CHANNEL) == DMA_Channel_1) || \
- ((CHANNEL) == DMA_Channel_2) || \
- ((CHANNEL) == DMA_Channel_3) || \
- ((CHANNEL) == DMA_Channel_4) || \
- ((CHANNEL) == DMA_Channel_5) || \
- ((CHANNEL) == DMA_Channel_6) || \
- ((CHANNEL) == DMA_Channel_7))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_data_transfer_direction
- * @{
- */
-#define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000)
-#define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040)
-#define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080)
-
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \
- ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \
- ((DIRECTION) == DMA_DIR_MemoryToMemory))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_data_buffer_size
- * @{
- */
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_peripheral_incremented_mode
- * @{
- */
-#define DMA_PeripheralInc_Enable ((uint32_t)0x00000200)
-#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
- ((STATE) == DMA_PeripheralInc_Disable))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_memory_incremented_mode
- * @{
- */
-#define DMA_MemoryInc_Enable ((uint32_t)0x00000400)
-#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
- ((STATE) == DMA_MemoryInc_Disable))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_peripheral_data_size
- * @{
- */
-#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
-#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800)
-#define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000)
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
- ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
- ((SIZE) == DMA_PeripheralDataSize_Word))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_memory_data_size
- * @{
- */
-#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
-#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000)
-#define DMA_MemoryDataSize_Word ((uint32_t)0x00004000)
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
- ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
- ((SIZE) == DMA_MemoryDataSize_Word ))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_circular_normal_mode
- * @{
- */
-#define DMA_Mode_Normal ((uint32_t)0x00000000)
-#define DMA_Mode_Circular ((uint32_t)0x00000100)
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \
- ((MODE) == DMA_Mode_Circular))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_priority_level
- * @{
- */
-#define DMA_Priority_Low ((uint32_t)0x00000000)
-#define DMA_Priority_Medium ((uint32_t)0x00010000)
-#define DMA_Priority_High ((uint32_t)0x00020000)
-#define DMA_Priority_VeryHigh ((uint32_t)0x00030000)
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \
- ((PRIORITY) == DMA_Priority_Medium) || \
- ((PRIORITY) == DMA_Priority_High) || \
- ((PRIORITY) == DMA_Priority_VeryHigh))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_fifo_direct_mode
- * @{
- */
-#define DMA_FIFOMode_Disable ((uint32_t)0x00000000)
-#define DMA_FIFOMode_Enable ((uint32_t)0x00000004)
-
-#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \
- ((STATE) == DMA_FIFOMode_Enable))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_fifo_threshold_level
- * @{
- */
-#define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000)
-#define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001)
-#define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002)
-#define DMA_FIFOThreshold_Full ((uint32_t)0x00000003)
-
-#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \
- ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \
- ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \
- ((THRESHOLD) == DMA_FIFOThreshold_Full))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_memory_burst
- * @{
- */
-#define DMA_MemoryBurst_Single ((uint32_t)0x00000000)
-#define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000)
-#define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000)
-#define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000)
-
-#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \
- ((BURST) == DMA_MemoryBurst_INC4) || \
- ((BURST) == DMA_MemoryBurst_INC8) || \
- ((BURST) == DMA_MemoryBurst_INC16))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_peripheral_burst
- * @{
- */
-#define DMA_PeripheralBurst_Single ((uint32_t)0x00000000)
-#define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000)
-#define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000)
-#define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000)
-
-#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \
- ((BURST) == DMA_PeripheralBurst_INC4) || \
- ((BURST) == DMA_PeripheralBurst_INC8) || \
- ((BURST) == DMA_PeripheralBurst_INC16))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_fifo_status_level
- * @{
- */
-#define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3)
-#define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3)
-#define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3)
-#define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3)
-#define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3)
-#define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3)
-
-#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \
- ((STATUS) == DMA_FIFOStatus_HalfFull) || \
- ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \
- ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \
- ((STATUS) == DMA_FIFOStatus_Full) || \
- ((STATUS) == DMA_FIFOStatus_Empty))
-/**
- * @}
- */
-
-/** @defgroup DMA_flags_definition
- * @{
- */
-#define DMA_FLAG_FEIF0 ((uint32_t)0x10800001)
-#define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004)
-#define DMA_FLAG_TEIF0 ((uint32_t)0x10000008)
-#define DMA_FLAG_HTIF0 ((uint32_t)0x10000010)
-#define DMA_FLAG_TCIF0 ((uint32_t)0x10000020)
-#define DMA_FLAG_FEIF1 ((uint32_t)0x10000040)
-#define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100)
-#define DMA_FLAG_TEIF1 ((uint32_t)0x10000200)
-#define DMA_FLAG_HTIF1 ((uint32_t)0x10000400)
-#define DMA_FLAG_TCIF1 ((uint32_t)0x10000800)
-#define DMA_FLAG_FEIF2 ((uint32_t)0x10010000)
-#define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000)
-#define DMA_FLAG_TEIF2 ((uint32_t)0x10080000)
-#define DMA_FLAG_HTIF2 ((uint32_t)0x10100000)
-#define DMA_FLAG_TCIF2 ((uint32_t)0x10200000)
-#define DMA_FLAG_FEIF3 ((uint32_t)0x10400000)
-#define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000)
-#define DMA_FLAG_TEIF3 ((uint32_t)0x12000000)
-#define DMA_FLAG_HTIF3 ((uint32_t)0x14000000)
-#define DMA_FLAG_TCIF3 ((uint32_t)0x18000000)
-#define DMA_FLAG_FEIF4 ((uint32_t)0x20000001)
-#define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004)
-#define DMA_FLAG_TEIF4 ((uint32_t)0x20000008)
-#define DMA_FLAG_HTIF4 ((uint32_t)0x20000010)
-#define DMA_FLAG_TCIF4 ((uint32_t)0x20000020)
-#define DMA_FLAG_FEIF5 ((uint32_t)0x20000040)
-#define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100)
-#define DMA_FLAG_TEIF5 ((uint32_t)0x20000200)
-#define DMA_FLAG_HTIF5 ((uint32_t)0x20000400)
-#define DMA_FLAG_TCIF5 ((uint32_t)0x20000800)
-#define DMA_FLAG_FEIF6 ((uint32_t)0x20010000)
-#define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000)
-#define DMA_FLAG_TEIF6 ((uint32_t)0x20080000)
-#define DMA_FLAG_HTIF6 ((uint32_t)0x20100000)
-#define DMA_FLAG_TCIF6 ((uint32_t)0x20200000)
-#define DMA_FLAG_FEIF7 ((uint32_t)0x20400000)
-#define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000)
-#define DMA_FLAG_TEIF7 ((uint32_t)0x22000000)
-#define DMA_FLAG_HTIF7 ((uint32_t)0x24000000)
-#define DMA_FLAG_TCIF7 ((uint32_t)0x28000000)
-
-#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \
- (((FLAG) & 0xC002F082) == 0x00) && ((FLAG) != 0x00))
-
-#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \
- ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \
- ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \
- ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \
- ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \
- ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \
- ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \
- ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \
- ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \
- ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \
- ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \
- ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \
- ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \
- ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \
- ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \
- ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \
- ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \
- ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \
- ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \
- ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_interrupt_enable_definitions
- * @{
- */
-#define DMA_IT_TC ((uint32_t)0x00000010)
-#define DMA_IT_HT ((uint32_t)0x00000008)
-#define DMA_IT_TE ((uint32_t)0x00000004)
-#define DMA_IT_DME ((uint32_t)0x00000002)
-#define DMA_IT_FE ((uint32_t)0x00000080)
-
-#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_interrupts_definitions
- * @{
- */
-#define DMA_IT_FEIF0 ((uint32_t)0x90000001)
-#define DMA_IT_DMEIF0 ((uint32_t)0x10001004)
-#define DMA_IT_TEIF0 ((uint32_t)0x10002008)
-#define DMA_IT_HTIF0 ((uint32_t)0x10004010)
-#define DMA_IT_TCIF0 ((uint32_t)0x10008020)
-#define DMA_IT_FEIF1 ((uint32_t)0x90000040)
-#define DMA_IT_DMEIF1 ((uint32_t)0x10001100)
-#define DMA_IT_TEIF1 ((uint32_t)0x10002200)
-#define DMA_IT_HTIF1 ((uint32_t)0x10004400)
-#define DMA_IT_TCIF1 ((uint32_t)0x10008800)
-#define DMA_IT_FEIF2 ((uint32_t)0x90010000)
-#define DMA_IT_DMEIF2 ((uint32_t)0x10041000)
-#define DMA_IT_TEIF2 ((uint32_t)0x10082000)
-#define DMA_IT_HTIF2 ((uint32_t)0x10104000)
-#define DMA_IT_TCIF2 ((uint32_t)0x10208000)
-#define DMA_IT_FEIF3 ((uint32_t)0x90400000)
-#define DMA_IT_DMEIF3 ((uint32_t)0x11001000)
-#define DMA_IT_TEIF3 ((uint32_t)0x12002000)
-#define DMA_IT_HTIF3 ((uint32_t)0x14004000)
-#define DMA_IT_TCIF3 ((uint32_t)0x18008000)
-#define DMA_IT_FEIF4 ((uint32_t)0xA0000001)
-#define DMA_IT_DMEIF4 ((uint32_t)0x20001004)
-#define DMA_IT_TEIF4 ((uint32_t)0x20002008)
-#define DMA_IT_HTIF4 ((uint32_t)0x20004010)
-#define DMA_IT_TCIF4 ((uint32_t)0x20008020)
-#define DMA_IT_FEIF5 ((uint32_t)0xA0000040)
-#define DMA_IT_DMEIF5 ((uint32_t)0x20001100)
-#define DMA_IT_TEIF5 ((uint32_t)0x20002200)
-#define DMA_IT_HTIF5 ((uint32_t)0x20004400)
-#define DMA_IT_TCIF5 ((uint32_t)0x20008800)
-#define DMA_IT_FEIF6 ((uint32_t)0xA0010000)
-#define DMA_IT_DMEIF6 ((uint32_t)0x20041000)
-#define DMA_IT_TEIF6 ((uint32_t)0x20082000)
-#define DMA_IT_HTIF6 ((uint32_t)0x20104000)
-#define DMA_IT_TCIF6 ((uint32_t)0x20208000)
-#define DMA_IT_FEIF7 ((uint32_t)0xA0400000)
-#define DMA_IT_DMEIF7 ((uint32_t)0x21001000)
-#define DMA_IT_TEIF7 ((uint32_t)0x22002000)
-#define DMA_IT_HTIF7 ((uint32_t)0x24004000)
-#define DMA_IT_TCIF7 ((uint32_t)0x28008000)
-
-#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \
- (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \
- (((IT) & 0x40820082) == 0x00))
-
-#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \
- ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \
- ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \
- ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \
- ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \
- ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \
- ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \
- ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \
- ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \
- ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \
- ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \
- ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \
- ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \
- ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \
- ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \
- ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \
- ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \
- ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \
- ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \
- ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_peripheral_increment_offset
- * @{
- */
-#define DMA_PINCOS_Psize ((uint32_t)0x00000000)
-#define DMA_PINCOS_WordAligned ((uint32_t)0x00008000)
-
-#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \
- ((SIZE) == DMA_PINCOS_WordAligned))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_flow_controller_definitions
- * @{
- */
-#define DMA_FlowCtrl_Memory ((uint32_t)0x00000000)
-#define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020)
-
-#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \
- ((CTRL) == DMA_FlowCtrl_Peripheral))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_memory_targets_definitions
- * @{
- */
-#define DMA_Memory_0 ((uint32_t)0x00000000)
-#define DMA_Memory_1 ((uint32_t)0x00080000)
-
-#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the DMA configuration to the default reset state *****/
-void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx);
-
-/* Initialization and Configuration functions *********************************/
-void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct);
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
-void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
-
-/* Optional Configuration functions *******************************************/
-void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos);
-void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl);
-
-/* Data Counter functions *****************************************************/
-void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
-uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
-
-/* Double Buffer mode functions ***********************************************/
-void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
- uint32_t DMA_CurrentMemory);
-void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
-void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
- uint32_t DMA_MemoryTarget);
-uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
-
-/* Interrupts and flags management functions **********************************/
-FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);
-uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);
-FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
-void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
-void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
-ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
-void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_DMA_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_dma2d.c b/底盘/底盘-old/底盘/Library/stm32f4xx_dma2d.c
deleted file mode 100644
index b14722b..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_dma2d.c
+++ /dev/null
@@ -1,776 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_dma2d.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the DMA2D controller (DMA2D) peripheral:
- * + Initialization and configuration
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable DMA2D clock using
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_DMA2D, ENABLE) function.
-
- (#) Configures DMA2D
- (++) transfer mode
- (++) pixel format, line_number, pixel_per_line
- (++) output memory address
- (++) alpha value
- (++) output offset
- (++) Default color (RGB)
-
- (#) Configures Foreground or/and background
- (++) memory address
- (++) alpha value
- (++) offset and default color
-
- (#) Call the DMA2D_Start() to enable the DMA2D controller.
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_dma2d.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DMA2D
- * @brief DMA2D driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-#define CR_MASK ((uint32_t)0xFFFCE0FC) /* DMA2D CR Mask */
-#define PFCCR_MASK ((uint32_t)0x00FC00C0) /* DMA2D FGPFCCR Mask */
-#define DEAD_MASK ((uint32_t)0xFFFF00FE) /* DMA2D DEAD Mask */
-
-/** @defgroup DMA2D_Private_Functions
- * @{
- */
-
-/** @defgroup DMA2D_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the DMA2D
- (+) Start/Abort/Suspend Transfer
- (+) Initialize, configure and set Foreground and background
- (+) configure and enable DeadTime
- (+) configure lineWatermark
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the DMA2D peripheral registers to their default reset
- * values.
- * @param None
- * @retval None
- */
-
-void DMA2D_DeInit(void)
-{
- /* Enable DMA2D reset state */
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2D, ENABLE);
- /* Release DMA2D from reset state */
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2D, DISABLE);
-}
-
-
-/**
- * @brief Initializes the DMA2D peripheral according to the specified parameters
- * in the DMA2D_InitStruct.
- * @note This function can be used only when the DMA2D is disabled.
- * @param DMA2D_InitStruct: pointer to a DMA2D_InitTypeDef structure that contains
- * the configuration information for the specified DMA2D peripheral.
- * @retval None
- */
-void DMA2D_Init(DMA2D_InitTypeDef* DMA2D_InitStruct)
-{
-
- uint32_t outgreen = 0;
- uint32_t outred = 0;
- uint32_t outalpha = 0;
- uint32_t pixline = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA2D_MODE(DMA2D_InitStruct->DMA2D_Mode));
- assert_param(IS_DMA2D_CMODE(DMA2D_InitStruct->DMA2D_CMode));
- assert_param(IS_DMA2D_OGREEN(DMA2D_InitStruct->DMA2D_OutputGreen));
- assert_param(IS_DMA2D_ORED(DMA2D_InitStruct->DMA2D_OutputRed));
- assert_param(IS_DMA2D_OBLUE(DMA2D_InitStruct->DMA2D_OutputBlue));
- assert_param(IS_DMA2D_OALPHA(DMA2D_InitStruct->DMA2D_OutputAlpha));
- assert_param(IS_DMA2D_OUTPUT_OFFSET(DMA2D_InitStruct->DMA2D_OutputOffset));
- assert_param(IS_DMA2D_LINE(DMA2D_InitStruct->DMA2D_NumberOfLine));
- assert_param(IS_DMA2D_PIXEL(DMA2D_InitStruct->DMA2D_PixelPerLine));
-
- /* Configures the DMA2D operation mode */
- DMA2D->CR &= (uint32_t)CR_MASK;
- DMA2D->CR |= (DMA2D_InitStruct->DMA2D_Mode);
-
- /* Configures the color mode of the output image */
- DMA2D->OPFCCR &= ~(uint32_t)DMA2D_OPFCCR_CM;
- DMA2D->OPFCCR |= (DMA2D_InitStruct->DMA2D_CMode);
-
- /* Configures the output color */
-
- if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_ARGB8888)
- {
- outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 8;
- outred = DMA2D_InitStruct->DMA2D_OutputRed << 16;
- outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 24;
- }
- else
-
- if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_RGB888)
- {
- outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 8;
- outred = DMA2D_InitStruct->DMA2D_OutputRed << 16;
- outalpha = (uint32_t)0x00000000;
- }
-
- else
-
- if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_RGB565)
- {
- outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 5;
- outred = DMA2D_InitStruct->DMA2D_OutputRed << 11;
- outalpha = (uint32_t)0x00000000;
- }
-
- else
-
- if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_ARGB1555)
- {
- outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 5;
- outred = DMA2D_InitStruct->DMA2D_OutputRed << 10;
- outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 15;
- }
-
- else /* DMA2D_CMode = DMA2D_ARGB4444 */
- {
- outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 4;
- outred = DMA2D_InitStruct->DMA2D_OutputRed << 8;
- outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 12;
- }
- DMA2D->OCOLR = ((outgreen) | (outred) | (DMA2D_InitStruct->DMA2D_OutputBlue) | (outalpha));
-
- /* Configures the output memory address */
- DMA2D->OMAR = (DMA2D_InitStruct->DMA2D_OutputMemoryAdd);
-
- /* Configure the line Offset */
- DMA2D->OOR &= ~(uint32_t)DMA2D_OOR_LO;
- DMA2D->OOR |= (DMA2D_InitStruct->DMA2D_OutputOffset);
-
- /* Configure the number of line and pixel per line */
- pixline = DMA2D_InitStruct->DMA2D_PixelPerLine << 16;
- DMA2D->NLR &= ~(DMA2D_NLR_NL | DMA2D_NLR_PL);
- DMA2D->NLR |= ((DMA2D_InitStruct->DMA2D_NumberOfLine) | (pixline));
-
-/**
- * @brief Fills each DMA2D_InitStruct member with its default value.
- * @param DMA2D_InitStruct: pointer to a DMA2D_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-}
-void DMA2D_StructInit(DMA2D_InitTypeDef* DMA2D_InitStruct)
-{
- /* Initialize the transfer mode member */
- DMA2D_InitStruct->DMA2D_Mode = DMA2D_M2M;
-
- /* Initialize the output color mode members */
- DMA2D_InitStruct->DMA2D_CMode = DMA2D_ARGB8888;
-
- /* Initialize the alpha and RGB values */
- DMA2D_InitStruct->DMA2D_OutputGreen = 0x00;
- DMA2D_InitStruct->DMA2D_OutputBlue = 0x00;
- DMA2D_InitStruct->DMA2D_OutputRed = 0x00;
- DMA2D_InitStruct->DMA2D_OutputAlpha = 0x00;
-
- /* Initialize the output memory address */
- DMA2D_InitStruct->DMA2D_OutputMemoryAdd = 0x00;
-
- /* Initialize the output offset */
- DMA2D_InitStruct->DMA2D_OutputOffset = 0x00;
-
- /* Initialize the number of line and the number of pixel per line */
- DMA2D_InitStruct->DMA2D_NumberOfLine = 0x00;
- DMA2D_InitStruct->DMA2D_PixelPerLine = 0x00;
-}
-
-/**
- * @brief Start the DMA2D transfer.
- * @param
- * @retval None
- */
-
-void DMA2D_StartTransfer(void)
-{
- /* Start DMA2D transfer by setting START bit */
- DMA2D->CR |= (uint32_t)DMA2D_CR_START;
-}
-
-/**
- * @brief Abort the DMA2D transfer.
- * @param
- * @retval None
- */
-
-void DMA2D_AbortTransfer(void)
-{
- /* Start DMA2D transfer by setting START bit */
- DMA2D->CR |= (uint32_t)DMA2D_CR_ABORT;
-
-}
-
-/**
- * @brief Stop or continue the DMA2D transfer.
- * @param NewState: new state of the DMA2D peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DMA2D_Suspend(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Suspend DMA2D transfer by setting STOP bit */
- DMA2D->CR |= (uint32_t)DMA2D_CR_SUSP;
- }
- else
- {
- /* Continue DMA2D transfer by clearing STOP bit */
- DMA2D->CR &= ~(uint32_t)DMA2D_CR_SUSP;
- }
-}
-
-/**
- * @brief Configures the Foreground according to the specified parameters
- * in the DMA2D_FGStruct.
- * @note This function can be used only when the transfer is disabled.
- * @param DMA2D_FGStruct: pointer to a DMA2D_FGTypeDef structure that contains
- * the configuration information for the specified Background.
- * @retval None
- */
-void DMA2D_FGConfig(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct)
-{
-
- uint32_t fg_clutcolormode = 0;
- uint32_t fg_clutsize = 0;
- uint32_t fg_alpha_mode = 0;
- uint32_t fg_alphavalue = 0;
- uint32_t fg_colorgreen = 0;
- uint32_t fg_colorred = 0;
-
- assert_param(IS_DMA2D_FGO(DMA2D_FG_InitStruct->DMA2D_FGO));
- assert_param(IS_DMA2D_FGCM(DMA2D_FG_InitStruct->DMA2D_FGCM));
- assert_param(IS_DMA2D_FG_CLUT_CM(DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM));
- assert_param(IS_DMA2D_FG_CLUT_SIZE(DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE));
- assert_param(IS_DMA2D_FG_ALPHA_MODE(DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE));
- assert_param(IS_DMA2D_FG_ALPHA_VALUE(DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE));
- assert_param(IS_DMA2D_FGC_BLUE(DMA2D_FG_InitStruct->DMA2D_FGC_BLUE));
- assert_param(IS_DMA2D_FGC_GREEN(DMA2D_FG_InitStruct->DMA2D_FGC_GREEN));
- assert_param(IS_DMA2D_FGC_RED(DMA2D_FG_InitStruct->DMA2D_FGC_RED));
-
- /* Configures the FG memory address */
- DMA2D->FGMAR = (DMA2D_FG_InitStruct->DMA2D_FGMA);
-
- /* Configures the FG offset */
- DMA2D->FGOR &= ~(uint32_t)DMA2D_FGOR_LO;
- DMA2D->FGOR |= (DMA2D_FG_InitStruct->DMA2D_FGO);
-
- /* Configures foreground Pixel Format Convertor */
- DMA2D->FGPFCCR &= (uint32_t)PFCCR_MASK;
- fg_clutcolormode = DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM << 4;
- fg_clutsize = DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE << 8;
- fg_alpha_mode = DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE << 16;
- fg_alphavalue = DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE << 24;
- DMA2D->FGPFCCR |= (DMA2D_FG_InitStruct->DMA2D_FGCM | fg_clutcolormode | fg_clutsize | \
- fg_alpha_mode | fg_alphavalue);
-
- /* Configures foreground color */
- DMA2D->FGCOLR &= ~(DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_RED);
- fg_colorgreen = DMA2D_FG_InitStruct->DMA2D_FGC_GREEN << 8;
- fg_colorred = DMA2D_FG_InitStruct->DMA2D_FGC_RED << 16;
- DMA2D->FGCOLR |= (DMA2D_FG_InitStruct->DMA2D_FGC_BLUE | fg_colorgreen | fg_colorred);
-
- /* Configures foreground CLUT memory address */
- DMA2D->FGCMAR = DMA2D_FG_InitStruct->DMA2D_FGCMAR;
-}
-
-/**
- * @brief Fills each DMA2D_FGStruct member with its default value.
- * @param DMA2D_FGStruct: pointer to a DMA2D_FGTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void DMA2D_FG_StructInit(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct)
-{
- /*!< Initialize the DMA2D foreground memory address */
- DMA2D_FG_InitStruct->DMA2D_FGMA = 0x00;
-
- /*!< Initialize the DMA2D foreground offset */
- DMA2D_FG_InitStruct->DMA2D_FGO = 0x00;
-
- /*!< Initialize the DMA2D foreground color mode */
- DMA2D_FG_InitStruct->DMA2D_FGCM = CM_ARGB8888;
-
- /*!< Initialize the DMA2D foreground CLUT color mode */
- DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM = CLUT_CM_ARGB8888;
-
- /*!< Initialize the DMA2D foreground CLUT size */
- DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE = 0x00;
-
- /*!< Initialize the DMA2D foreground alpha mode */
- DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE;
-
- /*!< Initialize the DMA2D foreground alpha value */
- DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE = 0x00;
-
- /*!< Initialize the DMA2D foreground blue value */
- DMA2D_FG_InitStruct->DMA2D_FGC_BLUE = 0x00;
-
- /*!< Initialize the DMA2D foreground green value */
- DMA2D_FG_InitStruct->DMA2D_FGC_GREEN = 0x00;
-
- /*!< Initialize the DMA2D foreground red value */
- DMA2D_FG_InitStruct->DMA2D_FGC_RED = 0x00;
-
- /*!< Initialize the DMA2D foreground CLUT memory address */
- DMA2D_FG_InitStruct->DMA2D_FGCMAR = 0x00;
-}
-
-
-/**
- * @brief Configures the Background according to the specified parameters
- * in the DMA2D_BGStruct.
- * @note This function can be used only when the transfer is disabled.
- * @param DMA2D_BGStruct: pointer to a DMA2D_BGTypeDef structure that contains
- * the configuration information for the specified Background.
- * @retval None
- */
-void DMA2D_BGConfig(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct)
-{
-
- uint32_t bg_clutcolormode = 0;
- uint32_t bg_clutsize = 0;
- uint32_t bg_alpha_mode = 0;
- uint32_t bg_alphavalue = 0;
- uint32_t bg_colorgreen = 0;
- uint32_t bg_colorred = 0;
-
- assert_param(IS_DMA2D_BGO(DMA2D_BG_InitStruct->DMA2D_BGO));
- assert_param(IS_DMA2D_BGCM(DMA2D_BG_InitStruct->DMA2D_BGCM));
- assert_param(IS_DMA2D_BG_CLUT_CM(DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM));
- assert_param(IS_DMA2D_BG_CLUT_SIZE(DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE));
- assert_param(IS_DMA2D_BG_ALPHA_MODE(DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE));
- assert_param(IS_DMA2D_BG_ALPHA_VALUE(DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE));
- assert_param(IS_DMA2D_BGC_BLUE(DMA2D_BG_InitStruct->DMA2D_BGC_BLUE));
- assert_param(IS_DMA2D_BGC_GREEN(DMA2D_BG_InitStruct->DMA2D_BGC_GREEN));
- assert_param(IS_DMA2D_BGC_RED(DMA2D_BG_InitStruct->DMA2D_BGC_RED));
-
- /* Configures the BG memory address */
- DMA2D->BGMAR = (DMA2D_BG_InitStruct->DMA2D_BGMA);
-
- /* Configures the BG offset */
- DMA2D->BGOR &= ~(uint32_t)DMA2D_BGOR_LO;
- DMA2D->BGOR |= (DMA2D_BG_InitStruct->DMA2D_BGO);
-
- /* Configures background Pixel Format Convertor */
- DMA2D->BGPFCCR &= (uint32_t)PFCCR_MASK;
- bg_clutcolormode = DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM << 4;
- bg_clutsize = DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE << 8;
- bg_alpha_mode = DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE << 16;
- bg_alphavalue = DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE << 24;
- DMA2D->BGPFCCR |= (DMA2D_BG_InitStruct->DMA2D_BGCM | bg_clutcolormode | bg_clutsize | \
- bg_alpha_mode | bg_alphavalue);
-
- /* Configures background color */
- DMA2D->BGCOLR &= ~(DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_RED);
- bg_colorgreen = DMA2D_BG_InitStruct->DMA2D_BGC_GREEN << 8;
- bg_colorred = DMA2D_BG_InitStruct->DMA2D_BGC_RED << 16;
- DMA2D->BGCOLR |= (DMA2D_BG_InitStruct->DMA2D_BGC_BLUE | bg_colorgreen | bg_colorred);
-
- /* Configures background CLUT memory address */
- DMA2D->BGCMAR = DMA2D_BG_InitStruct->DMA2D_BGCMAR;
-
-}
-
-/**
- * @brief Fills each DMA2D_BGStruct member with its default value.
- * @param DMA2D_BGStruct: pointer to a DMA2D_BGTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void DMA2D_BG_StructInit(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct)
-{
- /*!< Initialize the DMA2D background memory address */
- DMA2D_BG_InitStruct->DMA2D_BGMA = 0x00;
-
- /*!< Initialize the DMA2D background offset */
- DMA2D_BG_InitStruct->DMA2D_BGO = 0x00;
-
- /*!< Initialize the DMA2D background color mode */
- DMA2D_BG_InitStruct->DMA2D_BGCM = CM_ARGB8888;
-
- /*!< Initialize the DMA2D background CLUT color mode */
- DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM = CLUT_CM_ARGB8888;
-
- /*!< Initialize the DMA2D background CLUT size */
- DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE = 0x00;
-
- /*!< Initialize the DMA2D background alpha mode */
- DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE;
-
- /*!< Initialize the DMA2D background alpha value */
- DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE = 0x00;
-
- /*!< Initialize the DMA2D background blue value */
- DMA2D_BG_InitStruct->DMA2D_BGC_BLUE = 0x00;
-
- /*!< Initialize the DMA2D background green value */
- DMA2D_BG_InitStruct->DMA2D_BGC_GREEN = 0x00;
-
- /*!< Initialize the DMA2D background red value */
- DMA2D_BG_InitStruct->DMA2D_BGC_RED = 0x00;
-
- /*!< Initialize the DMA2D background CLUT memory address */
- DMA2D_BG_InitStruct->DMA2D_BGCMAR = 0x00;
-}
-
-/**
- * @brief Start the automatic loading of the CLUT or abort the transfer.
- * @param NewState: new state of the DMA2D peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-
-void DMA2D_FGStart(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Start the automatic loading of the CLUT */
- DMA2D->FGPFCCR |= DMA2D_FGPFCCR_START;
- }
- else
- {
- /* abort the transfer */
- DMA2D->FGPFCCR &= (uint32_t)~DMA2D_FGPFCCR_START;
- }
-}
-
-/**
- * @brief Start the automatic loading of the CLUT or abort the transfer.
- * @param NewState: new state of the DMA2D peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-
-void DMA2D_BGStart(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Start the automatic loading of the CLUT */
- DMA2D->BGPFCCR |= DMA2D_BGPFCCR_START;
- }
- else
- {
- /* abort the transfer */
- DMA2D->BGPFCCR &= (uint32_t)~DMA2D_BGPFCCR_START;
- }
-}
-
-/**
- * @brief Configures the DMA2D dead time.
- * @param DMA2D_DeadTime: specifies the DMA2D dead time.
- * This parameter can be one of the following values:
- * @retval None
- */
-void DMA2D_DeadTimeConfig(uint32_t DMA2D_DeadTime, FunctionalState NewState)
-{
- uint32_t DeadTime;
-
- /* Check the parameters */
- assert_param(IS_DMA2D_DEAD_TIME(DMA2D_DeadTime));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable and Configures the dead time */
- DMA2D->AMTCR &= (uint32_t)DEAD_MASK;
- DeadTime = DMA2D_DeadTime << 8;
- DMA2D->AMTCR |= (DeadTime | DMA2D_AMTCR_EN);
- }
- else
- {
- DMA2D->AMTCR &= ~(uint32_t)DMA2D_AMTCR_EN;
- }
-}
-
-/**
- * @brief Define the configuration of the line watermark .
- * @param DMA2D_LWatermarkConfig: Line Watermark configuration.
- * @retval None
- */
-
-void DMA2D_LineWatermarkConfig(uint32_t DMA2D_LWatermarkConfig)
-{
- /* Check the parameters */
- assert_param(IS_DMA2D_LineWatermark(DMA2D_LWatermarkConfig));
-
- /* Sets the Line watermark configuration */
- DMA2D->LWR = (uint32_t)DMA2D_LWatermarkConfig;
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA2D_Group2 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure the DMA2D
- Interrupts and to get the status and clear flags and Interrupts
- pending bits.
- [..] The DMA2D provides 6 Interrupts sources and 6 Flags
-
- *** Flags ***
- =============
- [..]
- (+) DMA2D_FLAG_CE : Configuration Error Interrupt flag
- (+) DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag
- (+) DMA2D_FLAG_TW: Transfer Watermark Interrupt flag
- (+) DMA2D_FLAG_TC: Transfer Complete interrupt flag
- (+) DMA2D_FLAG_TE: Transfer Error interrupt flag
- (+) DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag
-
- *** Interrupts ***
- ==================
- [..]
- (+) DMA2D_IT_CE: Configuration Error Interrupt is generated when a wrong
- configuration is detected
- (+) DMA2D_IT_CAE: CLUT Access Error Interrupt
- (+) DMA2D_IT_TW: Transfer Watermark Interrupt is generated when
- the programmed watermark is reached
- (+) DMA2D_IT_TE: Transfer Error interrupt is generated when the CPU trying
- to access the CLUT while a CLUT loading or a DMA2D1 transfer
- is on going
- (+) DMA2D_IT_CTC: CLUT Transfer Complete Interrupt
- (+) DMA2D_IT_TC: Transfer Complete interrupt
-@endverbatim
- * @{
- */
-/**
- * @brief Enables or disables the specified DMA2D's interrupts.
- * @param DMA2D_IT: specifies the DMA2D interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg DMA2D_IT_CE: Configuration Error Interrupt Enable.
- * @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt Enable.
- * @arg DMA2D_IT_CAE: CLUT Access Error Interrupt Enable.
- * @arg DMA2D_IT_TW: Transfer Watermark Interrupt Enable.
- * @arg DMA2D_IT_TC: Transfer Complete interrupt enable.
- * @arg DMA2D_IT_TE: Transfer Error interrupt enable.
- * @param NewState: new state of the specified DMA2D interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-
-void DMA2D_ITConfig(uint32_t DMA2D_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA2D_IT(DMA2D_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DMA2D interrupts */
- DMA2D->CR |= DMA2D_IT;
- }
- else
- {
- /* Disable the selected DMA2D interrupts */
- DMA2D->CR &= (uint32_t)~DMA2D_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified DMA2D's flag is set or not.
- * @param DMA2D_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg DMA2D_FLAG_CE: Configuration Error Interrupt flag.
- * @arg DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag.
- * @arg DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag.
- * @arg DMA2D_FLAG_TW: Transfer Watermark Interrupt flag.
- * @arg DMA2D_FLAG_TC: Transfer Complete interrupt flag.
- * @arg DMA2D_FLAG_TE: Transfer Error interrupt flag.
- * @retval The new state of DMA2D_FLAG (SET or RESET).
- */
-
-FlagStatus DMA2D_GetFlagStatus(uint32_t DMA2D_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_DMA2D_GET_FLAG(DMA2D_FLAG));
-
- /* Check the status of the specified DMA2D flag */
- if (((DMA2D->ISR) & DMA2D_FLAG) != (uint32_t)RESET)
- {
- /* DMA2D_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* DMA2D_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the DMA2D_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DMA2D's pending flags.
- * @param DMA2D_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DMA2D_FLAG_CE: Configuration Error Interrupt flag.
- * @arg DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag.
- * @arg DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag.
- * @arg DMA2D_FLAG_TW: Transfer Watermark Interrupt flag.
- * @arg DMA2D_FLAG_TC: Transfer Complete interrupt flag.
- * @arg DMA2D_FLAG_TE: Transfer Error interrupt flag.
- * @retval None
- */
-void DMA2D_ClearFlag(uint32_t DMA2D_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_DMA2D_GET_FLAG(DMA2D_FLAG));
-
- /* Clear the corresponding DMA2D flag */
- DMA2D->IFCR = (uint32_t)DMA2D_FLAG;
-}
-
-/**
- * @brief Checks whether the specified DMA2D's interrupt has occurred or not.
- * @param DMA2D_IT: specifies the DMA2D interrupts sources to check.
- * This parameter can be one of the following values:
- * @arg DMA2D_IT_CE: Configuration Error Interrupt Enable.
- * @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt Enable.
- * @arg DMA2D_IT_CAE: CLUT Access Error Interrupt Enable.
- * @arg DMA2D_IT_TW: Transfer Watermark Interrupt Enable.
- * @arg DMA2D_IT_TC: Transfer Complete interrupt enable.
- * @arg DMA2D_IT_TE: Transfer Error interrupt enable.
- * @retval The new state of the DMA2D_IT (SET or RESET).
- */
-ITStatus DMA2D_GetITStatus(uint32_t DMA2D_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t DMA2D_IT_FLAG = DMA2D_IT >> 8;
-
- /* Check the parameters */
- assert_param(IS_DMA2D_IT(DMA2D_IT));
-
- if ((DMA2D->ISR & DMA2D_IT_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- if (((DMA2D->CR & DMA2D_IT) != (uint32_t)RESET) && (bitstatus != (uint32_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the DMA2D's interrupt pending bits.
- * @param DMA2D_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg DMA2D_IT_CE: Configuration Error Interrupt.
- * @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt.
- * @arg DMA2D_IT_CAE: CLUT Access Error Interrupt.
- * @arg DMA2D_IT_TW: Transfer Watermark Interrupt.
- * @arg DMA2D_IT_TC: Transfer Complete interrupt.
- * @arg DMA2D_IT_TE: Transfer Error interrupt.
- * @retval None
- */
-void DMA2D_ClearITPendingBit(uint32_t DMA2D_IT)
-{
- /* Check the parameters */
- assert_param(IS_DMA2D_IT(DMA2D_IT));
- DMA2D_IT = DMA2D_IT >> 8;
-
- /* Clear the corresponding DMA2D Interrupt */
- DMA2D->IFCR = (uint32_t)DMA2D_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_dma2d.h b/底盘/底盘-old/底盘/Library/stm32f4xx_dma2d.h
deleted file mode 100644
index 6cb04e1..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_dma2d.h
+++ /dev/null
@@ -1,467 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_dma2d.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the DMA2D firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_DMA2D_H
-#define __STM32F4xx_DMA2D_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup DMA2D
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief DMA2D Init structure definition
- */
-
-typedef struct
-{
- uint32_t DMA2D_Mode; /*!< configures the DMA2D transfer mode.
- This parameter can be one value of @ref DMA2D_MODE */
-
- uint32_t DMA2D_CMode; /*!< configures the color format of the output image.
- This parameter can be one value of @ref DMA2D_CMODE */
-
- uint32_t DMA2D_OutputBlue; /*!< configures the blue value of the output image.
- This parameter must range:
- - from 0x00 to 0xFF if ARGB8888 color mode is slected
- - from 0x00 to 0xFF if RGB888 color mode is slected
- - from 0x00 to 0x1F if RGB565 color mode is slected
- - from 0x00 to 0x1F if ARGB1555 color mode is slected
- - from 0x00 to 0x0F if ARGB4444 color mode is slected */
-
- uint32_t DMA2D_OutputGreen; /*!< configures the green value of the output image.
- This parameter must range:
- - from 0x00 to 0xFF if ARGB8888 color mode is selected
- - from 0x00 to 0xFF if RGB888 color mode is selected
- - from 0x00 to 0x2F if RGB565 color mode is selected
- - from 0x00 to 0x1F if ARGB1555 color mode is selected
- - from 0x00 to 0x0F if ARGB4444 color mode is selected */
-
- uint32_t DMA2D_OutputRed; /*!< configures the red value of the output image.
- This parameter must range:
- - from 0x00 to 0xFF if ARGB8888 color mode is slected
- - from 0x00 to 0xFF if RGB888 color mode is slected
- - from 0x00 to 0x1F if RGB565 color mode is slected
- - from 0x00 to 0x1F if ARGB1555 color mode is slected
- - from 0x00 to 0x0F if ARGB4444 color mode is slected */
-
- uint32_t DMA2D_OutputAlpha; /*!< configures the alpha channel of the output color.
- This parameter must range:
- - from 0x00 to 0xFF if ARGB8888 color mode is selected
- - from 0x00 to 0x01 if ARGB1555 color mode is selected
- - from 0x00 to 0x0F if ARGB4444 color mode is selected */
-
- uint32_t DMA2D_OutputMemoryAdd; /*!< Specifies the memory address. This parameter
- must be range from 0x00000000 to 0xFFFFFFFF. */
-
- uint32_t DMA2D_OutputOffset; /*!< Specifies the Offset value. This parameter must be range from
- 0x0000 to 0x3FFF. */
-
- uint32_t DMA2D_NumberOfLine; /*!< Configures the number of line of the area to be transfered.
- This parameter must range from 0x0000 to 0xFFFF */
-
- uint32_t DMA2D_PixelPerLine; /*!< Configures the number pixel per line of the area to be transferred.
- This parameter must range from 0x0000 to 0x3FFF */
-} DMA2D_InitTypeDef;
-
-
-
-typedef struct
-{
- uint32_t DMA2D_FGMA; /*!< configures the DMA2D foreground memory address.
- This parameter must be range from 0x00000000 to 0xFFFFFFFF. */
-
- uint32_t DMA2D_FGO; /*!< configures the DMA2D foreground offset.
- This parameter must be range from 0x0000 to 0x3FFF. */
-
- uint32_t DMA2D_FGCM; /*!< configures the DMA2D foreground color mode .
- This parameter can be one value of @ref DMA2D_FGCM */
-
- uint32_t DMA2D_FG_CLUT_CM; /*!< configures the DMA2D foreground CLUT color mode.
- This parameter can be one value of @ref DMA2D_FG_CLUT_CM */
-
- uint32_t DMA2D_FG_CLUT_SIZE; /*!< configures the DMA2D foreground CLUT size.
- This parameter must range from 0x00 to 0xFF. */
-
- uint32_t DMA2D_FGPFC_ALPHA_MODE; /*!< configures the DMA2D foreground alpha mode.
- This parameter can be one value of @ref DMA2D_FGPFC_ALPHA_MODE */
-
- uint32_t DMA2D_FGPFC_ALPHA_VALUE; /*!< Specifies the DMA2D foreground alpha value
- must be range from 0x00 to 0xFF. */
-
- uint32_t DMA2D_FGC_BLUE; /*!< Specifies the DMA2D foreground blue value
- must be range from 0x00 to 0xFF. */
-
- uint32_t DMA2D_FGC_GREEN; /*!< Specifies the DMA2D foreground green value
- must be range from 0x00 to 0xFF. */
-
- uint32_t DMA2D_FGC_RED; /*!< Specifies the DMA2D foreground red value
- must be range from 0x00 to 0xFF. */
-
- uint32_t DMA2D_FGCMAR; /*!< Configures the DMA2D foreground CLUT memory address.
- This parameter must range from 0x00000000 to 0xFFFFFFFF. */
-} DMA2D_FG_InitTypeDef;
-
-
-typedef struct
-{
- uint32_t DMA2D_BGMA; /*!< configures the DMA2D background memory address.
- This parameter must be range from 0x00000000 to 0xFFFFFFFF. */
-
- uint32_t DMA2D_BGO; /*!< configures the DMA2D background offset.
- This parameter must be range from 0x0000 to 0x3FFF. */
-
- uint32_t DMA2D_BGCM; /*!< configures the DMA2D background color mode .
- This parameter can be one value of @ref DMA2D_FGCM */
-
- uint32_t DMA2D_BG_CLUT_CM; /*!< configures the DMA2D background CLUT color mode.
- This parameter can be one value of @ref DMA2D_FG_CLUT_CM */
-
- uint32_t DMA2D_BG_CLUT_SIZE; /*!< configures the DMA2D background CLUT size.
- This parameter must range from 0x00 to 0xFF. */
-
- uint32_t DMA2D_BGPFC_ALPHA_MODE; /*!< configures the DMA2D background alpha mode.
- This parameter can be one value of @ref DMA2D_FGPFC_ALPHA_MODE */
-
- uint32_t DMA2D_BGPFC_ALPHA_VALUE; /*!< Specifies the DMA2D background alpha value
- must be range from 0x00 to 0xFF. */
-
- uint32_t DMA2D_BGC_BLUE; /*!< Specifies the DMA2D background blue value
- must be range from 0x00 to 0xFF. */
-
- uint32_t DMA2D_BGC_GREEN; /*!< Specifies the DMA2D background green value
- must be range from 0x00 to 0xFF. */
-
- uint32_t DMA2D_BGC_RED; /*!< Specifies the DMA2D background red value
- must be range from 0x00 to 0xFF. */
-
- uint32_t DMA2D_BGCMAR; /*!< Configures the DMA2D background CLUT memory address.
- This parameter must range from 0x00000000 to 0xFFFFFFFF. */
-} DMA2D_BG_InitTypeDef;
-
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA2D_Exported_Constants
- * @{
- */
-
-/** @defgroup DMA2D_MODE
- * @{
- */
-
-
-#define DMA2D_M2M ((uint32_t)0x00000000)
-#define DMA2D_M2M_PFC ((uint32_t)0x00010000)
-#define DMA2D_M2M_BLEND ((uint32_t)0x00020000)
-#define DMA2D_R2M ((uint32_t)0x00030000)
-
-#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
- ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
-
-
-/**
- * @}
- */
-
-/** @defgroup DMA2D_CMODE
- * @{
- */
-#define DMA2D_ARGB8888 ((uint32_t)0x00000000)
-#define DMA2D_RGB888 ((uint32_t)0x00000001)
-#define DMA2D_RGB565 ((uint32_t)0x00000002)
-#define DMA2D_ARGB1555 ((uint32_t)0x00000003)
-#define DMA2D_ARGB4444 ((uint32_t)0x00000004)
-
-#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \
- ((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \
- ((MODE_ARGB) == DMA2D_ARGB4444))
-
-
-/**
- * @}
- */
-
-/** @defgroup DMA2D_OUTPUT_COLOR
- * @{
- */
-#define DMA2D_Output_Color ((uint32_t)0x000000FF)
-
-#define IS_DMA2D_OGREEN(OGREEN) ((OGREEN) <= DMA2D_Output_Color)
-#define IS_DMA2D_ORED(ORED) ((ORED) <= DMA2D_Output_Color)
-#define IS_DMA2D_OBLUE(OBLUE) ((OBLUE) <= DMA2D_Output_Color)
-#define IS_DMA2D_OALPHA(OALPHA) ((OALPHA) <= DMA2D_Output_Color)
-
-/**
- * @}
- */
-
-/** @defgroup DMA2D_OUTPUT_OFFSET
- * @{
- */
-#define DMA2D_OUTPUT_OFFSET ((uint32_t)0x00003FFF)
-
-#define IS_DMA2D_OUTPUT_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OUTPUT_OFFSET)
-
-
-/**
- * @}
- */
-
-/** @defgroup DMA2D_SIZE
- * @{
- */
-
-#define DMA2D_pixel ((uint32_t)0x00003FFF)
-#define DMA2D_Line ((uint32_t)0x0000FFFF)
-
-#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_Line)
-#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_pixel)
-
-
-/**
- * @}
- */
-
-/** @defgroup DMA2D_OFFSET
- * @{
- */
-#define OFFSET ((uint32_t)0x00003FFF)
-
-#define IS_DMA2D_FGO(FGO) ((FGO) <= OFFSET)
-
-#define IS_DMA2D_BGO(BGO) ((BGO) <= OFFSET)
-
-/**
- * @}
- */
-
-
-/** @defgroup DMA2D_FGCM
- * @{
- */
-
-#define CM_ARGB8888 ((uint32_t)0x00000000)
-#define CM_RGB888 ((uint32_t)0x00000001)
-#define CM_RGB565 ((uint32_t)0x00000002)
-#define CM_ARGB1555 ((uint32_t)0x00000003)
-#define CM_ARGB4444 ((uint32_t)0x00000004)
-#define CM_L8 ((uint32_t)0x00000005)
-#define CM_AL44 ((uint32_t)0x00000006)
-#define CM_AL88 ((uint32_t)0x00000007)
-#define CM_L4 ((uint32_t)0x00000008)
-#define CM_A8 ((uint32_t)0x00000009)
-#define CM_A4 ((uint32_t)0x0000000A)
-
-#define IS_DMA2D_FGCM(FGCM) (((FGCM) == CM_ARGB8888) || ((FGCM) == CM_RGB888) || \
- ((FGCM) == CM_RGB565) || ((FGCM) == CM_ARGB1555) || \
- ((FGCM) == CM_ARGB4444) || ((FGCM) == CM_L8) || \
- ((FGCM) == CM_AL44) || ((FGCM) == CM_AL88) || \
- ((FGCM) == CM_L4) || ((FGCM) == CM_A8) || \
- ((FGCM) == CM_A4))
-
-#define IS_DMA2D_BGCM(BGCM) (((BGCM) == CM_ARGB8888) || ((BGCM) == CM_RGB888) || \
- ((BGCM) == CM_RGB565) || ((BGCM) == CM_ARGB1555) || \
- ((BGCM) == CM_ARGB4444) || ((BGCM) == CM_L8) || \
- ((BGCM) == CM_AL44) || ((BGCM) == CM_AL88) || \
- ((BGCM) == CM_L4) || ((BGCM) == CM_A8) || \
- ((BGCM) == CM_A4))
-
-/**
- * @}
- */
-
-/** @defgroup DMA2D_FG_CLUT_CM
- * @{
- */
-
-#define CLUT_CM_ARGB8888 ((uint32_t)0x00000000)
-#define CLUT_CM_RGB888 ((uint32_t)0x00000001)
-
-#define IS_DMA2D_FG_CLUT_CM(FG_CLUT_CM) (((FG_CLUT_CM) == CLUT_CM_ARGB8888) || ((FG_CLUT_CM) == CLUT_CM_RGB888))
-
-#define IS_DMA2D_BG_CLUT_CM(BG_CLUT_CM) (((BG_CLUT_CM) == CLUT_CM_ARGB8888) || ((BG_CLUT_CM) == CLUT_CM_RGB888))
-
-/**
- * @}
- */
-
-/** @defgroup DMA2D_FG_COLOR_VALUE
- * @{
- */
-
-#define COLOR_VALUE ((uint32_t)0x000000FF)
-
-#define IS_DMA2D_FG_CLUT_SIZE(FG_CLUT_SIZE) ((FG_CLUT_SIZE) <= COLOR_VALUE)
-
-#define IS_DMA2D_FG_ALPHA_VALUE(FG_ALPHA_VALUE) ((FG_ALPHA_VALUE) <= COLOR_VALUE)
-#define IS_DMA2D_FGC_BLUE(FGC_BLUE) ((FGC_BLUE) <= COLOR_VALUE)
-#define IS_DMA2D_FGC_GREEN(FGC_GREEN) ((FGC_GREEN) <= COLOR_VALUE)
-#define IS_DMA2D_FGC_RED(FGC_RED) ((FGC_RED) <= COLOR_VALUE)
-
-#define IS_DMA2D_BG_CLUT_SIZE(BG_CLUT_SIZE) ((BG_CLUT_SIZE) <= COLOR_VALUE)
-
-#define IS_DMA2D_BG_ALPHA_VALUE(BG_ALPHA_VALUE) ((BG_ALPHA_VALUE) <= COLOR_VALUE)
-#define IS_DMA2D_BGC_BLUE(BGC_BLUE) ((BGC_BLUE) <= COLOR_VALUE)
-#define IS_DMA2D_BGC_GREEN(BGC_GREEN) ((BGC_GREEN) <= COLOR_VALUE)
-#define IS_DMA2D_BGC_RED(BGC_RED) ((BGC_RED) <= COLOR_VALUE)
-
-/**
- * @}
- */
-
-/** DMA2D_FGPFC_ALPHA_MODE
- * @{
- */
-
-#define NO_MODIF_ALPHA_VALUE ((uint32_t)0x00000000)
-#define REPLACE_ALPHA_VALUE ((uint32_t)0x00000001)
-#define COMBINE_ALPHA_VALUE ((uint32_t)0x00000002)
-
-#define IS_DMA2D_FG_ALPHA_MODE(FG_ALPHA_MODE) (((FG_ALPHA_MODE) == NO_MODIF_ALPHA_VALUE) || \
- ((FG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \
- ((FG_ALPHA_MODE) == COMBINE_ALPHA_VALUE))
-
-#define IS_DMA2D_BG_ALPHA_MODE(BG_ALPHA_MODE) (((BG_ALPHA_MODE) == NO_MODIF_ALPHA_VALUE) || \
- ((BG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \
- ((BG_ALPHA_MODE) == COMBINE_ALPHA_VALUE))
-
-/**
- * @}
- */
-
-/** @defgroup DMA2D_Interrupts
- * @{
- */
-
-#define DMA2D_IT_CE DMA2D_CR_CEIE
-#define DMA2D_IT_CTC DMA2D_CR_CTCIE
-#define DMA2D_IT_CAE DMA2D_CR_CAEIE
-#define DMA2D_IT_TW DMA2D_CR_TWIE
-#define DMA2D_IT_TC DMA2D_CR_TCIE
-#define DMA2D_IT_TE DMA2D_CR_TEIE
-
-#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
- ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
- ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
-
-/**
- * @}
- */
-
-/** @defgroup DMA2D_Flag
- * @{
- */
-
-#define DMA2D_FLAG_CE DMA2D_ISR_CEIF
-#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF
-#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF
-#define DMA2D_FLAG_TW DMA2D_ISR_TWIF
-#define DMA2D_FLAG_TC DMA2D_ISR_TCIF
-#define DMA2D_FLAG_TE DMA2D_ISR_TEIF
-
-
-#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
- ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
- ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
-
-
-/**
- * @}
- */
-
-/** @defgroup DMA2D_DeadTime
- * @{
- */
-
-#define DEADTIME ((uint32_t)0x000000FF)
-
-#define IS_DMA2D_DEAD_TIME(DEAD_TIME) ((DEAD_TIME) <= DEADTIME)
-
-
-#define LINE_WATERMARK DMA2D_LWR_LW
-
-#define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the DMA2D configuration to the default reset state *****/
-void DMA2D_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void DMA2D_Init(DMA2D_InitTypeDef* DMA2D_InitStruct);
-void DMA2D_StructInit(DMA2D_InitTypeDef* DMA2D_InitStruct);
-void DMA2D_StartTransfer(void);
-void DMA2D_AbortTransfer(void);
-void DMA2D_Suspend(FunctionalState NewState);
-void DMA2D_FGConfig(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct);
-void DMA2D_FG_StructInit(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct);
-void DMA2D_BGConfig(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct);
-void DMA2D_BG_StructInit(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct);
-void DMA2D_FGStart(FunctionalState NewState);
-void DMA2D_BGStart(FunctionalState NewState);
-void DMA2D_DeadTimeConfig(uint32_t DMA2D_DeadTime, FunctionalState NewState);
-void DMA2D_LineWatermarkConfig(uint32_t DMA2D_LWatermarkConfig);
-
-/* Interrupts and flags management functions **********************************/
-void DMA2D_ITConfig(uint32_t DMA2D_IT, FunctionalState NewState);
-FlagStatus DMA2D_GetFlagStatus(uint32_t DMA2D_FLAG);
-void DMA2D_ClearFlag(uint32_t DMA2D_FLAG);
-ITStatus DMA2D_GetITStatus(uint32_t DMA2D_IT);
-void DMA2D_ClearITPendingBit(uint32_t DMA2D_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_DMA2D_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_dsi.c b/底盘/底盘-old/底盘/Library/stm32f4xx_dsi.c
deleted file mode 100644
index 0a4abe4..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_dsi.c
+++ /dev/null
@@ -1,1762 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_dsi.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Display Serial Interface (DSI):
- * + Initialization and Configuration
- * + Data transfers management functions
- * + Low Power functions
- * + Interrupts and flags management
- *
-@verbatim
-
- ===================================================================
- ##### How to use this driver #####
- ===================================================================
- [..]
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_dsi.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-/** @addtogroup DSI
- * @brief DSI driver modules
- * @{
- */
-#if defined(STM32F469_479xx)
-
-/* Private types -------------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @addtogroup DSI_Private_Constants
- * @{
- */
-#define DSI_TIMEOUT_VALUE ((uint32_t)1000) /* 1s */
-
-#define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \
- DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \
- DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \
- DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15)
-#define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4)
-#define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX
-#define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX
-#define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME)
-#define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE
-#define DSI_ERROR_PSE_MASK DSI_ISR1_PSE
-#define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE
-#define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE
-#define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE)
-
-#define DSI_MAX_RETURN_PKT_SIZE ((uint32_t)0x00000037) /*!< Maximum return packet configuration */
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1);
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DSI_Exported_Functions
- * @{
- */
-
-/** @defgroup DSI_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the DSI
- (+) De-initialize the DSI
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initializes the DSI peripheral registers to their default reset
- * values.
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @retval None
- */
-void DSI_DeInit(DSI_TypeDef *DSIx)
-{
- /* Disable the DSI wrapper */
- DSIx->WCR &= ~DSI_WCR_DSIEN;
-
- /* Disable the DSI host */
- DSIx->CR &= ~DSI_CR_EN;
-
- /* D-PHY clock and digital disable */
- DSIx->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN);
-
- /* Turn off the DSI PLL */
- DSIx->WRPCR &= ~DSI_WRPCR_PLLEN;
-
- /* Disable the regulator */
- DSIx->WRPCR &= ~DSI_WRPCR_REGEN;
-
- /* Check the parameters */
- assert_param(IS_DSI_ALL_PERIPH(DSIx));
- if(DSIx == DSI)
- {
- /* Enable DSI reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_DSI, ENABLE);
- /* Release DSI from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_DSI, DISABLE);
- }
-}
-
-/**
- * @brief Deinitialize the DSIx peripheral registers to their default reset values.
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @param DSI_InitStruct: pointer to a DSI_InitTypeDef structure that
- * contains the configuration information for the specified DSI peripheral.
- * @param DSI_InitTIMStruct: pointer to a DSI_TIMTypeDef structure that
- * contains the configuration information for the specified DSI Timings.
- * @retval None
- */
-void DSI_Init(DSI_TypeDef *DSIx,DSI_InitTypeDef* DSI_InitStruct, DSI_PLLInitTypeDef *PLLInit)
-{
- uint32_t unitIntervalx4 = 0;
- uint32_t tempIDF = 0;
-
- /* Check function parameters */
- assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV));
- assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF));
- assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF));
- assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(DSI_InitStruct->AutomaticClockLaneControl));
- assert_param(IS_DSI_NUMBER_OF_LANES(DSI_InitStruct->NumberOfLanes));
-
- /**************** Turn on the regulator and enable the DSI PLL ****************/
-
- /* Enable the regulator */
- DSIx->WRPCR |= DSI_WRPCR_REGEN;
-
- /* Wait until the regulator is ready */
- while(DSI_GetFlagStatus(DSIx, DSI_FLAG_RRS) == RESET )
- {}
-
- /* Set the PLL division factors */
- DSIx->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
- DSIx->WRPCR |= (((PLLInit->PLLNDIV)<<2) | ((PLLInit->PLLIDF)<<11) | ((PLLInit->PLLODF)<<16));
-
- /* Enable the DSI PLL */
- DSIx->WRPCR |= DSI_WRPCR_PLLEN;
-
- /* Wait for the lock of the PLL */
- while(DSI_GetFlagStatus(DSIx, DSI_FLAG_PLLLS) == RESET)
- {}
-
- /*************************** Set the PHY parameters ***************************/
-
- /* D-PHY clock and digital enable*/
- DSIx->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
-
- /* Clock lane configuration */
- DSIx->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
- DSIx->CLCR |= (DSI_CLCR_DPCC | DSI_InitStruct->AutomaticClockLaneControl);
-
- /* Configure the number of active data lanes */
- DSIx->PCONFR &= ~DSI_PCONFR_NL;
- DSIx->PCONFR |= DSI_InitStruct->NumberOfLanes;
-
- /************************ Set the DSI clock parameters ************************/
- /* Set the TX escape clock division factor */
- DSIx->CCR &= ~DSI_CCR_TXECKDIV;
- DSIx->CCR = DSI_InitStruct->TXEscapeCkdiv;
-
- /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
- /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
- /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */
- tempIDF = (PLLInit->PLLIDF > 0) ? PLLInit->PLLIDF : 1;
- unitIntervalx4 = (4000000 * tempIDF * (1 << PLLInit->PLLODF)) / ((HSE_VALUE/1000) * PLLInit->PLLNDIV);
-
- /* Set the bit period in high-speed mode */
- DSIx->WPCR[0] &= ~DSI_WPCR0_UIX4;
- DSIx->WPCR[0] |= unitIntervalx4;
-
- /****************************** Error management *****************************/
- /* Disable all error interrupts */
- DSIx->IER[0] = 0;
- DSIx->IER[1] = 0;
-}
-
-/**
- * @brief Fills each DSI_InitStruct member with its default value.
- * @param DSI_InitStruct: pointer to a DSI_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void DSI_StructInit(DSI_InitTypeDef* DSI_InitStruct, DSI_HOST_TimeoutTypeDef* DSI_HOST_TimeoutInitStruct)
-{
- /*--------------- Reset DSI init structure parameters values ---------------*/
- /* Initialize the AutomaticClockLaneControl member */
- DSI_InitStruct->AutomaticClockLaneControl = DSI_AUTO_CLK_LANE_CTRL_DISABLE;
- /* Initialize the NumberOfLanes member */
- DSI_InitStruct->NumberOfLanes = DSI_ONE_DATA_LANE;
- /* Initialize the TX Escape clock division */
- DSI_InitStruct->TXEscapeCkdiv = 0;
-
- /*--------------- Reset DSI timings init structure parameters values -------*/
- /* Initialize the TimeoutCkdiv member */
- DSI_HOST_TimeoutInitStruct->TimeoutCkdiv = 0;
- /* Initialize the HighSpeedTransmissionTimeout member */
- DSI_HOST_TimeoutInitStruct->HighSpeedTransmissionTimeout = 0;
- /* Initialize the LowPowerReceptionTimeout member */
- DSI_HOST_TimeoutInitStruct->LowPowerReceptionTimeout = 0;
- /* Initialize the HighSpeedReadTimeout member */
- DSI_HOST_TimeoutInitStruct->HighSpeedReadTimeout = 0;
- /* Initialize the LowPowerReadTimeout member */
- DSI_HOST_TimeoutInitStruct->LowPowerReadTimeout = 0;
- /* Initialize the HighSpeedWriteTimeout member */
- DSI_HOST_TimeoutInitStruct->HighSpeedWriteTimeout = 0;
- /* Initialize the HighSpeedWritePrespMode member */
- DSI_HOST_TimeoutInitStruct->HighSpeedWritePrespMode = 0;
- /* Initialize the LowPowerWriteTimeout member */
- DSI_HOST_TimeoutInitStruct->LowPowerWriteTimeout = 0;
- /* Initialize the BTATimeout member */
- DSI_HOST_TimeoutInitStruct->BTATimeout = 0;
-}
-
-/**
- * @brief Configure the Generic interface read-back Virtual Channel ID.
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @param VirtualChannelID: Virtual channel ID
- * @retval None
- */
-void DSI_SetGenericVCID(DSI_TypeDef *DSIx, uint32_t VirtualChannelID)
-{
- /* Update the GVCID register */
- DSIx->GVCIDR &= ~DSI_GVCIDR_VCID;
- DSIx->GVCIDR |= VirtualChannelID;
-}
-
-/**
- * @brief Select video mode and configure the corresponding parameters
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains
- * the DSI video mode configuration parameters
- * @retval None
- */
-void DSI_ConfigVideoMode(DSI_TypeDef *DSIx, DSI_VidCfgTypeDef *VidCfg)
-{
- /* Check the parameters */
- assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding));
- assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode));
- assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable));
- assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable));
- assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable));
- assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable));
- assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable));
- assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable));
- assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable));
- assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable));
- assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity));
- assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));
- assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));
- /* Check the LooselyPacked variant only in 18-bit mode */
- if(VidCfg->ColorCoding == DSI_RGB666)
- {
- assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));
- }
-
- /* Select video mode by resetting CMDM and DSIM bits */
- DSIx->MCR &= ~DSI_MCR_CMDM;
- DSIx->WCFGR &= ~DSI_WCFGR_DSIM;
-
- /* Configure the video mode transmission type */
- DSIx->VMCR &= ~DSI_VMCR_VMT;
- DSIx->VMCR |= VidCfg->Mode;
-
- /* Configure the video packet size */
- DSIx->VPCR &= ~DSI_VPCR_VPSIZE;
- DSIx->VPCR |= VidCfg->PacketSize;
-
- /* Set the chunks number to be transmitted through the DSI link */
- DSIx->VCCR &= ~DSI_VCCR_NUMC;
- DSIx->VCCR |= VidCfg->NumberOfChunks;
-
- /* Set the size of the null packet */
- DSIx->VNPCR &= ~DSI_VNPCR_NPSIZE;
- DSIx->VNPCR |= VidCfg->NullPacketSize;
-
- /* Select the virtual channel for the LTDC interface traffic */
- DSIx->LVCIDR &= ~DSI_LVCIDR_VCID;
- DSIx->LVCIDR |= VidCfg->VirtualChannelID;
-
- /* Configure the polarity of control signals */
- DSIx->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
- DSIx->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity);
-
- /* Select the color coding for the host */
- DSIx->LCOLCR &= ~DSI_LCOLCR_COLC;
- DSIx->LCOLCR |= VidCfg->ColorCoding;
-
- /* Select the color coding for the wrapper */
- DSIx->WCFGR &= ~DSI_WCFGR_COLMUX;
- DSIx->WCFGR |= ((VidCfg->ColorCoding)<<1);
-
- /* Enable/disable the loosely packed variant to 18-bit configuration */
- if(VidCfg->ColorCoding == DSI_RGB666)
- {
- DSIx->LCOLCR &= ~DSI_LCOLCR_LPE;
- DSIx->LCOLCR |= VidCfg->LooselyPacked;
- }
-
- /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */
- DSIx->VHSACR &= ~DSI_VHSACR_HSA;
- DSIx->VHSACR |= VidCfg->HorizontalSyncActive;
-
- /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */
- DSIx->VHBPCR &= ~DSI_VHBPCR_HBP;
- DSIx->VHBPCR |= VidCfg->HorizontalBackPorch;
-
- /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */
- DSIx->VLCR &= ~DSI_VLCR_HLINE;
- DSIx->VLCR |= VidCfg->HorizontalLine;
-
- /* Set the Vertical Synchronization Active (VSA) */
- DSIx->VVSACR &= ~DSI_VVSACR_VSA;
- DSIx->VVSACR |= VidCfg->VerticalSyncActive;
-
- /* Set the Vertical Back Porch (VBP)*/
- DSIx->VVBPCR &= ~DSI_VVBPCR_VBP;
- DSIx->VVBPCR |= VidCfg->VerticalBackPorch;
-
- /* Set the Vertical Front Porch (VFP)*/
- DSIx->VVFPCR &= ~DSI_VVFPCR_VFP;
- DSIx->VVFPCR |= VidCfg->VerticalFrontPorch;
-
- /* Set the Vertical Active period*/
- DSIx->VVACR &= ~DSI_VVACR_VA;
- DSIx->VVACR |= VidCfg->VerticalActive;
-
- /* Configure the command transmission mode */
- DSIx->VMCR &= ~DSI_VMCR_LPCE;
- DSIx->VMCR |= VidCfg->LPCommandEnable;
-
- /* Low power largest packet size */
- DSIx->LPMCR &= ~DSI_LPMCR_LPSIZE;
- DSIx->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16);
-
- /* Low power VACT largest packet size */
- DSIx->LPMCR &= ~DSI_LPMCR_VLPSIZE;
- DSIx->LPMCR |= VidCfg->LPVACTLargestPacketSize;
-
- /* Enable LP transition in HFP period */
- DSIx->VMCR &= ~DSI_VMCR_LPHFPE;
- DSIx->VMCR |= VidCfg->LPHorizontalFrontPorchEnable;
-
- /* Enable LP transition in HBP period */
- DSIx->VMCR &= ~DSI_VMCR_LPHBPE;
- DSIx->VMCR |= VidCfg->LPHorizontalBackPorchEnable;
-
- /* Enable LP transition in VACT period */
- DSIx->VMCR &= ~DSI_VMCR_LPVAE;
- DSIx->VMCR |= VidCfg->LPVerticalActiveEnable;
-
- /* Enable LP transition in VFP period */
- DSIx->VMCR &= ~DSI_VMCR_LPVFPE;
- DSIx->VMCR |= VidCfg->LPVerticalFrontPorchEnable;
-
- /* Enable LP transition in VBP period */
- DSIx->VMCR &= ~DSI_VMCR_LPVBPE;
- DSIx->VMCR |= VidCfg->LPVerticalBackPorchEnable;
-
- /* Enable LP transition in vertical sync period */
- DSIx->VMCR &= ~DSI_VMCR_LPVSAE;
- DSIx->VMCR |= VidCfg->LPVerticalSyncActiveEnable;
-
- /* Enable the request for an acknowledge response at the end of a frame */
- DSIx->VMCR &= ~DSI_VMCR_FBTAAE;
- DSIx->VMCR |= VidCfg->FrameBTAAcknowledgeEnable;
-}
-
-/**
- * @brief Select adapted command mode and configure the corresponding parameters
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains
- * the DSI command mode configuration parameters
- * @retval None
- */
-void DSI_ConfigAdaptedCommandMode(DSI_TypeDef *DSIx, DSI_CmdCfgTypeDef *CmdCfg)
-{
- /* Check the parameters */
- assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding));
- assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource));
- assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity));
- assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh));
- assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol));
- assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest));
- assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity));
- assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity));
- assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity));
-
- /* Select command mode by setting CMDM and DSIM bits */
- DSIx->MCR |= DSI_MCR_CMDM;
- DSIx->WCFGR &= ~DSI_WCFGR_DSIM;
- DSIx->WCFGR |= DSI_WCFGR_DSIM;
-
- /* Select the virtual channel for the LTDC interface traffic */
- DSIx->LVCIDR &= ~DSI_LVCIDR_VCID;
- DSIx->LVCIDR |= CmdCfg->VirtualChannelID;
-
- /* Configure the polarity of control signals */
- DSIx->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
- DSIx->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity);
-
- /* Select the color coding for the host */
- DSIx->LCOLCR &= ~DSI_LCOLCR_COLC;
- DSIx->LCOLCR |= CmdCfg->ColorCoding;
-
- /* Select the color coding for the wrapper */
- DSIx->WCFGR &= ~DSI_WCFGR_COLMUX;
- DSIx->WCFGR |= ((CmdCfg->ColorCoding)<<1);
-
- /* Configure the maximum allowed size for write memory command */
- DSIx->LCCR &= ~DSI_LCCR_CMDSIZE;
- DSIx->LCCR |= CmdCfg->CommandSize;
-
- /* Configure the tearing effect source and polarity and select the refresh mode */
- DSIx->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);
- DSIx->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol);
-
- /* Configure the tearing effect acknowledge request */
- DSIx->CMCR &= ~DSI_CMCR_TEARE;
- DSIx->CMCR |= CmdCfg->TEAcknowledgeRequest;
-
- /* Enable the Tearing Effect interrupt */
- DSI_ITConfig(DSIx, DSI_IT_TE, ENABLE);
- /* Enable the End of Refresh interrupt */
- DSI_ITConfig(DSIx, DSI_IT_ER, ENABLE);
-}
-
-/**
- * @brief Configure command transmission mode: High-speed or Low-power
- * and enable/disable acknowledge request after packet transmission
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @param LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains
- * the DSI command transmission mode configuration parameters
- * @retval None
- */
-void DSI_ConfigCommand(DSI_TypeDef *DSIx, DSI_LPCmdTypeDef *LPCmd)
-{
- assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP));
- assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP));
- assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP));
- assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP));
- assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP));
- assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP));
- assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite));
- assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP));
- assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP));
- assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP));
- assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite));
- assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket));
- assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));
-
- /* Select High-speed or Low-power for command transmission */
- DSIx->CMCR &= ~(DSI_CMCR_GSW0TX |\
- DSI_CMCR_GSW1TX |\
- DSI_CMCR_GSW2TX |\
- DSI_CMCR_GSR0TX |\
- DSI_CMCR_GSR1TX |\
- DSI_CMCR_GSR2TX |\
- DSI_CMCR_GLWTX |\
- DSI_CMCR_DSW0TX |\
- DSI_CMCR_DSW1TX |\
- DSI_CMCR_DSR0TX |\
- DSI_CMCR_DLWTX |\
- DSI_CMCR_MRDPS);
- DSIx->CMCR |= (LPCmd->LPGenShortWriteNoP |\
- LPCmd->LPGenShortWriteOneP |\
- LPCmd->LPGenShortWriteTwoP |\
- LPCmd->LPGenShortReadNoP |\
- LPCmd->LPGenShortReadOneP |\
- LPCmd->LPGenShortReadTwoP |\
- LPCmd->LPGenLongWrite |\
- LPCmd->LPDcsShortWriteNoP |\
- LPCmd->LPDcsShortWriteOneP |\
- LPCmd->LPDcsShortReadNoP |\
- LPCmd->LPDcsLongWrite |\
- LPCmd->LPMaxReadPacket);
-
- /* Configure the acknowledge request after each packet transmission */
- DSIx->CMCR &= ~DSI_CMCR_ARE;
- DSIx->CMCR |= LPCmd->AcknowledgeRequest;
-}
-
-/**
- * @brief Configure the flow control parameters
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @param FlowControl: flow control feature(s) to be enabled.
- * This parameter can be any combination of @ref DSI_FlowControl.
- * @retval None
- */
-void DSI_ConfigFlowControl(DSI_TypeDef *DSIx, uint32_t FlowControl)
-{
- /* Check the parameters */
- assert_param(IS_DSI_FLOW_CONTROL(FlowControl));
-
- /* Set the DSI Host Protocol Configuration Register */
- DSIx->PCR &= ~DSI_FLOW_CONTROL_ALL;
- DSIx->PCR |= FlowControl;
-}
-
-/**
- * @brief Configure the DSI PHY timer parameters
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @param PhyTimers: DSI_PHY_TimerTypeDef structure that contains
- * the DSI PHY timing parameters
- * @retval None
- */
-void DSI_ConfigPhyTimer(DSI_TypeDef *DSIx, DSI_PHY_TimerTypeDef *PhyTimers)
-{
- uint32_t maxTime = 0;
-
- maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime;
-
- /* Clock lane timer configuration */
- /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two
- High-Speed transmission.
- To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
- to Low-Power and from Low-Power to High-Speed.
- This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR).
- But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
-
- Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
- */
- DSIx->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);
- DSIx->CLTCR |= (maxTime | ((maxTime)<<16));
-
- /* Data lane timer configuration */
- DSIx->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);
- DSIx->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16) | ((PhyTimers->DataLaneHS2LPTime)<<24));
-
- /* Configure the wait period to request HS transmission after a stop state */
- DSIx->PCONFR &= ~DSI_PCONFR_SW_TIME;
- DSIx->PCONFR |= ((PhyTimers->StopWaitTime)<<8);
-}
-
-/**
- * @brief Configure the DSI HOST timeout parameters
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @param HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains
- * the DSI host timeout parameters
- * @retval None
- */
-void DSI_ConfigHostTimeouts(DSI_TypeDef *DSIx, DSI_HOST_TimeoutTypeDef *HostTimeouts)
-{
- /* Set the timeout clock division factor */
- DSIx->CCR &= ~DSI_CCR_TOCKDIV;
- DSIx->CCR = ((HostTimeouts->TimeoutCkdiv)<<8);
-
- /* High-speed transmission timeout */
- DSIx->TCCR[0] &= ~DSI_TCCR0_HSTX_TOCNT;
- DSIx->TCCR[0] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16);
-
- /* Low-power reception timeout */
- DSIx->TCCR[0] &= ~DSI_TCCR0_LPRX_TOCNT;
- DSIx->TCCR[0] |= HostTimeouts->LowPowerReceptionTimeout;
-
- /* High-speed read timeout */
- DSIx->TCCR[1] &= ~DSI_TCCR1_HSRD_TOCNT;
- DSIx->TCCR[1] |= HostTimeouts->HighSpeedReadTimeout;
-
- /* Low-power read timeout */
- DSIx->TCCR[2] &= ~DSI_TCCR2_LPRD_TOCNT;
- DSIx->TCCR[2] |= HostTimeouts->LowPowerReadTimeout;
-
- /* High-speed write timeout */
- DSIx->TCCR[3] &= ~DSI_TCCR3_HSWR_TOCNT;
- DSIx->TCCR[3] |= HostTimeouts->HighSpeedWriteTimeout;
-
- /* High-speed write presp mode */
- DSIx->TCCR[3] &= ~DSI_TCCR3_PM;
- DSIx->TCCR[3] |= HostTimeouts->HighSpeedWritePrespMode;
-
- /* Low-speed write timeout */
- DSIx->TCCR[4] &= ~DSI_TCCR4_LPWR_TOCNT;
- DSIx->TCCR[4] |= HostTimeouts->LowPowerWriteTimeout;
-
- /* BTA timeout */
- DSIx->TCCR[5] &= ~DSI_TCCR5_BTA_TOCNT;
- DSIx->TCCR[5] |= HostTimeouts->BTATimeout;
-}
-
-/**
- * @brief Start the DSI module
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * the configuration information for the DSI.
- * @retval None
- */
-void DSI_Start(DSI_TypeDef *DSIx)
-{
- /* Enable the DSI host */
- DSIx->CR |= DSI_CR_EN;
- /* Enable the DSI wrapper */
- DSIx->WCR |= DSI_WCR_DSIEN;
-}
-
-/**
- * @brief Stop the DSI module
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @retval None
- */
-void DSI_Stop(DSI_TypeDef *DSIx)
-{
- /* Disable the DSI host */
- DSIx->CR &= ~DSI_CR_EN;
-
- /* Disable the DSI wrapper */
- DSIx->WCR &= ~DSI_WCR_DSIEN;
-}
-
-/**
- * @brief Refresh the display in command mode
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * the configuration information for the DSI.
- * @retval None
- */
-void DSI_Refresh(DSI_TypeDef *DSIx)
-{
- /* Update the display */
- DSIx->WCR |= DSI_WCR_LTDCEN;
-}
-
-/**
- * @brief Controls the display color mode in Video mode
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @param ColorMode: Color mode (full or 8-colors).
- * This parameter can be any value of @ref DSI_Color_Mode
- * @retval None
- */
-void DSI_ColorMode(DSI_TypeDef *DSIx, uint32_t ColorMode)
-{
- /* Check the parameters */
- assert_param(IS_DSI_COLOR_MODE(ColorMode));
-
- /* Update the display color mode */
- DSIx->WCR &= ~DSI_WCR_COLM;
- DSIx->WCR |= ColorMode;
-}
-
-/**
- * @brief Control the display shutdown in Video mode
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @param Shutdown: Shut-down (Display-ON or Display-OFF).
- * This parameter can be any value of @ref DSI_ShutDown
- * @retval None
- */
-void DSI_Shutdown(DSI_TypeDef *DSIx, uint32_t Shutdown)
-{
- /* Check the parameters */
- assert_param(IS_DSI_SHUT_DOWN(Shutdown));
-
- /* Update the display Shutdown */
- DSIx->WCR &= ~DSI_WCR_SHTDN;
- DSIx->WCR |= Shutdown;
-}
-
-/**
- * @}
- */
-
-/** @defgroup Data transfers management functions
- * @brief DSI data transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers management functions #####
- ===============================================================================
-@endverbatim
- * @{
- */
-
-/**
- * @brief DCS or Generic short write command
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @param ChannelID: Virtual channel ID.
- * @param Mode: DSI short packet data type.
- * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
- * @param Param1: DSC command or first generic parameter.
- * This parameter can be any value of @ref DSI_DCS_Command or a
- * generic command code.
- * @param Param2: DSC parameter or second generic parameter.
- * @retval None
- */
-void DSI_ShortWrite(DSI_TypeDef *DSIx,
- uint32_t ChannelID,
- uint32_t Mode,
- uint32_t Param1,
- uint32_t Param2)
-{
- /* Check the parameters */
- assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));
-
- /* Wait for Command FIFO Empty */
- while((DSIx->GPSR & DSI_GPSR_CMDFE) == 0)
- {}
-
- /* Configure the packet to send a short DCS command with 0 or 1 parameter */
- DSI_ConfigPacketHeader(DSIx,
- ChannelID,
- Mode,
- Param1,
- Param2);
-}
-
-/**
- * @brief DCS or Generic long write command
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @param ChannelID: Virtual channel ID.
- * @param Mode: DSI long packet data type.
- * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type.
- * @param NbParams: Number of parameters.
- * @param Param1: DSC command or first generic parameter.
- * This parameter can be any value of @ref DSI_DCS_Command or a
- * generic command code
- * @param ParametersTable: Pointer to parameter values table.
- * @retval None
- */
-void DSI_LongWrite(DSI_TypeDef *DSIx,
- uint32_t ChannelID,
- uint32_t Mode,
- uint32_t NbParams,
- uint32_t Param1,
- uint8_t* ParametersTable)
-{
- uint32_t uicounter = 0;
-
- /* Check the parameters */
- assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode));
-
- /* Wait for Command FIFO Empty */
- while((DSIx->GPSR & DSI_GPSR_CMDFE) == 0)
- {}
-
- /* Set the DCS code hexadecimal on payload byte 1, and the other parameters on the write FIFO command*/
- while(uicounter < NbParams)
- {
- if(uicounter == 0x00)
- {
- DSIx->GPDR=(Param1 | \
- ((uint32_t)(*(ParametersTable+uicounter))<<8) | \
- ((uint32_t)(*(ParametersTable+uicounter+1))<<16) | \
- ((uint32_t)(*(ParametersTable+uicounter+2))<<24));
- uicounter += 3;
- }
- else
- {
- DSIx->GPDR=((*(ParametersTable+uicounter)) | \
- ((uint32_t)(*(ParametersTable+uicounter+1))<<8) | \
- ((uint32_t)(*(ParametersTable+uicounter+2))<<16) | \
- ((uint32_t)(*(ParametersTable+uicounter+3))<<24));
- uicounter+=4;
- }
- }
-
- /* Configure the packet to send a long DCS command */
- DSI_ConfigPacketHeader(DSIx,
- ChannelID,
- Mode,
- ((NbParams+1)&0x00FF),
- (((NbParams+1)&0xFF00)>>8));
-}
-
-/**
- * @brief Read command (DCS or generic)
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @param ChannelNbr: Virtual channel ID
- * @param Array: pointer to a buffer to store the payload of a read back operation.
- * @param Size: Data size to be read (in byte).
- * @param Mode: DSI read packet data type.
- * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type.
- * @param DCSCmd: DCS get/read command.
- * @param ParametersTable: Pointer to parameter values table.
- * @retval None
- */
-void DSI_Read(DSI_TypeDef *DSIx,
- uint32_t ChannelNbr,
- uint8_t* Array,
- uint32_t Size,
- uint32_t Mode,
- uint32_t DCSCmd,
- uint8_t* ParametersTable)
-{
-
- /* Check the parameters */
- assert_param(IS_DSI_READ_PACKET_TYPE(Mode));
-
- if(Size > 2)
- {
- /* set max return packet size */
- DSI_ShortWrite(DSIx, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((Size)&0xFF), (((Size)>>8)&0xFF));
- }
-
- /* Configure the packet to read command */
- if (Mode == DSI_DCS_SHORT_PKT_READ)
- {
- DSI_ConfigPacketHeader(DSIx, ChannelNbr, Mode, DCSCmd, 0);
- }
- else if (Mode == DSI_GEN_SHORT_PKT_READ_P0)
- {
- DSI_ConfigPacketHeader(DSIx, ChannelNbr, Mode, 0, 0);
- }
- else if (Mode == DSI_GEN_SHORT_PKT_READ_P1)
- {
- DSI_ConfigPacketHeader(DSIx, ChannelNbr, Mode, ParametersTable[0], 0);
- }
- else /* DSI_GEN_SHORT_PKT_READ_P2 */
- {
- DSI_ConfigPacketHeader(DSIx, ChannelNbr, Mode, ParametersTable[0], ParametersTable[1]);
- }
-
- /* Check that the payload read FIFO is not empty */
- while((DSIx->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE)
- {}
-
- /* Get the first byte */
- *((uint32_t *)Array) = (DSIx->GPDR);
- if (Size > 4)
- {
- Size -= 4;
- Array += 4;
- }
-
- /* Get the remaining bytes if any */
- while(((int)(Size)) > 0)
- {
- if((DSIx->GPSR & DSI_GPSR_PRDFE) == 0)
- {
- *((uint32_t *)Array) = (DSIx->GPDR);
- Size -= 4;
- Array += 4;
- }
- }
-}
-
-/**
- * @brief Generic DSI packet header configuration
- * @param DSIx: Pointer to DSI register base
- * @param ChannelID: Virtual channel ID of the header packet
- * @param DataType: Packet data type of the header packet
- * This parameter can be any value of :
- * @ref DSI_SHORT_WRITE_PKT_Data_Type
- * or @ref DSI_LONG_WRITE_PKT_Data_Type
- * or @ref DSI_SHORT_READ_PKT_Data_Type
- * or DSI_MAX_RETURN_PKT_SIZE
- * @param Data0: Word count LSB
- * @param Data1: Word count MSB
- * @retval None
- */
-static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
- uint32_t ChannelID,
- uint32_t DataType,
- uint32_t Data0,
- uint32_t Data1)
-{
- /* Update the DSI packet header with new information */
- DSIx->GHCR = (DataType | (ChannelID<<6) | (Data0<<8) | (Data1<<16));
-}
-
-/**
- * @}
- */
-
-/** @defgroup DSI_Group3 Low Power functions
- * @brief DSI Low Power management functions
- *
-@verbatim
- ===============================================================================
- ##### DSI Low Power functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
- * (only data lanes are in ULPM)
- * @param DSIx: Pointer to DSI register base
- * @retval None
- */
-void DSI_EnterULPMData(DSI_TypeDef *DSIx)
-{
- /* ULPS Request on Data Lanes */
- DSIx->PUCR |= DSI_PUCR_URDL;
-
-
- /* Wait until the D-PHY active lanes enter into ULPM */
- if((DSIx->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
- {
- while((DSIx->PSR & DSI_PSR_UAN0) != 0)
- {}
- }
- else /* DSI_TWO_DATA_LANES */
- {
- while((DSIx->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0)
- {}
- }
-}
-
-/**
- * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
- * (only data lanes are in ULPM)
- * @param DSIx: Pointer to DSI register base
- * @retval None
- */
-void DSI_ExitULPMData(DSI_TypeDef *DSIx)
-{
- /* Exit ULPS on Data Lanes */
- DSIx->PUCR |= DSI_PUCR_UEDL;
-
- /* Wait until all active lanes exit ULPM */
- if((DSIx->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
- {
- while((DSIx->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
- {}
- }
- else /* DSI_TWO_DATA_LANES */
- {
- while((DSIx->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
- {}
- }
-
- /* De-assert the ULPM requests and the ULPM exit bits */
- DSIx->PUCR = 0;
-}
-
-/**
- * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
- * (both data and clock lanes are in ULPM)
- * @param DSIx: Pointer to DSI register base
- * @retval None
- */
-void DSI_EnterULPM(DSI_TypeDef *DSIx)
-{
- /* Clock lane configuration: no more HS request */
- DSIx->CLCR &= ~DSI_CLCR_DPCC;
-
- /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */
- RCC_DSIClockSourceConfig(RCC_DSICLKSource_PLLR);
-
- /* ULPS Request on Clock and Data Lanes */
- DSIx->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL);
-
- /* Wait until all active lanes exit ULPM */
- if((DSIx->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
- {
- while((DSIx->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != 0)
- {}
- }
- else /* DSI_TWO_DATA_LANES */
- {
- while((DSIx->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != 0)
- {}
- }
-
- /* Turn off the DSI PLL */
- DSIx->WRPCR &= ~DSI_WRPCR_PLLEN;
-}
-
-/**
- * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
- * (both data and clock lanes are in ULPM)
- * @param DSIx: Pointer to DSI register base
- * @retval None
- */
-void DSI_ExitULPM(DSI_TypeDef *DSIx)
-{
- /* Turn on the DSI PLL */
- DSIx->WRPCR |= DSI_WRPCR_PLLEN;
-
- /* Wait for the lock of the PLL */
- while(DSI_GetFlagStatus(DSIx, DSI_FLAG_PLLLS) == RESET)
- {}
-
- /* Exit ULPS on Clock and Data Lanes */
- DSIx->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL);
-
- /* Wait until all active lanes exit ULPM */
- if((DSIx->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
- {
- while((DSIx->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
- {}
- }
- else /* DSI_TWO_DATA_LANES */
- {
- while((DSIx->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC))
- {}
- }
-
- /* De-assert the ULPM requests and the ULPM exit bits */
- DSIx->PUCR = 0;
-
- /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */
- RCC_DSIClockSourceConfig(RCC_DSICLKSource_PHY);
-
- /* Restore clock lane configuration to HS */
- DSIx->CLCR |= DSI_CLCR_DPCC;
-}
-
-/**
- * @brief Start test pattern generation
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @param Mode: Pattern generator mode
- * This parameter can be one of the following values:
- * 0 : Color bars (horizontal or vertical)
- * 1 : BER pattern (vertical only)
- * @param Orientation: Pattern generator orientation
- * This parameter can be one of the following values:
- * 0 : Vertical color bars
- * 1 : Horizontal color bars
- * @retval None
- */
-void DSI_PatternGeneratorStart(DSI_TypeDef *DSIx, uint32_t Mode, uint32_t Orientation)
-{
-
- /* Configure pattern generator mode and orientation */
- DSIx->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);
- DSIx->VMCR |= ((Mode<<20) | (Orientation<<24));
-
- /* Enable pattern generator by setting PGE bit */
- DSIx->VMCR |= DSI_VMCR_PGE;
-
-}
-
-/**
- * @brief Stop test pattern generation
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @retval None
- */
-void DSI_PatternGeneratorStop(DSI_TypeDef *DSIx)
-{
- /* Disable pattern generator by clearing PGE bit */
- DSIx->VMCR &= ~DSI_VMCR_PGE;
-}
-
-/**
- * @brief Set Slew-Rate And Delay Tuning
- * @param DSIx: Pointer to DSI register base
- * @param CommDelay: Communication delay to be adjusted.
- * This parameter can be any value of @ref DSI_Communication_Delay
- * @param Lane: select between clock or data lanes.
- * This parameter can be any value of @ref DSI_Lane_Group
- * @param Value: Custom value of the slew-rate or delay
- * @retval None
- */
-void DSI_SetSlewRateAndDelayTuning(DSI_TypeDef *DSIx, uint32_t CommDelay, uint32_t Lane, uint32_t Value)
-{
- /* Check function parameters */
- assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));
- assert_param(IS_DSI_LANE_GROUP(Lane));
-
- switch(CommDelay)
- {
- case DSI_SLEW_RATE_HSTX:
- if(Lane == DSI_CLOCK_LANE)
- {
- /* High-Speed Transmission Slew Rate Control on Clock Lane */
- DSIx->WPCR[1] &= ~DSI_WPCR1_HSTXSRCCL;
- DSIx->WPCR[1] |= Value<<16;
- }
- else /* DSI_DATA_LANES */
- {
- /* High-Speed Transmission Slew Rate Control on Data Lanes */
- DSIx->WPCR[1] &= ~DSI_WPCR1_HSTXSRCDL;
- DSIx->WPCR[1] |= Value<<18;
- }
- break;
- case DSI_SLEW_RATE_LPTX:
- if(Lane == DSI_CLOCK_LANE)
- {
- /* Low-Power transmission Slew Rate Compensation on Clock Lane */
- DSIx->WPCR[1] &= ~DSI_WPCR1_LPSRCCL;
- DSIx->WPCR[1] |= Value<<6;
- }
- else /* DSI_DATA_LANES */
- {
- /* Low-Power transmission Slew Rate Compensation on Data Lanes */
- DSIx->WPCR[1] &= ~DSI_WPCR1_LPSRCDL;
- DSIx->WPCR[1] |= Value<<8;
- }
- break;
- case DSI_HS_DELAY:
- if(Lane == DSI_CLOCK_LANE)
- {
- /* High-Speed Transmission Delay on Clock Lane */
- DSIx->WPCR[1] &= ~DSI_WPCR1_HSTXDCL;
- DSIx->WPCR[1] |= Value;
- }
- else /* DSI_DATA_LANES */
- {
- /* High-Speed Transmission Delay on Data Lanes */
- DSIx->WPCR[1] &= ~DSI_WPCR1_HSTXDDL;
- DSIx->WPCR[1] |= Value<<2;
- }
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Low-Power Reception Filter Tuning
- * @param DSIx: Pointer to DSI register base
- * @param Frequency: cutoff frequency of low-pass filter at the input of LPRX
- * @retval None
- */
-void DSI_SetLowPowerRXFilter(DSI_TypeDef *DSIx, uint32_t Frequency)
-{
- /* Low-Power RX low-pass Filtering Tuning */
- DSIx->WPCR[1] &= ~DSI_WPCR1_LPRXFT;
- DSIx->WPCR[1] |= Frequency<<25;
-}
-
-/**
- * @brief Activate an additional current path on all lanes to meet the SDDTx parameter
- * defined in the MIPI D-PHY specification
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
- * the configuration information for the DSI.
- * @param State: ENABLE or DISABLE
- * @retval None
- */
-void DSI_SetSDD(DSI_TypeDef *DSIx, FunctionalState State)
-{
- /* Check function parameters */
- assert_param(IS_FUNCTIONAL_STATE(State));
-
- /* Activate/Disactivate additional current path on all lanes */
- DSIx->WPCR[1] &= ~DSI_WPCR1_SDDC;
- DSIx->WPCR[1] |= ((uint32_t)State<<12);
-}
-
-/**
- * @brief Custom lane pins configuration
- * @param DSIx: Pointer to DSI register base
- * @param CustomLane: Function to be applyed on selected lane.
- * This parameter can be any value of @ref DSI_CustomLane
- * @param Lane: select between clock or data lane 0 or data lane 1.
- * This parameter can be any value of @ref DSI_Lane_Select
- * @param State: ENABLE or DISABLE
- * @retval None
- */
-void DSI_SetLanePinsConfiguration(DSI_TypeDef *DSIx, uint32_t CustomLane, uint32_t Lane, FunctionalState State)
-{
- /* Check function parameters */
- assert_param(IS_DSI_CUSTOM_LANE(CustomLane));
- assert_param(IS_DSI_LANE(Lane));
- assert_param(IS_FUNCTIONAL_STATE(State));
-
- switch(CustomLane)
- {
- case DSI_SWAP_LANE_PINS:
- if(Lane == DSI_CLOCK_LANE)
- {
- /* Swap pins on clock lane */
- DSIx->WPCR[0] &= ~DSI_WPCR0_SWCL;
- DSIx->WPCR[0] |= ((uint32_t)State<<6);
- }
- else if(Lane == DSI_DATA_LANE0)
- {
- /* Swap pins on data lane 0 */
- DSIx->WPCR[0] &= ~DSI_WPCR0_SWDL0;
- DSIx->WPCR[0] |= ((uint32_t)State<<7);
- }
- else /* DSI_DATA_LANE1 */
- {
- /* Swap pins on data lane 1 */
- DSIx->WPCR[0] &= ~DSI_WPCR0_SWDL1;
- DSIx->WPCR[0] |= ((uint32_t)State<<8);
- }
- break;
- case DSI_INVERT_HS_SIGNAL:
- if(Lane == DSI_CLOCK_LANE)
- {
- /* Invert HS signal on clock lane */
- DSIx->WPCR[0] &= ~DSI_WPCR0_HSICL;
- DSIx->WPCR[0] |= ((uint32_t)State<<9);
- }
- else if(Lane == DSI_DATA_LANE0)
- {
- /* Invert HS signal on data lane 0 */
- DSIx->WPCR[0] &= ~DSI_WPCR0_HSIDL0;
- DSIx->WPCR[0] |= ((uint32_t)State<<10);
- }
- else /* DSI_DATA_LANE1 */
- {
- /* Invert HS signal on data lane 1 */
- DSIx->WPCR[0] &= ~DSI_WPCR0_HSIDL1;
- DSIx->WPCR[0] |= ((uint32_t)State<<11);
- }
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Set custom timing for the PHY
- * @param DSIx: Pointer to DSI register base
- * @param Timing: PHY timing to be adjusted.
- * This parameter can be any value of @ref DSI_PHY_Timing
- * @param State: ENABLE or DISABLE
- * @param Value: Custom value of the timing
- * @retval None
- */
-void DSI_SetPHYTimings(DSI_TypeDef *DSIx, uint32_t Timing, FunctionalState State, uint32_t Value)
-{
- /* Check function parameters */
- assert_param(IS_DSI_PHY_TIMING(Timing));
- assert_param(IS_FUNCTIONAL_STATE(State));
-
- switch(Timing)
- {
- case DSI_TCLK_POST:
- /* Enable/Disable custom timing setting */
- DSIx->WPCR[0] &= ~DSI_WPCR0_TCLKPOSTEN;
- DSIx->WPCR[0] |= ((uint32_t)State<<27);
-
- if(State)
- {
- /* Set custom value */
- DSIx->WPCR[4] &= ~DSI_WPCR4_TCLKPOST;
- DSIx->WPCR[4] |= Value;
- }
-
- break;
- case DSI_TLPX_CLK:
- /* Enable/Disable custom timing setting */
- DSIx->WPCR[0] &= ~DSI_WPCR0_TLPXCEN;
- DSIx->WPCR[0] |= ((uint32_t)State<<26);
-
- if(State)
- {
- /* Set custom value */
- DSIx->WPCR[3] &= ~DSI_WPCR3_TLPXC;
- DSIx->WPCR[3] |= Value;
- }
-
- break;
- case DSI_THS_EXIT:
- /* Enable/Disable custom timing setting */
- DSIx->WPCR[0] &= ~DSI_WPCR0_THSEXITEN;
- DSIx->WPCR[0] |= ((uint32_t)State<<25);
-
- if(State)
- {
- /* Set custom value */
- DSIx->WPCR[3] &= ~DSI_WPCR3_THSEXIT;
- DSIx->WPCR[3] |= Value;
- }
-
- break;
- case DSI_TLPX_DATA:
- /* Enable/Disable custom timing setting */
- DSIx->WPCR[0] &= ~DSI_WPCR0_TLPXDEN;
- DSIx->WPCR[0] |= ((uint32_t)State<<24);
-
- if(State)
- {
- /* Set custom value */
- DSIx->WPCR[3] &= ~DSI_WPCR3_TLPXD;
- DSIx->WPCR[3] |= Value;
- }
-
- break;
- case DSI_THS_ZERO:
- /* Enable/Disable custom timing setting */
- DSIx->WPCR[0] &= ~DSI_WPCR0_THSZEROEN;
- DSIx->WPCR[0] |= ((uint32_t)State<<23);
-
- if(State)
- {
- /* Set custom value */
- DSIx->WPCR[3] &= ~DSI_WPCR3_THSZERO;
- DSIx->WPCR[3] |= Value;
- }
-
- break;
- case DSI_THS_TRAIL:
- /* Enable/Disable custom timing setting */
- DSIx->WPCR[0] &= ~DSI_WPCR0_THSTRAILEN;
- DSIx->WPCR[0] |= ((uint32_t)State<<22);
-
- if(State)
- {
- /* Set custom value */
- DSIx->WPCR[2] &= ~DSI_WPCR2_THSTRAIL;
- DSIx->WPCR[2] |= Value;
- }
-
- break;
- case DSI_THS_PREPARE:
- /* Enable/Disable custom timing setting */
- DSIx->WPCR[0] &= ~DSI_WPCR0_THSPREPEN;
- DSIx->WPCR[0] |= ((uint32_t)State<<21);
-
- if(State)
- {
- /* Set custom value */
- DSIx->WPCR[2] &= ~DSI_WPCR2_THSPREP;
- DSIx->WPCR[2] |= Value;
- }
-
- break;
- case DSI_TCLK_ZERO:
- /* Enable/Disable custom timing setting */
- DSIx->WPCR[0] &= ~DSI_WPCR0_TCLKZEROEN;
- DSIx->WPCR[0] |= ((uint32_t)State<<20);
-
- if(State)
- {
- /* Set custom value */
- DSIx->WPCR[2] &= ~DSI_WPCR2_TCLKZERO;
- DSIx->WPCR[2] |= Value;
- }
-
- break;
- case DSI_TCLK_PREPARE:
- /* Enable/Disable custom timing setting */
- DSIx->WPCR[0] &= ~DSI_WPCR0_TCLKPREPEN;
- DSIx->WPCR[0] |= ((uint32_t)State<<19);
-
- if(State)
- {
- /* Set custom value */
- DSIx->WPCR[2] &= ~DSI_WPCR2_TCLKPREP;
- DSIx->WPCR[2] |= Value;
- }
-
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Force the Clock/Data Lane in TX Stop Mode
- * @param DSIx: Pointer to DSI register base
- * @param Lane: select between clock or data lanes.
- * This parameter can be any value of @ref DSI_Lane_Group
- * @param State: ENABLE or DISABLE
- * @retval None
- */
-void DSI_ForceTXStopMode(DSI_TypeDef *DSIx, uint32_t Lane, FunctionalState State)
-{
- /* Check function parameters */
- assert_param(IS_DSI_LANE_GROUP(Lane));
- assert_param(IS_FUNCTIONAL_STATE(State));
-
- if(Lane == DSI_CLOCK_LANE)
- {
- /* Force/Unforce the Clock Lane in TX Stop Mode */
- DSIx->WPCR[0] &= ~DSI_WPCR0_FTXSMCL;
- DSIx->WPCR[0] |= ((uint32_t)State<<12);
- }
- else /* DSI_DATA_LANES */
- {
- /* Force/Unforce the Data Lanes in TX Stop Mode */
- DSIx->WPCR[0] &= ~DSI_WPCR0_FTXSMDL;
- DSIx->WPCR[0] |= ((uint32_t)State<<13);
- }
-}
-
-/**
- * @brief Forces LP Receiver in Low-Power Mode
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
- * the configuration information for the DSI.
- * @param State: ENABLE or DISABLE
- * @retval None
- */
-void DSI_ForceRXLowPower(DSI_TypeDef *DSIx, FunctionalState State)
-{
- /* Check function parameters */
- assert_param(IS_FUNCTIONAL_STATE(State));
-
- /* Force/Unforce LP Receiver in Low-Power Mode */
- DSIx->WPCR[1] &= ~DSI_WPCR1_FLPRXLPM;
- DSIx->WPCR[1] |= ((uint32_t)State<<22);
-}
-
-/**
- * @brief Force Data Lanes in RX Mode after a BTA
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
- * the configuration information for the DSI.
- * @param State: ENABLE or DISABLE
- * @retval None
- */
-void DSI_ForceDataLanesInRX(DSI_TypeDef *DSIx, FunctionalState State)
-{
- /* Check function parameters */
- assert_param(IS_FUNCTIONAL_STATE(State));
-
- /* Force Data Lanes in RX Mode */
- DSIx->WPCR[0] &= ~DSI_WPCR0_TDDL;
- DSIx->WPCR[0] |= ((uint32_t)State<<16);
-}
-
-/**
- * @brief Enable a pull-down on the lanes to prevent from floating states when unused
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
- * the configuration information for the DSI.
- * @param State: ENABLE or DISABLE
- * @retval None
- */
-void DSI_SetPullDown(DSI_TypeDef *DSIx, FunctionalState State)
-{
- /* Check function parameters */
- assert_param(IS_FUNCTIONAL_STATE(State));
-
- /* Enable/Disable pull-down on lanes */
- DSIx->WPCR[0] &= ~DSI_WPCR0_PDEN;
- DSIx->WPCR[0] |= ((uint32_t)State<<18);
-}
-
-/**
- * @brief Switch off the contention detection on data lanes
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
- * the configuration information for the DSI.
- * @param State: ENABLE or DISABLE
- * @retval None
- */
-void DSI_SetContentionDetectionOff(DSI_TypeDef *DSIx, FunctionalState State)
-{
- /* Check function parameters */
- assert_param(IS_FUNCTIONAL_STATE(State));
-
- /* Contention Detection on Data Lanes OFF */
- DSIx->WPCR[0] &= ~DSI_WPCR0_CDOFFDL;
- DSIx->WPCR[0] |= ((uint32_t)State<<14);
-}
-
-/**
- * @}
- */
-
-/** @defgroup DSI_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
- [..] This section provides a set of functions allowing to configure the DSI Interrupts
- sources and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to manage
- the communication: Polling mode or Interrupt mode.
-
- *** Polling Mode ***
- ====================
-[..] In Polling Mode, the DSI communication can be managed by 8 flags:
- (#) DSI_FLAG_TE : Tearing Effect Interrupt Flag
- (#) DSI_FLAG_ER : End of Refresh Interrupt Flag
- (#) DSI_FLAG_BUSY : Busy Flag
- (#) DSI_FLAG_PLLLS : PLL Lock Status
- (#) DSI_FLAG_PLLL : PLL Lock Interrupt Flag
- (#) DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
- (#) DSI_FLAG_RRS: Regulator Ready Status.
- (#) DSI_FLAG_RR: Regulator Ready Interrupt Flag.
-
-
- [..] In this Mode it is advised to use the following functions:
- (+) FlagStatus DSI_GetFlagStatus(DSI_TypeDef* DSIx, uint32_t DSI_FLAG);
- (+) void DSI_ClearFlag(DSI_TypeDef* DSIx, uint32_t DSI_FLAG);
-
- *** Interrupt Mode ***
- ======================
- [..] In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources
- and 7 pending bits:
- (+) Pending Bits:
- (##) DSI_IT_TE : Tearing Effect Interrupt Flag
- (##) DSI_IT_ER : End of Refresh Interrupt Flag
- (##) DSI_IT_PLLL : PLL Lock Interrupt Flag
- (##) DSI_IT_PLLU : PLL Unlock Interrupt Flag
- (##) DSI_IT_RR: Regulator Ready Interrupt Flag.
-
- (+) Interrupt Source:
- (##) DSI_IT_TE : Tearing Effect Interrupt Enable
- (##) DSI_IT_ER : End of Refresh Interrupt Enable
- (##) DSI_IT_PLLL : PLL Lock Interrupt Enable
- (##) DSI_IT_PLLU : PLL Unlock Interrupt Enable
- (##) DSI_IT_RR: Regulator Ready Interrupt Enable
-
- [..] In this Mode it is advised to use the following functions:
- (+) void DSI_ITConfig(DSI_TypeDef* DSIx, uint32_t DSI_IT, FunctionalState NewState);
- (+) ITStatus DSI_GetITStatus(DSI_TypeDef* DSIx, uint32_t DSI_IT);
- (+) void DSI_ClearITPendingBit(DSI_TypeDef* DSIx, uint32_t DSI_IT);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified DSI interrupts.
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @param DSI_IT: specifies the DSI interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg DSI_IT_TE : Tearing Effect Interrupt
- * @arg DSI_IT_ER : End of Refresh Interrupt
- * @arg DSI_IT_PLLL: PLL Lock Interrupt
- * @arg DSI_IT_PLLU: PLL Unlock Interrupt
- * @arg DSI_IT_RR : Regulator Ready Interrupt
- * @param NewState: new state of the specified DSI interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DSI_ITConfig(DSI_TypeDef* DSIx, uint32_t DSI_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DSI_ALL_PERIPH(DSIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_DSI_IT(DSI_IT));
-
- if(NewState != DISABLE)
- {
- /* Enable the selected DSI interrupt */
- DSIx->WIER |= DSI_IT;
- }
- else
- {
- /* Disable the selected DSI interrupt */
- DSIx->WIER &= ~DSI_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified DSI flag is set or not.
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @param DSI_FLAG: specifies the SPI flag to be checked.
- * This parameter can be one of the following values:
- * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
- * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
- * @arg DSI_FLAG_BUSY : Busy Flag
- * @arg DSI_FLAG_PLLLS: PLL Lock Status
- * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
- * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
- * @arg DSI_FLAG_RRS : Regulator Ready Flag
- * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
- * @retval The new state of DSI_FLAG (SET or RESET).
- */
-FlagStatus DSI_GetFlagStatus(DSI_TypeDef* DSIx, uint16_t DSI_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_DSI_ALL_PERIPH(DSIx));
- assert_param(IS_DSI_GET_FLAG(DSI_FLAG));
-
- /* Check the status of the specified DSI flag */
- if((DSIx->WISR & DSI_FLAG) != (uint32_t)RESET)
- {
- /* DSI_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* DSI_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the DSI_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the specified DSI flag.
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @param DSI_FLAG: specifies the SPI flag to be cleared.
- * This parameter can be one of the following values:
- * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
- * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
- * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
- * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
- * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
- * @retval None
- */
-void DSI_ClearFlag(DSI_TypeDef* DSIx, uint16_t DSI_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_DSI_ALL_PERIPH(DSIx));
- assert_param(IS_DSI_CLEAR_FLAG(DSI_FLAG));
-
- /* Clear the selected DSI flag */
- DSIx->WIFCR = (uint32_t)DSI_FLAG;
-}
-
-/**
- * @brief Checks whether the specified DSIx interrupt has occurred or not.
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @param DSI_IT: specifies the DSI interrupt sources to be checked.
- * This parameter can be one of the following values:
- * @arg DSI_IT_TE : Tearing Effect Interrupt
- * @arg DSI_IT_ER : End of Refresh Interrupt
- * @arg DSI_IT_PLLL: PLL Lock Interrupt
- * @arg DSI_IT_PLLU: PLL Unlock Interrupt
- * @arg DSI_IT_RR : Regulator Ready Interrupt
- * @retval The new state of SPI_I2S_IT (SET or RESET).
- */
-ITStatus DSI_GetITStatus(DSI_TypeDef* DSIx, uint32_t DSI_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_DSI_ALL_PERIPH(DSIx));
- assert_param(IS_DSI_IT(DSI_IT));
-
- /* Get the DSI_IT enable bit status */
- enablestatus = (DSIx->WIER & DSI_IT);
-
- /* Check the status of the specified SPI interrupt */
- if (((DSIx->WISR & DSI_IT) != (uint32_t)RESET) && enablestatus)
- {
- /* DSI_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* DSI_IT is reset */
- bitstatus = RESET;
- }
-
- /* Return the DSI_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DSIx interrupt pending bit.
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @param DSI_IT: specifies the DSI interrupt sources to be cleared.
- * This parameter can be one of the following values:
- * @arg DSI_IT_TE : Tearing Effect Interrupt
- * @arg DSI_IT_ER : End of Refresh Interrupt
- * @arg DSI_IT_PLLL: PLL Lock Interrupt
- * @arg DSI_IT_PLLU: PLL Unlock Interrupt
- * @arg DSI_IT_RR : Regulator Ready Interrupt
- * @retval None
- */
-void DSI_ClearITPendingBit(DSI_TypeDef* DSIx, uint32_t DSI_IT)
-{
- /* Check the parameters */
- assert_param(IS_DSI_ALL_PERIPH(DSIx));
- assert_param(IS_DSI_IT(DSI_IT));
-
- /* Clear the selected DSI interrupt pending bit */
- DSIx->WIFCR = (uint32_t)DSI_IT;
-}
-
-/**
- * @brief Enable the error monitor flags
- * @param DSIx: To select the DSIx peripheral, where x can be the different DSI instances
- * @param ActiveErrors: indicates which error interrupts will be enabled.
- * This parameter can be any combination of @ref DSI_Error_Data_Type.
- * @retval None
- */
-void DSI_ConfigErrorMonitor(DSI_TypeDef *DSIx, uint32_t ActiveErrors)
-{
- DSIx->IER[0] = 0;
- DSIx->IER[1] = 0;
-
- if((ActiveErrors & DSI_ERROR_ACK) != RESET)
- {
- /* Enable the interrupt generation on selected errors */
- DSIx->IER[0] |= DSI_ERROR_ACK_MASK;
- }
-
- if((ActiveErrors & DSI_ERROR_PHY) != RESET)
- {
- /* Enable the interrupt generation on selected errors */
- DSIx->IER[0] |= DSI_ERROR_PHY_MASK;
- }
-
- if((ActiveErrors & DSI_ERROR_TX) != RESET)
- {
- /* Enable the interrupt generation on selected errors */
- DSIx->IER[1] |= DSI_ERROR_TX_MASK;
- }
-
- if((ActiveErrors & DSI_ERROR_RX) != RESET)
- {
- /* Enable the interrupt generation on selected errors */
- DSIx->IER[1] |= DSI_ERROR_RX_MASK;
- }
-
- if((ActiveErrors & DSI_ERROR_ECC) != RESET)
- {
- /* Enable the interrupt generation on selected errors */
- DSIx->IER[1] |= DSI_ERROR_ECC_MASK;
- }
-
- if((ActiveErrors & DSI_ERROR_CRC) != RESET)
- {
- /* Enable the interrupt generation on selected errors */
- DSIx->IER[1] |= DSI_ERROR_CRC_MASK;
- }
-
- if((ActiveErrors & DSI_ERROR_PSE) != RESET)
- {
- /* Enable the interrupt generation on selected errors */
- DSIx->IER[1] |= DSI_ERROR_PSE_MASK;
- }
-
- if((ActiveErrors & DSI_ERROR_EOT) != RESET)
- {
- /* Enable the interrupt generation on selected errors */
- DSIx->IER[1] |= DSI_ERROR_EOT_MASK;
- }
-
- if((ActiveErrors & DSI_ERROR_OVF) != RESET)
- {
- /* Enable the interrupt generation on selected errors */
- DSIx->IER[1] |= DSI_ERROR_OVF_MASK;
- }
-
- if((ActiveErrors & DSI_ERROR_GEN) != RESET)
- {
- /* Enable the interrupt generation on selected errors */
- DSIx->IER[1] |= DSI_ERROR_GEN_MASK;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* STM32F469_479xx */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_dsi.h b/底盘/底盘-old/底盘/Library/stm32f4xx_dsi.h
deleted file mode 100644
index 1d0186d..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_dsi.h
+++ /dev/null
@@ -1,1003 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_dsi.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief Header file of DSI module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_DSI_H
-#define __STM32F4xx_DSI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DSI
- * @{
- */
-#if defined(STM32F469_479xx)
-/* Exported types ------------------------------------------------------------*/
-/**
- * @brief DSI Init Structure definition
- */
-typedef struct
-{
- uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control
- This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */
-
- uint32_t TXEscapeCkdiv; /*!< TX Escape clock division
- The values 0 and 1 stop the TX_ESC clock generation */
-
- uint32_t NumberOfLanes; /*!< Number of lanes
- This parameter can be any value of @ref DSI_Number_Of_Lanes */
-
-}DSI_InitTypeDef;
-
-/**
- * @brief DSI PLL Clock structure definition
- */
-typedef struct
-{
- uint32_t PLLNDIV; /*!< PLL Loop Division Factor
- This parameter must be a value between 10 and 125 */
-
- uint32_t PLLIDF; /*!< PLL Input Division Factor
- This parameter can be any value of @ref DSI_PLL_IDF */
-
- uint32_t PLLODF; /*!< PLL Output Division Factor
- This parameter can be any value of @ref DSI_PLL_ODF */
-
-}DSI_PLLInitTypeDef;
-
-/**
- * @brief DSI Video mode configuration
- */
-typedef struct
-{
- uint32_t VirtualChannelID; /*!< Virtual channel ID */
-
- uint32_t ColorCoding; /*!< Color coding for LTDC interface
- This parameter can be any value of @ref DSI_Color_Coding */
-
- uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using
- 18-bit configuration).
- This parameter can be any value of @ref DSI_LooselyPacked */
-
- uint32_t Mode; /*!< Video mode type
- This parameter can be any value of @ref DSI_Video_Mode_Type */
-
- uint32_t PacketSize; /*!< Video packet size */
-
- uint32_t NumberOfChunks; /*!< Number of chunks */
-
- uint32_t NullPacketSize; /*!< Null packet size */
-
- uint32_t HSPolarity; /*!< HSYNC pin polarity
- This parameter can be any value of @ref DSI_HSYNC_Polarity */
-
- uint32_t VSPolarity; /*!< VSYNC pin polarity
- This parameter can be any value of @ref DSI_VSYNC_Polarity */
-
- uint32_t DEPolarity; /*!< Data Enable pin polarity
- This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
-
- uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */
-
- uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */
-
- uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */
-
- uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */
-
- uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */
-
- uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */
-
- uint32_t VerticalActive; /*!< Vertical active duration */
-
- uint32_t LPCommandEnable; /*!< Low-power command enable
- This parameter can be any value of @ref DSI_LP_Command */
-
- uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
- can fit in a line during VSA, VBP and VFP regions */
-
- uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
- can fit in a line during VACT region */
-
- uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable
- This parameter can be any value of @ref DSI_LP_HFP */
-
- uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable
- This parameter can be any value of @ref DSI_LP_HBP */
-
- uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable
- This parameter can be any value of @ref DSI_LP_VACT */
-
- uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable
- This parameter can be any value of @ref DSI_LP_VFP */
-
- uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable
- This parameter can be any value of @ref DSI_LP_VBP */
-
- uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable
- This parameter can be any value of @ref DSI_LP_VSYNC */
-
- uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable
- This parameter can be any value of @ref DSI_FBTA_acknowledge */
-
-}DSI_VidCfgTypeDef;
-
-/**
- * @brief DSI Adapted command mode configuration
- */
-typedef struct
-{
- uint32_t VirtualChannelID; /*!< Virtual channel ID */
-
- uint32_t ColorCoding; /*!< Color coding for LTDC interface
- This parameter can be any value of @ref DSI_Color_Coding */
-
- uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in
- pixels. This parameter can be any value between 0x00 and 0xFFFF */
-
- uint32_t TearingEffectSource; /*!< Tearing effect source
- This parameter can be any value of @ref DSI_TearingEffectSource */
-
- uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity
- This parameter can be any value of @ref DSI_TearingEffectPolarity */
-
- uint32_t HSPolarity; /*!< HSYNC pin polarity
- This parameter can be any value of @ref DSI_HSYNC_Polarity */
-
- uint32_t VSPolarity; /*!< VSYNC pin polarity
- This parameter can be any value of @ref DSI_VSYNC_Polarity */
-
- uint32_t DEPolarity; /*!< Data Enable pin polarity
- This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
-
- uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted
- This parameter can be any value of @ref DSI_Vsync_Polarity */
-
- uint32_t AutomaticRefresh; /*!< Automatic refresh mode
- This parameter can be any value of @ref DSI_AutomaticRefresh */
-
- uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable
- This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */
-
-}DSI_CmdCfgTypeDef;
-
-/**
- * @brief DSI command transmission mode configuration
- */
-typedef struct
-{
- uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission
- This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */
-
- uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission
- This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */
-
- uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission
- This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */
-
- uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission
- This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */
-
- uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission
- This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */
-
- uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission
- This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */
-
- uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission
- This parameter can be any value of @ref DSI_LP_LPGenLongWrite */
-
- uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission
- This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */
-
- uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission
- This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */
-
- uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission
- This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */
-
- uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission
- This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */
-
- uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission
- This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */
-
- uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable
- This parameter can be any value of @ref DSI_AcknowledgeRequest */
-
-}DSI_LPCmdTypeDef;
-
-/**
- * @brief DSI PHY Timings definition
- */
-typedef struct
-{
- uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed
- to low-power transmission */
-
- uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power
- to high-speed transmission */
-
- uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed
- to low-power transmission */
-
- uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power
- to high-speed transmission */
-
- uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */
-
- uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the
- Stop state */
-
-}DSI_PHY_TimerTypeDef;
-
-/**
- * @brief DSI HOST Timeouts definition
- */
-typedef struct
-{
- uint32_t TimeoutCkdiv; /*!< Time-out clock division */
-
- uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */
-
- uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */
-
- uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */
-
- uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */
-
- uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */
-
- uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode
- This parameter can be any value of @ref DSI_HS_PrespMode */
-
- uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */
-
- uint32_t BTATimeout; /*!< BTA time-out */
-
-}DSI_HOST_TimeoutTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DSI_DCS_Command
- * @{
- */
-#define DSI_ENTER_IDLE_MODE 0x39
-#define DSI_ENTER_INVERT_MODE 0x21
-#define DSI_ENTER_NORMAL_MODE 0x13
-#define DSI_ENTER_PARTIAL_MODE 0x12
-#define DSI_ENTER_SLEEP_MODE 0x10
-#define DSI_EXIT_IDLE_MODE 0x38
-#define DSI_EXIT_INVERT_MODE 0x20
-#define DSI_EXIT_SLEEP_MODE 0x11
-#define DSI_GET_3D_CONTROL 0x3F
-#define DSI_GET_ADDRESS_MODE 0x0B
-#define DSI_GET_BLUE_CHANNEL 0x08
-#define DSI_GET_DIAGNOSTIC_RESULT 0x0F
-#define DSI_GET_DISPLAY_MODE 0x0D
-#define DSI_GET_GREEN_CHANNEL 0x07
-#define DSI_GET_PIXEL_FORMAT 0x0C
-#define DSI_GET_POWER_MODE 0x0A
-#define DSI_GET_RED_CHANNEL 0x06
-#define DSI_GET_SCANLINE 0x45
-#define DSI_GET_SIGNAL_MODE 0x0E
-#define DSI_NOP 0x00
-#define DSI_READ_DDB_CONTINUE 0xA8
-#define DSI_READ_DDB_START 0xA1
-#define DSI_READ_MEMORY_CONTINUE 0x3E
-#define DSI_READ_MEMORY_START 0x2E
-#define DSI_SET_3D_CONTROL 0x3D
-#define DSI_SET_ADDRESS_MODE 0x36
-#define DSI_SET_COLUMN_ADDRESS 0x2A
-#define DSI_SET_DISPLAY_OFF 0x28
-#define DSI_SET_DISPLAY_ON 0x29
-#define DSI_SET_GAMMA_CURVE 0x26
-#define DSI_SET_PAGE_ADDRESS 0x2B
-#define DSI_SET_PARTIAL_COLUMNS 0x31
-#define DSI_SET_PARTIAL_ROWS 0x30
-#define DSI_SET_PIXEL_FORMAT 0x3A
-#define DSI_SET_SCROLL_AREA 0x33
-#define DSI_SET_SCROLL_START 0x37
-#define DSI_SET_TEAR_OFF 0x34
-#define DSI_SET_TEAR_ON 0x35
-#define DSI_SET_TEAR_SCANLINE 0x44
-#define DSI_SET_VSYNC_TIMING 0x40
-#define DSI_SOFT_RESET 0x01
-#define DSI_WRITE_LUT 0x2D
-#define DSI_WRITE_MEMORY_CONTINUE 0x3C
-#define DSI_WRITE_MEMORY_START 0x2C
-/**
- * @}
- */
-
-/** @defgroup DSI_Video_Mode_Type
- * @{
- */
-#define DSI_VID_MODE_NB_PULSES 0
-#define DSI_VID_MODE_NB_EVENTS 1
-#define DSI_VID_MODE_BURST 2
-#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
- ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
- ((VideoModeType) == DSI_VID_MODE_BURST))
-/**
- * @}
- */
-
-/** @defgroup DSI_Color_Mode
- * @{
- */
-#define DSI_COLOR_MODE_FULL 0
-#define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM
-#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
-/**
- * @}
- */
-
-/** @defgroup DSI_ShutDown
- * @{
- */
-#define DSI_DISPLAY_ON 0
-#define DSI_DISPLAY_OFF DSI_WCR_SHTDN
-#define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))
-/**
- * @}
- */
-
-/** @defgroup DSI_LP_Command
- * @{
- */
-#define DSI_LP_COMMAND_DISABLE 0
-#define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE
-#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_LP_HFP
- * @{
- */
-#define DSI_LP_HFP_DISABLE 0
-#define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE
-#define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_LP_HBP
- * @{
- */
-#define DSI_LP_HBP_DISABLE 0
-#define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE
-#define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_LP_VACT
- * @{
- */
-#define DSI_LP_VACT_DISABLE 0
-#define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE
-#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_LP_VFP
- * @{
- */
-#define DSI_LP_VFP_DISABLE 0
-#define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE
-#define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_LP_VBP
- * @{
- */
-#define DSI_LP_VBP_DISABLE 0
-#define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE
-#define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_LP_VSYNC
- * @{
- */
-#define DSI_LP_VSYNC_DISABLE 0
-#define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE
-#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_FBTA_acknowledge
- * @{
- */
-#define DSI_FBTAA_DISABLE 0
-#define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE
-#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_TearingEffectSource
- * @{
- */
-#define DSI_TE_DSILINK 0
-#define DSI_TE_EXTERNAL DSI_WCFGR_TESRC
-#define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))
-/**
- * @}
- */
-
-/** @defgroup DSI_TearingEffectPolarity
- * @{
- */
-#define DSI_TE_RISING_EDGE 0
-#define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL
-#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE))
-/**
- * @}
- */
-
-/** @defgroup DSI_Vsync_Polarity
- * @{
- */
-#define DSI_VSYNC_FALLING 0
-#define DSI_VSYNC_RISING DSI_WCFGR_VSPOL
-#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING))
-/**
- * @}
- */
-
-/** @defgroup DSI_AutomaticRefresh
- * @{
- */
-#define DSI_AR_DISABLE 0
-#define DSI_AR_ENABLE DSI_WCFGR_AR
-#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_TE_AcknowledgeRequest
- * @{
- */
-#define DSI_TE_ACKNOWLEDGE_DISABLE 0
-#define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE
-#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_AcknowledgeRequest
- * @{
- */
-#define DSI_ACKNOWLEDGE_DISABLE 0
-#define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE
-#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
-
-/**
- * @}
- */
-
-/** @defgroup DSI_LP_LPGenShortWriteNoP
- * @{
- */
-#define DSI_LP_GSW0P_DISABLE 0
-#define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX
-#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_LP_LPGenShortWriteOneP
- * @{
- */
-#define DSI_LP_GSW1P_DISABLE 0
-#define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX
-#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_LP_LPGenShortWriteTwoP
- * @{
- */
-#define DSI_LP_GSW2P_DISABLE 0
-#define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX
-#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_LP_LPGenShortReadNoP
- * @{
- */
-#define DSI_LP_GSR0P_DISABLE 0
-#define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX
-#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_LP_LPGenShortReadOneP
- * @{
- */
-#define DSI_LP_GSR1P_DISABLE 0
-#define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX
-#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_LP_LPGenShortReadTwoP
- * @{
- */
-#define DSI_LP_GSR2P_DISABLE 0
-#define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX
-#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_LP_LPGenLongWrite
- * @{
- */
-#define DSI_LP_GLW_DISABLE 0
-#define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX
-#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_LP_LPDcsShortWriteNoP
- * @{
- */
-#define DSI_LP_DSW0P_DISABLE 0
-#define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX
-#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_LP_LPDcsShortWriteOneP
- * @{
- */
-#define DSI_LP_DSW1P_DISABLE 0
-#define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX
-#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_LP_LPDcsShortReadNoP
- * @{
- */
-#define DSI_LP_DSR0P_DISABLE 0
-#define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX
-#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_LP_LPDcsLongWrite
- * @{
- */
-#define DSI_LP_DLW_DISABLE 0
-#define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX
-#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_LP_LPMaxReadPacket
- * @{
- */
-#define DSI_LP_MRDP_DISABLE 0
-#define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS
-#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_HS_PrespMode
- * @{
- */
-#define DSI_HS_PM_DISABLE 0
-#define DSI_HS_PM_ENABLE DSI_TCCR3_PM
-/**
- * @}
- */
-
-
-/** @defgroup DSI_Automatic_Clk_Lane_Control
- * @{
- */
-#define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0
-#define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR
-#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup DSI_Number_Of_Lanes
- * @{
- */
-#define DSI_ONE_DATA_LANE 0
-#define DSI_TWO_DATA_LANES 1
-#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
-/**
- * @}
- */
-
-/** @defgroup DSI_FlowControl
- * @{
- */
-#define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE
-#define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE
-#define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
-#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
-#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
-#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
- DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
- DSI_FLOW_CONTROL_EOTP_TX)
-#define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
-/**
- * @}
- */
-
-/** @defgroup DSI_Color_Coding
- * @{
- */
-#define DSI_RGB565 ((uint32_t)0x00000000) /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */
-#define DSI_RGB666 ((uint32_t)0x00000003) /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */
-#define DSI_RGB888 ((uint32_t)0x00000005)
-#define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5)
-
-/**
- * @}
- */
-
-/** @defgroup DSI_LooselyPacked
- * @{
- */
-#define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE
-#define DSI_LOOSELY_PACKED_DISABLE 0
-#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
-
-/**
- * @}
- */
-
-/** @defgroup DSI_HSYNC_Polarity
- * @{
- */
-#define DSI_HSYNC_ACTIVE_HIGH 0
-#define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP
-#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
-/**
- * @}
- */
-
-/** @defgroup DSI_VSYNC_Polarity
- * @{
- */
-#define DSI_VSYNC_ACTIVE_HIGH 0
-#define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP
-#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
-/**
- * @}
- */
-
-/** @defgroup DSI_DATA_ENABLE_Polarity
- * @{
- */
-#define DSI_DATA_ENABLE_ACTIVE_HIGH 0
-#define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP
-#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
-/**
- * @}
- */
-
-/** @defgroup DSI_PLL_IDF
- * @{
- */
-#define DSI_PLL_IN_DIV1 ((uint32_t)0x00000001)
-#define DSI_PLL_IN_DIV2 ((uint32_t)0x00000002)
-#define DSI_PLL_IN_DIV3 ((uint32_t)0x00000003)
-#define DSI_PLL_IN_DIV4 ((uint32_t)0x00000004)
-#define DSI_PLL_IN_DIV5 ((uint32_t)0x00000005)
-#define DSI_PLL_IN_DIV6 ((uint32_t)0x00000006)
-#define DSI_PLL_IN_DIV7 ((uint32_t)0x00000007)
-#define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \
- ((IDF) == DSI_PLL_IN_DIV2) || \
- ((IDF) == DSI_PLL_IN_DIV3) || \
- ((IDF) == DSI_PLL_IN_DIV4) || \
- ((IDF) == DSI_PLL_IN_DIV5) || \
- ((IDF) == DSI_PLL_IN_DIV6) || \
- ((IDF) == DSI_PLL_IN_DIV7))
-/**
- * @}
- */
-
-/** @defgroup DSI_PLL_ODF
- * @{
- */
-#define DSI_PLL_OUT_DIV1 ((uint32_t)0x00000000)
-#define DSI_PLL_OUT_DIV2 ((uint32_t)0x00000001)
-#define DSI_PLL_OUT_DIV4 ((uint32_t)0x00000002)
-#define DSI_PLL_OUT_DIV8 ((uint32_t)0x00000003)
-#define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \
- ((ODF) == DSI_PLL_OUT_DIV2) || \
- ((ODF) == DSI_PLL_OUT_DIV4) || \
- ((ODF) == DSI_PLL_OUT_DIV8))
-#define IS_DSI_PLL_NDIV(NDIV) ((10 <= (NDIV)) && ((NDIV) <= 125))
-/**
- * @}
- */
-
-/** @defgroup DSI_Flags
- * @{
- */
-#define DSI_FLAG_TE DSI_WISR_TEIF
-#define DSI_FLAG_ER DSI_WISR_ERIF
-#define DSI_FLAG_BUSY DSI_WISR_BUSY
-#define DSI_FLAG_PLLLS DSI_WISR_PLLLS
-#define DSI_FLAG_PLLL DSI_WISR_PLLLIF
-#define DSI_FLAG_PLLU DSI_WISR_PLLUIF
-#define DSI_FLAG_RRS DSI_WISR_RRS
-#define DSI_FLAG_RR DSI_WISR_RRIF
-
-#define IS_DSI_CLEAR_FLAG(FLAG) (((FLAG) == DSI_FLAG_TE) || ((FLAG) == DSI_FLAG_ER) || \
- ((FLAG) == DSI_FLAG_PLLL) || ((FLAG) == DSI_FLAG_PLLU) || \
- ((FLAG) == DSI_FLAG_RR))
-#define IS_DSI_GET_FLAG(FLAG) (((FLAG) == DSI_FLAG_TE) || ((FLAG) == DSI_FLAG_ER) || \
- ((FLAG) == DSI_FLAG_BUSY) || ((FLAG) == DSI_FLAG_PLLLS) || \
- ((FLAG) == DSI_FLAG_PLLL) || ((FLAG) == DSI_FLAG_PLLU) || \
- ((FLAG) == DSI_FLAG_RRS) || ((FLAG) == DSI_FLAG_RR))
-/**
- * @}
- */
-
-/** @defgroup DSI_Interrupts
- * @{
- */
-#define DSI_IT_TE DSI_WIER_TEIE
-#define DSI_IT_ER DSI_WIER_ERIE
-#define DSI_IT_PLLL DSI_WIER_PLLLIE
-#define DSI_IT_PLLU DSI_WIER_PLLUIE
-#define DSI_IT_RR DSI_WIER_RRIE
-
-#define IS_DSI_IT(IT) (((IT) == DSI_IT_TE) || ((IT) == DSI_IT_ER) || \
- ((IT) == DSI_IT_PLLL) || ((IT) == DSI_IT_PLLU) || \
- ((IT) == DSI_IT_RR))
-/**
- * @}
- */
-
-/** @defgroup DSI_SHORT_WRITE_PKT_Data_Type
- * @{
- */
-#define DSI_DCS_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000005) /*!< DCS short write, no parameters */
-#define DSI_DCS_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000015) /*!< DCS short write, one parameter */
-#define DSI_GEN_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000003) /*!< Generic short write, no parameters */
-#define DSI_GEN_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000013) /*!< Generic short write, one parameter */
-#define DSI_GEN_SHORT_PKT_WRITE_P2 ((uint32_t)0x00000023) /*!< Generic short write, two parameters */
-#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \
- ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \
- ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \
- ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \
- ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))
-/**
- * @}
- */
-
-/** @defgroup DSI_LONG_WRITE_PKT_Data_Type
- * @{
- */
-#define DSI_DCS_LONG_PKT_WRITE ((uint32_t)0x00000039) /*!< DCS long write */
-#define DSI_GEN_LONG_PKT_WRITE ((uint32_t)0x00000029) /*!< Generic long write */
-#define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \
- ((MODE) == DSI_GEN_LONG_PKT_WRITE))
-/**
- * @}
- */
-
-/** @defgroup DSI_SHORT_READ_PKT_Data_Type
- * @{
- */
-#define DSI_DCS_SHORT_PKT_READ ((uint32_t)0x00000006) /*!< DCS short read */
-#define DSI_GEN_SHORT_PKT_READ_P0 ((uint32_t)0x00000004) /*!< Generic short read, no parameters */
-#define DSI_GEN_SHORT_PKT_READ_P1 ((uint32_t)0x00000014) /*!< Generic short read, one parameter */
-#define DSI_GEN_SHORT_PKT_READ_P2 ((uint32_t)0x00000024) /*!< Generic short read, two parameters */
-#define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \
- ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \
- ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \
- ((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
-/**
- * @}
- */
-
-/** @defgroup DSI_Error_Data_Type
- * @{
- */
-#define DSI_ERROR_NONE 0
-#define DSI_ERROR_ACK ((uint32_t)0x00000001) /*!< acknowledge errors */
-#define DSI_ERROR_PHY ((uint32_t)0x00000002) /*!< PHY related errors */
-#define DSI_ERROR_TX ((uint32_t)0x00000004) /*!< transmission error */
-#define DSI_ERROR_RX ((uint32_t)0x00000008) /*!< reception error */
-#define DSI_ERROR_ECC ((uint32_t)0x00000010) /*!< ECC errors */
-#define DSI_ERROR_CRC ((uint32_t)0x00000020) /*!< CRC error */
-#define DSI_ERROR_PSE ((uint32_t)0x00000040) /*!< Packet Size error */
-#define DSI_ERROR_EOT ((uint32_t)0x00000080) /*!< End Of Transmission error */
-#define DSI_ERROR_OVF ((uint32_t)0x00000100) /*!< FIFO overflow error */
-#define DSI_ERROR_GEN ((uint32_t)0x00000200) /*!< Generic FIFO related errors */
-/**
- * @}
- */
-
-/** @defgroup DSI_Lane_Group
- * @{
- */
-#define DSI_CLOCK_LANE ((uint32_t)0x00000000)
-#define DSI_DATA_LANES ((uint32_t)0x00000001)
-#define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))
-/**
- * @}
- */
-
-/** @defgroup DSI_Communication_Delay
- * @{
- */
-#define DSI_SLEW_RATE_HSTX ((uint32_t)0x00000000)
-#define DSI_SLEW_RATE_LPTX ((uint32_t)0x00000001)
-#define DSI_HS_DELAY ((uint32_t)0x00000002)
-#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY))
-/**
- * @}
- */
-
-/** @defgroup DSI_CustomLane
- * @{
- */
-#define DSI_SWAP_LANE_PINS ((uint32_t)0x00000000)
-#define DSI_INVERT_HS_SIGNAL ((uint32_t)0x00000001)
-#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
-/**
- * @}
- */
-
-/** @defgroup DSI_Lane_Select
- * @{
- */
-#define DSI_CLOCK_LANE ((uint32_t)0x00000000)
-#define DSI_DATA_LANE0 ((uint32_t)0x00000001)
-#define DSI_DATA_LANE1 ((uint32_t)0x00000002)
-#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
-/**
- * @}
- */
-
-/** @defgroup DSI_PHY_Timing
- * @{
- */
-#define DSI_TCLK_POST ((uint32_t)0x00000000)
-#define DSI_TLPX_CLK ((uint32_t)0x00000001)
-#define DSI_THS_EXIT ((uint32_t)0x00000002)
-#define DSI_TLPX_DATA ((uint32_t)0x00000003)
-#define DSI_THS_ZERO ((uint32_t)0x00000004)
-#define DSI_THS_TRAIL ((uint32_t)0x00000005)
-#define DSI_THS_PREPARE ((uint32_t)0x00000006)
-#define DSI_TCLK_ZERO ((uint32_t)0x00000007)
-#define DSI_TCLK_PREPARE ((uint32_t)0x00000008)
-#define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \
- ((Timing) == DSI_TLPX_CLK ) || \
- ((Timing) == DSI_THS_EXIT ) || \
- ((Timing) == DSI_TLPX_DATA ) || \
- ((Timing) == DSI_THS_ZERO ) || \
- ((Timing) == DSI_THS_TRAIL ) || \
- ((Timing) == DSI_THS_PREPARE ) || \
- ((Timing) == DSI_TCLK_ZERO ) || \
- ((Timing) == DSI_TCLK_PREPARE))
-/**
- * @}
- */
-#define IS_DSI_ALL_PERIPH(PERIPH) ((PERIPH) == DSI)
-
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/* Initialization and Configuration functions *********************************/
-void DSI_DeInit(DSI_TypeDef *DSIx);
-void DSI_Init(DSI_TypeDef *DSIx,DSI_InitTypeDef* DSI_InitStruct, DSI_PLLInitTypeDef *PLLInit);
-void DSI_StructInit(DSI_InitTypeDef* DSI_InitStruct, DSI_HOST_TimeoutTypeDef* DSI_HOST_TimeoutInitStruct);
-void DSI_SetGenericVCID(DSI_TypeDef *DSIx, uint32_t VirtualChannelID);
-void DSI_ConfigVideoMode(DSI_TypeDef *DSIx, DSI_VidCfgTypeDef *VidCfg);
-void DSI_ConfigAdaptedCommandMode(DSI_TypeDef *DSIx, DSI_CmdCfgTypeDef *CmdCfg);
-void DSI_ConfigCommand(DSI_TypeDef *DSIx, DSI_LPCmdTypeDef *LPCmd);
-void DSI_ConfigFlowControl(DSI_TypeDef *DSIx, uint32_t FlowControl);
-void DSI_ConfigPhyTimer(DSI_TypeDef *DSIx, DSI_PHY_TimerTypeDef *PhyTimers);
-void DSI_ConfigHostTimeouts(DSI_TypeDef *DSIx, DSI_HOST_TimeoutTypeDef *HostTimeouts);
-void DSI_PatternGeneratorStart(DSI_TypeDef *DSIx, uint32_t Mode, uint32_t Orientation);
-void DSI_PatternGeneratorStop(DSI_TypeDef *DSIx);
-void DSI_Start(DSI_TypeDef *DSIx);
-void DSI_Stop(DSI_TypeDef *DSIx);
-void DSI_Refresh(DSI_TypeDef *DSIx);
-void DSI_ColorMode(DSI_TypeDef *DSIx, uint32_t ColorMode);
-void DSI_Shutdown(DSI_TypeDef *DSIx, uint32_t Shutdown);
-
-/* Alias for compatibility with STM32F4XX Standard Peripherals Library version number V1.6.0 */
-#define DSI_ConfigLowPowerCommand DSI_ConfigCommand
-
-/* Data transfers management functions ****************************************/
-void DSI_ShortWrite(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t Mode, uint32_t Param1, uint32_t Param2);
-void DSI_LongWrite(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t Mode, uint32_t NbParams, uint32_t Param1, uint8_t* ParametersTable);
-void DSI_Read(DSI_TypeDef *DSIx, uint32_t ChannelNbr, uint8_t* Array, uint32_t Size, uint32_t Mode, uint32_t DCSCmd, uint8_t* ParametersTable);
-
-/* Low Power functions ********************************************************/
-void DSI_EnterULPMData(DSI_TypeDef *DSIx);
-void DSI_ExitULPMData(DSI_TypeDef *DSIx);
-void DSI_EnterULPM(DSI_TypeDef *DSIx);
-void DSI_ExitULPM(DSI_TypeDef *DSIx);
-void DSI_SetSlewRateAndDelayTuning(DSI_TypeDef *DSIx, uint32_t CommDelay, uint32_t Lane, uint32_t Value);
-void DSI_SetLowPowerRXFilter(DSI_TypeDef *DSIx, uint32_t Frequency);
-void DSI_SetSDD(DSI_TypeDef *DSIx, FunctionalState State);
-void DSI_SetLanePinsConfiguration(DSI_TypeDef *DSIx, uint32_t CustomLane, uint32_t Lane, FunctionalState State);
-void DSI_SetPHYTimings(DSI_TypeDef *DSIx, uint32_t Timing, FunctionalState State, uint32_t Value);
-void DSI_ForceTXStopMode(DSI_TypeDef *DSIx, uint32_t Lane, FunctionalState State);
-void DSI_ForceRXLowPower(DSI_TypeDef *DSIx, FunctionalState State);
-void DSI_ForceDataLanesInRX(DSI_TypeDef *DSIx, FunctionalState State);
-void DSI_SetPullDown(DSI_TypeDef *DSIx, FunctionalState State);
-void DSI_SetContentionDetectionOff(DSI_TypeDef *DSIx, FunctionalState State);
-
-/* Interrupts and flags management functions **********************************/
-void DSI_ITConfig(DSI_TypeDef* DSIx, uint32_t DSI_IT, FunctionalState NewState);
-FlagStatus DSI_GetFlagStatus(DSI_TypeDef* DSIx, uint16_t DSI_FLAG);
-void DSI_ClearFlag(DSI_TypeDef* DSIx, uint16_t DSI_FLAG);
-ITStatus DSI_GetITStatus(DSI_TypeDef* DSIx, uint32_t DSI_IT);
-void DSI_ClearITPendingBit(DSI_TypeDef* DSIx, uint32_t DSI_IT);
-void DSI_ConfigErrorMonitor(DSI_TypeDef *DSIx, uint32_t ActiveErrors);
-
-#endif /* STM32F469_479xx */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_DSI_H */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_exti.c b/底盘/底盘-old/底盘/Library/stm32f4xx_exti.c
deleted file mode 100644
index d06b789..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_exti.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_exti.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the EXTI peripheral:
- * + Initialization and Configuration
- * + Interrupts and flags management
- *
-@verbatim
-
- ===============================================================================
- ##### EXTI features #####
- ===============================================================================
-
- [..] External interrupt/event lines are mapped as following:
- (#) All available GPIO pins are connected to the 16 external
- interrupt/event lines from EXTI0 to EXTI15.
- (#) EXTI line 16 is connected to the PVD Output
- (#) EXTI line 17 is connected to the RTC Alarm event
- (#) EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event
- (#) EXTI line 19 is connected to the Ethernet Wakeup event
- (#) EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event
- (#) EXTI line 21 is connected to the RTC Tamper and Time Stamp events
- (#) EXTI line 22 is connected to the RTC Wakeup event
- (#) EXTI line 23 is connected to the LPTIM Wakeup event
-
- ##### How to use this driver #####
- ===============================================================================
-
- [..] In order to use an I/O pin as an external interrupt source, follow steps
- below:
- (#) Configure the I/O in input mode using GPIO_Init()
- (#) Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig()
- (#) Select the mode(interrupt, event) and configure the trigger
- selection (Rising, falling or both) using EXTI_Init()
- (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()
-
- [..]
- (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
- registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_exti.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup EXTI
- * @brief EXTI driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup EXTI_Private_Functions
- * @{
- */
-
-/** @defgroup EXTI_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the EXTI peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void EXTI_DeInit(void)
-{
- EXTI->IMR = 0x00000000;
- EXTI->EMR = 0x00000000;
- EXTI->RTSR = 0x00000000;
- EXTI->FTSR = 0x00000000;
- EXTI->PR = 0x007FFFFF;
-}
-
-/**
- * @brief Initializes the EXTI peripheral according to the specified
- * parameters in the EXTI_InitStruct.
- * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
- * that contains the configuration information for the EXTI peripheral.
- * @retval None
- */
-void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
- assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
- assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
- assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
-
- tmp = (uint32_t)EXTI_BASE;
-
- if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
- {
- /* Clear EXTI line configuration */
- EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
- EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
-
- tmp += EXTI_InitStruct->EXTI_Mode;
-
- *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
-
- /* Clear Rising Falling edge configuration */
- EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
- EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
-
- /* Select the trigger for the selected external interrupts */
- if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
- {
- /* Rising Falling edge */
- EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
- EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
- }
- else
- {
- tmp = (uint32_t)EXTI_BASE;
- tmp += EXTI_InitStruct->EXTI_Trigger;
-
- *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
- }
- }
- else
- {
- tmp += EXTI_InitStruct->EXTI_Mode;
-
- /* Disable the selected external lines */
- *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
- }
-}
-
-/**
- * @brief Fills each EXTI_InitStruct member with its reset value.
- * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
-{
- EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
- EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
- EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
- EXTI_InitStruct->EXTI_LineCmd = DISABLE;
-}
-
-/**
- * @brief Generates a Software interrupt on selected EXTI line.
- * @param EXTI_Line: specifies the EXTI line on which the software interrupt
- * will be generated.
- * This parameter can be any combination of EXTI_Linex where x can be (0..22)
- * @retval None
- */
-void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE(EXTI_Line));
-
- EXTI->SWIER |= EXTI_Line;
-}
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_Group2 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the specified EXTI line flag is set or not.
- * @param EXTI_Line: specifies the EXTI line flag to check.
- * This parameter can be EXTI_Linex where x can be(0..22)
- * @retval The new state of EXTI_Line (SET or RESET).
- */
-FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_GET_EXTI_LINE(EXTI_Line));
-
- if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the EXTI's line pending flags.
- * @param EXTI_Line: specifies the EXTI lines flags to clear.
- * This parameter can be any combination of EXTI_Linex where x can be (0..22)
- * @retval None
- */
-void EXTI_ClearFlag(uint32_t EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE(EXTI_Line));
-
- EXTI->PR = EXTI_Line;
-}
-
-/**
- * @brief Checks whether the specified EXTI line is asserted or not.
- * @param EXTI_Line: specifies the EXTI line to check.
- * This parameter can be EXTI_Linex where x can be(0..22)
- * @retval The new state of EXTI_Line (SET or RESET).
- */
-ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_GET_EXTI_LINE(EXTI_Line));
-
- if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-
-}
-
-/**
- * @brief Clears the EXTI's line pending bits.
- * @param EXTI_Line: specifies the EXTI lines to clear.
- * This parameter can be any combination of EXTI_Linex where x can be (0..22)
- * @retval None
- */
-void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE(EXTI_Line));
-
- EXTI->PR = EXTI_Line;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_exti.h b/底盘/底盘-old/底盘/Library/stm32f4xx_exti.h
deleted file mode 100644
index f231072..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_exti.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_exti.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the EXTI firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_EXTI_H
-#define __STM32F4xx_EXTI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup EXTI
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief EXTI mode enumeration
- */
-
-typedef enum
-{
- EXTI_Mode_Interrupt = 0x00,
- EXTI_Mode_Event = 0x04
-}EXTIMode_TypeDef;
-
-#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
-
-/**
- * @brief EXTI Trigger enumeration
- */
-
-typedef enum
-{
- EXTI_Trigger_Rising = 0x08,
- EXTI_Trigger_Falling = 0x0C,
- EXTI_Trigger_Rising_Falling = 0x10
-}EXTITrigger_TypeDef;
-
-#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
- ((TRIGGER) == EXTI_Trigger_Falling) || \
- ((TRIGGER) == EXTI_Trigger_Rising_Falling))
-/**
- * @brief EXTI Init Structure definition
- */
-
-typedef struct
-{
- uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
- This parameter can be any combination value of @ref EXTI_Lines */
-
- EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
- This parameter can be a value of @ref EXTIMode_TypeDef */
-
- EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
- This parameter can be a value of @ref EXTITrigger_TypeDef */
-
- FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
- This parameter can be set either to ENABLE or DISABLE */
-}EXTI_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup EXTI_Exported_Constants
- * @{
- */
-
-/** @defgroup EXTI_Lines
- * @{
- */
-
-#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
-#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
-#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
-#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
-#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
-#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
-#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
-#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
-#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
-#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
-#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
-#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
-#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
-#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
-#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
-#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
-#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
-#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
-#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
-#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
-#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
-#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
-#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
-#define EXTI_Line23 ((uint32_t)0x00800000) /*!< External interrupt line 23 Connected to the LPTIM Wakeup event */
-
-
-#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))
-
-#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
- ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
- ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
- ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
- ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
- ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
- ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
- ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
- ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
- ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
- ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\
- ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the EXTI configuration to the default reset state *****/
-void EXTI_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
-void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
-
-/* Interrupts and flags management functions **********************************/
-FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
-void EXTI_ClearFlag(uint32_t EXTI_Line);
-ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
-void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_EXTI_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_flash.c b/底盘/底盘-old/底盘/Library/stm32f4xx_flash.c
deleted file mode 100644
index 9553e46..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_flash.c
+++ /dev/null
@@ -1,1611 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_flash.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the FLASH peripheral:
- * + FLASH Interface configuration
- * + FLASH Memory Programming
- * + Option Bytes Programming
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- This driver provides functions to configure and program the FLASH memory
- of all STM32F4xx devices. These functions are split in 4 groups:
-
- (#) FLASH Interface configuration functions: this group includes the
- management of the following features:
- (++) Set the latency
- (++) Enable/Disable the prefetch buffer
- (++) Enable/Disable the Instruction cache and the Data cache
- (++) Reset the Instruction cache and the Data cache
-
- (#) FLASH Memory Programming functions: this group includes all needed
- functions to erase and program the main memory:
- (++) Lock and Unlock the FLASH interface
- (++) Erase function: Erase sector, erase all sectors
- (++) Program functions: byte, half word, word and double word
-
- (#) Option Bytes Programming functions: this group includes all needed
- functions to manage the Option Bytes:
- (++) Set/Reset the write protection
- (++) Set the Read protection Level
- (++) Set the BOR level
- (++) Program the user Option Bytes
- (++) Launch the Option Bytes loader
-
- (#) Interrupts and flags management functions: this group
- includes all needed functions to:
- (++) Enable/Disable the FLASH interrupt sources
- (++) Get flags status
- (++) Clear flags
- (++) Get FLASH operation status
- (++) Wait for last FLASH operation
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_flash.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup FLASH
- * @brief FLASH driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define SECTOR_MASK ((uint32_t)0xFFFFFF07)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup FLASH_Private_Functions
- * @{
- */
-
-/** @defgroup FLASH_Group1 FLASH Interface configuration functions
- * @brief FLASH Interface configuration functions
- *
-
-@verbatim
- ===============================================================================
- ##### FLASH Interface configuration functions #####
- ===============================================================================
- [..]
- This group includes the following functions:
- (+) void FLASH_SetLatency(uint32_t FLASH_Latency)
- To correctly read data from FLASH memory, the number of wait states (LATENCY)
- must be correctly programmed according to the frequency of the CPU clock
- (HCLK) and the supply voltage of the device.
- [..]
- For STM32F405xx/07xx and STM32F415xx/17xx devices
- +-------------------------------------------------------------------------------------+
- | Latency | HCLK clock frequency (MHz) |
- | |---------------------------------------------------------------------|
- | | voltage range | voltage range | voltage range | voltage range |
- | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
- |---------------|----------------|----------------|-----------------|-----------------|
- |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
- |---------------|----------------|----------------|-----------------|-----------------|
- |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
- |---------------|----------------|----------------|-----------------|-----------------|
- |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160|
- +---------------|----------------|----------------|-----------------|-----------------+
-
- [..]
- For STM32F42xxx/43xxx devices
- +-------------------------------------------------------------------------------------+
- | Latency | HCLK clock frequency (MHz) |
- | |---------------------------------------------------------------------|
- | | voltage range | voltage range | voltage range | voltage range |
- | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
- |---------------|----------------|----------------|-----------------|-----------------|
- |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
- |---------------|----------------|----------------|-----------------|-----------------|
- |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
- |---------------|----------------|----------------|-----------------|-----------------|
- |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160|
- |---------------|----------------|----------------|-----------------|-----------------|
- |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168|
- +-------------------------------------------------------------------------------------+
-
- [..]
- For STM32F401x devices
- +-------------------------------------------------------------------------------------+
- | Latency | HCLK clock frequency (MHz) |
- | |---------------------------------------------------------------------|
- | | voltage range | voltage range | voltage range | voltage range |
- | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
- |---------------|----------------|----------------|-----------------|-----------------|
- |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 |
- +-------------------------------------------------------------------------------------+
-
- [..]
- For STM32F410xx/STM32F411xE devices
- +-------------------------------------------------------------------------------------+
- | Latency | HCLK clock frequency (MHz) |
- | |---------------------------------------------------------------------|
- | | voltage range | voltage range | voltage range | voltage range |
- | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
- |---------------|----------------|----------------|-----------------|-----------------|
- |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |1WS(2CPU cycle)|30 < HCLK <= 64 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |2WS(3CPU cycle)|64 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |3WS(4CPU cycle)|90 < HCLK <= 100|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |4WS(5CPU cycle)| NA |96 < HCLK <= 100|72 < HCLK <= 90 |64 < HCLK <= 80 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 100 |80 < HCLK <= 96 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |6WS(7CPU cycle)| NA | NA | NA |96 < HCLK <= 100 |
- +-------------------------------------------------------------------------------------+
-
- [..]
- +-------------------------------------------------------------------------------------------------------------------+
- | | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V |
- | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V |
- |---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
- |Max Parallelism| x32 | x16 | x8 | x64 |
- |---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
- |PSIZE[1:0] | 10 | 01 | 00 | 11 |
- +-------------------------------------------------------------------------------------------------------------------+
-
- -@- On STM32F405xx/407xx and STM32F415xx/417xx devices:
- (++) when VOS = '0' Scale 2 mode, the maximum value of fHCLK = 144MHz.
- (++) when VOS = '1' Scale 1 mode, the maximum value of fHCLK = 168MHz.
- [..]
- On STM32F42xxx/43xxx devices:
- (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 120MHz.
- (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 144MHz if OverDrive OFF and 168MHz if OverDrive ON.
- (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 168MHz if OverDrive OFF and 180MHz if OverDrive ON.
- [..]
- On STM32F401x devices:
- (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 60MHz.
- (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
- [..]
- On STM32F410xx/STM32F411xE devices:
- (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 64MHz.
- (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
- (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 100MHz.
-
- For more details please refer product DataSheet
- You can use PWR_MainRegulatorModeConfig() function to control VOS bits.
-
- (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState)
- (+) void FLASH_InstructionCacheCmd(FunctionalState NewState)
- (+) void FLASH_DataCacheCmd(FunctionalState NewState)
- (+) void FLASH_InstructionCacheReset(void)
- (+) void FLASH_DataCacheReset(void)
-
- [..]
- The unlock sequence is not needed for these functions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the code latency value.
- * @param FLASH_Latency: specifies the FLASH Latency value.
- * This parameter can be one of the following values:
- * @arg FLASH_Latency_0: FLASH Zero Latency cycle
- * @arg FLASH_Latency_1: FLASH One Latency cycle
- * @arg FLASH_Latency_2: FLASH Two Latency cycles
- * @arg FLASH_Latency_3: FLASH Three Latency cycles
- * @arg FLASH_Latency_4: FLASH Four Latency cycles
- * @arg FLASH_Latency_5: FLASH Five Latency cycles
- * @arg FLASH_Latency_6: FLASH Six Latency cycles
- * @arg FLASH_Latency_7: FLASH Seven Latency cycles
- * @arg FLASH_Latency_8: FLASH Eight Latency cycles
- * @arg FLASH_Latency_9: FLASH Nine Latency cycles
- * @arg FLASH_Latency_10: FLASH Teen Latency cycles
- * @arg FLASH_Latency_11: FLASH Eleven Latency cycles
- * @arg FLASH_Latency_12: FLASH Twelve Latency cycles
- * @arg FLASH_Latency_13: FLASH Thirteen Latency cycles
- * @arg FLASH_Latency_14: FLASH Fourteen Latency cycles
- * @arg FLASH_Latency_15: FLASH Fifteen Latency cycles
- *
- * @note For STM32F405xx/407xx, STM32F415xx/417xx, STM32F401xx/411xE/STM32F412xG and STM32F413_423xx devices
- * this parameter can be a value between FLASH_Latency_0 and FLASH_Latency_7.
- *
- * @note For STM32F42xxx/43xxx devices this parameter can be a value between
- * FLASH_Latency_0 and FLASH_Latency_15.
- *
- * @retval None
- */
-void FLASH_SetLatency(uint32_t FLASH_Latency)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_LATENCY(FLASH_Latency));
-
- /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */
- *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency;
-}
-
-/**
- * @brief Enables or disables the Prefetch Buffer.
- * @param NewState: new state of the Prefetch Buffer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_PrefetchBufferCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Enable or disable the Prefetch Buffer */
- if(NewState != DISABLE)
- {
- FLASH->ACR |= FLASH_ACR_PRFTEN;
- }
- else
- {
- FLASH->ACR &= (~FLASH_ACR_PRFTEN);
- }
-}
-
-/**
- * @brief Enables or disables the Instruction Cache feature.
- * @param NewState: new state of the Instruction Cache.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_InstructionCacheCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- FLASH->ACR |= FLASH_ACR_ICEN;
- }
- else
- {
- FLASH->ACR &= (~FLASH_ACR_ICEN);
- }
-}
-
-/**
- * @brief Enables or disables the Data Cache feature.
- * @param NewState: new state of the Data Cache.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_DataCacheCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- FLASH->ACR |= FLASH_ACR_DCEN;
- }
- else
- {
- FLASH->ACR &= (~FLASH_ACR_DCEN);
- }
-}
-
-/**
- * @brief Resets the Instruction Cache.
- * @note This function must be used only when the Instruction Cache is disabled.
- * @param None
- * @retval None
- */
-void FLASH_InstructionCacheReset(void)
-{
- FLASH->ACR |= FLASH_ACR_ICRST;
-}
-
-/**
- * @brief Resets the Data Cache.
- * @note This function must be used only when the Data Cache is disabled.
- * @param None
- * @retval None
- */
-void FLASH_DataCacheReset(void)
-{
- FLASH->ACR |= FLASH_ACR_DCRST;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group2 FLASH Memory Programming functions
- * @brief FLASH Memory Programming functions
- *
-@verbatim
- ===============================================================================
- ##### FLASH Memory Programming functions #####
- ===============================================================================
- [..]
- This group includes the following functions:
- (+) void FLASH_Unlock(void)
- (+) void FLASH_Lock(void)
- (+) FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
- (+) FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
- (+) FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
- (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
- (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
- (+) FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
- The following functions can be used only for STM32F42xxx/43xxx devices.
- (+) FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange)
- (+) FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)
- [..]
- Any operation of erase or program should follow these steps:
- (#) Call the FLASH_Unlock() function to enable the FLASH control register access
-
- (#) Call the desired function to erase sector(s) or program data
-
- (#) Call the FLASH_Lock() function to disable the FLASH control register access
- (recommended to protect the FLASH memory against possible unwanted operation)
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Unlocks the FLASH control register access
- * @param None
- * @retval None
- */
-void FLASH_Unlock(void)
-{
- if((FLASH->CR & FLASH_CR_LOCK) != RESET)
- {
- /* Authorize the FLASH Registers access */
- FLASH->KEYR = FLASH_KEY1;
- FLASH->KEYR = FLASH_KEY2;
- }
-}
-
-/**
- * @brief Locks the FLASH control register access
- * @param None
- * @retval None
- */
-void FLASH_Lock(void)
-{
- /* Set the LOCK Bit to lock the FLASH Registers access */
- FLASH->CR |= FLASH_CR_LOCK;
-}
-
-/**
- * @brief Erases a specified FLASH Sector.
- *
- * @note If an erase and a program operations are requested simultaneously,
- * the erase operation is performed before the program one.
- *
- * @param FLASH_Sector: The Sector number to be erased.
- *
- * @note For STM32F405xx/407xx and STM32F415xx/417xx devices this parameter can
- * be a value between FLASH_Sector_0 and FLASH_Sector_11.
- *
- * For STM32F42xxx/43xxx devices this parameter can be a value between
- * FLASH_Sector_0 and FLASH_Sector_23.
- *
- * For STM32F401xx devices this parameter can be a value between
- * FLASH_Sector_0 and FLASH_Sector_5.
- *
- * For STM32F411xE and STM32F412xG devices this parameter can be a value between
- * FLASH_Sector_0 and FLASH_Sector_7.
- *
- * For STM32F410xx devices this parameter can be a value between
- * FLASH_Sector_0 and FLASH_Sector_4.
- *
- * For STM32F413_423xx devices this parameter can be a value between
- * FLASH_Sector_0 and FLASH_Sector_15.
- *
- * @param VoltageRange: The device voltage range which defines the erase parallelism.
- * This parameter can be one of the following values:
- * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
- * the operation will be done by byte (8-bit)
- * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
- * the operation will be done by half word (16-bit)
- * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
- * the operation will be done by word (32-bit)
- * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
- * the operation will be done by double word (64-bit)
- *
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
-{
- uint32_t tmp_psize = 0x0;
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_SECTOR(FLASH_Sector));
- assert_param(IS_VOLTAGERANGE(VoltageRange));
-
- if(VoltageRange == VoltageRange_1)
- {
- tmp_psize = FLASH_PSIZE_BYTE;
- }
- else if(VoltageRange == VoltageRange_2)
- {
- tmp_psize = FLASH_PSIZE_HALF_WORD;
- }
- else if(VoltageRange == VoltageRange_3)
- {
- tmp_psize = FLASH_PSIZE_WORD;
- }
- else
- {
- tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
- }
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase the sector */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= tmp_psize;
- FLASH->CR &= SECTOR_MASK;
- FLASH->CR |= FLASH_CR_SER | FLASH_Sector;
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the erase operation is completed, disable the SER Bit */
- FLASH->CR &= (~FLASH_CR_SER);
- FLASH->CR &= SECTOR_MASK;
- }
- /* Return the Erase Status */
- return status;
-}
-
-/**
- * @brief Erases all FLASH Sectors.
- *
- * @note If an erase and a program operations are requested simultaneously,
- * the erase operation is performed before the program one.
- *
- * @param VoltageRange: The device voltage range which defines the erase parallelism.
- * This parameter can be one of the following values:
- * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
- * the operation will be done by byte (8-bit)
- * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
- * the operation will be done by half word (16-bit)
- * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
- * the operation will be done by word (32-bit)
- * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
- * the operation will be done by double word (64-bit)
- *
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
-{
- uint32_t tmp_psize = 0x0;
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
- assert_param(IS_VOLTAGERANGE(VoltageRange));
-
- if(VoltageRange == VoltageRange_1)
- {
- tmp_psize = FLASH_PSIZE_BYTE;
- }
- else if(VoltageRange == VoltageRange_2)
- {
- tmp_psize = FLASH_PSIZE_HALF_WORD;
- }
- else if(VoltageRange == VoltageRange_3)
- {
- tmp_psize = FLASH_PSIZE_WORD;
- }
- else
- {
- tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
- }
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase all sectors */
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= tmp_psize;
- FLASH->CR |= (FLASH_CR_MER1 | FLASH_CR_MER2);
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the erase operation is completed, disable the MER Bit */
- FLASH->CR &= ~(FLASH_CR_MER1 | FLASH_CR_MER2);
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= tmp_psize;
- FLASH->CR |= FLASH_CR_MER;
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the erase operation is completed, disable the MER Bit */
- FLASH->CR &= (~FLASH_CR_MER);
-#endif /* STM32F40_41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG || STM32F413_423xx || STM32F446xx */
-
- }
- /* Return the Erase Status */
- return status;
-}
-
-/**
- * @brief Erases all FLASH Sectors in Bank 1.
- *
- * @note This function can be used only for STM32F42xxx/43xxx devices.
- *
- * @note If an erase and a program operations are requested simultaneously,
- * the erase operation is performed before the program one.
- *
- * @param VoltageRange: The device voltage range which defines the erase parallelism.
- * This parameter can be one of the following values:
- * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
- * the operation will be done by byte (8-bit)
- * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
- * the operation will be done by half word (16-bit)
- * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
- * the operation will be done by word (32-bit)
- * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
- * the operation will be done by double word (64-bit)
- *
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange)
-{
- uint32_t tmp_psize = 0x0;
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
- assert_param(IS_VOLTAGERANGE(VoltageRange));
-
- if(VoltageRange == VoltageRange_1)
- {
- tmp_psize = FLASH_PSIZE_BYTE;
- }
- else if(VoltageRange == VoltageRange_2)
- {
- tmp_psize = FLASH_PSIZE_HALF_WORD;
- }
- else if(VoltageRange == VoltageRange_3)
- {
- tmp_psize = FLASH_PSIZE_WORD;
- }
- else
- {
- tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
- }
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase all sectors */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= tmp_psize;
- FLASH->CR |= FLASH_CR_MER1;
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the erase operation is completed, disable the MER Bit */
- FLASH->CR &= (~FLASH_CR_MER1);
-
- }
- /* Return the Erase Status */
- return status;
-}
-
-
-/**
- * @brief Erases all FLASH Sectors in Bank 2.
- *
- * @note This function can be used only for STM32F42xxx/43xxx devices.
- *
- * @note If an erase and a program operations are requested simultaneously,
- * the erase operation is performed before the program one.
- *
- * @param VoltageRange: The device voltage range which defines the erase parallelism.
- * This parameter can be one of the following values:
- * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
- * the operation will be done by byte (8-bit)
- * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
- * the operation will be done by half word (16-bit)
- * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
- * the operation will be done by word (32-bit)
- * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
- * the operation will be done by double word (64-bit)
- *
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)
-{
- uint32_t tmp_psize = 0x0;
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
- assert_param(IS_VOLTAGERANGE(VoltageRange));
-
- if(VoltageRange == VoltageRange_1)
- {
- tmp_psize = FLASH_PSIZE_BYTE;
- }
- else if(VoltageRange == VoltageRange_2)
- {
- tmp_psize = FLASH_PSIZE_HALF_WORD;
- }
- else if(VoltageRange == VoltageRange_3)
- {
- tmp_psize = FLASH_PSIZE_WORD;
- }
- else
- {
- tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
- }
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase all sectors */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= tmp_psize;
- FLASH->CR |= FLASH_CR_MER2;
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the erase operation is completed, disable the MER Bit */
- FLASH->CR &= (~FLASH_CR_MER2);
-
- }
- /* Return the Erase Status */
- return status;
-}
-
-/**
- * @brief Programs a double word (64-bit) at a specified address.
- * @note This function must be used when the device voltage range is from
- * 2.7V to 3.6V and an External Vpp is present.
- *
- * @note If an erase and a program operations are requested simultaneously,
- * the erase operation is performed before the program one.
- *
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
- FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint64_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the program operation is completed, disable the PG Bit */
- FLASH->CR &= (~FLASH_CR_PG);
- }
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @brief Programs a word (32-bit) at a specified address.
- *
- * @note This function must be used when the device voltage range is from 2.7V to 3.6V.
- *
- * @note If an erase and a program operations are requested simultaneously,
- * the erase operation is performed before the program one.
- *
- * @param Address: specifies the address to be programmed.
- * This parameter can be any address in Program memory zone or in OTP zone.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= FLASH_PSIZE_WORD;
- FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint32_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the program operation is completed, disable the PG Bit */
- FLASH->CR &= (~FLASH_CR_PG);
- }
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @brief Programs a half word (16-bit) at a specified address.
- * @note This function must be used when the device voltage range is from 2.1V to 3.6V.
- *
- * @note If an erase and a program operations are requested simultaneously,
- * the erase operation is performed before the program one.
- *
- * @param Address: specifies the address to be programmed.
- * This parameter can be any address in Program memory zone or in OTP zone.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= FLASH_PSIZE_HALF_WORD;
- FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint16_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the program operation is completed, disable the PG Bit */
- FLASH->CR &= (~FLASH_CR_PG);
- }
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @brief Programs a byte (8-bit) at a specified address.
- * @note This function can be used within all the device supply voltage ranges.
- *
- * @note If an erase and a program operations are requested simultaneously,
- * the erase operation is performed before the program one.
- *
- * @param Address: specifies the address to be programmed.
- * This parameter can be any address in Program memory zone or in OTP zone.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= FLASH_PSIZE_BYTE;
- FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint8_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the program operation is completed, disable the PG Bit */
- FLASH->CR &= (~FLASH_CR_PG);
- }
-
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group3 Option Bytes Programming functions
- * @brief Option Bytes Programming functions
- *
-@verbatim
- ===============================================================================
- ##### Option Bytes Programming functions #####
- ===============================================================================
- [..]
- This group includes the following functions:
- (+) void FLASH_OB_Unlock(void)
- (+) void FLASH_OB_Lock(void)
- (+) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
- (+) void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
- (+) void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PCROPSelect)
- (+) void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState)
- (+) void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState)
- (+) void FLASH_OB_RDPConfig(uint8_t OB_RDP)
- (+) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
- (+) void FLASH_OB_BORConfig(uint8_t OB_BOR)
- (+) FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data)
- (+) FLASH_Status FLASH_OB_Launch(void)
- (+) uint32_t FLASH_OB_GetUser(void)
- (+) uint8_t FLASH_OB_GetWRP(void)
- (+) uint8_t FLASH_OB_GetWRP1(void)
- (+) uint8_t FLASH_OB_GetPCROP(void)
- (+) uint8_t FLASH_OB_GetPCROP1(void)
- (+) uint8_t FLASH_OB_GetRDP(void)
- (+) uint8_t FLASH_OB_GetBOR(void)
- [..]
- The following function can be used only for STM32F42xxx/43xxx devices.
- (+) void FLASH_OB_BootConfig(uint8_t OB_BOOT)
- [..]
- Any operation of erase or program should follow these steps:
- (#) Call the FLASH_OB_Unlock() function to enable the FLASH option control
- register access
-
- (#) Call one or several functions to program the desired Option Bytes:
- (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
- => to Enable/Disable the desired sector write protection
- (++) void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read
- Protection Level
- (++) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
- => to configure the user Option Bytes.
- (++) void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level
-
- (#) Once all needed Option Bytes to be programmed are correctly written,
- call the FLASH_OB_Launch() function to launch the Option Bytes
- programming process.
-
- -@- When changing the IWDG mode from HW to SW or from SW to HW, a system
- reset is needed to make the change effective.
-
- (#) Call the FLASH_OB_Lock() function to disable the FLASH option control
- register access (recommended to protect the Option Bytes against
- possible unwanted operations)
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Unlocks the FLASH Option Control Registers access.
- * @param None
- * @retval None
- */
-void FLASH_OB_Unlock(void)
-{
- if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
- {
- /* Authorizes the Option Byte register programming */
- FLASH->OPTKEYR = FLASH_OPT_KEY1;
- FLASH->OPTKEYR = FLASH_OPT_KEY2;
- }
-}
-
-/**
- * @brief Locks the FLASH Option Control Registers access.
- * @param None
- * @retval None
- */
-void FLASH_OB_Lock(void)
-{
- /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
- FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
-}
-
-/**
- * @brief Enables or disables the write protection of the desired sectors, for the first
- * 1 Mb of the Flash
- *
- * @note When the memory read protection level is selected (RDP level = 1),
- * it is not possible to program or erase the flash sector i if CortexM4
- * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
- * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
- *
- * @param OB_WRP: specifies the sector(s) to be write protected or unprotected.
- * This parameter can be one of the following values:
- * @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11
- * @arg OB_WRP_Sector_All
- * @param Newstate: new state of the Write Protection.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_WRP(OB_WRP));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- if(NewState != DISABLE)
- {
- *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP);
- }
- else
- {
- *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP;
- }
- }
-}
-
-/**
- * @brief Enables or disables the write protection of the desired sectors, for the second
- * 1 Mb of the Flash
- *
- * @note This function can be used only for STM32F42xxx/43xxx devices.
- *
- * @note When the memory read out protection is selected (RDP level = 1),
- * it is not possible to program or erase the flash sector i if CortexM4
- * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
- * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
- *
- * @param OB_WRP: specifies the sector(s) to be write protected or unprotected.
- * This parameter can be one of the following values:
- * @arg OB_WRP: A value between OB_WRP_Sector12 and OB_WRP_Sector23
- * @arg OB_WRP_Sector_All
- * @param Newstate: new state of the Write Protection.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_WRP(OB_WRP));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- if(NewState != DISABLE)
- {
- *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_WRP);
- }
- else
- {
- *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_WRP;
- }
- }
-}
-
-/**
- * @brief Select the Protection Mode (SPRMOD).
- *
- * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.
- *
- * @note After PCROP activation, Option Byte modification is not possible.
- * Exception made for the global Read Out Protection modification level (level1 to level0)
- * @note Once SPRMOD bit is active unprotection of a protected sector is not possible
- *
- * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
- *
- * @note Some Precautions should be taken when activating the PCROP feature :
- * The active value of nWRPi bits is inverted when PCROP mode is active, this means if SPRMOD = 1
- * and WRPi = 1 (default value), then the user sector i is read/write protected.
- * In order to avoid activation of PCROP Mode for undesired sectors, please follow the
- * below safety sequence :
- * - Disable PCROP for all Sectors using FLASH_OB_PCROPConfig(OB_PCROP_Sector_All, DISABLE) function
- * for Bank1 or FLASH_OB_PCROP1Config(OB_PCROP_Sector_All, DISABLE) function for Bank2
- * - Enable PCROP for the desired Sector i using FLASH_OB_PCROPConfig(Sector i, ENABLE) function
- * - Activate the PCROP Mode FLASH_OB_PCROPSelectionConfig() function.
- *
- * @param OB_PCROP: Select the Protection Mode of nWPRi bits
- * This parameter can be one of the following values:
- * @arg OB_PcROP_Disable: nWRPi control the write protection of respective user sectors.
- * @arg OB_PcROP_Enable: nWRPi control the read&write protection (PCROP) of respective user sectors.
- * @retval None
- */
-void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP)
-{
- uint8_t optiontmp = 0xFF;
-
- /* Check the parameters */
- assert_param(IS_OB_PCROP_SELECT(OB_PcROP));
-
- /* Mask SPRMOD bit */
- optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F);
- /* Update Option Byte */
- *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PcROP | optiontmp);
-
-}
-
-/**
- * @brief Enables or disables the read/write protection (PCROP) of the desired
- * sectors, for the first 1 MB of the Flash.
- *
- * @note This function can be used only for STM32F42xxx/43xxx , STM32F401xx/411xE
- * STM32F412xG and STM32F413_423xx devices.
- *
- * @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected.
- * This parameter can be one of the following values:
- * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector11 for
- * STM32F42xxx/43xxx devices and between OB_PCROP_Sector0 and
- * OB_PCROP_Sector5 for STM32F401xx/411xE devices.
- * @arg OB_PCROP_Sector_All
- * @param Newstate: new state of the Write Protection.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_PCROP(OB_PCROP));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- if(NewState != DISABLE)
- {
- *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_PCROP;
- }
- else
- {
- *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_PCROP);
- }
- }
-}
-
-/**
- * @brief Enables or disables the read/write protection (PCROP) of the desired
- * sectors
- *
- * @note This function can be used only for STM32F42xxx/43xxx devices.
- *
- * @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected.
- * This parameter can be one of the following values:
- * @arg OB_PCROP: A value between OB_PCROP_Sector12 and OB_PCROP_Sector23
- * @arg OB_PCROP_Sector_All
- * @param Newstate: new state of the Write Protection.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_PCROP(OB_PCROP));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- if(NewState != DISABLE)
- {
- *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_PCROP;
- }
- else
- {
- *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_PCROP);
- }
- }
-}
-
-
-/**
- * @brief Sets the read protection level.
- * @param OB_RDP: specifies the read protection level.
- * This parameter can be one of the following values:
- * @arg OB_RDP_Level_0: No protection
- * @arg OB_RDP_Level_1: Read protection of the memory
- * @arg OB_RDP_Level_2: Full chip protection
- *
- * /!\ Warning /!\ When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
- *
- * @retval None
- */
-void FLASH_OB_RDPConfig(uint8_t OB_RDP)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_RDP(OB_RDP));
-
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP;
-
- }
-}
-
-/**
- * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
- * @param OB_IWDG: Selects the IWDG mode
- * This parameter can be one of the following values:
- * @arg OB_IWDG_SW: Software IWDG selected
- * @arg OB_IWDG_HW: Hardware IWDG selected
- * @param OB_STOP: Reset event when entering STOP mode.
- * This parameter can be one of the following values:
- * @arg OB_STOP_NoRST: No reset generated when entering in STOP
- * @arg OB_STOP_RST: Reset generated when entering in STOP
- * @param OB_STDBY: Reset event when entering Standby mode.
- * This parameter can be one of the following values:
- * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
- * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
- * @retval None
- */
-void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
-{
- uint8_t optiontmp = 0xFF;
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
- assert_param(IS_OB_STOP_SOURCE(OB_STOP));
- assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
- /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */
- optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F);
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F446xx)
- /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */
- optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F);
-#endif /* STM32F40_41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx */
-
- /* Update User Option Byte */
- *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp)));
- }
-}
-
-/**
- * @brief Configure the Dual Bank Boot.
- *
- * @note This function can be used only for STM32F42xxx/43xxx devices.
- *
- * @param OB_BOOT: specifies the Dual Bank Boot Option byte.
- * This parameter can be one of the following values:
- * @arg OB_Dual_BootEnabled: Dual Bank Boot Enable
- * @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled
- * @retval None
- */
-void FLASH_OB_BootConfig(uint8_t OB_BOOT)
-{
- /* Check the parameters */
- assert_param(IS_OB_BOOT(OB_BOOT));
-
- /* Set Dual Bank Boot */
- *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2);
- *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOOT;
-
-}
-
-/**
- * @brief Sets the BOR Level.
- * @param OB_BOR: specifies the Option Bytes BOR Reset Level.
- * This parameter can be one of the following values:
- * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
- * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
- * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
- * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
- * @retval None
- */
-void FLASH_OB_BORConfig(uint8_t OB_BOR)
-{
- /* Check the parameters */
- assert_param(IS_OB_BOR(OB_BOR));
-
- /* Set the BOR Level */
- *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);
- *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR;
-
-}
-
-/**
- * @brief Launch the option byte loading.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_OB_Launch(void)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Set the OPTSTRT bit in OPTCR register */
- *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- return status;
-}
-
-/**
- * @brief Returns the FLASH User Option Bytes values.
- * @param None
- * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
- * and RST_STDBY(Bit2).
- */
-uint8_t FLASH_OB_GetUser(void)
-{
- /* Return the User Option Byte */
- return (uint8_t)(FLASH->OPTCR >> 5);
-}
-
-/**
- * @brief Returns the FLASH Write Protection Option Bytes value.
- * @param None
- * @retval The FLASH Write Protection Option Bytes value
- */
-uint16_t FLASH_OB_GetWRP(void)
-{
- /* Return the FLASH write protection Register value */
- return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
-}
-
-/**
- * @brief Returns the FLASH Write Protection Option Bytes value.
- *
- * @note This function can be used only for STM32F42xxx/43xxx devices.
- *
- * @param None
- * @retval The FLASH Write Protection Option Bytes value
- */
-uint16_t FLASH_OB_GetWRP1(void)
-{
- /* Return the FLASH write protection Register value */
- return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
-}
-
-/**
- * @brief Returns the FLASH PC Read/Write Protection Option Bytes value.
- *
- * @note This function can be used only for STM32F42xxx/43xxx devices and STM32F401xx/411xE devices.
- *
- * @param None
- * @retval The FLASH PC Read/Write Protection Option Bytes value
- */
-uint16_t FLASH_OB_GetPCROP(void)
-{
- /* Return the FLASH PC Read/write protection Register value */
- return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
-}
-
-/**
- * @brief Returns the FLASH PC Read/Write Protection Option Bytes value.
- *
- * @note This function can be used only for STM32F42xxx/43xxx devices.
- *
- * @param None
- * @retval The FLASH PC Read/Write Protection Option Bytes value
- */
-uint16_t FLASH_OB_GetPCROP1(void)
-{
- /* Return the FLASH write protection Register value */
- return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
-}
-
-/**
- * @brief Returns the FLASH Read Protection level.
- * @param None
- * @retval FLASH ReadOut Protection Status:
- * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
- * - RESET, when OB_RDP_Level_0 is set
- */
-FlagStatus FLASH_OB_GetRDP(void)
-{
- FlagStatus readstatus = RESET;
-
- if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0))
- {
- readstatus = SET;
- }
- else
- {
- readstatus = RESET;
- }
- return readstatus;
-}
-
-/**
- * @brief Returns the FLASH BOR level.
- * @param None
- * @retval The FLASH BOR level:
- * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
- * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
- * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
- * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V
- */
-uint8_t FLASH_OB_GetBOR(void)
-{
- /* Return the FLASH BOR level */
- return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C);
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified FLASH interrupts.
- * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg FLASH_IT_ERR: FLASH Error Interrupt
- * @arg FLASH_IT_EOP: FLASH end of operation Interrupt
- * @retval None
- */
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_IT(FLASH_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- /* Enable the interrupt sources */
- FLASH->CR |= FLASH_IT;
- }
- else
- {
- /* Disable the interrupt sources */
- FLASH->CR &= ~(uint32_t)FLASH_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified FLASH flag is set or not.
- * @param FLASH_FLAG: specifies the FLASH flag to check.
- * This parameter can be one of the following values:
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
- * @arg FLASH_FLAG_OPERR: FLASH operation Error flag
- * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
- * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
- * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
- * @arg FLASH_FLAG_RDERR: FLASH (PCROP) Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices)
- * @arg FLASH_FLAG_BSY: FLASH Busy flag
- * @retval The new state of FLASH_FLAG (SET or RESET).
- */
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
-
- if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the new state of FLASH_FLAG (SET or RESET) */
- return bitstatus;
-}
-
-/**
- * @brief Clears the FLASH's pending flags.
- * @param FLASH_FLAG: specifies the FLASH flags to clear.
- * This parameter can be any combination of the following values:
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
- * @arg FLASH_FLAG_OPERR: FLASH operation Error flag
- * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
- * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
- * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
- * @arg FLASH_FLAG_RDERR: FLASH Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices)
- * @retval None
- */
-void FLASH_ClearFlag(uint32_t FLASH_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
-
- /* Clear the flags */
- FLASH->SR = FLASH_FLAG;
-}
-
-/**
- * @brief Returns the FLASH Status.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_RD, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_GetStatus(void)
-{
- FLASH_Status flashstatus = FLASH_COMPLETE;
-
- if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
- {
- flashstatus = FLASH_BUSY;
- }
- else
- {
- if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00)
- {
- flashstatus = FLASH_ERROR_WRP;
- }
- else
- {
- if((FLASH->SR & FLASH_FLAG_RDERR) != (uint32_t)0x00)
- {
- flashstatus = FLASH_ERROR_RD;
- }
- else
- {
- if((FLASH->SR & (uint32_t)0xE0) != (uint32_t)0x00)
- {
- flashstatus = FLASH_ERROR_PROGRAM;
- }
- else
- {
- if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00)
- {
- flashstatus = FLASH_ERROR_OPERATION;
- }
- else
- {
- flashstatus = FLASH_COMPLETE;
- }
- }
- }
- }
- }
- /* Return the FLASH Status */
- return flashstatus;
-}
-
-/**
- * @brief Waits for a FLASH operation to complete.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_WaitForLastOperation(void)
-{
- __IO FLASH_Status status = FLASH_COMPLETE;
-
- /* Check for the FLASH Status */
- status = FLASH_GetStatus();
-
- /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
- Even if the FLASH operation fails, the BUSY flag will be reset and an error
- flag will be set */
- while(status == FLASH_BUSY)
- {
- status = FLASH_GetStatus();
- }
- /* Return the operation status */
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_flash.h b/底盘/底盘-old/底盘/Library/stm32f4xx_flash.h
deleted file mode 100644
index c7c3e6f..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_flash.h
+++ /dev/null
@@ -1,489 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_flash.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the FLASH
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_FLASH_H
-#define __STM32F4xx_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup FLASH
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/**
- * @brief FLASH Status
- */
-typedef enum
-{
- FLASH_BUSY = 1,
- FLASH_ERROR_RD,
- FLASH_ERROR_PGS,
- FLASH_ERROR_PGP,
- FLASH_ERROR_PGA,
- FLASH_ERROR_WRP,
- FLASH_ERROR_PROGRAM,
- FLASH_ERROR_OPERATION,
- FLASH_COMPLETE
-}FLASH_Status;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FLASH_Exported_Constants
- * @{
- */
-
-/** @defgroup Flash_Latency
- * @{
- */
-#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
-#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */
-#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */
-#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */
-#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */
-#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */
-#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */
-#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */
-#define FLASH_Latency_8 ((uint8_t)0x0008) /*!< FLASH Eight Latency cycles */
-#define FLASH_Latency_9 ((uint8_t)0x0009) /*!< FLASH Nine Latency cycles */
-#define FLASH_Latency_10 ((uint8_t)0x000A) /*!< FLASH Ten Latency cycles */
-#define FLASH_Latency_11 ((uint8_t)0x000B) /*!< FLASH Eleven Latency cycles */
-#define FLASH_Latency_12 ((uint8_t)0x000C) /*!< FLASH Twelve Latency cycles */
-#define FLASH_Latency_13 ((uint8_t)0x000D) /*!< FLASH Thirteen Latency cycles */
-#define FLASH_Latency_14 ((uint8_t)0x000E) /*!< FLASH Fourteen Latency cycles */
-#define FLASH_Latency_15 ((uint8_t)0x000F) /*!< FLASH Fifteen Latency cycles */
-
-
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
- ((LATENCY) == FLASH_Latency_1) || \
- ((LATENCY) == FLASH_Latency_2) || \
- ((LATENCY) == FLASH_Latency_3) || \
- ((LATENCY) == FLASH_Latency_4) || \
- ((LATENCY) == FLASH_Latency_5) || \
- ((LATENCY) == FLASH_Latency_6) || \
- ((LATENCY) == FLASH_Latency_7) || \
- ((LATENCY) == FLASH_Latency_8) || \
- ((LATENCY) == FLASH_Latency_9) || \
- ((LATENCY) == FLASH_Latency_10) || \
- ((LATENCY) == FLASH_Latency_11) || \
- ((LATENCY) == FLASH_Latency_12) || \
- ((LATENCY) == FLASH_Latency_13) || \
- ((LATENCY) == FLASH_Latency_14) || \
- ((LATENCY) == FLASH_Latency_15))
-/**
- * @}
- */
-
-/** @defgroup FLASH_Voltage_Range
- * @{
- */
-#define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */
-#define VoltageRange_2 ((uint8_t)0x01) /*!= 0x08000000) && ((ADDRESS) <= 0x081FFFFF)) ||\
- (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
-
-#if defined (STM32F40_41xxx) || defined(STM32F412xG)
-#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x080FFFFF)) ||\
- (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
-#endif /* STM32F40_41xxx || STM32F412xG */
-
-#if defined (STM32F401xx)
-#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF)) ||\
- (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
-#endif /* STM32F401xx */
-
-#if defined (STM32F411xE) || defined (STM32F446xx)
-#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0807FFFF)) ||\
- (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
-#endif /* STM32F411xE || STM32F446xx */
-
-#if defined (STM32F410xx)
-#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF)) ||\
- (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
-#endif /* STM32F410xx */
-
-#if defined(STM32F413_423xx)
-#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0817FFFF)) ||\
- (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7BDF)))
-#endif /* STM32F413_423xx */
-/**
- * @}
- */
-
-/** @defgroup Option_Bytes_Write_Protection
- * @{
- */
-#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
-#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
-#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
-#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
-#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
-#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
-#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
-#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
-#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */
-#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */
-#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */
-#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
-#define OB_WRP_Sector_12 ((uint32_t)0x00000001) /*!< Write protection of Sector12 */
-#define OB_WRP_Sector_13 ((uint32_t)0x00000002) /*!< Write protection of Sector13 */
-#define OB_WRP_Sector_14 ((uint32_t)0x00000004) /*!< Write protection of Sector14 */
-#define OB_WRP_Sector_15 ((uint32_t)0x00000008) /*!< Write protection of Sector15 */
-#define OB_WRP_Sector_16 ((uint32_t)0x00000010) /*!< Write protection of Sector16 */
-#define OB_WRP_Sector_17 ((uint32_t)0x00000020) /*!< Write protection of Sector17 */
-#define OB_WRP_Sector_18 ((uint32_t)0x00000040) /*!< Write protection of Sector18 */
-#define OB_WRP_Sector_19 ((uint32_t)0x00000080) /*!< Write protection of Sector19 */
-#define OB_WRP_Sector_20 ((uint32_t)0x00000100) /*!< Write protection of Sector20 */
-#define OB_WRP_Sector_21 ((uint32_t)0x00000200) /*!< Write protection of Sector21 */
-#define OB_WRP_Sector_22 ((uint32_t)0x00000400) /*!< Write protection of Sector22 */
-#define OB_WRP_Sector_23 ((uint32_t)0x00000800) /*!< Write protection of Sector23 */
-#define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
-
-#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
-/**
- * @}
- */
-
-/** @defgroup Selection_Protection_Mode
- * @{
- */
-#define OB_PcROP_Disable ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
-#define OB_PcROP_Enable ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */
-#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PcROP_Disable) || ((PCROP) == OB_PcROP_Enable))
-/**
- * @}
- */
-
-/** @defgroup Option_Bytes_PC_ReadWrite_Protection
- * @{
- */
-#define OB_PCROP_Sector_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */
-#define OB_PCROP_Sector_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */
-#define OB_PCROP_Sector_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */
-#define OB_PCROP_Sector_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */
-#define OB_PCROP_Sector_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */
-#define OB_PCROP_Sector_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */
-#define OB_PCROP_Sector_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */
-#define OB_PCROP_Sector_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */
-#define OB_PCROP_Sector_8 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector8 */
-#define OB_PCROP_Sector_9 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector9 */
-#define OB_PCROP_Sector_10 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector10 */
-#define OB_PCROP_Sector_11 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector11 */
-#define OB_PCROP_Sector_12 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector12 */
-#define OB_PCROP_Sector_13 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector13 */
-#define OB_PCROP_Sector_14 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector14 */
-#define OB_PCROP_Sector_15 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector15 */
-#define OB_PCROP_Sector_16 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector16 */
-#define OB_PCROP_Sector_17 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector17 */
-#define OB_PCROP_Sector_18 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector18 */
-#define OB_PCROP_Sector_19 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector19 */
-#define OB_PCROP_Sector_20 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector20 */
-#define OB_PCROP_Sector_21 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector21 */
-#define OB_PCROP_Sector_22 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22 */
-#define OB_PCROP_Sector_23 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23 */
-#define OB_PCROP_Sector_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */
-
-#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_Read_Protection
- * @{
- */
-#define OB_RDP_Level_0 ((uint8_t)0xAA)
-#define OB_RDP_Level_1 ((uint8_t)0x55)
-/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2
- it's no more possible to go back to level 1 or 0 */
-#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
- ((LEVEL) == OB_RDP_Level_1))/*||\
- ((LEVEL) == OB_RDP_Level_2))*/
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_IWatchdog
- * @{
- */
-#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */
-#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_nRST_STOP
- * @{
- */
-#define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
-#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
-/**
- * @}
- */
-
-
-/** @defgroup FLASH_Option_Bytes_nRST_STDBY
- * @{
- */
-#define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
-/**
- * @}
- */
-
-/** @defgroup FLASH_BOR_Reset_Level
- * @{
- */
-#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */
-#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */
-#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */
-#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */
-#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
- ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
-/**
- * @}
- */
-
-/** @defgroup FLASH_Dual_Boot
- * @{
- */
-#define OB_Dual_BootEnabled ((uint8_t)0x10) /*!< Dual Bank Boot Enable */
-#define OB_Dual_BootDisabled ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */
-#define IS_OB_BOOT(BOOT) (((BOOT) == OB_Dual_BootEnabled) || ((BOOT) == OB_Dual_BootDisabled))
-/**
- * @}
- */
-
-/** @defgroup FLASH_Interrupts
- * @{
- */
-#define FLASH_IT_EOP ((uint32_t)0x01000000) /*!< End of FLASH Operation Interrupt source */
-#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */
-#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000))
-/**
- * @}
- */
-
-/** @defgroup FLASH_Flags
- * @{
- */
-#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */
-#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */
-#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
-#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */
-#define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */
-#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */
-#define FLASH_FLAG_RDERR ((uint32_t)0x00000100) /*!< Read Protection error flag (PCROP) */
-#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */
-#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFE0C) == 0x00000000) && ((FLAG) != 0x00000000))
-#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \
- ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \
- ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \
- ((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_RDERR))
-/**
- * @}
- */
-
-/** @defgroup FLASH_Program_Parallelism
- * @{
- */
-#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000)
-#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100)
-#define FLASH_PSIZE_WORD ((uint32_t)0x00000200)
-#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300)
-#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF)
-/**
- * @}
- */
-
-/** @defgroup FLASH_Keys
- * @{
- */
-#define RDP_KEY ((uint16_t)0x00A5)
-#define FLASH_KEY1 ((uint32_t)0x45670123)
-#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
-#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B)
-#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F)
-/**
- * @}
- */
-
-/**
- * @brief ACR register byte 0 (Bits[7:0]) base address
- */
-#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
-/**
- * @brief OPTCR register byte 0 (Bits[7:0]) base address
- */
-#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14)
-/**
- * @brief OPTCR register byte 1 (Bits[15:8]) base address
- */
-#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)
-/**
- * @brief OPTCR register byte 2 (Bits[23:16]) base address
- */
-#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16)
-/**
- * @brief OPTCR register byte 3 (Bits[31:24]) base address
- */
-#define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17)
-
-/**
- * @brief OPTCR1 register byte 0 (Bits[7:0]) base address
- */
-#define OPTCR1_BYTE2_ADDRESS ((uint32_t)0x40023C1A)
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* FLASH Interface configuration functions ************************************/
-void FLASH_SetLatency(uint32_t FLASH_Latency);
-void FLASH_PrefetchBufferCmd(FunctionalState NewState);
-void FLASH_InstructionCacheCmd(FunctionalState NewState);
-void FLASH_DataCacheCmd(FunctionalState NewState);
-void FLASH_InstructionCacheReset(void);
-void FLASH_DataCacheReset(void);
-
-/* FLASH Memory Programming functions *****************************************/
-void FLASH_Unlock(void);
-void FLASH_Lock(void);
-FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange);
-FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange);
-FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange);
-FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange);
-FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data);
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
-FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);
-
-/* Option Bytes Programming functions *****************************************/
-void FLASH_OB_Unlock(void);
-void FLASH_OB_Lock(void);
-void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
-void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState);
-void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP);
-void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState);
-void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState);
-void FLASH_OB_RDPConfig(uint8_t OB_RDP);
-void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
-void FLASH_OB_BORConfig(uint8_t OB_BOR);
-void FLASH_OB_BootConfig(uint8_t OB_BOOT);
-FLASH_Status FLASH_OB_Launch(void);
-uint8_t FLASH_OB_GetUser(void);
-uint16_t FLASH_OB_GetWRP(void);
-uint16_t FLASH_OB_GetWRP1(void);
-uint16_t FLASH_OB_GetPCROP(void);
-uint16_t FLASH_OB_GetPCROP1(void);
-FlagStatus FLASH_OB_GetRDP(void);
-uint8_t FLASH_OB_GetBOR(void);
-
-/* Interrupts and flags management functions **********************************/
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
-void FLASH_ClearFlag(uint32_t FLASH_FLAG);
-FLASH_Status FLASH_GetStatus(void);
-FLASH_Status FLASH_WaitForLastOperation(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_FLASH_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_flash_ramfunc.c b/底盘/底盘-old/底盘/Library/stm32f4xx_flash_ramfunc.c
deleted file mode 100644
index 65401ca..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_flash_ramfunc.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_flash_ramfunc.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief FLASH RAMFUNC module driver.
- * This file provides a FLASH firmware functions which should be
- * executed from internal SRAM
- * + Stop/Start the flash interface while System Run
- * + Enable/Disable the flash sleep while System Run
- *
- @verbatim
- ==============================================================================
- ##### APIs executed from Internal RAM #####
- ==============================================================================
- [..]
- *** ARM Compiler ***
- --------------------
- [..] RAM functions are defined using the toolchain options.
- Functions that are be executed in RAM should reside in a separate
- source module. Using the 'Options for File' dialog you can simply change
- the 'Code / Const' area of a module to a memory space in physical RAM.
- Available memory areas are declared in the 'Target' tab of the
- Options for Target' dialog.
-
- *** ICCARM Compiler ***
- -----------------------
- [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
-
- *** GNU Compiler ***
- --------------------
- [..] RAM functions are defined using a specific toolchain attribute
- "__attribute__((section(".RamFunc")))".
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_flash_ramfunc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup FLASH RAMFUNC
- * @brief FLASH RAMFUNC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup FLASH_RAMFUNC_Private_Functions
- * @{
- */
-
-/** @defgroup FLASH_RAMFUNC_Group1 Peripheral features functions executed from internal RAM
- * @brief Peripheral Extended features functions
- *
-@verbatim
-
- ===============================================================================
- ##### ramfunc functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions that should be executed from RAM
- transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start/Stop the flash interface while System Run
- * @note This mode is only available for STM32F411xx devices.
- * @note This mode could n't be set while executing with the flash itself.
- * It should be done with specific routine executed from RAM.
- * @param NewState: new state of the Smart Card mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-__RAM_FUNC FLASH_FlashInterfaceCmd(FunctionalState NewState)
-{
- if (NewState != DISABLE)
- {
- /* Start the flash interface while System Run */
- CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
- }
- else
- {
- /* Stop the flash interface while System Run */
- SET_BIT(PWR->CR, PWR_CR_FISSR);
- }
-}
-
-/**
- * @brief Enable/Disable the flash sleep while System Run
- * @note This mode is only available for STM32F411xx devices.
- * @note This mode could n't be set while executing with the flash itself.
- * It should be done with specific routine executed from RAM.
- * @param NewState: new state of the Smart Card mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-__RAM_FUNC FLASH_FlashSleepModeCmd(FunctionalState NewState)
-{
- if (NewState != DISABLE)
- {
- /* Enable the flash sleep while System Run */
- SET_BIT(PWR->CR, PWR_CR_FMSSR);
- }
- else
- {
- /* Disable the flash sleep while System Run */
- CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_flash_ramfunc.h b/底盘/底盘-old/底盘/Library/stm32f4xx_flash_ramfunc.h
deleted file mode 100644
index 503120d..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_flash_ramfunc.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_flash_ramfunc.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief Header file of FLASH RAMFUNC driver.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_FLASH_RAMFUNC_H
-#define __STM32F4xx_FLASH_RAMFUNC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup FLASH RAMFUNC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/**
- * @brief __RAM_FUNC definition
- */
-#if defined ( __CC_ARM )
-/* ARM Compiler
- ------------
- RAM functions are defined using the toolchain options.
- Functions that are executed in RAM should reside in a separate source module.
- Using the 'Options for File' dialog you can simply change the 'Code / Const'
- area of a module to a memory space in physical RAM.
- Available memory areas are declared in the 'Target' tab of the 'Options for Target'
- dialog.
-*/
-#define __RAM_FUNC void
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
- ---------------
- RAM functions are defined using a specific toolchain keyword "__ramfunc".
-*/
-#define __RAM_FUNC __ramfunc void
-
-#elif defined ( __GNUC__ )
-/* GNU Compiler
- ------------
- RAM functions are defined using a specific toolchain attribute
- "__attribute__((section(".RamFunc")))".
-*/
-#define __RAM_FUNC void __attribute__((section(".RamFunc")))
-
-#endif
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-__RAM_FUNC FLASH_FlashInterfaceCmd(FunctionalState NewState);
-__RAM_FUNC FLASH_FlashSleepModeCmd(FunctionalState NewState);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_FLASH_RAMFUNC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_fmpi2c.c b/底盘/底盘-old/底盘/Library/stm32f4xx_fmpi2c.c
deleted file mode 100644
index 5d4be0d..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_fmpi2c.c
+++ /dev/null
@@ -1,1546 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_fmpi2c.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Inter-Integrated circuit Fast Mode Plus (FMPI2C):
- * + Initialization and Configuration
- * + Communications handling
- * + SMBUS management
- * + FMPI2C registers management
- * + Data transfers management
- * + DMA transfers management
- * + Interrupts and flags management
- *
- * @verbatim
- ============================================================================
- ##### How to use this driver #####
- ============================================================================
- [..]
- (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)
- function for FMPI2C peripheral.
- (#) Enable SDA, SCL and SMBA (when used) GPIO clocks using
- RCC_AHBPeriphClockCmd() function.
- (#) Peripherals alternate function:
- (++) Connect the pin to the desired peripherals' Alternate
- Function (AF) using GPIO_PinAFConfig() function.
- (++) Configure the desired pin in alternate function by:
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- (++) Select the type, OpenDrain and speed via
- GPIO_PuPd, GPIO_OType and GPIO_Speed members
- (++) Call GPIO_Init() function.
- (#) Program the Mode, Timing , Own address, Ack and Acknowledged Address
- using the FMPI2C_Init() function.
- (#) Optionally you can enable/configure the following parameters without
- re-initialization (i.e there is no need to call again FMPI2C_Init() function):
- (++) Enable the acknowledge feature using FMPI2C_AcknowledgeConfig() function.
- (++) Enable the dual addressing mode using FMPI2C_DualAddressCmd() function.
- (++) Enable the general call using the FMPI2C_GeneralCallCmd() function.
- (++) Enable the clock stretching using FMPI2C_StretchClockCmd() function.
- (++) Enable the PEC Calculation using FMPI2C_CalculatePEC() function.
- (++) For SMBus Mode:
- (+++) Enable the SMBusAlert pin using FMPI2C_SMBusAlertCmd() function.
- (#) Enable the NVIC and the corresponding interrupt using the function
- FMPI2C_ITConfig() if you need to use interrupt mode.
- (#) When using the DMA mode
- (++) Configure the DMA using DMA_Init() function.
- (++) Active the needed channel Request using FMPI2C_DMACmd() function.
- (#) Enable the FMPI2C using the FMPI2C_Cmd() function.
- (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the
- transfers.
- [..]
- (@) When using FMPI2C in Fast Mode Plus, SCL and SDA pin 20mA current drive capability
- must be enabled by setting the driving capability control bit in SYSCFG.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_fmpi2c.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup FMPI2C FMPI2C
- * @brief FMPI2C driver modules
- * @{
- */
-#if defined(STM32F410xx) || defined(STM32F412xG)|| defined(STM32F413_423xx) || defined(STM32F446xx)
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-#define CR1_CLEAR_MASK ((uint32_t)0x00CFE0FF) /*FMPI2C_AnalogFilter));
- assert_param(IS_FMPI2C_DIGITAL_FILTER(FMPI2C_InitStruct->FMPI2C_DigitalFilter));
- assert_param(IS_FMPI2C_MODE(FMPI2C_InitStruct->FMPI2C_Mode));
- assert_param(IS_FMPI2C_OWN_ADDRESS1(FMPI2C_InitStruct->FMPI2C_OwnAddress1));
- assert_param(IS_FMPI2C_ACK(FMPI2C_InitStruct->FMPI2C_Ack));
- assert_param(IS_FMPI2C_ACKNOWLEDGE_ADDRESS(FMPI2C_InitStruct->FMPI2C_AcknowledgedAddress));
-
- /* Disable FMPI2Cx Peripheral */
- FMPI2Cx->CR1 &= (uint32_t)~((uint32_t)FMPI2C_CR1_PE);
-
- /*---------------------------- FMPI2Cx FILTERS Configuration ------------------*/
- /* Get the FMPI2Cx CR1 value */
- tmpreg = FMPI2Cx->CR1;
- /* Clear FMPI2Cx CR1 register */
- tmpreg &= CR1_CLEAR_MASK;
- /* Configure FMPI2Cx: analog and digital filter */
- /* Set ANFOFF bit according to FMPI2C_AnalogFilter value */
- /* Set DFN bits according to FMPI2C_DigitalFilter value */
- tmpreg |= (uint32_t)FMPI2C_InitStruct->FMPI2C_AnalogFilter |(FMPI2C_InitStruct->FMPI2C_DigitalFilter << 8);
-
- /* Write to FMPI2Cx CR1 */
- FMPI2Cx->CR1 = tmpreg;
-
- /*---------------------------- FMPI2Cx TIMING Configuration -------------------*/
- /* Configure FMPI2Cx: Timing */
- /* Set TIMINGR bits according to FMPI2C_Timing */
- /* Write to FMPI2Cx TIMING */
- FMPI2Cx->TIMINGR = FMPI2C_InitStruct->FMPI2C_Timing & TIMING_CLEAR_MASK;
-
- /* Enable FMPI2Cx Peripheral */
- FMPI2Cx->CR1 |= FMPI2C_CR1_PE;
-
- /*---------------------------- FMPI2Cx OAR1 Configuration ---------------------*/
- /* Clear tmpreg local variable */
- tmpreg = 0;
- /* Clear OAR1 register */
- FMPI2Cx->OAR1 = (uint32_t)tmpreg;
- /* Clear OAR2 register */
- FMPI2Cx->OAR2 = (uint32_t)tmpreg;
- /* Configure FMPI2Cx: Own Address1 and acknowledged address */
- /* Set OA1MODE bit according to FMPI2C_AcknowledgedAddress value */
- /* Set OA1 bits according to FMPI2C_OwnAddress1 value */
- tmpreg = (uint32_t)((uint32_t)FMPI2C_InitStruct->FMPI2C_AcknowledgedAddress | \
- (uint32_t)FMPI2C_InitStruct->FMPI2C_OwnAddress1);
- /* Write to FMPI2Cx OAR1 */
- FMPI2Cx->OAR1 = tmpreg;
- /* Enable Own Address1 acknowledgement */
- FMPI2Cx->OAR1 |= FMPI2C_OAR1_OA1EN;
-
- /*---------------------------- FMPI2Cx MODE Configuration ---------------------*/
- /* Configure FMPI2Cx: mode */
- /* Set SMBDEN and SMBHEN bits according to FMPI2C_Mode value */
- tmpreg = FMPI2C_InitStruct->FMPI2C_Mode;
- /* Write to FMPI2Cx CR1 */
- FMPI2Cx->CR1 |= tmpreg;
-
- /*---------------------------- FMPI2Cx ACK Configuration ----------------------*/
- /* Get the FMPI2Cx CR2 value */
- tmpreg = FMPI2Cx->CR2;
- /* Clear FMPI2Cx CR2 register */
- tmpreg &= CR2_CLEAR_MASK;
- /* Configure FMPI2Cx: acknowledgement */
- /* Set NACK bit according to FMPI2C_Ack value */
- tmpreg |= FMPI2C_InitStruct->FMPI2C_Ack;
- /* Write to FMPI2Cx CR2 */
- FMPI2Cx->CR2 = tmpreg;
-}
-
-/**
- * @brief Fills each FMPI2C_InitStruct member with its default value.
- * @param FMPI2C_InitStruct: pointer to an FMPI2C_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void FMPI2C_StructInit(FMPI2C_InitTypeDef* FMPI2C_InitStruct)
-{
- /*---------------- Reset FMPI2C init structure parameters values --------------*/
- /* Initialize the FMPI2C_Timing member */
- FMPI2C_InitStruct->FMPI2C_Timing = 0;
- /* Initialize the FMPI2C_AnalogFilter member */
- FMPI2C_InitStruct->FMPI2C_AnalogFilter = FMPI2C_AnalogFilter_Enable;
- /* Initialize the FMPI2C_DigitalFilter member */
- FMPI2C_InitStruct->FMPI2C_DigitalFilter = 0;
- /* Initialize the FMPI2C_Mode member */
- FMPI2C_InitStruct->FMPI2C_Mode = FMPI2C_Mode_FMPI2C;
- /* Initialize the FMPI2C_OwnAddress1 member */
- FMPI2C_InitStruct->FMPI2C_OwnAddress1 = 0;
- /* Initialize the FMPI2C_Ack member */
- FMPI2C_InitStruct->FMPI2C_Ack = FMPI2C_Ack_Disable;
- /* Initialize the FMPI2C_AcknowledgedAddress member */
- FMPI2C_InitStruct->FMPI2C_AcknowledgedAddress = FMPI2C_AcknowledgedAddress_7bit;
-}
-
-/**
- * @brief Enables or disables the specified FMPI2C peripheral.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param NewState: new state of the FMPI2Cx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMPI2C_Cmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected FMPI2C peripheral */
- FMPI2Cx->CR1 |= FMPI2C_CR1_PE;
- }
- else
- {
- /* Disable the selected FMPI2C peripheral */
- FMPI2Cx->CR1 &= (uint32_t)~((uint32_t)FMPI2C_CR1_PE);
- }
-}
-
-
-/**
- * @brief Enables or disables the specified FMPI2C software reset.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @retval None
- */
-void FMPI2C_SoftwareResetCmd(FMPI2C_TypeDef* FMPI2Cx)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
-
- /* Disable peripheral */
- FMPI2Cx->CR1 &= (uint32_t)~((uint32_t)FMPI2C_CR1_PE);
-
- /* Perform a dummy read to delay the disable of peripheral for minimum
- 3 APB clock cycles to perform the software reset functionality */
- *(__IO uint32_t *)(uint32_t)FMPI2Cx;
-
- /* Enable peripheral */
- FMPI2Cx->CR1 |= FMPI2C_CR1_PE;
-}
-
-/**
- * @brief Enables or disables the specified FMPI2C interrupts.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param FMPI2C_IT: specifies the FMPI2C interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg FMPI2C_IT_ERRI: Error interrupt mask
- * @arg FMPI2C_IT_TCI: Transfer Complete interrupt mask
- * @arg FMPI2C_IT_STOPI: Stop Detection interrupt mask
- * @arg FMPI2C_IT_NACKI: Not Acknowledge received interrupt mask
- * @arg FMPI2C_IT_ADDRI: Address Match interrupt mask
- * @arg FMPI2C_IT_RXI: RX interrupt mask
- * @arg FMPI2C_IT_TXI: TX interrupt mask
- * @param NewState: new state of the specified FMPI2C interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMPI2C_ITConfig(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_FMPI2C_CONFIG_IT(FMPI2C_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected FMPI2C interrupts */
- FMPI2Cx->CR1 |= FMPI2C_IT;
- }
- else
- {
- /* Disable the selected FMPI2C interrupts */
- FMPI2Cx->CR1 &= (uint32_t)~((uint32_t)FMPI2C_IT);
- }
-}
-
-/**
- * @brief Enables or disables the FMPI2C Clock stretching.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param NewState: new state of the FMPI2Cx Clock stretching.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMPI2C_StretchClockCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable clock stretching */
- FMPI2Cx->CR1 &= (uint32_t)~((uint32_t)FMPI2C_CR1_NOSTRETCH);
- }
- else
- {
- /* Disable clock stretching */
- FMPI2Cx->CR1 |= FMPI2C_CR1_NOSTRETCH;
- }
-}
-
-/**
- * @brief Enables or disables the FMPI2C own address 2.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param NewState: new state of the FMPI2C own address 2.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMPI2C_DualAddressCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable own address 2 */
- FMPI2Cx->OAR2 |= FMPI2C_OAR2_OA2EN;
- }
- else
- {
- /* Disable own address 2 */
- FMPI2Cx->OAR2 &= (uint32_t)~((uint32_t)FMPI2C_OAR2_OA2EN);
- }
-}
-
-/**
- * @brief Configures the FMPI2C slave own address 2 and mask.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param Address: specifies the slave address to be programmed.
- * @param Mask: specifies own address 2 mask to be programmed.
- * This parameter can be one of the following values:
- * @arg FMPI2C_OA2_NoMask: no mask.
- * @arg FMPI2C_OA2_Mask01: OA2[1] is masked and don't care.
- * @arg FMPI2C_OA2_Mask02: OA2[2:1] are masked and don't care.
- * @arg FMPI2C_OA2_Mask03: OA2[3:1] are masked and don't care.
- * @arg FMPI2C_OA2_Mask04: OA2[4:1] are masked and don't care.
- * @arg FMPI2C_OA2_Mask05: OA2[5:1] are masked and don't care.
- * @arg FMPI2C_OA2_Mask06: OA2[6:1] are masked and don't care.
- * @arg FMPI2C_OA2_Mask07: OA2[7:1] are masked and don't care.
- * @retval None
- */
-void FMPI2C_OwnAddress2Config(FMPI2C_TypeDef* FMPI2Cx, uint16_t Address, uint8_t Mask)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FMPI2C_OWN_ADDRESS2(Address));
- assert_param(IS_FMPI2C_OWN_ADDRESS2_MASK(Mask));
-
- /* Get the old register value */
- tmpreg = FMPI2Cx->OAR2;
-
- /* Reset FMPI2Cx OA2 bit [7:1] and OA2MSK bit [1:0] */
- tmpreg &= (uint32_t)~((uint32_t)(FMPI2C_OAR2_OA2 | FMPI2C_OAR2_OA2MSK));
-
- /* Set FMPI2Cx SADD */
- tmpreg |= (uint32_t)(((uint32_t)Address & FMPI2C_OAR2_OA2) | \
- (((uint32_t)Mask << 8) & FMPI2C_OAR2_OA2MSK)) ;
-
- /* Store the new register value */
- FMPI2Cx->OAR2 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the FMPI2C general call mode.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param NewState: new state of the FMPI2C general call mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMPI2C_GeneralCallCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable general call mode */
- FMPI2Cx->CR1 |= FMPI2C_CR1_GCEN;
- }
- else
- {
- /* Disable general call mode */
- FMPI2Cx->CR1 &= (uint32_t)~((uint32_t)FMPI2C_CR1_GCEN);
- }
-}
-
-/**
- * @brief Enables or disables the FMPI2C slave byte control.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param NewState: new state of the FMPI2C slave byte control.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMPI2C_SlaveByteControlCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable slave byte control */
- FMPI2Cx->CR1 |= FMPI2C_CR1_SBC;
- }
- else
- {
- /* Disable slave byte control */
- FMPI2Cx->CR1 &= (uint32_t)~((uint32_t)FMPI2C_CR1_SBC);
- }
-}
-
-/**
- * @brief Configures the slave address to be transmitted after start generation.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param Address: specifies the slave address to be programmed.
- * @note This function should be called before generating start condition.
- * @retval None
- */
-void FMPI2C_SlaveAddressConfig(FMPI2C_TypeDef* FMPI2Cx, uint16_t Address)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FMPI2C_SLAVE_ADDRESS(Address));
-
- /* Get the old register value */
- tmpreg = FMPI2Cx->CR2;
-
- /* Reset FMPI2Cx SADD bit [9:0] */
- tmpreg &= (uint32_t)~((uint32_t)FMPI2C_CR2_SADD);
-
- /* Set FMPI2Cx SADD */
- tmpreg |= (uint32_t)((uint32_t)Address & FMPI2C_CR2_SADD);
-
- /* Store the new register value */
- FMPI2Cx->CR2 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the FMPI2C 10-bit addressing mode for the master.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param NewState: new state of the FMPI2C 10-bit addressing mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note This function should be called before generating start condition.
- * @retval None
- */
-void FMPI2C_10BitAddressingModeCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable 10-bit addressing mode */
- FMPI2Cx->CR2 |= FMPI2C_CR2_ADD10;
- }
- else
- {
- /* Disable 10-bit addressing mode */
- FMPI2Cx->CR2 &= (uint32_t)~((uint32_t)FMPI2C_CR2_ADD10);
- }
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup FMPI2C_Group2 Communications handling functions
- * @brief Communications handling functions
- *
-@verbatim
- ===============================================================================
- ##### Communications handling functions #####
- ===============================================================================
- [..] This section provides a set of functions that handles FMPI2C communication.
-
- [..] Automatic End mode is enabled using FMPI2C_AutoEndCmd() function. When Reload
- mode is enabled via FMPI2C_ReloadCmd() AutoEnd bit has no effect.
-
- [..] FMPI2C_NumberOfBytesConfig() function set the number of bytes to be transferred,
- this configuration should be done before generating start condition in master
- mode.
-
- [..] When switching from master write operation to read operation in 10Bit addressing
- mode, master can only sends the 1st 7 bits of the 10 bit address, followed by
- Read direction by enabling HEADR bit using FMPI2C_10BitAddressHeader() function.
-
- [..] In master mode, when transferring more than 255 bytes Reload mode should be used
- to handle communication. In the first phase of transfer, Nbytes should be set to
- 255. After transferring these bytes TCR flag is set and FMPI2C_TransferHandling()
- function should be called to handle remaining communication.
-
- [..] In master mode, when software end mode is selected when all data is transferred
- TC flag is set FMPI2C_TransferHandling() function should be called to generate STOP
- or generate ReStart.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the FMPI2C automatic end mode (stop condition is
- * automatically sent when nbytes data are transferred).
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param NewState: new state of the FMPI2C automatic end mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note This function has effect if Reload mode is disabled.
- * @retval None
- */
-void FMPI2C_AutoEndCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Auto end mode */
- FMPI2Cx->CR2 |= FMPI2C_CR2_AUTOEND;
- }
- else
- {
- /* Disable Auto end mode */
- FMPI2Cx->CR2 &= (uint32_t)~((uint32_t)FMPI2C_CR2_AUTOEND);
- }
-}
-
-/**
- * @brief Enables or disables the FMPI2C nbytes reload mode.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param NewState: new state of the nbytes reload mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMPI2C_ReloadCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Auto Reload mode */
- FMPI2Cx->CR2 |= FMPI2C_CR2_RELOAD;
- }
- else
- {
- /* Disable Auto Reload mode */
- FMPI2Cx->CR2 &= (uint32_t)~((uint32_t)FMPI2C_CR2_RELOAD);
- }
-}
-
-/**
- * @brief Configures the number of bytes to be transmitted/received.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param Number_Bytes: specifies the number of bytes to be programmed.
- * @retval None
- */
-void FMPI2C_NumberOfBytesConfig(FMPI2C_TypeDef* FMPI2Cx, uint8_t Number_Bytes)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
-
- /* Get the old register value */
- tmpreg = FMPI2Cx->CR2;
-
- /* Reset FMPI2Cx Nbytes bit [7:0] */
- tmpreg &= (uint32_t)~((uint32_t)FMPI2C_CR2_NBYTES);
-
- /* Set FMPI2Cx Nbytes */
- tmpreg |= (uint32_t)(((uint32_t)Number_Bytes << 16 ) & FMPI2C_CR2_NBYTES);
-
- /* Store the new register value */
- FMPI2Cx->CR2 = tmpreg;
-}
-
-/**
- * @brief Configures the type of transfer request for the master.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param FMPI2C_Direction: specifies the transfer request direction to be programmed.
- * This parameter can be one of the following values:
- * @arg FMPI2C_Direction_Transmitter: Master request a write transfer
- * @arg FMPI2C_Direction_Receiver: Master request a read transfer
- * @retval None
- */
-void FMPI2C_MasterRequestConfig(FMPI2C_TypeDef* FMPI2Cx, uint16_t FMPI2C_Direction)
-{
-/* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FMPI2C_DIRECTION(FMPI2C_Direction));
-
- /* Test on the direction to set/reset the read/write bit */
- if (FMPI2C_Direction == FMPI2C_Direction_Transmitter)
- {
- /* Request a write Transfer */
- FMPI2Cx->CR2 &= (uint32_t)~((uint32_t)FMPI2C_CR2_RD_WRN);
- }
- else
- {
- /* Request a read Transfer */
- FMPI2Cx->CR2 |= FMPI2C_CR2_RD_WRN;
- }
-}
-
-/**
- * @brief Generates FMPI2Cx communication START condition.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param NewState: new state of the FMPI2C START condition generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMPI2C_GenerateSTART(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Generate a START condition */
- FMPI2Cx->CR2 |= FMPI2C_CR2_START;
- }
- else
- {
- /* Disable the START condition generation */
- FMPI2Cx->CR2 &= (uint32_t)~((uint32_t)FMPI2C_CR2_START);
- }
-}
-
-/**
- * @brief Generates FMPI2Cx communication STOP condition.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param NewState: new state of the FMPI2C STOP condition generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMPI2C_GenerateSTOP(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Generate a STOP condition */
- FMPI2Cx->CR2 |= FMPI2C_CR2_STOP;
- }
- else
- {
- /* Disable the STOP condition generation */
- FMPI2Cx->CR2 &= (uint32_t)~((uint32_t)FMPI2C_CR2_STOP);
- }
-}
-
-/**
- * @brief Enables or disables the FMPI2C 10-bit header only mode with read direction.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param NewState: new state of the FMPI2C 10-bit header only mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note This mode can be used only when switching from master transmitter mode
- * to master receiver mode.
- * @retval None
- */
-void FMPI2C_10BitAddressHeaderCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable 10-bit header only mode */
- FMPI2Cx->CR2 |= FMPI2C_CR2_HEAD10R;
- }
- else
- {
- /* Disable 10-bit header only mode */
- FMPI2Cx->CR2 &= (uint32_t)~((uint32_t)FMPI2C_CR2_HEAD10R);
- }
-}
-
-/**
- * @brief Generates FMPI2C communication Acknowledge.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param NewState: new state of the Acknowledge.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMPI2C_AcknowledgeConfig(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable ACK generation */
- FMPI2Cx->CR2 &= (uint32_t)~((uint32_t)FMPI2C_CR2_NACK);
- }
- else
- {
- /* Enable NACK generation */
- FMPI2Cx->CR2 |= FMPI2C_CR2_NACK;
- }
-}
-
-/**
- * @brief Returns the FMPI2C slave matched address .
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @retval The value of the slave matched address .
- */
-uint8_t FMPI2C_GetAddressMatched(FMPI2C_TypeDef* FMPI2Cx)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
-
- /* Return the slave matched address in the SR1 register */
- return (uint8_t)(((uint32_t)FMPI2Cx->ISR & FMPI2C_ISR_ADDCODE) >> 16) ;
-}
-
-/**
- * @brief Returns the FMPI2C slave received request.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @retval The value of the received request.
- */
-uint16_t FMPI2C_GetTransferDirection(FMPI2C_TypeDef* FMPI2Cx)
-{
- uint32_t tmpreg = 0;
- uint16_t direction = 0;
-
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
-
- /* Return the slave matched address in the SR1 register */
- tmpreg = (uint32_t)(FMPI2Cx->ISR & FMPI2C_ISR_DIR);
-
- /* If write transfer is requested */
- if (tmpreg == 0)
- {
- /* write transfer is requested */
- direction = FMPI2C_Direction_Transmitter;
- }
- else
- {
- /* Read transfer is requested */
- direction = FMPI2C_Direction_Receiver;
- }
- return direction;
-}
-
-/**
- * @brief Handles FMPI2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param Address: specifies the slave address to be programmed.
- * @param Number_Bytes: specifies the number of bytes to be programmed.
- * This parameter must be a value between 0 and 255.
- * @param ReloadEndMode: new state of the FMPI2C START condition generation.
- * This parameter can be one of the following values:
- * @arg FMPI2C_Reload_Mode: Enable Reload mode .
- * @arg FMPI2C_AutoEnd_Mode: Enable Automatic end mode.
- * @arg FMPI2C_SoftEnd_Mode: Enable Software end mode.
- * @param StartStopMode: new state of the FMPI2C START condition generation.
- * This parameter can be one of the following values:
- * @arg FMPI2C_No_StartStop: Don't Generate stop and start condition.
- * @arg FMPI2C_Generate_Stop: Generate stop condition (Number_Bytes should be set to 0).
- * @arg FMPI2C_Generate_Start_Read: Generate Restart for read request.
- * @arg FMPI2C_Generate_Start_Write: Generate Restart for write request.
- * @retval None
- */
-void FMPI2C_TransferHandling(FMPI2C_TypeDef* FMPI2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FMPI2C_SLAVE_ADDRESS(Address));
- assert_param(IS_RELOAD_END_MODE(ReloadEndMode));
- assert_param(IS_START_STOP_MODE(StartStopMode));
-
- /* Get the CR2 register value */
- tmpreg = FMPI2Cx->CR2;
-
- /* clear tmpreg specific bits */
- tmpreg &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_RD_WRN | FMPI2C_CR2_START | FMPI2C_CR2_STOP));
-
- /* update tmpreg */
- tmpreg |= (uint32_t)(((uint32_t)Address & FMPI2C_CR2_SADD) | (((uint32_t)Number_Bytes << 16 ) & FMPI2C_CR2_NBYTES) | \
- (uint32_t)ReloadEndMode | (uint32_t)StartStopMode);
-
- /* update CR2 register */
- FMPI2Cx->CR2 = tmpreg;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup FMPI2C_Group3 SMBUS management functions
- * @brief SMBUS management functions
- *
-@verbatim
- ===============================================================================
- ##### SMBUS management functions #####
- ===============================================================================
- [..] This section provides a set of functions that handles SMBus communication
- and timeouts detection.
-
- [..] The SMBus Device default address (0b1100 001) is enabled by calling FMPI2C_Init()
- function and setting FMPI2C_Mode member of FMPI2C_InitTypeDef() structure to
- FMPI2C_Mode_SMBusDevice.
-
- [..] The SMBus Host address (0b0001 000) is enabled by calling FMPI2C_Init()
- function and setting FMPI2C_Mode member of FMPI2C_InitTypeDef() structure to
- FMPI2C_Mode_SMBusHost.
-
- [..] The Alert Response Address (0b0001 100) is enabled using FMPI2C_SMBusAlertCmd()
- function.
-
- [..] To detect cumulative SCL stretch in master and slave mode, TIMEOUTB should be
- configured (in accordance to SMBus specification) using FMPI2C_TimeoutBConfig()
- function then FMPI2C_ExtendedClockTimeoutCmd() function should be called to enable
- the detection.
-
- [..] SCL low timeout is detected by configuring TIMEOUTB using FMPI2C_TimeoutBConfig()
- function followed by the call of FMPI2C_ClockTimeoutCmd(). When adding to this
- procedure the call of FMPI2C_IdleClockTimeoutCmd() function, Bus Idle condition
- (both SCL and SDA high) is detected also.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables FMPI2C SMBus alert.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param NewState: new state of the FMPI2Cx SMBus alert.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMPI2C_SMBusAlertCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable SMBus alert */
- FMPI2Cx->CR1 |= FMPI2C_CR1_ALERTEN;
- }
- else
- {
- /* Disable SMBus alert */
- FMPI2Cx->CR1 &= (uint32_t)~((uint32_t)FMPI2C_CR1_ALERTEN);
- }
-}
-
-/**
- * @brief Enables or disables FMPI2C Clock Timeout (SCL Timeout detection).
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param NewState: new state of the FMPI2Cx clock Timeout.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMPI2C_ClockTimeoutCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Clock Timeout */
- FMPI2Cx->TIMEOUTR |= FMPI2C_TIMEOUTR_TIMOUTEN;
- }
- else
- {
- /* Disable Clock Timeout */
- FMPI2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)FMPI2C_TIMEOUTR_TIMOUTEN);
- }
-}
-
-/**
- * @brief Enables or disables FMPI2C Extended Clock Timeout (SCL cumulative Timeout detection).
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param NewState: new state of the FMPI2Cx Extended clock Timeout.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMPI2C_ExtendedClockTimeoutCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Clock Timeout */
- FMPI2Cx->TIMEOUTR |= FMPI2C_TIMEOUTR_TEXTEN;
- }
- else
- {
- /* Disable Clock Timeout */
- FMPI2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)FMPI2C_TIMEOUTR_TEXTEN);
- }
-}
-
-/**
- * @brief Enables or disables FMPI2C Idle Clock Timeout (Bus idle SCL and SDA
- * high detection).
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param NewState: new state of the FMPI2Cx Idle clock Timeout.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMPI2C_IdleClockTimeoutCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Clock Timeout */
- FMPI2Cx->TIMEOUTR |= FMPI2C_TIMEOUTR_TIDLE;
- }
- else
- {
- /* Disable Clock Timeout */
- FMPI2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)FMPI2C_TIMEOUTR_TIDLE);
- }
-}
-
-/**
- * @brief Configures the FMPI2C Bus Timeout A (SCL Timeout when TIDLE = 0 or Bus
- * idle SCL and SDA high when TIDLE = 1).
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param Timeout: specifies the TimeoutA to be programmed.
- * @retval None
- */
-void FMPI2C_TimeoutAConfig(FMPI2C_TypeDef* FMPI2Cx, uint16_t Timeout)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FMPI2C_TIMEOUT(Timeout));
-
- /* Get the old register value */
- tmpreg = FMPI2Cx->TIMEOUTR;
-
- /* Reset FMPI2Cx TIMEOUTA bit [11:0] */
- tmpreg &= (uint32_t)~((uint32_t)FMPI2C_TIMEOUTR_TIMEOUTA);
-
- /* Set FMPI2Cx TIMEOUTA */
- tmpreg |= (uint32_t)((uint32_t)Timeout & FMPI2C_TIMEOUTR_TIMEOUTA) ;
-
- /* Store the new register value */
- FMPI2Cx->TIMEOUTR = tmpreg;
-}
-
-/**
- * @brief Configures the FMPI2C Bus Timeout B (SCL cumulative Timeout).
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param Timeout: specifies the TimeoutB to be programmed.
- * @retval None
- */
-void FMPI2C_TimeoutBConfig(FMPI2C_TypeDef* FMPI2Cx, uint16_t Timeout)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FMPI2C_TIMEOUT(Timeout));
-
- /* Get the old register value */
- tmpreg = FMPI2Cx->TIMEOUTR;
-
- /* Reset FMPI2Cx TIMEOUTB bit [11:0] */
- tmpreg &= (uint32_t)~((uint32_t)FMPI2C_TIMEOUTR_TIMEOUTB);
-
- /* Set FMPI2Cx TIMEOUTB */
- tmpreg |= (uint32_t)(((uint32_t)Timeout << 16) & FMPI2C_TIMEOUTR_TIMEOUTB) ;
-
- /* Store the new register value */
- FMPI2Cx->TIMEOUTR = tmpreg;
-}
-
-/**
- * @brief Enables or disables FMPI2C PEC calculation.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param NewState: new state of the FMPI2Cx PEC calculation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMPI2C_CalculatePEC(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable PEC calculation */
- FMPI2Cx->CR1 |= FMPI2C_CR1_PECEN;
- }
- else
- {
- /* Disable PEC calculation */
- FMPI2Cx->CR1 &= (uint32_t)~((uint32_t)FMPI2C_CR1_PECEN);
- }
-}
-
-/**
- * @brief Enables or disables FMPI2C PEC transmission/reception request.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param NewState: new state of the FMPI2Cx PEC request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMPI2C_PECRequestCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable PEC transmission/reception request */
- FMPI2Cx->CR1 |= FMPI2C_CR2_PECBYTE;
- }
- else
- {
- /* Disable PEC transmission/reception request */
- FMPI2Cx->CR1 &= (uint32_t)~((uint32_t)FMPI2C_CR2_PECBYTE);
- }
-}
-
-/**
- * @brief Returns the FMPI2C PEC.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @retval The value of the PEC .
- */
-uint8_t FMPI2C_GetPEC(FMPI2C_TypeDef* FMPI2Cx)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
-
- /* Return the slave matched address in the SR1 register */
- return (uint8_t)((uint32_t)FMPI2Cx->PECR & FMPI2C_PECR_PEC);
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup FMPI2C_Group4 FMPI2C registers management functions
- * @brief FMPI2C registers management functions
- *
-@verbatim
- ===============================================================================
- ##### FMPI2C registers management functions #####
- ===============================================================================
- [..] This section provides a functions that allow user the management of
- FMPI2C registers.
-
-@endverbatim
- * @{
- */
-
- /**
- * @brief Reads the specified FMPI2C register and returns its value.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param FMPI2C_Register: specifies the register to read.
- * This parameter can be one of the following values:
- * @arg FMPI2C_Register_CR1: CR1 register.
- * @arg FMPI2C_Register_CR2: CR2 register.
- * @arg FMPI2C_Register_OAR1: OAR1 register.
- * @arg FMPI2C_Register_OAR2: OAR2 register.
- * @arg FMPI2C_Register_TIMINGR: TIMING register.
- * @arg FMPI2C_Register_TIMEOUTR: TIMEOUTR register.
- * @arg FMPI2C_Register_ISR: ISR register.
- * @arg FMPI2C_Register_ICR: ICR register.
- * @arg FMPI2C_Register_PECR: PECR register.
- * @arg FMPI2C_Register_RXDR: RXDR register.
- * @arg FMPI2C_Register_TXDR: TXDR register.
- * @retval The value of the read register.
- */
-uint32_t FMPI2C_ReadRegister(FMPI2C_TypeDef* FMPI2Cx, uint8_t FMPI2C_Register)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FMPI2C_REGISTER(FMPI2C_Register));
-
- tmp = (uint32_t)FMPI2Cx;
- tmp += FMPI2C_Register;
-
- /* Return the selected register value */
- return (*(__IO uint32_t *) tmp);
-}
-
-/**
- * @}
- */
-
-/** @defgroup FMPI2C_Group5 Data transfers management functions
- * @brief Data transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers management functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage
- the FMPI2C data transfers.
-
- [..] The read access of the FMPI2C_RXDR register can be done using
- the FMPI2C_ReceiveData() function and returns the received value.
- Whereas a write access to the FMPI2C_TXDR can be done using FMPI2C_SendData()
- function and stores the written data into TXDR.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sends a data byte through the FMPI2Cx peripheral.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param Data: Byte to be transmitted..
- * @retval None
- */
-void FMPI2C_SendData(FMPI2C_TypeDef* FMPI2Cx, uint8_t Data)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
-
- /* Write in the DR register the data to be sent */
- FMPI2Cx->TXDR = (uint8_t)Data;
-}
-
-/**
- * @brief Returns the most recent received data by the FMPI2Cx peripheral.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @retval The value of the received data.
- */
-uint8_t FMPI2C_ReceiveData(FMPI2C_TypeDef* FMPI2Cx)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
-
- /* Return the data in the DR register */
- return (uint8_t)FMPI2Cx->RXDR;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup FMPI2C_Group6 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
- [..] This section provides two functions that can be used only in DMA mode.
- [..] In DMA Mode, the FMPI2C communication can be managed by 2 DMA Channel
- requests:
- (#) FMPI2C_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
- (#) FMPI2C_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
- [..] In this Mode it is advised to use the following function:
- (+) FMPI2C_DMACmd(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_DMAReq, FunctionalState NewState);
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the FMPI2C DMA interface.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param FMPI2C_DMAReq: specifies the FMPI2C DMA transfer request to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg FMPI2C_DMAReq_Tx: Tx DMA transfer request
- * @arg FMPI2C_DMAReq_Rx: Rx DMA transfer request
- * @param NewState: new state of the selected FMPI2C DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMPI2C_DMACmd(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_FMPI2C_DMA_REQ(FMPI2C_DMAReq));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected FMPI2C DMA requests */
- FMPI2Cx->CR1 |= FMPI2C_DMAReq;
- }
- else
- {
- /* Disable the selected FMPI2C DMA requests */
- FMPI2Cx->CR1 &= (uint32_t)~FMPI2C_DMAReq;
- }
-}
-/**
- * @}
- */
-
-
-/** @defgroup FMPI2C_Group7 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the FMPI2C Interrupts
- sources and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to manage
- the communication: Polling mode, Interrupt mode or DMA mode(refer FMPI2C_Group6) .
-
- *** Polling Mode ***
- ====================
- [..] In Polling Mode, the FMPI2C communication can be managed by 15 flags:
- (#) FMPI2C_FLAG_TXE: to indicate the status of Transmit data register empty flag.
- (#) FMPI2C_FLAG_TXIS: to indicate the status of Transmit interrupt status flag .
- (#) FMPI2C_FLAG_RXNE: to indicate the status of Receive data register not empty flag.
- (#) FMPI2C_FLAG_ADDR: to indicate the status of Address matched flag (slave mode).
- (#) FMPI2C_FLAG_NACKF: to indicate the status of NACK received flag.
- (#) FMPI2C_FLAG_STOPF: to indicate the status of STOP detection flag.
- (#) FMPI2C_FLAG_TC: to indicate the status of Transfer complete flag(master mode).
- (#) FMPI2C_FLAG_TCR: to indicate the status of Transfer complete reload flag.
- (#) FMPI2C_FLAG_BERR: to indicate the status of Bus error flag.
- (#) FMPI2C_FLAG_ARLO: to indicate the status of Arbitration lost flag.
- (#) FMPI2C_FLAG_OVR: to indicate the status of Overrun/Underrun flag.
- (#) FMPI2C_FLAG_PECERR: to indicate the status of PEC error in reception flag.
- (#) FMPI2C_FLAG_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.
- (#) FMPI2C_FLAG_ALERT: to indicate the status of SMBus Alert flag.
- (#) FMPI2C_FLAG_BUSY: to indicate the status of Bus busy flag.
-
- [..] In this Mode it is advised to use the following functions:
- (+) FlagStatus FMPI2C_GetFlagStatus(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_FLAG);
- (+) void FMPI2C_ClearFlag(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_FLAG);
-
- [..]
- (@)Do not use the BUSY flag to handle each data transmission or reception.It is
- better to use the TXIS and RXNE flags instead.
-
- *** Interrupt Mode ***
- ======================
- [..] In Interrupt Mode, the FMPI2C communication can be managed by 7 interrupt sources
- and 15 pending bits:
- [..] Interrupt Source:
- (#) FMPI2C_IT_ERRI: specifies the interrupt source for the Error interrupt.
- (#) FMPI2C_IT_TCI: specifies the interrupt source for the Transfer Complete interrupt.
- (#) FMPI2C_IT_STOPI: specifies the interrupt source for the Stop Detection interrupt.
- (#) FMPI2C_IT_NACKI: specifies the interrupt source for the Not Acknowledge received interrupt.
- (#) FMPI2C_IT_ADDRI: specifies the interrupt source for the Address Match interrupt.
- (#) FMPI2C_IT_RXI: specifies the interrupt source for the RX interrupt.
- (#) FMPI2C_IT_TXI: specifies the interrupt source for the TX interrupt.
-
- [..] Pending Bits:
- (#) FMPI2C_IT_TXIS: to indicate the status of Transmit interrupt status flag.
- (#) FMPI2C_IT_RXNE: to indicate the status of Receive data register not empty flag.
- (#) FMPI2C_IT_ADDR: to indicate the status of Address matched flag (slave mode).
- (#) FMPI2C_IT_NACKF: to indicate the status of NACK received flag.
- (#) FMPI2C_IT_STOPF: to indicate the status of STOP detection flag.
- (#) FMPI2C_IT_TC: to indicate the status of Transfer complete flag (master mode).
- (#) FMPI2C_IT_TCR: to indicate the status of Transfer complete reload flag.
- (#) FMPI2C_IT_BERR: to indicate the status of Bus error flag.
- (#) FMPI2C_IT_ARLO: to indicate the status of Arbitration lost flag.
- (#) FMPI2C_IT_OVR: to indicate the status of Overrun/Underrun flag.
- (#) FMPI2C_IT_PECERR: to indicate the status of PEC error in reception flag.
- (#) FMPI2C_IT_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.
- (#) FMPI2C_IT_ALERT: to indicate the status of SMBus Alert flag.
-
- [..] In this Mode it is advised to use the following functions:
- (+) void FMPI2C_ClearITPendingBit(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_IT);
- (+) ITStatus FMPI2C_GetITStatus(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_IT);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the specified FMPI2C flag is set or not.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param FMPI2C_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg FMPI2C_FLAG_TXE: Transmit data register empty
- * @arg FMPI2C_FLAG_TXIS: Transmit interrupt status
- * @arg FMPI2C_FLAG_RXNE: Receive data register not empty
- * @arg FMPI2C_FLAG_ADDR: Address matched (slave mode)
- * @arg FMPI2C_FLAG_NACKF: NACK received flag
- * @arg FMPI2C_FLAG_STOPF: STOP detection flag
- * @arg FMPI2C_FLAG_TC: Transfer complete (master mode)
- * @arg FMPI2C_FLAG_TCR: Transfer complete reload
- * @arg FMPI2C_FLAG_BERR: Bus error
- * @arg FMPI2C_FLAG_ARLO: Arbitration lost
- * @arg FMPI2C_FLAG_OVR: Overrun/Underrun
- * @arg FMPI2C_FLAG_PECERR: PEC error in reception
- * @arg FMPI2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
- * @arg FMPI2C_FLAG_ALERT: SMBus Alert
- * @arg FMPI2C_FLAG_BUSY: Bus busy
- * @retval The new state of FMPI2C_FLAG (SET or RESET).
- */
-FlagStatus FMPI2C_GetFlagStatus(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_FLAG)
-{
- uint32_t tmpreg = 0;
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FMPI2C_GET_FLAG(FMPI2C_FLAG));
-
- /* Get the ISR register value */
- tmpreg = FMPI2Cx->ISR;
-
- /* Get flag status */
- tmpreg &= FMPI2C_FLAG;
-
- if(tmpreg != 0)
- {
- /* FMPI2C_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* FMPI2C_FLAG is reset */
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the FMPI2Cx's pending flags.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param FMPI2C_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg FMPI2C_FLAG_ADDR: Address matched (slave mode)
- * @arg FMPI2C_FLAG_NACKF: NACK received flag
- * @arg FMPI2C_FLAG_STOPF: STOP detection flag
- * @arg FMPI2C_FLAG_BERR: Bus error
- * @arg FMPI2C_FLAG_ARLO: Arbitration lost
- * @arg FMPI2C_FLAG_OVR: Overrun/Underrun
- * @arg FMPI2C_FLAG_PECERR: PEC error in reception
- * @arg FMPI2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
- * @arg FMPI2C_FLAG_ALERT: SMBus Alert
- * @retval The new state of FMPI2C_FLAG (SET or RESET).
- */
-void FMPI2C_ClearFlag(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FMPI2C_CLEAR_FLAG(FMPI2C_FLAG));
-
- /* Clear the selected flag */
- FMPI2Cx->ICR = FMPI2C_FLAG;
- }
-
-/**
- * @brief Checks whether the specified FMPI2C interrupt has occurred or not.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param FMPI2C_IT: specifies the interrupt source to check.
- * This parameter can be one of the following values:
- * @arg FMPI2C_IT_TXIS: Transmit interrupt status
- * @arg FMPI2C_IT_RXNE: Receive data register not empty
- * @arg FMPI2C_IT_ADDR: Address matched (slave mode)
- * @arg FMPI2C_IT_NACKF: NACK received flag
- * @arg FMPI2C_IT_STOPF: STOP detection flag
- * @arg FMPI2C_IT_TC: Transfer complete (master mode)
- * @arg FMPI2C_IT_TCR: Transfer complete reload
- * @arg FMPI2C_IT_BERR: Bus error
- * @arg FMPI2C_IT_ARLO: Arbitration lost
- * @arg FMPI2C_IT_OVR: Overrun/Underrun
- * @arg FMPI2C_IT_PECERR: PEC error in reception
- * @arg FMPI2C_IT_TIMEOUT: Timeout or Tlow detection flag
- * @arg FMPI2C_IT_ALERT: SMBus Alert
- * @retval The new state of FMPI2C_IT (SET or RESET).
- */
-ITStatus FMPI2C_GetITStatus(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_IT)
-{
- uint32_t tmpreg = 0;
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FMPI2C_GET_IT(FMPI2C_IT));
-
- /* Check if the interrupt source is enabled or not */
- /* If Error interrupt */
- if((uint32_t)(FMPI2C_IT & ERROR_IT_MASK))
- {
- enablestatus = (uint32_t)((FMPI2C_CR1_ERRIE) & (FMPI2Cx->CR1));
- }
- /* If TC interrupt */
- else if((uint32_t)(FMPI2C_IT & TC_IT_MASK))
- {
- enablestatus = (uint32_t)((FMPI2C_CR1_TCIE) & (FMPI2Cx->CR1));
- }
- else
- {
- enablestatus = (uint32_t)((FMPI2C_IT) & (FMPI2Cx->CR1));
- }
-
- /* Get the ISR register value */
- tmpreg = FMPI2Cx->ISR;
-
- /* Get flag status */
- tmpreg &= FMPI2C_IT;
-
- /* Check the status of the specified FMPI2C flag */
- if((tmpreg != RESET) && enablestatus)
- {
- /* FMPI2C_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* FMPI2C_IT is reset */
- bitstatus = RESET;
- }
-
- /* Return the FMPI2C_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the FMPI2Cx's interrupt pending bits.
- * @param FMPI2Cx: where x can be 1 to select the FMPI2C peripheral.
- * @param FMPI2C_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg FMPI2C_IT_ADDR: Address matched (slave mode)
- * @arg FMPI2C_IT_NACKF: NACK received flag
- * @arg FMPI2C_IT_STOPF: STOP detection flag
- * @arg FMPI2C_IT_BERR: Bus error
- * @arg FMPI2C_IT_ARLO: Arbitration lost
- * @arg FMPI2C_IT_OVR: Overrun/Underrun
- * @arg FMPI2C_IT_PECERR: PEC error in reception
- * @arg FMPI2C_IT_TIMEOUT: Timeout or Tlow detection flag
- * @arg FMPI2C_IT_ALERT: SMBus Alert
- * @retval The new state of FMPI2C_IT (SET or RESET).
- */
-void FMPI2C_ClearITPendingBit(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_IT)
-{
- /* Check the parameters */
- assert_param(IS_FMPI2C_ALL_PERIPH(FMPI2Cx));
- assert_param(IS_FMPI2C_CLEAR_IT(FMPI2C_IT));
-
- /* Clear the selected flag */
- FMPI2Cx->ICR = FMPI2C_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_fmpi2c.h b/底盘/底盘-old/底盘/Library/stm32f4xx_fmpi2c.h
deleted file mode 100644
index 341da24..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_fmpi2c.h
+++ /dev/null
@@ -1,466 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_fmpi2c.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the I2C Fast Mode
- * Plus firmware library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_FMPI2C_H
-#define __STM32F4xx_FMPI2C_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup FMPI2C
- * @{
- */
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief FMPI2C Init structure definition
- */
-
-typedef struct
-{
- uint32_t FMPI2C_Timing; /*!< Specifies the FMPI2C_TIMINGR_register value.
- This parameter calculated by referring to FMPI2C initialization
- section in Reference manual*/
-
- uint32_t FMPI2C_AnalogFilter; /*!< Enables or disables analog noise filter.
- This parameter can be a value of @ref FMPI2C_Analog_Filter */
-
- uint32_t FMPI2C_DigitalFilter; /*!< Configures the digital noise filter.
- This parameter can be a number between 0x00 and 0x0F */
-
- uint32_t FMPI2C_Mode; /*!< Specifies the FMPI2C mode.
- This parameter can be a value of @ref FMPI2C_mode */
-
- uint32_t FMPI2C_OwnAddress1; /*!< Specifies the device own address 1.
- This parameter can be a 7-bit or 10-bit address */
-
- uint32_t FMPI2C_Ack; /*!< Enables or disables the acknowledgement.
- This parameter can be a value of @ref FMPI2C_acknowledgement */
-
- uint32_t FMPI2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
- This parameter can be a value of @ref FMPI2C_acknowledged_address */
-}FMPI2C_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-
-/** @defgroup FMPI2C_Exported_Constants
- * @{
- */
-
-#define IS_FMPI2C_ALL_PERIPH(PERIPH) ((PERIPH) == FMPI2C1)
-
-/** @defgroup FMPI2C_Analog_Filter
- * @{
- */
-
-#define FMPI2C_AnalogFilter_Enable ((uint32_t)0x00000000)
-#define FMPI2C_AnalogFilter_Disable FMPI2C_CR1_ANFOFF
-
-#define IS_FMPI2C_ANALOG_FILTER(FILTER) (((FILTER) == FMPI2C_AnalogFilter_Enable) || \
- ((FILTER) == FMPI2C_AnalogFilter_Disable))
-/**
- * @}
- */
-
-/** @defgroup FMPI2C_Digital_Filter
- * @{
- */
-
-#define IS_FMPI2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
-/**
- * @}
- */
-
-/** @defgroup FMPI2C_mode
- * @{
- */
-
-#define FMPI2C_Mode_FMPI2C ((uint32_t)0x00000000)
-#define FMPI2C_Mode_SMBusDevice FMPI2C_CR1_SMBDEN
-#define FMPI2C_Mode_SMBusHost FMPI2C_CR1_SMBHEN
-
-#define IS_FMPI2C_MODE(MODE) (((MODE) == FMPI2C_Mode_FMPI2C) || \
- ((MODE) == FMPI2C_Mode_SMBusDevice) || \
- ((MODE) == FMPI2C_Mode_SMBusHost))
-/**
- * @}
- */
-
-/** @defgroup FMPI2C_acknowledgement
- * @{
- */
-
-#define FMPI2C_Ack_Enable ((uint32_t)0x00000000)
-#define FMPI2C_Ack_Disable FMPI2C_CR2_NACK
-
-#define IS_FMPI2C_ACK(ACK) (((ACK) == FMPI2C_Ack_Enable) || \
- ((ACK) == FMPI2C_Ack_Disable))
-/**
- * @}
- */
-
-/** @defgroup FMPI2C_acknowledged_address
- * @{
- */
-
-#define FMPI2C_AcknowledgedAddress_7bit ((uint32_t)0x00000000)
-#define FMPI2C_AcknowledgedAddress_10bit FMPI2C_OAR1_OA1MODE
-
-#define IS_FMPI2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == FMPI2C_AcknowledgedAddress_7bit) || \
- ((ADDRESS) == FMPI2C_AcknowledgedAddress_10bit))
-/**
- * @}
- */
-
-/** @defgroup FMPI2C_own_address1
- * @{
- */
-
-#define IS_FMPI2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
-/**
- * @}
- */
-
-/** @defgroup FMPI2C_transfer_direction
- * @{
- */
-
-#define FMPI2C_Direction_Transmitter ((uint16_t)0x0000)
-#define FMPI2C_Direction_Receiver ((uint16_t)0x0400)
-
-#define IS_FMPI2C_DIRECTION(DIRECTION) (((DIRECTION) == FMPI2C_Direction_Transmitter) || \
- ((DIRECTION) == FMPI2C_Direction_Receiver))
-/**
- * @}
- */
-
-/** @defgroup FMPI2C_DMA_transfer_requests
- * @{
- */
-
-#define FMPI2C_DMAReq_Tx FMPI2C_CR1_TXDMAEN
-#define FMPI2C_DMAReq_Rx FMPI2C_CR1_RXDMAEN
-
-#define IS_FMPI2C_DMA_REQ(REQ) ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup FMPI2C_slave_address
- * @{
- */
-
-#define IS_FMPI2C_SLAVE_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF)
-/**
- * @}
- */
-
-
-/** @defgroup FMPI2C_own_address2
- * @{
- */
-
-#define IS_FMPI2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
-
-/**
- * @}
- */
-
-/** @defgroup FMPI2C_own_address2_mask
- * @{
- */
-
-#define FMPI2C_OA2_NoMask ((uint8_t)0x00)
-#define FMPI2C_OA2_Mask01 ((uint8_t)0x01)
-#define FMPI2C_OA2_Mask02 ((uint8_t)0x02)
-#define FMPI2C_OA2_Mask03 ((uint8_t)0x03)
-#define FMPI2C_OA2_Mask04 ((uint8_t)0x04)
-#define FMPI2C_OA2_Mask05 ((uint8_t)0x05)
-#define FMPI2C_OA2_Mask06 ((uint8_t)0x06)
-#define FMPI2C_OA2_Mask07 ((uint8_t)0x07)
-
-#define IS_FMPI2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPI2C_OA2_NoMask) || \
- ((MASK) == FMPI2C_OA2_Mask01) || \
- ((MASK) == FMPI2C_OA2_Mask02) || \
- ((MASK) == FMPI2C_OA2_Mask03) || \
- ((MASK) == FMPI2C_OA2_Mask04) || \
- ((MASK) == FMPI2C_OA2_Mask05) || \
- ((MASK) == FMPI2C_OA2_Mask06) || \
- ((MASK) == FMPI2C_OA2_Mask07))
-
-/**
- * @}
- */
-
-/** @defgroup FMPI2C_timeout
- * @{
- */
-
-#define IS_FMPI2C_TIMEOUT(TIMEOUT) ((TIMEOUT) <= (uint16_t)0x0FFF)
-
-/**
- * @}
- */
-
-/** @defgroup FMPI2C_registers
- * @{
- */
-
-#define FMPI2C_Register_CR1 ((uint8_t)0x00)
-#define FMPI2C_Register_CR2 ((uint8_t)0x04)
-#define FMPI2C_Register_OAR1 ((uint8_t)0x08)
-#define FMPI2C_Register_OAR2 ((uint8_t)0x0C)
-#define FMPI2C_Register_TIMINGR ((uint8_t)0x10)
-#define FMPI2C_Register_TIMEOUTR ((uint8_t)0x14)
-#define FMPI2C_Register_ISR ((uint8_t)0x18)
-#define FMPI2C_Register_ICR ((uint8_t)0x1C)
-#define FMPI2C_Register_PECR ((uint8_t)0x20)
-#define FMPI2C_Register_RXDR ((uint8_t)0x24)
-#define FMPI2C_Register_TXDR ((uint8_t)0x28)
-
-#define IS_FMPI2C_REGISTER(REGISTER) (((REGISTER) == FMPI2C_Register_CR1) || \
- ((REGISTER) == FMPI2C_Register_CR2) || \
- ((REGISTER) == FMPI2C_Register_OAR1) || \
- ((REGISTER) == FMPI2C_Register_OAR2) || \
- ((REGISTER) == FMPI2C_Register_TIMINGR) || \
- ((REGISTER) == FMPI2C_Register_TIMEOUTR) || \
- ((REGISTER) == FMPI2C_Register_ISR) || \
- ((REGISTER) == FMPI2C_Register_ICR) || \
- ((REGISTER) == FMPI2C_Register_PECR) || \
- ((REGISTER) == FMPI2C_Register_RXDR) || \
- ((REGISTER) == FMPI2C_Register_TXDR))
-/**
- * @}
- */
-
-/** @defgroup FMPI2C_interrupts_definition
- * @{
- */
-
-#define FMPI2C_IT_ERRI FMPI2C_CR1_ERRIE
-#define FMPI2C_IT_TCI FMPI2C_CR1_TCIE
-#define FMPI2C_IT_STOPI FMPI2C_CR1_STOPIE
-#define FMPI2C_IT_NACKI FMPI2C_CR1_NACKIE
-#define FMPI2C_IT_ADDRI FMPI2C_CR1_ADDRIE
-#define FMPI2C_IT_RXI FMPI2C_CR1_RXIE
-#define FMPI2C_IT_TXI FMPI2C_CR1_TXIE
-
-#define IS_FMPI2C_CONFIG_IT(IT) ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00))
-
-/**
- * @}
- */
-
-/** @defgroup FMPI2C_flags_definition
- * @{
- */
-
-#define FMPI2C_FLAG_TXE FMPI2C_ISR_TXE
-#define FMPI2C_FLAG_TXIS FMPI2C_ISR_TXIS
-#define FMPI2C_FLAG_RXNE FMPI2C_ISR_RXNE
-#define FMPI2C_FLAG_ADDR FMPI2C_ISR_ADDR
-#define FMPI2C_FLAG_NACKF FMPI2C_ISR_NACKF
-#define FMPI2C_FLAG_STOPF FMPI2C_ISR_STOPF
-#define FMPI2C_FLAG_TC FMPI2C_ISR_TC
-#define FMPI2C_FLAG_TCR FMPI2C_ISR_TCR
-#define FMPI2C_FLAG_BERR FMPI2C_ISR_BERR
-#define FMPI2C_FLAG_ARLO FMPI2C_ISR_ARLO
-#define FMPI2C_FLAG_OVR FMPI2C_ISR_OVR
-#define FMPI2C_FLAG_PECERR FMPI2C_ISR_PECERR
-#define FMPI2C_FLAG_TIMEOUT FMPI2C_ISR_TIMEOUT
-#define FMPI2C_FLAG_ALERT FMPI2C_ISR_ALERT
-#define FMPI2C_FLAG_BUSY FMPI2C_ISR_BUSY
-
-#define IS_FMPI2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00))
-
-#define IS_FMPI2C_GET_FLAG(FLAG) (((FLAG) == FMPI2C_FLAG_TXE) || ((FLAG) == FMPI2C_FLAG_TXIS) || \
- ((FLAG) == FMPI2C_FLAG_RXNE) || ((FLAG) == FMPI2C_FLAG_ADDR) || \
- ((FLAG) == FMPI2C_FLAG_NACKF) || ((FLAG) == FMPI2C_FLAG_STOPF) || \
- ((FLAG) == FMPI2C_FLAG_TC) || ((FLAG) == FMPI2C_FLAG_TCR) || \
- ((FLAG) == FMPI2C_FLAG_BERR) || ((FLAG) == FMPI2C_FLAG_ARLO) || \
- ((FLAG) == FMPI2C_FLAG_OVR) || ((FLAG) == FMPI2C_FLAG_PECERR) || \
- ((FLAG) == FMPI2C_FLAG_TIMEOUT) || ((FLAG) == FMPI2C_FLAG_ALERT) || \
- ((FLAG) == FMPI2C_FLAG_BUSY))
-
-/**
- * @}
- */
-
-
-/** @defgroup FMPI2C_interrupts_definition
- * @{
- */
-
-#define FMPI2C_IT_TXIS FMPI2C_ISR_TXIS
-#define FMPI2C_IT_RXNE FMPI2C_ISR_RXNE
-#define FMPI2C_IT_ADDR FMPI2C_ISR_ADDR
-#define FMPI2C_IT_NACKF FMPI2C_ISR_NACKF
-#define FMPI2C_IT_STOPF FMPI2C_ISR_STOPF
-#define FMPI2C_IT_TC FMPI2C_ISR_TC
-#define FMPI2C_IT_TCR FMPI2C_ISR_TCR
-#define FMPI2C_IT_BERR FMPI2C_ISR_BERR
-#define FMPI2C_IT_ARLO FMPI2C_ISR_ARLO
-#define FMPI2C_IT_OVR FMPI2C_ISR_OVR
-#define FMPI2C_IT_PECERR FMPI2C_ISR_PECERR
-#define FMPI2C_IT_TIMEOUT FMPI2C_ISR_TIMEOUT
-#define FMPI2C_IT_ALERT FMPI2C_ISR_ALERT
-
-#define IS_FMPI2C_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00))
-
-#define IS_FMPI2C_GET_IT(IT) (((IT) == FMPI2C_IT_TXIS) || ((IT) == FMPI2C_IT_RXNE) || \
- ((IT) == FMPI2C_IT_ADDR) || ((IT) == FMPI2C_IT_NACKF) || \
- ((IT) == FMPI2C_IT_STOPF) || ((IT) == FMPI2C_IT_TC) || \
- ((IT) == FMPI2C_IT_TCR) || ((IT) == FMPI2C_IT_BERR) || \
- ((IT) == FMPI2C_IT_ARLO) || ((IT) == FMPI2C_IT_OVR) || \
- ((IT) == FMPI2C_IT_PECERR) || ((IT) == FMPI2C_IT_TIMEOUT) || \
- ((IT) == FMPI2C_IT_ALERT))
-
-/**
- * @}
- */
-
-/** @defgroup FMPI2C_ReloadEndMode_definition
- * @{
- */
-
-#define FMPI2C_Reload_Mode FMPI2C_CR2_RELOAD
-#define FMPI2C_AutoEnd_Mode FMPI2C_CR2_AUTOEND
-#define FMPI2C_SoftEnd_Mode ((uint32_t)0x00000000)
-
-
-#define IS_RELOAD_END_MODE(MODE) (((MODE) == FMPI2C_Reload_Mode) || \
- ((MODE) == FMPI2C_AutoEnd_Mode) || \
- ((MODE) == FMPI2C_SoftEnd_Mode))
-
-
-/**
- * @}
- */
-
-/** @defgroup FMPI2C_StartStopMode_definition
- * @{
- */
-
-#define FMPI2C_No_StartStop ((uint32_t)0x00000000)
-#define FMPI2C_Generate_Stop FMPI2C_CR2_STOP
-#define FMPI2C_Generate_Start_Read (uint32_t)(FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN)
-#define FMPI2C_Generate_Start_Write FMPI2C_CR2_START
-
-
-#define IS_START_STOP_MODE(MODE) (((MODE) == FMPI2C_Generate_Stop) || \
- ((MODE) == FMPI2C_Generate_Start_Read) || \
- ((MODE) == FMPI2C_Generate_Start_Write) || \
- ((MODE) == FMPI2C_No_StartStop))
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-
-/* Initialization and Configuration functions *********************************/
-void FMPI2C_DeInit(FMPI2C_TypeDef* FMPI2Cx);
-void FMPI2C_Init(FMPI2C_TypeDef* FMPI2Cx, FMPI2C_InitTypeDef* FMPI2C_InitStruct);
-void FMPI2C_StructInit(FMPI2C_InitTypeDef* FMPI2C_InitStruct);
-void FMPI2C_Cmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_SoftwareResetCmd(FMPI2C_TypeDef* FMPI2Cx);
-void FMPI2C_ITConfig(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_IT, FunctionalState NewState);
-void FMPI2C_StretchClockCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_DualAddressCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_OwnAddress2Config(FMPI2C_TypeDef* FMPI2Cx, uint16_t Address, uint8_t Mask);
-void FMPI2C_GeneralCallCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_SlaveByteControlCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_SlaveAddressConfig(FMPI2C_TypeDef* FMPI2Cx, uint16_t Address);
-void FMPI2C_10BitAddressingModeCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-
-/* Communications handling functions ******************************************/
-void FMPI2C_AutoEndCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_ReloadCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_NumberOfBytesConfig(FMPI2C_TypeDef* FMPI2Cx, uint8_t Number_Bytes);
-void FMPI2C_MasterRequestConfig(FMPI2C_TypeDef* FMPI2Cx, uint16_t FMPI2C_Direction);
-void FMPI2C_GenerateSTART(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_GenerateSTOP(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_10BitAddressHeaderCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_AcknowledgeConfig(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-uint8_t FMPI2C_GetAddressMatched(FMPI2C_TypeDef* FMPI2Cx);
-uint16_t FMPI2C_GetTransferDirection(FMPI2C_TypeDef* FMPI2Cx);
-void FMPI2C_TransferHandling(FMPI2C_TypeDef* FMPI2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode);
-
-/* SMBUS management functions ************************************************/
-void FMPI2C_SMBusAlertCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_ClockTimeoutCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_ExtendedClockTimeoutCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_IdleClockTimeoutCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_TimeoutAConfig(FMPI2C_TypeDef* FMPI2Cx, uint16_t Timeout);
-void FMPI2C_TimeoutBConfig(FMPI2C_TypeDef* FMPI2Cx, uint16_t Timeout);
-void FMPI2C_CalculatePEC(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_PECRequestCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-uint8_t FMPI2C_GetPEC(FMPI2C_TypeDef* FMPI2Cx);
-
-/* FMPI2C registers management functions *****************************************/
-uint32_t FMPI2C_ReadRegister(FMPI2C_TypeDef* FMPI2Cx, uint8_t FMPI2C_Register);
-
-/* Data transfers management functions ****************************************/
-void FMPI2C_SendData(FMPI2C_TypeDef* FMPI2Cx, uint8_t Data);
-uint8_t FMPI2C_ReceiveData(FMPI2C_TypeDef* FMPI2Cx);
-
-/* DMA transfers management functions *****************************************/
-void FMPI2C_DMACmd(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_DMAReq, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-FlagStatus FMPI2C_GetFlagStatus(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_FLAG);
-void FMPI2C_ClearFlag(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_FLAG);
-ITStatus FMPI2C_GetITStatus(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_IT);
-void FMPI2C_ClearITPendingBit(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_IT);
-
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_FMPI2C_H */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_fsmc.c b/底盘/底盘-old/底盘/Library/stm32f4xx_fsmc.c
deleted file mode 100644
index 3f110af..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_fsmc.c
+++ /dev/null
@@ -1,1092 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_fsmc.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the FSMC peripheral:
- * + Interface with SRAM, PSRAM, NOR and OneNAND memories
- * + Interface with NAND memories
- * + Interface with 16-bit PC Card compatible memories
- * + Interrupts and flags management
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_fsmc.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup FSMC
- * @brief FSMC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-const FSMC_NORSRAMTimingInitTypeDef FSMC_DefaultTimingStruct = {0x0F, /* FSMC_AddressSetupTime */
- 0x0F, /* FSMC_AddressHoldTime */
- 0xFF, /* FSMC_DataSetupTime */
- 0x0F, /* FSMC_BusTurnAroundDuration */
- 0x0F, /* FSMC_CLKDivision */
- 0x0F, /* FSMC_DataLatency */
- FSMC_AccessMode_A /* FSMC_AccessMode */
- };
-/* Private define ------------------------------------------------------------*/
-
-/* --------------------- FSMC registers bit mask ---------------------------- */
-/* FSMC BCRx Mask */
-#define BCR_MBKEN_SET ((uint32_t)0x00000001)
-#define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE)
-#define BCR_FACCEN_SET ((uint32_t)0x00000040)
-
-/* FSMC PCRx Mask */
-#define PCR_PBKEN_SET ((uint32_t)0x00000004)
-#define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB)
-#define PCR_ECCEN_SET ((uint32_t)0x00000040)
-#define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF)
-#define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup FSMC_Private_Functions
- * @{
- */
-
-/** @defgroup FSMC_Group1 NOR/SRAM Controller functions
- * @brief NOR/SRAM Controller functions
- *
-@verbatim
- ===============================================================================
- ##### NOR and SRAM Controller functions #####
- ===============================================================================
-
- [..] The following sequence should be followed to configure the FSMC to interface
- with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank:
-
- (#) Enable the clock for the FSMC and associated GPIOs using the following functions:
- RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
-
- (#) FSMC pins configuration
- (++) Connect the involved FSMC pins to AF12 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
- (++) Configure these FSMC pins in alternate function mode by calling the function
- GPIO_Init();
-
- (#) Declare a FSMC_NORSRAMInitTypeDef structure, for example:
- FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
- and fill the FSMC_NORSRAMInitStructure variable with the allowed values of
- the structure member.
-
- (#) Initialize the NOR/SRAM Controller by calling the function
- FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
-
- (#) Then enable the NOR/SRAM Bank, for example:
- FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
-
- (#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initializes the FSMC NOR/SRAM Banks registers to their default
- * reset values.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
- * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
- * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
- * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
- * @retval None
- */
-void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
-{
- /* Check the parameter */
- assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
-
- /* FSMC_Bank1_NORSRAM1 */
- if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
- {
- FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
- }
- /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
- else
- {
- FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
- }
- FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
- FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
-}
-
-/**
- * @brief Initializes the FSMC NOR/SRAM Banks according to the specified
- * parameters in the FSMC_NORSRAMInitStruct.
- * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure
- * that contains the configuration information for the FSMC NOR/SRAM
- * specified Banks.
- * @retval None
- */
-void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
-{
- uint32_t tmpbcr = 0, tmpbtr = 0, tmpbwr = 0;
-
- /* Check the parameters */
- assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
- assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
- assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
- assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
- assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
- assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
- assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
- assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
- assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
- assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
- assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
- assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
- assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
- assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
- assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
- assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
- assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
- assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
- assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
- assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
-
- /* Get the BTCR register value */
- tmpbcr = FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank];
-
- /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
- WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
- tmpbcr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \
- FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \
- FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \
- FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \
- FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CBURSTRW));
-
- /* Bank1 NOR/SRAM control register configuration */
- tmpbcr |= (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
- FSMC_NORSRAMInitStruct->FSMC_MemoryType |
- FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
- FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
- FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
- FSMC_NORSRAMInitStruct->FSMC_WrapMode |
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
- FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
- FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
- FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
- FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
-
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = tmpbcr;
-
- if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
- {
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET;
- }
-
- /* Get the BTCR register value */
- tmpbtr = FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1];
-
- /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
- tmpbtr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \
- FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \
- FSMC_BTR1_ACCMOD));
-
- /* Bank1 NOR/SRAM timing register configuration */
- tmpbtr |= (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
-
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = tmpbtr;
-
- /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
- if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
- {
- assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
- assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
- assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
- assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration));
- assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
-
- /* Get the BWTR register value */
- tmpbwr = FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank];
-
- /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, and ACCMOD bits */
- tmpbwr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \
- FSMC_BWTR1_BUSTURN | FSMC_BWTR1_ACCMOD));
-
- tmpbwr |= (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
-
- FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = tmpbwr;
- }
- else
- {
- FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
- }
-}
-
-/**
- * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
- * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
-{
- /* Reset NOR/SRAM Init structure parameters values */
- FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
- FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
- FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
- FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
- FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
- FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
- FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
- FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
- FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
- FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
- FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct = (FSMC_NORSRAMTimingInitTypeDef*)((uint32_t)&FSMC_DefaultTimingStruct);
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct = (FSMC_NORSRAMTimingInitTypeDef*)((uint32_t)&FSMC_DefaultTimingStruct);
-}
-
-/**
- * @brief Enables or disables the specified NOR/SRAM Memory Bank.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
- * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
- * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
- * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
- * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
-{
- assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
- FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET;
- }
- else
- {
- /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
- FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup FSMC_Group2 NAND Controller functions
- * @brief NAND Controller functions
- *
-@verbatim
- ===============================================================================
- ##### NAND Controller functions #####
- ===============================================================================
-
- [..] The following sequence should be followed to configure the FSMC to interface
- with 8-bit or 16-bit NAND memory connected to the NAND Bank:
-
- (#) Enable the clock for the FSMC and associated GPIOs using the following functions:
- (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
- (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
-
- (#) FSMC pins configuration
- (++) Connect the involved FSMC pins to AF12 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
- (++) Configure these FSMC pins in alternate function mode by calling the function
- GPIO_Init();
-
- (#) Declare a FSMC_NANDInitTypeDef structure, for example:
- FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
- and fill the FSMC_NANDInitStructure variable with the allowed values of
- the structure member.
-
- (#) Initialize the NAND Controller by calling the function
- FSMC_NANDInit(&FSMC_NANDInitStructure);
-
- (#) Then enable the NAND Bank, for example:
- FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE);
-
- (#) At this stage you can read/write from/to the memory connected to the NAND Bank.
-
- [..]
- (@) To enable the Error Correction Code (ECC), you have to use the function
- FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE);
- [..]
- (@) and to get the current ECC value you have to use the function
- ECCval = FSMC_GetECC(FSMC_Bank3_NAND);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initializes the FSMC NAND Banks registers to their default reset values.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @retval None
- */
-void FSMC_NANDDeInit(uint32_t FSMC_Bank)
-{
- /* Check the parameter */
- assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- /* Set the FSMC_Bank2 registers to their reset values */
- FSMC_Bank2->PCR2 = 0x00000018;
- FSMC_Bank2->SR2 = 0x00000040;
- FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
- FSMC_Bank2->PATT2 = 0xFCFCFCFC;
- }
- /* FSMC_Bank3_NAND */
- else
- {
- /* Set the FSMC_Bank3 registers to their reset values */
- FSMC_Bank3->PCR3 = 0x00000018;
- FSMC_Bank3->SR3 = 0x00000040;
- FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
- FSMC_Bank3->PATT3 = 0xFCFCFCFC;
- }
-}
-
-/**
- * @brief Initializes the FSMC NAND Banks according to the specified parameters
- * in the FSMC_NANDInitStruct.
- * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that
- * contains the configuration information for the FSMC NAND specified Banks.
- * @retval None
- */
-void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
-{
- uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
-
- /* Check the parameters */
- assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
- assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
- assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
- assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
- assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
- assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
- assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
- assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
- assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
-
- if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
- {
- /* Get the NAND bank 2 register value */
- tmppcr = FSMC_Bank2->PCR2;
- }
- else
- {
- /* Get the NAND bank 3 register value */
- tmppcr = FSMC_Bank3->PCR3;
- }
-
- /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
- tmppcr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \
- FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \
- FSMC_PCR2_TAR | FSMC_PCR2_ECCPS));
-
- /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
- tmppcr |= (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
- PCR_MEMORYTYPE_NAND |
- FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
- FSMC_NANDInitStruct->FSMC_ECC |
- FSMC_NANDInitStruct->FSMC_ECCPageSize |
- (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
- (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
-
- if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
- {
- /* Get the NAND bank 2 register value */
- tmppmem = FSMC_Bank2->PMEM2;
- }
- else
- {
- /* Get the NAND bank 3 register value */
- tmppmem = FSMC_Bank3->PMEM3;
- }
-
- /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
- tmppmem &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \
- FSMC_PMEM2_MEMHIZ2));
-
- /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
- tmppmem |= (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-
- if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
- {
- /* Get the NAND bank 2 register value */
- tmppatt = FSMC_Bank2->PATT2;
- }
- else
- {
- /* Get the NAND bank 3 register value */
- tmppatt = FSMC_Bank3->PATT3;
- }
-
- /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
- tmppatt &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \
- FSMC_PATT2_ATTHIZ2));
-
- /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
- tmppatt |= (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-
- if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
- {
- /* FSMC_Bank2_NAND registers configuration */
- FSMC_Bank2->PCR2 = tmppcr;
- FSMC_Bank2->PMEM2 = tmppmem;
- FSMC_Bank2->PATT2 = tmppatt;
- }
- else
- {
- /* FSMC_Bank3_NAND registers configuration */
- FSMC_Bank3->PCR3 = tmppcr;
- FSMC_Bank3->PMEM3 = tmppmem;
- FSMC_Bank3->PATT3 = tmppatt;
- }
-}
-
-
-/**
- * @brief Fills each FSMC_NANDInitStruct member with its default value.
- * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
-{
- /* Reset NAND Init structure parameters values */
- FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
- FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
- FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
- FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
- FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
- FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
- FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
-}
-
-/**
- * @brief Enables or disables the specified NAND Memory Bank.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
-{
- assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->PCR2 |= PCR_PBKEN_SET;
- }
- else
- {
- FSMC_Bank3->PCR3 |= PCR_PBKEN_SET;
- }
- }
- else
- {
- /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET;
- }
- else
- {
- FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET;
- }
- }
-}
-/**
- * @brief Enables or disables the FSMC NAND ECC feature.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @param NewState: new state of the FSMC NAND ECC feature.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
-{
- assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->PCR2 |= PCR_ECCEN_SET;
- }
- else
- {
- FSMC_Bank3->PCR3 |= PCR_ECCEN_SET;
- }
- }
- else
- {
- /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET;
- }
- else
- {
- FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET;
- }
- }
-}
-
-/**
- * @brief Returns the error correction code register value.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @retval The Error Correction Code (ECC) value.
- */
-uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
-{
- uint32_t eccval = 0x00000000;
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- /* Get the ECCR2 register value */
- eccval = FSMC_Bank2->ECCR2;
- }
- else
- {
- /* Get the ECCR3 register value */
- eccval = FSMC_Bank3->ECCR3;
- }
- /* Return the error correction code value */
- return(eccval);
-}
-/**
- * @}
- */
-
-/** @defgroup FSMC_Group3 PCCARD Controller functions
- * @brief PCCARD Controller functions
- *
-@verbatim
- ===============================================================================
- ##### PCCARD Controller functions #####
- ===============================================================================
-
- [..] he following sequence should be followed to configure the FSMC to interface
- with 16-bit PC Card compatible memory connected to the PCCARD Bank:
-
- (#) Enable the clock for the FSMC and associated GPIOs using the following functions:
- (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
- (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
-
- (#) FSMC pins configuration
- (++) Connect the involved FSMC pins to AF12 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
- (++) Configure these FSMC pins in alternate function mode by calling the function
- GPIO_Init();
-
- (#) Declare a FSMC_PCCARDInitTypeDef structure, for example:
- FSMC_PCCARDInitTypeDef FSMC_PCCARDInitStructure;
- and fill the FSMC_PCCARDInitStructure variable with the allowed values of
- the structure member.
-
- (#) Initialize the PCCARD Controller by calling the function
- FSMC_PCCARDInit(&FSMC_PCCARDInitStructure);
-
- (#) Then enable the PCCARD Bank:
- FSMC_PCCARDCmd(ENABLE);
-
- (#) At this stage you can read/write from/to the memory connected to the PCCARD Bank.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initializes the FSMC PCCARD Bank registers to their default reset values.
- * @param None
- * @retval None
- */
-void FSMC_PCCARDDeInit(void)
-{
- /* Set the FSMC_Bank4 registers to their reset values */
- FSMC_Bank4->PCR4 = 0x00000018;
- FSMC_Bank4->SR4 = 0x00000000;
- FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
- FSMC_Bank4->PATT4 = 0xFCFCFCFC;
- FSMC_Bank4->PIO4 = 0xFCFCFCFC;
-}
-
-/**
- * @brief Initializes the FSMC PCCARD Bank according to the specified parameters
- * in the FSMC_PCCARDInitStruct.
- * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure
- * that contains the configuration information for the FSMC PCCARD Bank.
- * @retval None
- */
-void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
-{
- uint32_t tmppcr4 = 0, tmppmem4 = 0, tmppatt4 = 0, tmppio4 = 0;
-
- /* Check the parameters */
- assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
- assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
- assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
-
- assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
-
- assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
- assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
-
- /* Get PCCARD control register value */
- tmppcr4 = FSMC_Bank4->PCR4;
-
- /* Clear TAR, TCLR, PWAITEN and PWID bits */
- tmppcr4 &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \
- FSMC_PCR4_PWID));
-
- /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
- tmppcr4 |= (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
- FSMC_MemoryDataWidth_16b |
- (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
- (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
-
- FSMC_Bank4->PCR4 = tmppcr4;
-
- /* Get PCCARD common space timing register value */
- tmppmem4 = FSMC_Bank4->PMEM4;
-
- /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
- tmppmem4 &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \
- FSMC_PMEM4_MEMHIZ4));
-
- /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
- tmppmem4 |= (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-
- FSMC_Bank4->PMEM4 = tmppmem4;
-
- /* Get PCCARD timing parameters */
- tmppatt4 = FSMC_Bank4->PATT4;
-
- /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
- tmppatt4 &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \
- FSMC_PATT4_ATTHIZ4));
-
- /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
- tmppatt4 |= (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-
- FSMC_Bank4->PATT4 = tmppatt4;
-
- /* Get FSMC_PCCARD device timing parameters */
- tmppio4 = FSMC_Bank4->PIO4;
-
- /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
- tmppio4 &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \
- FSMC_PIO4_IOHIZ4));
-
- /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
- tmppio4 |= (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-
- FSMC_Bank4->PIO4 = tmppio4;
-}
-
-/**
- * @brief Fills each FSMC_PCCARDInitStruct member with its default value.
- * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
-{
- /* Reset PCCARD Init structure parameters values */
- FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
- FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
- FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
-}
-
-/**
- * @brief Enables or disables the PCCARD Memory Bank.
- * @param NewState: new state of the PCCARD Memory Bank.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FSMC_PCCARDCmd(FunctionalState NewState)
-{
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
- FSMC_Bank4->PCR4 |= PCR_PBKEN_SET;
- }
- else
- {
- /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
- FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup FSMC_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified FSMC interrupts.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
- * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
- * @arg FSMC_IT_Level: Level edge detection interrupt.
- * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
- * @param NewState: new state of the specified FSMC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
-{
- assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
- assert_param(IS_FSMC_IT(FSMC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected FSMC_Bank2 interrupts */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->SR2 |= FSMC_IT;
- }
- /* Enable the selected FSMC_Bank3 interrupts */
- else if (FSMC_Bank == FSMC_Bank3_NAND)
- {
- FSMC_Bank3->SR3 |= FSMC_IT;
- }
- /* Enable the selected FSMC_Bank4 interrupts */
- else
- {
- FSMC_Bank4->SR4 |= FSMC_IT;
- }
- }
- else
- {
- /* Disable the selected FSMC_Bank2 interrupts */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
-
- FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
- }
- /* Disable the selected FSMC_Bank3 interrupts */
- else if (FSMC_Bank == FSMC_Bank3_NAND)
- {
- FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
- }
- /* Disable the selected FSMC_Bank4 interrupts */
- else
- {
- FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
- }
- }
-}
-
-/**
- * @brief Checks whether the specified FSMC flag is set or not.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
- * @param FSMC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag.
- * @arg FSMC_FLAG_Level: Level detection Flag.
- * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag.
- * @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
- * @retval The new state of FSMC_FLAG (SET or RESET).
- */
-FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t tmpsr = 0x00000000;
-
- /* Check the parameters */
- assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
- assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- tmpsr = FSMC_Bank2->SR2;
- }
- else if(FSMC_Bank == FSMC_Bank3_NAND)
- {
- tmpsr = FSMC_Bank3->SR3;
- }
- /* FSMC_Bank4_PCCARD*/
- else
- {
- tmpsr = FSMC_Bank4->SR4;
- }
-
- /* Get the flag status */
- if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the FSMC's pending flags.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
- * @param FSMC_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag.
- * @arg FSMC_FLAG_Level: Level detection Flag.
- * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag.
- * @retval None
- */
-void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
- assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->SR2 &= ~FSMC_FLAG;
- }
- else if(FSMC_Bank == FSMC_Bank3_NAND)
- {
- FSMC_Bank3->SR3 &= ~FSMC_FLAG;
- }
- /* FSMC_Bank4_PCCARD*/
- else
- {
- FSMC_Bank4->SR4 &= ~FSMC_FLAG;
- }
-}
-
-/**
- * @brief Checks whether the specified FSMC interrupt has occurred or not.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
- * @param FSMC_IT: specifies the FSMC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
- * @arg FSMC_IT_Level: Level edge detection interrupt.
- * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
- * @retval The new state of FSMC_IT (SET or RESET).
- */
-ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
-
- /* Check the parameters */
- assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
- assert_param(IS_FSMC_GET_IT(FSMC_IT));
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- tmpsr = FSMC_Bank2->SR2;
- }
- else if(FSMC_Bank == FSMC_Bank3_NAND)
- {
- tmpsr = FSMC_Bank3->SR3;
- }
- /* FSMC_Bank4_PCCARD*/
- else
- {
- tmpsr = FSMC_Bank4->SR4;
- }
-
- itstatus = tmpsr & FSMC_IT;
-
- itenable = tmpsr & (FSMC_IT >> 3);
- if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the FSMC's interrupt pending bits.
- * @param FSMC_Bank: specifies the FSMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
- * @param FSMC_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
- * @arg FSMC_IT_Level: Level edge detection interrupt.
- * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
- * @retval None
- */
-void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
- assert_param(IS_FSMC_IT(FSMC_IT));
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
- }
- else if(FSMC_Bank == FSMC_Bank3_NAND)
- {
- FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
- }
- /* FSMC_Bank4_PCCARD*/
- else
- {
- FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_fsmc.h b/底盘/底盘-old/底盘/Library/stm32f4xx_fsmc.h
deleted file mode 100644
index da7cede..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_fsmc.h
+++ /dev/null
@@ -1,667 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_fsmc.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the FSMC firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_FSMC_H
-#define __STM32F4xx_FSMC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup FSMC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief Timing parameters For NOR/SRAM Banks
- */
-typedef struct
-{
- uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address setup time.
- This parameter can be a value between 0 and 0xF.
- @note This parameter is not used with synchronous NOR Flash memories. */
-
- uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address hold time.
- This parameter can be a value between 0 and 0xF.
- @note This parameter is not used with synchronous NOR Flash memories.*/
-
- uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the data setup time.
- This parameter can be a value between 0 and 0xFF.
- @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
-
- uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
- the duration of the bus turnaround.
- This parameter can be a value between 0 and 0xF.
- @note This parameter is only used for multiplexed NOR Flash memories. */
-
- uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
- This parameter can be a value between 1 and 0xF.
- @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
-
- uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
- to the memory before getting the first data.
- The parameter value depends on the memory type as shown below:
- - It must be set to 0 in case of a CRAM
- - It is don't care in asynchronous NOR, SRAM or ROM accesses
- - It may assume a value between 0 and 0xF in NOR Flash memories
- with synchronous burst mode enable */
-
- uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
- This parameter can be a value of @ref FSMC_Access_Mode */
-}FSMC_NORSRAMTimingInitTypeDef;
-
-/**
- * @brief FSMC NOR/SRAM Init structure definition
- */
-typedef struct
-{
- uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
- This parameter can be a value of @ref FSMC_NORSRAM_Bank */
-
- uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
- multiplexed on the data bus or not.
- This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
-
- uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
- the corresponding memory bank.
- This parameter can be a value of @ref FSMC_Memory_Type */
-
- uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be a value of @ref FSMC_Data_Width */
-
- uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
- valid only with synchronous burst Flash memories.
- This parameter can be a value of @ref FSMC_Burst_Access_Mode */
-
- uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
- valid only with asynchronous Flash memories.
- This parameter can be a value of @ref FSMC_AsynchronousWait */
-
- uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
- the Flash memory in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
-
- uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
- memory, valid only when accessing Flash memories in burst mode.
- This parameter can be a value of @ref FSMC_Wrap_Mode */
-
- uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
- clock cycle before the wait state or during the wait state,
- valid only when accessing memories in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Timing */
-
- uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
- This parameter can be a value of @ref FSMC_Write_Operation */
-
- uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait
- signal, valid for Flash memory access in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Signal */
-
- uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
- This parameter can be a value of @ref FSMC_Extended_Mode */
-
- uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
- This parameter can be a value of @ref FSMC_Write_Burst */
-
- FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/
-
- FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/
-}FSMC_NORSRAMInitTypeDef;
-
-/**
- * @brief Timing parameters For FSMC NAND and PCCARD Banks
- */
-typedef struct
-{
- uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
- the command assertion for NAND Flash read or write access
- to common/Attribute or I/O memory space (depending on
- the memory space timing to be configured).
- This parameter can be a value between 0 and 0xFF.*/
-
- uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
- command for NAND Flash read or write access to
- common/Attribute or I/O memory space (depending on the
- memory space timing to be configured).
- This parameter can be a number between 0x00 and 0xFF */
-
- uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
- (and data for write access) after the command de-assertion
- for NAND Flash read or write access to common/Attribute
- or I/O memory space (depending on the memory space timing
- to be configured).
- This parameter can be a number between 0x00 and 0xFF */
-
- uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
- data bus is kept in HiZ after the start of a NAND Flash
- write access to common/Attribute or I/O memory space (depending
- on the memory space timing to be configured).
- This parameter can be a number between 0x00 and 0xFF */
-}FSMC_NAND_PCCARDTimingInitTypeDef;
-
-/**
- * @brief FSMC NAND Init structure definition
- */
-typedef struct
-{
- uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
- This parameter can be a value of @ref FSMC_NAND_Bank */
-
- uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
- This parameter can be any value of @ref FSMC_Wait_feature */
-
- uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be any value of @ref FSMC_Data_Width */
-
- uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
- This parameter can be any value of @ref FSMC_ECC */
-
- uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
- This parameter can be any value of @ref FSMC_ECC_Page_Size */
-
- uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between 0 and 0xFF. */
-
- uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between 0x0 and 0xFF */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
-}FSMC_NANDInitTypeDef;
-
-/**
- * @brief FSMC PCCARD Init structure definition
- */
-
-typedef struct
-{
- uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
- This parameter can be any value of @ref FSMC_Wait_feature */
-
- uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between 0 and 0xFF. */
-
- uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between 0x0 and 0xFF */
-
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
-}FSMC_PCCARDInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FSMC_Exported_Constants
- * @{
- */
-
-/** @defgroup FSMC_NORSRAM_Bank
- * @{
- */
-#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
-#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
-#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
-#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
-/**
- * @}
- */
-
-/** @defgroup FSMC_NAND_Bank
- * @{
- */
-#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
-#define FSMC_Bank3_NAND ((uint32_t)0x00000100)
-/**
- * @}
- */
-
-/** @defgroup FSMC_PCCARD_Bank
- * @{
- */
-#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
-/**
- * @}
- */
-
-#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
- ((BANK) == FSMC_Bank1_NORSRAM2) || \
- ((BANK) == FSMC_Bank1_NORSRAM3) || \
- ((BANK) == FSMC_Bank1_NORSRAM4))
-
-#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
- ((BANK) == FSMC_Bank3_NAND))
-
-#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
- ((BANK) == FSMC_Bank3_NAND) || \
- ((BANK) == FSMC_Bank4_PCCARD))
-
-#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
- ((BANK) == FSMC_Bank3_NAND) || \
- ((BANK) == FSMC_Bank4_PCCARD))
-
-/** @defgroup FSMC_NOR_SRAM_Controller
- * @{
- */
-
-/** @defgroup FSMC_Data_Address_Bus_Multiplexing
- * @{
- */
-
-#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
-#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
-#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
- ((MUX) == FSMC_DataAddressMux_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Memory_Type
- * @{
- */
-
-#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
-#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
-#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
-#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
- ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
- ((MEMORY) == FSMC_MemoryType_NOR))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Width
- * @{
- */
-
-#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
-#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
-#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
- ((WIDTH) == FSMC_MemoryDataWidth_16b))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Burst_Access_Mode
- * @{
- */
-
-#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
-#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
-#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
- ((STATE) == FSMC_BurstAccessMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_AsynchronousWait
- * @{
- */
-#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
-#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
-#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
- ((STATE) == FSMC_AsynchronousWait_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Signal_Polarity
- * @{
- */
-#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
-#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
-#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
- ((POLARITY) == FSMC_WaitSignalPolarity_High))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wrap_Mode
- * @{
- */
-#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
-#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
-#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
- ((MODE) == FSMC_WrapMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Timing
- * @{
- */
-#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
-#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
-#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
- ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Write_Operation
- * @{
- */
-#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
-#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
-#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
- ((OPERATION) == FSMC_WriteOperation_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Signal
- * @{
- */
-#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
-#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
-#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
- ((SIGNAL) == FSMC_WaitSignal_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Extended_Mode
- * @{
- */
-#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
-#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
-
-#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
- ((MODE) == FSMC_ExtendedMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Write_Burst
- * @{
- */
-
-#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
-#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
-#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
- ((BURST) == FSMC_WriteBurst_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Address_Setup_Time
- * @{
- */
-#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Address_Hold_Time
- * @{
- */
-#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Setup_Time
- * @{
- */
-#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Bus_Turn_around_Duration
- * @{
- */
-#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_CLK_Division
- * @{
- */
-#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Latency
- * @{
- */
-#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Access_Mode
- * @{
- */
-#define FSMC_AccessMode_A ((uint32_t)0x00000000)
-#define FSMC_AccessMode_B ((uint32_t)0x10000000)
-#define FSMC_AccessMode_C ((uint32_t)0x20000000)
-#define FSMC_AccessMode_D ((uint32_t)0x30000000)
-#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
- ((MODE) == FSMC_AccessMode_B) || \
- ((MODE) == FSMC_AccessMode_C) || \
- ((MODE) == FSMC_AccessMode_D))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_NAND_PCCARD_Controller
- * @{
- */
-
-/** @defgroup FSMC_Wait_feature
- * @{
- */
-#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
-#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
-#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
- ((FEATURE) == FSMC_Waitfeature_Enable))
-/**
- * @}
- */
-
-
-/** @defgroup FSMC_ECC
- * @{
- */
-#define FSMC_ECC_Disable ((uint32_t)0x00000000)
-#define FSMC_ECC_Enable ((uint32_t)0x00000040)
-#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
- ((STATE) == FSMC_ECC_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_ECC_Page_Size
- * @{
- */
-#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
-#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
-#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
-#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
-#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
-#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
-#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_8192Bytes))
-/**
- * @}
- */
-
-/** @defgroup FSMC_TCLR_Setup_Time
- * @{
- */
-#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_TAR_Setup_Time
- * @{
- */
-#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Setup_Time
- * @{
- */
-#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Setup_Time
- * @{
- */
-#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Hold_Setup_Time
- * @{
- */
-#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_HiZ_Setup_Time
- * @{
- */
-#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Interrupt_sources
- * @{
- */
-#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
-#define FSMC_IT_Level ((uint32_t)0x00000010)
-#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
-#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
-#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
- ((IT) == FSMC_IT_Level) || \
- ((IT) == FSMC_IT_FallingEdge))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Flags
- * @{
- */
-#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
-#define FSMC_FLAG_Level ((uint32_t)0x00000002)
-#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
-#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
-#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
- ((FLAG) == FSMC_FLAG_Level) || \
- ((FLAG) == FSMC_FLAG_FallingEdge) || \
- ((FLAG) == FSMC_FLAG_FEMPT))
-
-#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* NOR/SRAM Controller functions **********************************************/
-void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
-void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
-void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
-void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-
-/* NAND Controller functions **************************************************/
-void FSMC_NANDDeInit(uint32_t FSMC_Bank);
-void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
-void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
-void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
-
-/* PCCARD Controller functions ************************************************/
-void FSMC_PCCARDDeInit(void);
-void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
-void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
-void FSMC_PCCARDCmd(FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
-FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
-void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
-ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
-void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_FSMC_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_gpio.c b/底盘/底盘-old/底盘/Library/stm32f4xx_gpio.c
deleted file mode 100644
index 12c43c8..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_gpio.c
+++ /dev/null
@@ -1,603 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_gpio.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the GPIO peripheral:
- * + Initialization and Configuration
- * + GPIO Read and Write
- * + GPIO Alternate functions configuration
- *
-@verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable the GPIO AHB clock using the following function
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
-
- (#) Configure the GPIO pin(s) using GPIO_Init()
- Four possible configuration are available for each pin:
- (++) Input: Floating, Pull-up, Pull-down.
- (++) Output: Push-Pull (Pull-up, Pull-down or no Pull)
- Open Drain (Pull-up, Pull-down or no Pull). In output mode, the speed
- is configurable: 2 MHz, 25 MHz, 50 MHz or 100 MHz.
- (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) Open
- Drain (Pull-up, Pull-down or no Pull).
- (++) Analog: required mode when a pin is to be used as ADC channel or DAC
- output.
-
- (#) Peripherals alternate function:
- (++) For ADC and DAC, configure the desired pin in analog mode using
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN;
- (+++) For other peripherals (TIM, USART...):
- (+++) Connect the pin to the desired peripherals' Alternate
- Function (AF) using GPIO_PinAFConfig() function
- (+++) Configure the desired pin in alternate function mode using
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- (+++) Select the type, pull-up/pull-down and output speed via
- GPIO_PuPd, GPIO_OType and GPIO_Speed members
- (+++) Call GPIO_Init() function
-
- (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
-
- (#) To set/reset the level of a pin configured in output mode use
- GPIO_SetBits()/GPIO_ResetBits()
-
- (#) During and just after reset, the alternate functions are not
- active and the GPIO pins are configured in input floating mode (except JTAG
- pins).
-
- (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
- (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
- priority over the GPIO function.
-
- (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
- general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
- The HSE has priority over the GPIO function.
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_gpio.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup GPIO
- * @brief GPIO driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup GPIO_Private_Functions
- * @{
- */
-
-/** @defgroup GPIO_Group1 Initialization and Configuration
- * @brief Initialization and Configuration
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initializes the GPIOx peripheral registers to their default reset values.
- * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins).
- * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
- * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
- * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
- * @retval None
- */
-void GPIO_DeInit(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- if (GPIOx == GPIOA)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE);
- }
- else if (GPIOx == GPIOB)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE);
- }
- else if (GPIOx == GPIOC)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE);
- }
- else if (GPIOx == GPIOD)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE);
- }
- else if (GPIOx == GPIOE)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE);
- }
- else if (GPIOx == GPIOF)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE);
- }
- else if (GPIOx == GPIOG)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE);
- }
- else if (GPIOx == GPIOH)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE);
- }
-
- else if (GPIOx == GPIOI)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE);
- }
- else if (GPIOx == GPIOJ)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, DISABLE);
- }
- else
- {
- if (GPIOx == GPIOK)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
- * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
- * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
- * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
- * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
- * the configuration information for the specified GPIO peripheral.
- * @retval None
- */
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
-{
- uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
- assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
- assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
-
- /* ------------------------- Configure the port pins ---------------- */
- /*-- GPIO Mode Configuration --*/
- for (pinpos = 0x00; pinpos < 0x10; pinpos++)
- {
- pos = ((uint32_t)0x01) << pinpos;
- /* Get the port pins position */
- currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
-
- if (currentpin == pos)
- {
- GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
- GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
-
- if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
- {
- /* Check Speed mode parameters */
- assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
-
- /* Speed mode configuration */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
- GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
-
- /* Check Output mode parameters */
- assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
-
- /* Output mode configuration*/
- GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;
- GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
- }
-
- /* Pull-up Pull down resistor configuration*/
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
- GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
- }
- }
-}
-
-/**
- * @brief Fills each GPIO_InitStruct member with its default value.
- * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
-{
- /* Reset GPIO init structure parameters values */
- GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
- GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
- GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
-}
-
-/**
- * @brief Locks GPIO Pins configuration registers.
- * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
- * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
- * @note The configuration of the locked GPIO pins can no longer be modified
- * until the next reset.
- * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
- * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
- * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
- * @param GPIO_Pin: specifies the port bit to be locked.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- __IO uint32_t tmp = 0x00010000;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- tmp |= GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LCKR = tmp;
- /* Reset LCKK bit */
- GPIOx->LCKR = GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LCKR = tmp;
- /* Read LCKK bit*/
- tmp = GPIOx->LCKR;
- /* Read LCKK bit*/
- tmp = GPIOx->LCKR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Group2 GPIO Read and Write
- * @brief GPIO Read and Write
- *
-@verbatim
- ===============================================================================
- ##### GPIO Read and Write #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads the specified input port pin.
- * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
- * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
- * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
- * @param GPIO_Pin: specifies the port bit to read.
- * This parameter can be GPIO_Pin_x where x can be (0..15).
- * @retval The input port pin value.
- */
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
- {
- bitstatus = (uint8_t)Bit_SET;
- }
- else
- {
- bitstatus = (uint8_t)Bit_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Reads the specified GPIO input data port.
- * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
- * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
- * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
- * @retval GPIO input data port value.
- */
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- return ((uint16_t)GPIOx->IDR);
-}
-
-/**
- * @brief Reads the specified output data port bit.
- * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
- * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
- * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
- * @param GPIO_Pin: specifies the port bit to read.
- * This parameter can be GPIO_Pin_x where x can be (0..15).
- * @retval The output port pin value.
- */
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if (((GPIOx->ODR) & GPIO_Pin) != (uint32_t)Bit_RESET)
- {
- bitstatus = (uint8_t)Bit_SET;
- }
- else
- {
- bitstatus = (uint8_t)Bit_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Reads the specified GPIO output data port.
- * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
- * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
- * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
- * @retval GPIO output data port value.
- */
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- return ((uint16_t)GPIOx->ODR);
-}
-
-/**
- * @brief Sets the selected data port bits.
- * @note This functions uses GPIOx_BSRR register to allow atomic read/modify
- * accesses. In this way, there is no risk of an IRQ occurring between
- * the read and the modify access.
- * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
- * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
- * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
- * @param GPIO_Pin: specifies the port bits to be written.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->BSRR = GPIO_Pin;
-}
-
-/**
- * @brief Clears the selected data port bits.
- * @note This functions uses GPIOx_BSRR register to allow atomic read/modify
- * accesses. In this way, there is no risk of an IRQ occurring between
- * the read and the modify access.
- * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
- * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
- * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
- * @param GPIO_Pin: specifies the port bits to be written.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
-}
-
-/**
- * @brief Sets or clears the selected data port bit.
- * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
- * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
- * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
- * @param GPIO_Pin: specifies the port bit to be written.
- * This parameter can be one of GPIO_Pin_x where x can be (0..15).
- * @param BitVal: specifies the value to be written to the selected bit.
- * This parameter can be one of the BitAction enum values:
- * @arg Bit_RESET: to clear the port pin
- * @arg Bit_SET: to set the port pin
- * @retval None
- */
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
- assert_param(IS_GPIO_BIT_ACTION(BitVal));
-
- if (BitVal != Bit_RESET)
- {
- GPIOx->BSRR = GPIO_Pin;
- }
- else
- {
- GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
- }
-}
-
-/**
- * @brief Writes data to the specified GPIO data port.
- * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
- * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
- * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
- * @param PortVal: specifies the value to be written to the port output data register.
- * @retval None
- */
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- GPIOx->ODR = PortVal;
-}
-
-/**
- * @brief Toggles the specified GPIO pins..
- * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
- * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
- * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
- * @param GPIO_Pin: Specifies the pins to be toggled.
- * @retval None
- */
-void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- GPIOx->ODR ^= GPIO_Pin;
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function
- * @brief GPIO Alternate functions configuration function
- *
-@verbatim
- ===============================================================================
- ##### GPIO Alternate functions configuration function #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Changes the mapping of the specified pin.
- * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
- * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
- * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
- * @param GPIO_PinSource: specifies the pin for the Alternate function.
- * This parameter can be GPIO_PinSourcex where x can be (0..15).
- * @param GPIO_AFSelection: selects the pin to used as Alternate function.
- * This parameter can be one of the following values:
- * @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset)
- * @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset)
- * @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset)
- * @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset)
- * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
- * @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1
- * @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1
- * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2
- * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2
- * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2
- * @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3
- * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3
- * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3
- * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3
- * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4
- * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4
- * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4
- * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5
- * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
- * @arg GPIO_AF_SPI4: Connect SPI4 pins to AF5
- * @arg GPIO_AF_SPI5: Connect SPI5 pins to AF5
- * @arg GPIO_AF_SPI6: Connect SPI6 pins to AF5
- * @arg GPIO_AF_SAI1: Connect SAI1 pins to AF6 for STM32F42xxx/43xxx devices.
- * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
- * @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7
- * @arg GPIO_AF_USART1: Connect USART1 pins to AF7
- * @arg GPIO_AF_USART2: Connect USART2 pins to AF7
- * @arg GPIO_AF_USART3: Connect USART3 pins to AF7
- * @arg GPIO_AF_UART4: Connect UART4 pins to AF8
- * @arg GPIO_AF_UART5: Connect UART5 pins to AF8
- * @arg GPIO_AF_USART6: Connect USART6 pins to AF8
- * @arg GPIO_AF_UART7: Connect UART7 pins to AF8
- * @arg GPIO_AF_UART8: Connect UART8 pins to AF8
- * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9
- * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9
- * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9
- * @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9
- * @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9
- * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10
- * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10
- * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11
- * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12
- * @arg GPIO_AF_FMC: Connect FMC pins to AF12 for STM32F42xxx/43xxx devices.
- * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12
- * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12
- * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13
- * @arg GPIO_AF_LTDC: Connect LTDC pins to AF14 for STM32F429xx/439xx devices.
- * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15
- * @retval None
- */
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
-{
- uint32_t temp = 0x00;
- uint32_t temp_2 = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
- assert_param(IS_GPIO_AF(GPIO_AF));
-
- temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
- GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
- temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
- GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_gpio.h b/底盘/底盘-old/底盘/Library/stm32f4xx_gpio.h
deleted file mode 100644
index efa1c21..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_gpio.h
+++ /dev/null
@@ -1,584 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_gpio.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the GPIO firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_GPIO_H
-#define __STM32F4xx_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup GPIO
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
- ((PERIPH) == GPIOB) || \
- ((PERIPH) == GPIOC) || \
- ((PERIPH) == GPIOD) || \
- ((PERIPH) == GPIOE) || \
- ((PERIPH) == GPIOF) || \
- ((PERIPH) == GPIOG) || \
- ((PERIPH) == GPIOH) || \
- ((PERIPH) == GPIOI) || \
- ((PERIPH) == GPIOJ) || \
- ((PERIPH) == GPIOK))
-
-/**
- * @brief GPIO Configuration Mode enumeration
- */
-typedef enum
-{
- GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
- GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
- GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
- GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */
-}GPIOMode_TypeDef;
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \
- ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
-
-/**
- * @brief GPIO Output type enumeration
- */
-typedef enum
-{
- GPIO_OType_PP = 0x00,
- GPIO_OType_OD = 0x01
-}GPIOOType_TypeDef;
-#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
-
-
-/**
- * @brief GPIO Output Maximum frequency enumeration
- */
-typedef enum
-{
- GPIO_Low_Speed = 0x00, /*!< Low speed */
- GPIO_Medium_Speed = 0x01, /*!< Medium speed */
- GPIO_Fast_Speed = 0x02, /*!< Fast speed */
- GPIO_High_Speed = 0x03 /*!< High speed */
-}GPIOSpeed_TypeDef;
-
-/* Add legacy definition */
-#define GPIO_Speed_2MHz GPIO_Low_Speed
-#define GPIO_Speed_25MHz GPIO_Medium_Speed
-#define GPIO_Speed_50MHz GPIO_Fast_Speed
-#define GPIO_Speed_100MHz GPIO_High_Speed
-
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) || \
- ((SPEED) == GPIO_Fast_Speed)|| ((SPEED) == GPIO_High_Speed))
-
-/**
- * @brief GPIO Configuration PullUp PullDown enumeration
- */
-typedef enum
-{
- GPIO_PuPd_NOPULL = 0x00,
- GPIO_PuPd_UP = 0x01,
- GPIO_PuPd_DOWN = 0x02
-}GPIOPuPd_TypeDef;
-#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
- ((PUPD) == GPIO_PuPd_DOWN))
-
-/**
- * @brief GPIO Bit SET and Bit RESET enumeration
- */
-typedef enum
-{
- Bit_RESET = 0,
- Bit_SET
-}BitAction;
-#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
-
-
-/**
- * @brief GPIO Init structure definition
- */
-typedef struct
-{
- uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
- This parameter can be any value of @ref GPIO_pins_define */
-
- GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref GPIOMode_TypeDef */
-
- GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
- This parameter can be a value of @ref GPIOSpeed_TypeDef */
-
- GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
- This parameter can be a value of @ref GPIOOType_TypeDef */
-
- GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
- This parameter can be a value of @ref GPIOPuPd_TypeDef */
-}GPIO_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Constants
- * @{
- */
-
-/** @defgroup GPIO_pins_define
- * @{
- */
-#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
-#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
-#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
-#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
-#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
-#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
-#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
-#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
-#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */
-#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */
-#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */
-#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */
-#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */
-#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */
-#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */
-#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */
-#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
-
-#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
-#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
-#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
- ((PIN) == GPIO_Pin_1) || \
- ((PIN) == GPIO_Pin_2) || \
- ((PIN) == GPIO_Pin_3) || \
- ((PIN) == GPIO_Pin_4) || \
- ((PIN) == GPIO_Pin_5) || \
- ((PIN) == GPIO_Pin_6) || \
- ((PIN) == GPIO_Pin_7) || \
- ((PIN) == GPIO_Pin_8) || \
- ((PIN) == GPIO_Pin_9) || \
- ((PIN) == GPIO_Pin_10) || \
- ((PIN) == GPIO_Pin_11) || \
- ((PIN) == GPIO_Pin_12) || \
- ((PIN) == GPIO_Pin_13) || \
- ((PIN) == GPIO_Pin_14) || \
- ((PIN) == GPIO_Pin_15))
-/**
- * @}
- */
-
-
-/** @defgroup GPIO_Pin_sources
- * @{
- */
-#define GPIO_PinSource0 ((uint8_t)0x00)
-#define GPIO_PinSource1 ((uint8_t)0x01)
-#define GPIO_PinSource2 ((uint8_t)0x02)
-#define GPIO_PinSource3 ((uint8_t)0x03)
-#define GPIO_PinSource4 ((uint8_t)0x04)
-#define GPIO_PinSource5 ((uint8_t)0x05)
-#define GPIO_PinSource6 ((uint8_t)0x06)
-#define GPIO_PinSource7 ((uint8_t)0x07)
-#define GPIO_PinSource8 ((uint8_t)0x08)
-#define GPIO_PinSource9 ((uint8_t)0x09)
-#define GPIO_PinSource10 ((uint8_t)0x0A)
-#define GPIO_PinSource11 ((uint8_t)0x0B)
-#define GPIO_PinSource12 ((uint8_t)0x0C)
-#define GPIO_PinSource13 ((uint8_t)0x0D)
-#define GPIO_PinSource14 ((uint8_t)0x0E)
-#define GPIO_PinSource15 ((uint8_t)0x0F)
-
-#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
- ((PINSOURCE) == GPIO_PinSource1) || \
- ((PINSOURCE) == GPIO_PinSource2) || \
- ((PINSOURCE) == GPIO_PinSource3) || \
- ((PINSOURCE) == GPIO_PinSource4) || \
- ((PINSOURCE) == GPIO_PinSource5) || \
- ((PINSOURCE) == GPIO_PinSource6) || \
- ((PINSOURCE) == GPIO_PinSource7) || \
- ((PINSOURCE) == GPIO_PinSource8) || \
- ((PINSOURCE) == GPIO_PinSource9) || \
- ((PINSOURCE) == GPIO_PinSource10) || \
- ((PINSOURCE) == GPIO_PinSource11) || \
- ((PINSOURCE) == GPIO_PinSource12) || \
- ((PINSOURCE) == GPIO_PinSource13) || \
- ((PINSOURCE) == GPIO_PinSource14) || \
- ((PINSOURCE) == GPIO_PinSource15))
-/**
- * @}
- */
-
-/** @defgroup GPIO_Alternat_function_selection_define
- * @{
- */
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
-#if defined(STM32F446xx)
-#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */
-#endif /* STM32F446xx */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
-#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#if defined(STM32F410xx) || defined(STM32F413_423xx)
-#define GPIO_AF_LPTIM ((uint8_t)0x01) /* LPTIM Alternate Function mapping */
-#endif /* STM32F410xx || STM32F413_423xx */
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
-#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
-#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
-#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
-#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
-#if defined(STM32F446xx)
-#define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */
-#endif /* STM32F446xx */
-#if defined(STM32F413_423xx)
-#define GPIO_AF3_DFSDM2 ((uint8_t)0x03) /* DFSDM2 Alternate Function mapping */
-#endif /* STM32F413_423xx */
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
-#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
-#if defined(STM32F446xx)
-#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
-#endif /* STM32F446xx */
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-#define GPIO_AF_FMPI2C ((uint8_t)0x04) /* FMPI2C Alternate Function mapping */
-#endif /* STM32F410xx || STM32F446xx */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
-#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping (Only for STM32F411xE and STM32F413_423xx Devices) */
-#define GPIO_AF_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */
-#define GPIO_AF_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
-#define GPIO_AF_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
-
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping (Only for STM32F410xx Devices) */
-#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping (Only for STM32F410xx/STM32F411xE Devices) */
-#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping (Only for STM32F411xE Devices) */
-#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5 Alternate Function mapping (Only for STM32F410xx/STM32F411xE Devices) */
-#define GPIO_AF_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
-#define GPIO_AF_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping (only for STM32F412xG and STM32F413_423xx Devices) */
-#if defined(STM32F412xG) || defined(STM32F413_423xx)
-#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */
-#endif /* STM32F412xG || STM32F413_423xx */
-#if defined(STM32F413_423xx)
-#define GPIO_AF6_DFSDM2 ((uint8_t)0x06) /* DFSDM2 Alternate Function mapping */
-#endif /* STM32F413_423xx */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3ext Alternate Function mapping */
-#if defined(STM32F413_423xx)
-#define GPIO_AF7_DFSDM2 ((uint8_t)0x07) /* DFSDM2 Alternate Function mapping */
-#define GPIO_AF7_SAI1 ((uint8_t)0x07) /* SAI1 Alternate Function mapping */
-#endif /* STM32F413_423xx */
-
-/**
- * @brief AF 7 selection Legacy
- */
-#define GPIO_AF_I2S3ext GPIO_AF7_SPI3
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
-#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
-#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
-#define GPIO_AF_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */
-#define GPIO_AF_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
-#if defined(STM32F412xG) || defined(STM32F413_423xx)
-#define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */
-#define GPIO_AF8_DFSDM1 ((uint8_t)0x08) /* DFSDM Alternate Function mapping */
-#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */
-#endif /* STM32F412xG || STM32F413_423xx */
-#if defined(STM32F446xx)
-#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
-#define GPIO_AF_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */
-#endif /* STM32F446xx */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
-#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
-#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
-#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
-#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
-#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping (Only for STM32F401xx/STM32F410xx/STM32F411xE/STM32F412xG/STM32F413_423xx Devices) */
-#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping (Only for STM32F401xx/STM32F411xE/STM32F412xG and STM32F413_423xx Devices) */
-#if defined(STM32F446xx)
-#define GPIO_AF9_SAI2 ((uint8_t)0x09) /* SAI2 Alternate Function mapping */
-#endif /* STM32F446xx */
-#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QuadSPI Alternate Function mapping */
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
-#define GPIO_AF9_FMPI2C ((uint8_t)0x09) /* FMPI2C Alternate Function mapping (Only for STM32F410xx Devices) */
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
-#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
-#if defined(STM32F446xx)
-#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */
-#endif /* STM32F446xx */
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QuadSPI Alternate Function mapping */
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
-#if defined(STM32F412xG) || defined(STM32F413_423xx)
-#define GPIO_AF10_FMC ((uint8_t)0xA) /* FMC Alternate Function mapping */
-#define GPIO_AF10_DFSDM1 ((uint8_t)0xA) /* DFSDM Alternate Function mapping */
-#endif /* STM32F412xG || STM32F413_423xx */
-#if defined(STM32F413_423xx)
-#define GPIO_AF10_DFSDM2 ((uint8_t)0x0A) /* DFSDM2 Alternate Function mapping */
-#define GPIO_AF10_SAI1 ((uint8_t)0x0A) /* SAI1 Alternate Function mapping */
-#endif /* STM32F413_423xx */
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
-#if defined(STM32F413_423xx)
-#define GPIO_AF11_UART4 ((uint8_t)0x0B) /* UART4 Alternate Function mapping */
-#define GPIO_AF11_UART5 ((uint8_t)0x0B) /* UART5 Alternate Function mapping */
-#define GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */
-#define GPIO_AF11_UART10 ((uint8_t)0x0B) /* UART10 Alternate Function mapping */
-#define GPIO_AF11_CAN3 ((uint8_t)0x0B) /* CAN3 Alternate Function mapping */
-#endif /* STM32F413_423xx */
-
-/**
- * @brief AF 12 selection
- */
-#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
-#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */
-#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#define GPIO_AF_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
-#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
-
-/**
- * @brief AF 13 selection
- */
-#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
-#if defined(STM32F469_479xx)
-#define GPIO_AF_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */
-#endif /* STM32F469_479xx */
-/**
- * @brief AF 14 selection
- */
-#define GPIO_AF_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */
-#if defined(STM32F413_423xx)
-#define GPIO_AF14_RNG ((uint8_t)0x0E) /* RNG Alternate Function mapping */
-#endif /* STM32F413_423xx */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
-
-#if defined(STM32F40_41xxx)
-#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
- ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
- ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
- ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
- ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
- ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
- ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
- ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
- ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
- ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
- ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
- ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \
- ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \
- ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \
- ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
- ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \
- ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \
- ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_FSMC))
-#endif /* STM32F40_41xxx */
-
-#if defined(STM32F401xx)
-#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
- ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
- ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
- ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
- ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
- ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
- ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
- ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
- ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
- ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
- ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
- ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_USART6) || \
- ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
- ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4))
-#endif /* STM32F401xx */
-
-#if defined(STM32F411xE)
-#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 13) && ((AF) != 14))
-#endif /* STM32F411xE */
-
-#if defined(STM32F410xx)
-#define IS_GPIO_AF(AF) (((AF) < 10) || ((AF) == 15))
-#endif /* STM32F410xx */
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx)
-#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
- ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
- ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
- ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
- ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
- ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
- ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
- ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
- ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
- ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
- ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
- ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \
- ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \
- ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \
- ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
- ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \
- ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \
- ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4) || \
- ((AF) == GPIO_AF_SPI5) || ((AF) == GPIO_AF_SPI6) || \
- ((AF) == GPIO_AF_UART7) || ((AF) == GPIO_AF_UART8) || \
- ((AF) == GPIO_AF_FMC) || ((AF) == GPIO_AF_SAI1) || \
- ((AF) == GPIO_AF_LTDC))
-#endif /* STM32F427_437xx || STM32F429_439xx */
-
-#if defined(STM32F412xG)
-#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 14))
-#endif /* STM32F412xG */
-
-#if defined(STM32F413_423xx)
-#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 13))
-#endif /* STM32F413_423xx */
-
-#if defined(STM32F446xx)
-#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 14))
-#endif /* STM32F446xx */
-
-#if defined(STM32F469_479xx)
-#define IS_GPIO_AF(AF) ((AF) < 16)
-#endif /* STM32F469_479xx */
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Legacy
- * @{
- */
-
-#define GPIO_Mode_AIN GPIO_Mode_AN
-
-#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS
-#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS
-#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the GPIO configuration to the default reset state ****/
-void GPIO_DeInit(GPIO_TypeDef* GPIOx);
-
-/* Initialization and Configuration functions *********************************/
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-
-/* GPIO Read and Write functions **********************************************/
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
-void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-
-/* GPIO Alternate functions configuration function ****************************/
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_GPIO_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_hash.c b/底盘/底盘-old/底盘/Library/stm32f4xx_hash.c
deleted file mode 100644
index 686bdad..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_hash.c
+++ /dev/null
@@ -1,718 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_hash.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the HASH / HMAC Processor (HASH) peripheral:
- * - Initialization and Configuration functions
- * - Message Digest generation functions
- * - context swapping functions
- * - DMA interface function
- * - Interrupts and flags management
- *
-@verbatim
- ===================================================================
- ##### How to use this driver #####
- ===================================================================
-
- *** HASH operation : ***
- ========================
- [..]
- (#) Enable the HASH controller clock using
- RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function.
-
- (#) Initialize the HASH using HASH_Init() function.
-
- (#) Reset the HASH processor core, so that the HASH will be ready
- to compute he message digest of a new message by using HASH_Reset() function.
-
- (#) Enable the HASH controller using the HASH_Cmd() function.
-
- (#) if using DMA for Data input transfer, Activate the DMA Request
- using HASH_DMACmd() function
-
- (#) if DMA is not used for data transfer, use HASH_DataIn() function
- to enter data to IN FIFO.
-
-
- (#) Configure the Number of valid bits in last word of the message
- using HASH_SetLastWordValidBitsNbr() function.
-
- (#) if the message length is not an exact multiple of 512 bits,
- then the function HASH_StartDigest() must be called to launch the computation
- of the final digest.
-
- (#) Once computed, the digest can be read using HASH_GetDigest() function.
-
- (#) To control HASH events you can use one of the following wo methods:
- (++) Check on HASH flags using the HASH_GetFlagStatus() function.
- (++) Use HASH interrupts through the function HASH_ITConfig() at
- initialization phase and HASH_GetITStatus() function into
- interrupt routines in hashing phase.
- After checking on a flag you should clear it using HASH_ClearFlag()
- function. And after checking on an interrupt event you should
- clear it using HASH_ClearITPendingBit() function.
-
- (#) Save and restore hash processor context using
- HASH_SaveContext() and HASH_RestoreContext() functions.
-
-
-
- *** HMAC operation : ***
- ========================
- [..] The HMAC algorithm is used for message authentication, by
- irreversibly binding the message being processed to a key chosen
- by the user.
- For HMAC specifications, refer to "HMAC: keyed-hashing for message
- authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997"
-
- [..] Basically, the HMAC algorithm consists of two nested hash operations:
- HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)]
- where:
- (+) "pad" is a sequence of zeroes needed to extend the key to the
- length of the underlying hash function data block (that is
- 512 bits for both the SHA-1 and MD5 hash algorithms)
- (+) "|" represents the concatenation operator
-
-
- [..]To compute the HMAC, four different phases are required:
- (#) Initialize the HASH using HASH_Init() function to do HMAC
- operation.
-
- (#) The key (to be used for the inner hash function) is then given to the core.
- This operation follows the same mechanism as the one used to send the
- message in the hash operation (that is, by HASH_DataIn() function and,
- finally, HASH_StartDigest() function.
-
- (#) Once the last word has been entered and computation has started,
- the hash processor elaborates the key. It is then ready to accept the message
- text using the same mechanism as the one used to send the message in the
- hash operation.
-
- (#) After the first hash round, the hash processor returns "ready" to indicate
- that it is ready to receive the key to be used for the outer hash function
- (normally, this key is the same as the one used for the inner hash function).
- When the last word of the key is entered and computation starts, the HMAC
- result is made available using HASH_GetDigest() function.
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hash.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup HASH
- * @brief HASH driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup HASH_Private_Functions
- * @{
- */
-
-/** @defgroup HASH_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to
- (+) Initialize the HASH peripheral
- (+) Configure the HASH Processor
- (+) MD5/SHA1,
- (+) HASH/HMAC,
- (+) datatype
- (+) HMAC Key (if mode = HMAC)
- (+) Reset the HASH Processor
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initializes the HASH peripheral registers to their default reset values
- * @param None
- * @retval None
- */
-void HASH_DeInit(void)
-{
- /* Enable HASH reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, ENABLE);
- /* Release HASH from reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, DISABLE);
-}
-
-/**
- * @brief Initializes the HASH peripheral according to the specified parameters
- * in the HASH_InitStruct structure.
- * @note the hash processor is reset when calling this function so that the
- * HASH will be ready to compute the message digest of a new message.
- * There is no need to call HASH_Reset() function.
- * @param HASH_InitStruct: pointer to a HASH_InitTypeDef structure that contains
- * the configuration information for the HASH peripheral.
- * @note The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only
- * if the algorithm mode is HMAC.
- * @retval None
- */
-void HASH_Init(HASH_InitTypeDef* HASH_InitStruct)
-{
- /* Check the parameters */
- assert_param(IS_HASH_ALGOSELECTION(HASH_InitStruct->HASH_AlgoSelection));
- assert_param(IS_HASH_DATATYPE(HASH_InitStruct->HASH_DataType));
- assert_param(IS_HASH_ALGOMODE(HASH_InitStruct->HASH_AlgoMode));
-
- /* Configure the Algorithm used, algorithm mode and the datatype */
- HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE);
- HASH->CR |= (HASH_InitStruct->HASH_AlgoSelection | \
- HASH_InitStruct->HASH_DataType | \
- HASH_InitStruct->HASH_AlgoMode);
-
- /* if algorithm mode is HMAC, set the Key */
- if(HASH_InitStruct->HASH_AlgoMode == HASH_AlgoMode_HMAC)
- {
- assert_param(IS_HASH_HMAC_KEYTYPE(HASH_InitStruct->HASH_HMACKeyType));
- HASH->CR &= ~HASH_CR_LKEY;
- HASH->CR |= HASH_InitStruct->HASH_HMACKeyType;
- }
-
- /* Reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_CR_INIT;
-}
-
-/**
- * @brief Fills each HASH_InitStruct member with its default value.
- * @param HASH_InitStruct : pointer to a HASH_InitTypeDef structure which will
- * be initialized.
- * @note The default values set are : Processor mode is HASH, Algorithm selected is SHA1,
- * Data type selected is 32b and HMAC Key Type is short key.
- * @retval None
- */
-void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct)
-{
- /* Initialize the HASH_AlgoSelection member */
- HASH_InitStruct->HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
-
- /* Initialize the HASH_AlgoMode member */
- HASH_InitStruct->HASH_AlgoMode = HASH_AlgoMode_HASH;
-
- /* Initialize the HASH_DataType member */
- HASH_InitStruct->HASH_DataType = HASH_DataType_32b;
-
- /* Initialize the HASH_HMACKeyType member */
- HASH_InitStruct->HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
-}
-
-/**
- * @brief Resets the HASH processor core, so that the HASH will be ready
- * to compute the message digest of a new message.
- * @note Calling this function will clear the HASH_SR_DCIS (Digest calculation
- * completion interrupt status) bit corresponding to HASH_IT_DCI
- * interrupt and HASH_FLAG_DCIS flag.
- * @param None
- * @retval None
- */
-void HASH_Reset(void)
-{
- /* Reset the HASH processor core */
- HASH->CR |= HASH_CR_INIT;
-}
-/**
- * @}
- */
-
-/** @defgroup HASH_Group2 Message Digest generation functions
- * @brief Message Digest generation functions
- *
-@verbatim
- ===============================================================================
- ##### Message Digest generation functions #####
- ===============================================================================
- [..] This section provides functions allowing the generation of message digest:
- (+) Push data in the IN FIFO : using HASH_DataIn()
- (+) Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr()
- (+) set the last word valid bits number using HASH_SetLastWordValidBitsNbr()
- (+) start digest calculation : using HASH_StartDigest()
- (+) Get the Digest message : using HASH_GetDigest()
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Configure the Number of valid bits in last word of the message
- * @param ValidNumber: Number of valid bits in last word of the message.
- * This parameter must be a number between 0 and 0x1F.
- * - 0x00: All 32 bits of the last data written are valid
- * - 0x01: Only bit [0] of the last data written is valid
- * - 0x02: Only bits[1:0] of the last data written are valid
- * - 0x03: Only bits[2:0] of the last data written are valid
- * - ...
- * - 0x1F: Only bits[30:0] of the last data written are valid
- * @note The Number of valid bits must be set before to start the message
- * digest competition (in Hash and HMAC) and key treatment(in HMAC).
- * @retval None
- */
-void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber)
-{
- /* Check the parameters */
- assert_param(IS_HASH_VALIDBITSNUMBER(ValidNumber));
-
- /* Configure the Number of valid bits in last word of the message */
- HASH->STR &= ~(HASH_STR_NBW);
- HASH->STR |= ValidNumber;
-}
-
-/**
- * @brief Writes data in the Data Input FIFO
- * @param Data: new data of the message to be processed.
- * @retval None
- */
-void HASH_DataIn(uint32_t Data)
-{
- /* Write in the DIN register a new data */
- HASH->DIN = Data;
-}
-
-/**
- * @brief Returns the number of words already pushed into the IN FIFO.
- * @param None
- * @retval The value of words already pushed into the IN FIFO.
- */
-uint8_t HASH_GetInFIFOWordsNbr(void)
-{
- /* Return the value of NBW bits */
- return ((HASH->CR & HASH_CR_NBW) >> 8);
-}
-
-/**
- * @brief Provides the message digest result.
- * @note In MD5 mode, Data[7] to Data[4] filed of HASH_MsgDigest structure is not used
- * and is read as zero.
- * In SHA-1 mode, Data[7] to Data[5] filed of HASH_MsgDigest structure is not used
- * and is read as zero.
- * In SHA-224 mode, Data[7] filed of HASH_MsgDigest structure is not used
- * and is read as zero.
- * @param HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will
- * hold the message digest result
- * @retval None
- */
-void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest)
-{
- /* Get the data field */
- HASH_MessageDigest->Data[0] = HASH->HR[0];
- HASH_MessageDigest->Data[1] = HASH->HR[1];
- HASH_MessageDigest->Data[2] = HASH->HR[2];
- HASH_MessageDigest->Data[3] = HASH->HR[3];
- HASH_MessageDigest->Data[4] = HASH->HR[4];
- HASH_MessageDigest->Data[5] = HASH_DIGEST->HR[5];
- HASH_MessageDigest->Data[6] = HASH_DIGEST->HR[6];
- HASH_MessageDigest->Data[7] = HASH_DIGEST->HR[7];
-}
-
-/**
- * @brief Starts the message padding and calculation of the final message
- * @param None
- * @retval None
- */
-void HASH_StartDigest(void)
-{
- /* Start the Digest calculation */
- HASH->STR |= HASH_STR_DCAL;
-}
-/**
- * @}
- */
-
-/** @defgroup HASH_Group3 Context swapping functions
- * @brief Context swapping functions
- *
-@verbatim
- ===============================================================================
- ##### Context swapping functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to save and store HASH Context
-
- [..] It is possible to interrupt a HASH/HMAC process to perform another processing
- with a higher priority, and to complete the interrupted process later on, when
- the higher priority task is complete. To do so, the context of the interrupted
- task must be saved from the HASH registers to memory, and then be restored
- from memory to the HASH registers.
-
- (#) To save the current context, use HASH_SaveContext() function
- (#) To restore the saved context, use HASH_RestoreContext() function
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Save the Hash peripheral Context.
- * @note The context can be saved only when no block is currently being
- * processed. So user must wait for DINIS = 1 (the last block has been
- * processed and the input FIFO is empty) or NBW != 0 (the FIFO is not
- * full and no processing is ongoing).
- * @param HASH_ContextSave: pointer to a HASH_Context structure that contains
- * the repository for current context.
- * @retval None
- */
-void HASH_SaveContext(HASH_Context* HASH_ContextSave)
-{
- uint8_t i = 0;
-
- /* save context registers */
- HASH_ContextSave->HASH_IMR = HASH->IMR;
- HASH_ContextSave->HASH_STR = HASH->STR;
- HASH_ContextSave->HASH_CR = HASH->CR;
- for(i=0; i<=53;i++)
- {
- HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i];
- }
-}
-
-/**
- * @brief Restore the Hash peripheral Context.
- * @note After calling this function, user can restart the processing from the
- * point where it has been interrupted.
- * @param HASH_ContextRestore: pointer to a HASH_Context structure that contains
- * the repository for saved context.
- * @retval None
- */
-void HASH_RestoreContext(HASH_Context* HASH_ContextRestore)
-{
- uint8_t i = 0;
-
- /* restore context registers */
- HASH->IMR = HASH_ContextRestore->HASH_IMR;
- HASH->STR = HASH_ContextRestore->HASH_STR;
- HASH->CR = HASH_ContextRestore->HASH_CR;
-
- /* Initialize the hash processor */
- HASH->CR |= HASH_CR_INIT;
-
- /* continue restoring context registers */
- for(i=0; i<=53;i++)
- {
- HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i];
- }
-}
-/**
- * @}
- */
-
-/** @defgroup HASH_Group4 HASH's DMA interface Configuration function
- * @brief HASH's DMA interface Configuration function
- *
-@verbatim
- ===============================================================================
- ##### HASH's DMA interface Configuration function #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure the DMA interface for
- HASH/ HMAC data input transfer.
-
- [..] When the DMA mode is enabled (using the HASH_DMACmd() function), data can be
- sent to the IN FIFO using the DMA peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables auto-start message padding and
- * calculation of the final message digest at the end of DMA transfer.
- * @param NewState: new state of the selected HASH DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void HASH_AutoStartDigest(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the auto start of the final message digest at the end of DMA transfer */
- HASH->CR &= ~HASH_CR_MDMAT;
- }
- else
- {
- /* Disable the auto start of the final message digest at the end of DMA transfer */
- HASH->CR |= HASH_CR_MDMAT;
- }
-}
-
-/**
- * @brief Enables or disables the HASH DMA interface.
- * @note The DMA is disabled by hardware after the end of transfer.
- * @param NewState: new state of the selected HASH DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void HASH_DMACmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the HASH DMA request */
- HASH->CR |= HASH_CR_DMAE;
- }
- else
- {
- /* Disable the HASH DMA request */
- HASH->CR &= ~HASH_CR_DMAE;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup HASH_Group5 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure the HASH Interrupts and
- to get the status and clear flags and Interrupts pending bits.
-
- [..] The HASH provides 2 Interrupts sources and 5 Flags:
-
- *** Flags : ***
- ===============
- [..]
- (#) HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO
- which means that a new block (512 bit) can be entered into the input buffer.
-
- (#) HASH_FLAG_DCIS : set when Digest calculation is complete
-
- (#) HASH_FLAG_DMAS : set when HASH's DMA interface is enabled (DMAE=1) or
- a transfer is ongoing. This Flag is cleared only by hardware.
-
- (#) HASH_FLAG_BUSY : set when The hash core is processing a block of data
- This Flag is cleared only by hardware.
-
- (#) HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that
- the Data IN FIFO contains at least one word of data. This Flag is cleared
- only by hardware.
-
- *** Interrupts : ***
- ====================
- [..]
- (#) HASH_IT_DINI : if enabled, this interrupt source is pending when 16
- locations are free in the Data IN FIFO which means that a new block (512 bit)
- can be entered into the input buffer. This interrupt source is cleared using
- HASH_ClearITPendingBit(HASH_IT_DINI) function.
-
- (#) HASH_IT_DCI : if enabled, this interrupt source is pending when Digest
- calculation is complete. This interrupt source is cleared using
- HASH_ClearITPendingBit(HASH_IT_DCI) function.
-
- *** Managing the HASH controller events : ***
- =============================================
- [..] The user should identify which mode will be used in his application to manage
- the HASH controller events: Polling mode or Interrupt mode.
-
- (#) In the Polling Mode it is advised to use the following functions:
- (++) HASH_GetFlagStatus() : to check if flags events occur.
- (++) HASH_ClearFlag() : to clear the flags events.
-
- (#) In the Interrupt Mode it is advised to use the following functions:
- (++) HASH_ITConfig() : to enable or disable the interrupt source.
- (++) HASH_GetITStatus() : to check if Interrupt occurs.
- (++) HASH_ClearITPendingBit() : to clear the Interrupt pending Bit
- (corresponding Flag).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified HASH interrupts.
- * @param HASH_IT: specifies the HASH interrupt source to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg HASH_IT_DINI: Data Input interrupt
- * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
- * @param NewState: new state of the specified HASH interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_HASH_IT(HASH_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected HASH interrupt */
- HASH->IMR |= HASH_IT;
- }
- else
- {
- /* Disable the selected HASH interrupt */
- HASH->IMR &= (uint32_t)(~HASH_IT);
- }
-}
-
-/**
- * @brief Checks whether the specified HASH flag is set or not.
- * @param HASH_FLAG: specifies the HASH flag to check.
- * This parameter can be one of the following values:
- * @arg HASH_FLAG_DINIS: Data input interrupt status flag
- * @arg HASH_FLAG_DCIS: Digest calculation completion interrupt status flag
- * @arg HASH_FLAG_BUSY: Busy flag
- * @arg HASH_FLAG_DMAS: DMAS Status flag
- * @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag
- * @retval The new state of HASH_FLAG (SET or RESET)
- */
-FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t tempreg = 0;
-
- /* Check the parameters */
- assert_param(IS_HASH_GET_FLAG(HASH_FLAG));
-
- /* check if the FLAG is in CR register */
- if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint32_t)RESET )
- {
- tempreg = HASH->CR;
- }
- else /* The FLAG is in SR register */
- {
- tempreg = HASH->SR;
- }
-
- /* Check the status of the specified HASH flag */
- if ((tempreg & HASH_FLAG) != (uint32_t)RESET)
- {
- /* HASH is set */
- bitstatus = SET;
- }
- else
- {
- /* HASH_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the HASH_FLAG status */
- return bitstatus;
-}
-/**
- * @brief Clears the HASH flags.
- * @param HASH_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg HASH_FLAG_DINIS: Data Input Flag
- * @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag
- * @retval None
- */
-void HASH_ClearFlag(uint32_t HASH_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG));
-
- /* Clear the selected HASH flags */
- HASH->SR = ~(uint32_t)HASH_FLAG;
-}
-/**
- * @brief Checks whether the specified HASH interrupt has occurred or not.
- * @param HASH_IT: specifies the HASH interrupt source to check.
- * This parameter can be one of the following values:
- * @arg HASH_IT_DINI: Data Input interrupt
- * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
- * @retval The new state of HASH_IT (SET or RESET).
- */
-ITStatus HASH_GetITStatus(uint32_t HASH_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_HASH_GET_IT(HASH_IT));
-
-
- /* Check the status of the specified HASH interrupt */
- tmpreg = HASH->SR;
-
- if (((HASH->IMR & tmpreg) & HASH_IT) != RESET)
- {
- /* HASH_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* HASH_IT is reset */
- bitstatus = RESET;
- }
- /* Return the HASH_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the HASH interrupt pending bit(s).
- * @param HASH_IT: specifies the HASH interrupt pending bit(s) to clear.
- * This parameter can be any combination of the following values:
- * @arg HASH_IT_DINI: Data Input interrupt
- * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
- * @retval None
- */
-void HASH_ClearITPendingBit(uint32_t HASH_IT)
-{
- /* Check the parameters */
- assert_param(IS_HASH_IT(HASH_IT));
-
- /* Clear the selected HASH interrupt pending bit */
- HASH->SR = (uint32_t)(~HASH_IT);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_hash.h b/底盘/底盘-old/底盘/Library/stm32f4xx_hash.h
deleted file mode 100644
index 0e64831..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_hash.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_hash.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the HASH
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HASH_H
-#define __STM32F4xx_HASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup HASH
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief HASH Init structure definition
- */
-typedef struct
-{
- uint32_t HASH_AlgoSelection; /*!< SHA-1, SHA-224, SHA-256 or MD5. This parameter
- can be a value of @ref HASH_Algo_Selection */
- uint32_t HASH_AlgoMode; /*!< HASH or HMAC. This parameter can be a value
- of @ref HASH_processor_Algorithm_Mode */
- uint32_t HASH_DataType; /*!< 32-bit data, 16-bit data, 8-bit data or
- bit string. This parameter can be a value of
- @ref HASH_Data_Type */
- uint32_t HASH_HMACKeyType; /*!< HMAC Short key or HMAC Long Key. This parameter
- can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */
-}HASH_InitTypeDef;
-
-/**
- * @brief HASH message digest result structure definition
- */
-typedef struct
-{
- uint32_t Data[8]; /*!< Message digest result : 8x 32bit wors for SHA-256,
- 7x 32bit wors for SHA-224,
- 5x 32bit words for SHA-1 or
- 4x 32bit words for MD5 */
-} HASH_MsgDigest;
-
-/**
- * @brief HASH context swapping structure definition
- */
-typedef struct
-{
- uint32_t HASH_IMR;
- uint32_t HASH_STR;
- uint32_t HASH_CR;
- uint32_t HASH_CSR[54];
-}HASH_Context;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HASH_Exported_Constants
- * @{
- */
-
-/** @defgroup HASH_Algo_Selection
- * @{
- */
-#define HASH_AlgoSelection_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */
-#define HASH_AlgoSelection_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
-#define HASH_AlgoSelection_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
-#define HASH_AlgoSelection_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
-
-#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \
- ((ALGOSELECTION) == HASH_AlgoSelection_SHA224) || \
- ((ALGOSELECTION) == HASH_AlgoSelection_SHA256) || \
- ((ALGOSELECTION) == HASH_AlgoSelection_MD5))
-/**
- * @}
- */
-
-/** @defgroup HASH_processor_Algorithm_Mode
- * @{
- */
-#define HASH_AlgoMode_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */
-#define HASH_AlgoMode_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
-
-#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \
- ((ALGOMODE) == HASH_AlgoMode_HMAC))
-/**
- * @}
- */
-
-/** @defgroup HASH_Data_Type
- * @{
- */
-#define HASH_DataType_32b ((uint32_t)0x0000) /*!< 32-bit data. No swapping */
-#define HASH_DataType_16b HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
-#define HASH_DataType_8b HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
-#define HASH_DataType_1b HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
-
-#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \
- ((DATATYPE) == HASH_DataType_16b)|| \
- ((DATATYPE) == HASH_DataType_8b) || \
- ((DATATYPE) == HASH_DataType_1b))
-/**
- * @}
- */
-
-/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode
- * @{
- */
-#define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */
-#define HASH_HMACKeyType_LongKey HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */
-
-#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \
- ((KEYTYPE) == HASH_HMACKeyType_LongKey))
-/**
- * @}
- */
-
-/** @defgroup Number_of_valid_bits_in_last_word_of_the_message
- * @{
- */
-#define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F)
-
-/**
- * @}
- */
-
-/** @defgroup HASH_interrupts_definition
- * @{
- */
-#define HASH_IT_DINI HASH_IMR_DINIM /*!< A new block can be entered into the input buffer (DIN) */
-#define HASH_IT_DCI HASH_IMR_DCIM /*!< Digest calculation complete */
-
-#define IS_HASH_IT(IT) ((((IT) & (uint32_t)0xFFFFFFFC) == 0x00000000) && ((IT) != 0x00000000))
-#define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI))
-
-/**
- * @}
- */
-
-/** @defgroup HASH_flags_definition
- * @{
- */
-#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
-#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
-#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
-#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy : processing a block of data */
-#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */
-
-#define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \
- ((FLAG) == HASH_FLAG_DCIS) || \
- ((FLAG) == HASH_FLAG_DMAS) || \
- ((FLAG) == HASH_FLAG_BUSY) || \
- ((FLAG) == HASH_FLAG_DINNE))
-
-#define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \
- ((FLAG) == HASH_FLAG_DCIS))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the HASH configuration to the default reset state ****/
-void HASH_DeInit(void);
-
-/* HASH Configuration function ************************************************/
-void HASH_Init(HASH_InitTypeDef* HASH_InitStruct);
-void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct);
-void HASH_Reset(void);
-
-/* HASH Message Digest generation functions ***********************************/
-void HASH_DataIn(uint32_t Data);
-uint8_t HASH_GetInFIFOWordsNbr(void);
-void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber);
-void HASH_StartDigest(void);
-void HASH_AutoStartDigest(FunctionalState NewState);
-void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest);
-
-/* HASH Context swapping functions ********************************************/
-void HASH_SaveContext(HASH_Context* HASH_ContextSave);
-void HASH_RestoreContext(HASH_Context* HASH_ContextRestore);
-
-/* HASH DMA interface function ************************************************/
-void HASH_DMACmd(FunctionalState NewState);
-
-/* HASH Interrupts and flags management functions *****************************/
-void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState);
-FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG);
-void HASH_ClearFlag(uint32_t HASH_FLAG);
-ITStatus HASH_GetITStatus(uint32_t HASH_IT);
-void HASH_ClearITPendingBit(uint32_t HASH_IT);
-
-/* High Level SHA1 functions **************************************************/
-ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]);
-ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen,
- uint8_t *Input, uint32_t Ilen,
- uint8_t Output[20]);
-
-/* High Level MD5 functions ***************************************************/
-ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]);
-ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen,
- uint8_t *Input, uint32_t Ilen,
- uint8_t Output[16]);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_HASH_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_hash_md5.c b/底盘/底盘-old/底盘/Library/stm32f4xx_hash_md5.c
deleted file mode 100644
index 727b81a..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_hash_md5.c
+++ /dev/null
@@ -1,312 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_hash_md5.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides high level functions to compute the HASH MD5 and
- * HMAC MD5 Digest of an input message.
- * It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH
- * peripheral.
- *
-@verbatim
- ===================================================================
- ##### How to use this driver #####
- ===================================================================
- [..]
- (#) Enable The HASH controller clock using
- RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function.
-
- (#) Calculate the HASH MD5 Digest using HASH_MD5() function.
-
- (#) Calculate the HMAC MD5 Digest using HMAC_MD5() function.
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hash.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup HASH
- * @brief HASH driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define MD5BUSY_TIMEOUT ((uint32_t) 0x00010000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup HASH_Private_Functions
- * @{
- */
-
-/** @defgroup HASH_Group7 High Level MD5 functions
- * @brief High Level MD5 Hash and HMAC functions
- *
-@verbatim
- ===============================================================================
- ##### High Level MD5 Hash and HMAC functions #####
- ===============================================================================
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Compute the HASH MD5 digest.
- * @param Input: pointer to the Input buffer to be treated.
- * @param Ilen: length of the Input buffer.
- * @param Output: the returned digest
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: digest computation done
- * - ERROR: digest computation failed
- */
-ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16])
-{
- HASH_InitTypeDef MD5_HASH_InitStructure;
- HASH_MsgDigest MD5_MessageDigest;
- __IO uint16_t nbvalidbitsdata = 0;
- uint32_t i = 0;
- __IO uint32_t counter = 0;
- uint32_t busystatus = 0;
- ErrorStatus status = SUCCESS;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
-
-
- /* Number of valid bits in last word of the Input data */
- nbvalidbitsdata = 8 * (Ilen % 4);
-
- /* HASH peripheral initialization */
- HASH_DeInit();
-
- /* HASH Configuration */
- MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5;
- MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH;
- MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
- HASH_Init(&MD5_HASH_InitStructure);
-
- /* Configure the number of valid bits in last word of the data */
- HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
-
- /* Write the Input block in the IN FIFO */
- for(i=0; i 64)
- {
- /* HMAC long Key */
- MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey;
- }
- else
- {
- /* HMAC short Key */
- MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
- }
- HASH_Init(&MD5_HASH_InitStructure);
-
- /* Configure the number of valid bits in last word of the Key */
- HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
-
- /* Write the Key */
- for(i=0; i 64)
- {
- /* HMAC long Key */
- SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey;
- }
- else
- {
- /* HMAC short Key */
- SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
- }
- HASH_Init(&SHA1_HASH_InitStructure);
-
- /* Configure the number of valid bits in last word of the Key */
- HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
-
- /* Write the Key */
- for(i=0; iGPIO_Mode = GPIO_Mode_AF
- (++) Select the type, pull-up/pull-down and output speed via
- GPIO_PuPd, GPIO_OType and GPIO_Speed members
- (++) Call GPIO_Init() function
- Recommended configuration is Push-Pull, Pull-up, Open-Drain.
- Add an external pull up if necessary (typically 4.7 KOhm).
-
- (#) Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged
- Address using the I2C_Init() function.
-
- (#) Optionally you can enable/configure the following parameters without
- re-initialization (i.e there is no need to call again I2C_Init() function):
- (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function
- (++) Enable the dual addressing mode using I2C_DualAddressCmd() function
- (++) Enable the general call using the I2C_GeneralCallCmd() function
- (++) Enable the clock stretching using I2C_StretchClockCmd() function
- (++) Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig()
- function.
- (++) Configure the NACK position for Master Receiver mode in case of
- 2 bytes reception using the function I2C_NACKPositionConfig().
- (++) Enable the PEC Calculation using I2C_CalculatePEC() function
- (++) For SMBus Mode:
- (+++) Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function
- (+++) Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function
-
- (#) Enable the NVIC and the corresponding interrupt using the function
- I2C_ITConfig() if you need to use interrupt mode.
-
- (#) When using the DMA mode
- (++) Configure the DMA using DMA_Init() function
- (++) Active the needed channel Request using I2C_DMACmd() or
- I2C_DMALastTransferCmd() function.
- -@@- When using DMA mode, I2C interrupts may be used at the same time to
- control the communication flow (Start/Stop/Ack... events and errors).
-
- (#) Enable the I2C using the I2C_Cmd() function.
-
- (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the
- transfers.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_i2c.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup I2C
- * @brief I2C driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-#define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*I2C_ClockSpeed));
- assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
- assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
- assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
- assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
- assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
-
-/*---------------------------- I2Cx CR2 Configuration ------------------------*/
- /* Get the I2Cx CR2 value */
- tmpreg = I2Cx->CR2;
- /* Clear frequency FREQ[5:0] bits */
- tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ);
- /* Get pclk1 frequency value */
- RCC_GetClocksFreq(&rcc_clocks);
- pclk1 = rcc_clocks.PCLK1_Frequency;
- /* Set frequency bits depending on pclk1 value */
- freqrange = (uint16_t)(pclk1 / 1000000);
- tmpreg |= freqrange;
- /* Write to I2Cx CR2 */
- I2Cx->CR2 = tmpreg;
-
-/*---------------------------- I2Cx CCR Configuration ------------------------*/
- /* Disable the selected I2C peripheral to configure TRISE */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);
- /* Reset tmpreg value */
- /* Clear F/S, DUTY and CCR[11:0] bits */
- tmpreg = 0;
-
- /* Configure speed in standard mode */
- if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
- {
- /* Standard mode speed calculate */
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
- /* Test if CCR value is under 0x4*/
- if (result < 0x04)
- {
- /* Set minimum allowed value */
- result = 0x04;
- }
- /* Set speed value for standard mode */
- tmpreg |= result;
- /* Set Maximum Rise Time for standard mode */
- I2Cx->TRISE = freqrange + 1;
- }
- /* Configure speed in fast mode */
- /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral
- input clock) must be a multiple of 10 MHz */
- else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
- {
- if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
- {
- /* Fast mode speed calculate: Tlow/Thigh = 2 */
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
- }
- else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
- {
- /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
- /* Set DUTY bit */
- result |= I2C_DutyCycle_16_9;
- }
-
- /* Test if CCR value is under 0x1*/
- if ((result & I2C_CCR_CCR) == 0)
- {
- /* Set minimum allowed value */
- result |= (uint16_t)0x0001;
- }
- /* Set speed value and set F/S bit for fast mode */
- tmpreg |= (uint16_t)(result | I2C_CCR_FS);
- /* Set Maximum Rise Time for fast mode */
- I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
- }
-
- /* Write to I2Cx CCR */
- I2Cx->CCR = tmpreg;
- /* Enable the selected I2C peripheral */
- I2Cx->CR1 |= I2C_CR1_PE;
-
-/*---------------------------- I2Cx CR1 Configuration ------------------------*/
- /* Get the I2Cx CR1 value */
- tmpreg = I2Cx->CR1;
- /* Clear ACK, SMBTYPE and SMBUS bits */
- tmpreg &= CR1_CLEAR_MASK;
- /* Configure I2Cx: mode and acknowledgement */
- /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
- /* Set ACK bit according to I2C_Ack value */
- tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
- /* Write to I2Cx CR1 */
- I2Cx->CR1 = tmpreg;
-
-/*---------------------------- I2Cx OAR1 Configuration -----------------------*/
- /* Set I2Cx Own Address1 and acknowledged address */
- I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
-}
-
-/**
- * @brief Fills each I2C_InitStruct member with its default value.
- * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
-{
-/*---------------- Reset I2C init structure parameters values ----------------*/
- /* initialize the I2C_ClockSpeed member */
- I2C_InitStruct->I2C_ClockSpeed = 5000;
- /* Initialize the I2C_Mode member */
- I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
- /* Initialize the I2C_DutyCycle member */
- I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
- /* Initialize the I2C_OwnAddress1 member */
- I2C_InitStruct->I2C_OwnAddress1 = 0;
- /* Initialize the I2C_Ack member */
- I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
- /* Initialize the I2C_AcknowledgedAddress member */
- I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
-}
-
-/**
- * @brief Enables or disables the specified I2C peripheral.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C peripheral */
- I2Cx->CR1 |= I2C_CR1_PE;
- }
- else
- {
- /* Disable the selected I2C peripheral */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);
- }
-}
-
-/**
- * @brief Enables or disables the Analog filter of I2C peripheral.
- *
- * @note This function can be used only for STM32F42xxx/STM3243xxx, STM32F401xx, STM32F410xx and STM32F411xE devices.
- *
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the Analog filter.
- * This parameter can be: ENABLE or DISABLE.
- * @note This function should be called before initializing and enabling
- the I2C Peripheral.
- * @retval None
- */
-void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the analog filter */
- I2Cx->FLTR &= (uint16_t)~((uint16_t)I2C_FLTR_ANOFF);
- }
- else
- {
- /* Disable the analog filter */
- I2Cx->FLTR |= I2C_FLTR_ANOFF;
- }
-}
-
-/**
- * @brief Configures the Digital noise filter of I2C peripheral.
- *
- * @note This function can be used only for STM32F42xxx/STM3243xxx, STM32F401xx, STM32F410xx and STM32F411xE devices.
- *
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_DigitalFilter: Coefficient of digital noise filter.
- * This parameter can be a number between 0x00 and 0x0F.
- * @note This function should be called before initializing and enabling
- the I2C Peripheral.
- * @retval None
- */
-void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter)
-{
- uint16_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_DIGITAL_FILTER(I2C_DigitalFilter));
-
- /* Get the old register value */
- tmpreg = I2Cx->FLTR;
-
- /* Reset I2Cx DNF bit [3:0] */
- tmpreg &= (uint16_t)~((uint16_t)I2C_FLTR_DNF);
-
- /* Set I2Cx DNF coefficient */
- tmpreg |= (uint16_t)((uint16_t)I2C_DigitalFilter & I2C_FLTR_DNF);
-
- /* Store the new register value */
- I2Cx->FLTR = tmpreg;
-}
-
-/**
- * @brief Generates I2Cx communication START condition.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C START condition generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Generate a START condition */
- I2Cx->CR1 |= I2C_CR1_START;
- }
- else
- {
- /* Disable the START condition generation */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START);
- }
-}
-
-/**
- * @brief Generates I2Cx communication STOP condition.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C STOP condition generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Generate a STOP condition */
- I2Cx->CR1 |= I2C_CR1_STOP;
- }
- else
- {
- /* Disable the STOP condition generation */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP);
- }
-}
-
-/**
- * @brief Transmits the address byte to select the slave device.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param Address: specifies the slave address which will be transmitted
- * @param I2C_Direction: specifies whether the I2C device will be a Transmitter
- * or a Receiver.
- * This parameter can be one of the following values
- * @arg I2C_Direction_Transmitter: Transmitter mode
- * @arg I2C_Direction_Receiver: Receiver mode
- * @retval None.
- */
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_DIRECTION(I2C_Direction));
- /* Test on the direction to set/reset the read/write bit */
- if (I2C_Direction != I2C_Direction_Transmitter)
- {
- /* Set the address bit0 for read */
- Address |= I2C_OAR1_ADD0;
- }
- else
- {
- /* Reset the address bit0 for write */
- Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0);
- }
- /* Send the address */
- I2Cx->DR = Address;
-}
-
-/**
- * @brief Enables or disables the specified I2C acknowledge feature.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C Acknowledgement.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the acknowledgement */
- I2Cx->CR1 |= I2C_CR1_ACK;
- }
- else
- {
- /* Disable the acknowledgement */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK);
- }
-}
-
-/**
- * @brief Configures the specified I2C own address2.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param Address: specifies the 7bit I2C own address2.
- * @retval None.
- */
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
-{
- uint16_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Get the old register value */
- tmpreg = I2Cx->OAR2;
-
- /* Reset I2Cx Own address2 bit [7:1] */
- tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2);
-
- /* Set I2Cx Own address2 */
- tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
-
- /* Store the new register value */
- I2Cx->OAR2 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the specified I2C dual addressing mode.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C dual addressing mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable dual addressing mode */
- I2Cx->OAR2 |= I2C_OAR2_ENDUAL;
- }
- else
- {
- /* Disable dual addressing mode */
- I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL);
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C general call feature.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C General call.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable general call */
- I2Cx->CR1 |= I2C_CR1_ENGC;
- }
- else
- {
- /* Disable general call */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC);
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C software reset.
- * @note When software reset is enabled, the I2C IOs are released (this can
- * be useful to recover from bus errors).
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C software reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Peripheral under reset */
- I2Cx->CR1 |= I2C_CR1_SWRST;
- }
- else
- {
- /* Peripheral not under reset */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST);
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C Clock stretching.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx Clock stretching.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState == DISABLE)
- {
- /* Enable the selected I2C Clock stretching */
- I2Cx->CR1 |= I2C_CR1_NOSTRETCH;
- }
- else
- {
- /* Disable the selected I2C Clock stretching */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH);
- }
-}
-
-/**
- * @brief Selects the specified I2C fast mode duty cycle.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_DutyCycle: specifies the fast mode duty cycle.
- * This parameter can be one of the following values:
- * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
- * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
- * @retval None
- */
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
- if (I2C_DutyCycle != I2C_DutyCycle_16_9)
- {
- /* I2C fast mode Tlow/Thigh=2 */
- I2Cx->CCR &= I2C_DutyCycle_2;
- }
- else
- {
- /* I2C fast mode Tlow/Thigh=16/9 */
- I2Cx->CCR |= I2C_DutyCycle_16_9;
- }
-}
-
-/**
- * @brief Selects the specified I2C NACK position in master receiver mode.
- * @note This function is useful in I2C Master Receiver mode when the number
- * of data to be received is equal to 2. In this case, this function
- * should be called (with parameter I2C_NACKPosition_Next) before data
- * reception starts,as described in the 2-byte reception procedure
- * recommended in Reference Manual in Section: Master receiver.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_NACKPosition: specifies the NACK position.
- * This parameter can be one of the following values:
- * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last
- * received byte.
- * @arg I2C_NACKPosition_Current: indicates that current byte is the last
- * received byte.
- *
- * @note This function configures the same bit (POS) as I2C_PECPositionConfig()
- * but is intended to be used in I2C mode while I2C_PECPositionConfig()
- * is intended to used in SMBUS mode.
- *
- * @retval None
- */
-void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition));
-
- /* Check the input parameter */
- if (I2C_NACKPosition == I2C_NACKPosition_Next)
- {
- /* Next byte in shift register is the last received byte */
- I2Cx->CR1 |= I2C_NACKPosition_Next;
- }
- else
- {
- /* Current byte in shift register is the last received byte */
- I2Cx->CR1 &= I2C_NACKPosition_Current;
- }
-}
-
-/**
- * @brief Drives the SMBusAlert pin high or low for the specified I2C.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_SMBusAlert: specifies SMBAlert pin level.
- * This parameter can be one of the following values:
- * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
- * @arg I2C_SMBusAlert_High: SMBAlert pin driven high
- * @retval None
- */
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
- if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
- {
- /* Drive the SMBusAlert pin Low */
- I2Cx->CR1 |= I2C_SMBusAlert_Low;
- }
- else
- {
- /* Drive the SMBusAlert pin High */
- I2Cx->CR1 &= I2C_SMBusAlert_High;
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C ARP.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx ARP.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C ARP */
- I2Cx->CR1 |= I2C_CR1_ENARP;
- }
- else
- {
- /* Disable the selected I2C ARP */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP);
- }
-}
-/**
- * @}
- */
-
-/** @defgroup I2C_Group2 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sends a data byte through the I2Cx peripheral.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param Data: Byte to be transmitted..
- * @retval None
- */
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- /* Write in the DR register the data to be sent */
- I2Cx->DR = Data;
-}
-
-/**
- * @brief Returns the most recent received data by the I2Cx peripheral.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @retval The value of the received data.
- */
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- /* Return the data in the DR register */
- return (uint8_t)I2Cx->DR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Group3 PEC management functions
- * @brief PEC management functions
- *
-@verbatim
- ===============================================================================
- ##### PEC management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified I2C PEC transfer.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C PEC transmission.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C PEC transmission */
- I2Cx->CR1 |= I2C_CR1_PEC;
- }
- else
- {
- /* Disable the selected I2C PEC transmission */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC);
- }
-}
-
-/**
- * @brief Selects the specified I2C PEC position.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_PECPosition: specifies the PEC position.
- * This parameter can be one of the following values:
- * @arg I2C_PECPosition_Next: indicates that the next byte is PEC
- * @arg I2C_PECPosition_Current: indicates that current byte is PEC
- *
- * @note This function configures the same bit (POS) as I2C_NACKPositionConfig()
- * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig()
- * is intended to used in I2C mode.
- *
- * @retval None
- */
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
- if (I2C_PECPosition == I2C_PECPosition_Next)
- {
- /* Next byte in shift register is PEC */
- I2Cx->CR1 |= I2C_PECPosition_Next;
- }
- else
- {
- /* Current byte in shift register is PEC */
- I2Cx->CR1 &= I2C_PECPosition_Current;
- }
-}
-
-/**
- * @brief Enables or disables the PEC value calculation of the transferred bytes.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx PEC value calculation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C PEC calculation */
- I2Cx->CR1 |= I2C_CR1_ENPEC;
- }
- else
- {
- /* Disable the selected I2C PEC calculation */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC);
- }
-}
-
-/**
- * @brief Returns the PEC value for the specified I2C.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @retval The PEC value.
- */
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- /* Return the selected I2C PEC value */
- return ((I2Cx->SR2) >> 8);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Group4 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
- This section provides functions allowing to configure the I2C DMA channels
- requests.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified I2C DMA requests.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C DMA transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C DMA requests */
- I2Cx->CR2 |= I2C_CR2_DMAEN;
- }
- else
- {
- /* Disable the selected I2C DMA requests */
- I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN);
- }
-}
-
-/**
- * @brief Specifies that the next DMA transfer is the last one.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C DMA last transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Next DMA transfer is the last transfer */
- I2Cx->CR2 |= I2C_CR2_LAST;
- }
- else
- {
- /* Next DMA transfer is not the last transfer */
- I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Group5 Interrupts events and flags management functions
- * @brief Interrupts, events and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts, events and flags management functions #####
- ===============================================================================
- [..]
- This section provides functions allowing to configure the I2C Interrupts
- sources and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to manage
- the communication: Polling mode, Interrupt mode or DMA mode.
-
-
- ##### I2C State Monitoring Functions #####
- ===============================================================================
- [..]
- This I2C driver provides three different ways for I2C state monitoring
- depending on the application requirements and constraints:
-
-
- (#) Basic state monitoring (Using I2C_CheckEvent() function)
-
- It compares the status registers (SR1 and SR2) content to a given event
- (can be the combination of one or more flags).
- It returns SUCCESS if the current status includes the given flags
- and returns ERROR if one or more flags are missing in the current status.
-
- (++) When to use
- (+++) This function is suitable for most applications as well as for startup
- activity since the events are fully described in the product reference
- manual (RM0090).
- (+++) It is also suitable for users who need to define their own events.
-
- (++) Limitations
- If an error occurs (ie. error flags are set besides to the monitored
- flags), the I2C_CheckEvent() function may return SUCCESS despite
- the communication hold or corrupted real state.
- In this case, it is advised to use error interrupts to monitor
- the error events and handle them in the interrupt IRQ handler.
-
- -@@- For error management, it is advised to use the following functions:
- (+@@) I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
- (+@@) I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
- Where x is the peripheral instance (I2C1, I2C2 ...)
- (+@@) I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
- I2Cx_ER_IRQHandler() function in order to determine which error occurred.
- (+@@) I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
- and/or I2C_GenerateStop() in order to clear the error flag and source
- and return to correct communication status.
-
-
- (#) Advanced state monitoring (Using the function I2C_GetLastEvent())
-
- Using the function I2C_GetLastEvent() which returns the image of both status
- registers in a single word (uint32_t) (Status Register 2 value is shifted left
- by 16 bits and concatenated to Status Register 1).
-
- (++) When to use
- (+++) This function is suitable for the same applications above but it
- allows to overcome the mentioned limitation of I2C_GetFlagStatus()
- function.
- (+++) The returned value could be compared to events already defined in
- the library (stm32f4xx_i2c.h) or to custom values defined by user.
- This function is suitable when multiple flags are monitored at the
- same time.
- (+++) At the opposite of I2C_CheckEvent() function, this function allows
- user to choose when an event is accepted (when all events flags are
- set and no other flags are set or just when the needed flags are set
- like I2C_CheckEvent() function.
-
- (++) Limitations
- (+++) User may need to define his own events.
- (+++) Same remark concerning the error management is applicable for this
- function if user decides to check only regular communication flags
- (and ignores error flags).
-
-
- (#) Flag-based state monitoring (Using the function I2C_GetFlagStatus())
-
- Using the function I2C_GetFlagStatus() which simply returns the status of
- one single flag (ie. I2C_FLAG_RXNE ...).
-
- (++) When to use
- (+++) This function could be used for specific applications or in debug
- phase.
- (+++) It is suitable when only one flag checking is needed (most I2C
- events are monitored through multiple flags).
- (++) Limitations:
- (+++) When calling this function, the Status register is accessed.
- Some flags are cleared when the status register is accessed.
- So checking the status of one Flag, may clear other ones.
- (+++) Function may need to be called twice or more in order to monitor
- one single event.
-
- For detailed description of Events, please refer to section I2C_Events in
- stm32f4xx_i2c.h file.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads the specified I2C register and returns its value.
- * @param I2C_Register: specifies the register to read.
- * This parameter can be one of the following values:
- * @arg I2C_Register_CR1: CR1 register.
- * @arg I2C_Register_CR2: CR2 register.
- * @arg I2C_Register_OAR1: OAR1 register.
- * @arg I2C_Register_OAR2: OAR2 register.
- * @arg I2C_Register_DR: DR register.
- * @arg I2C_Register_SR1: SR1 register.
- * @arg I2C_Register_SR2: SR2 register.
- * @arg I2C_Register_CCR: CCR register.
- * @arg I2C_Register_TRISE: TRISE register.
- * @retval The value of the read register.
- */
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_REGISTER(I2C_Register));
-
- tmp = (uint32_t) I2Cx;
- tmp += I2C_Register;
-
- /* Return the selected register value */
- return (*(__IO uint16_t *) tmp);
-}
-
-/**
- * @brief Enables or disables the specified I2C interrupts.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg I2C_IT_BUF: Buffer interrupt mask
- * @arg I2C_IT_EVT: Event interrupt mask
- * @arg I2C_IT_ERR: Error interrupt mask
- * @param NewState: new state of the specified I2C interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_I2C_CONFIG_IT(I2C_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C interrupts */
- I2Cx->CR2 |= I2C_IT;
- }
- else
- {
- /* Disable the selected I2C interrupts */
- I2Cx->CR2 &= (uint16_t)~I2C_IT;
- }
-}
-
-/*
- ===============================================================================
- 1. Basic state monitoring
- ===============================================================================
- */
-
-/**
- * @brief Checks whether the last I2Cx Event is equal to the one passed
- * as parameter.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_EVENT: specifies the event to be checked.
- * This parameter can be one of the following values:
- * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1
- * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1
- * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1
- * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1
- * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1
- * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2
- * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2
- * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2
- * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3
- * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3
- * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3
- * @arg I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2
- * @arg I2C_EVENT_SLAVE_STOP_DETECTED: EV4
- * @arg I2C_EVENT_MASTER_MODE_SELECT: EV5
- * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6
- * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6
- * @arg I2C_EVENT_MASTER_BYTE_RECEIVED: EV7
- * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8
- * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2
- * @arg I2C_EVENT_MASTER_MODE_ADDRESS10: EV9
- *
- * @note For detailed description of Events, please refer to section I2C_Events
- * in stm32f4xx_i2c.h file.
- *
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Last event is equal to the I2C_EVENT
- * - ERROR: Last event is different from the I2C_EVENT
- */
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
-{
- uint32_t lastevent = 0;
- uint32_t flag1 = 0, flag2 = 0;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_EVENT(I2C_EVENT));
-
- /* Read the I2Cx status register */
- flag1 = I2Cx->SR1;
-
- /* I2C_SR2 must be read only when ADDR is found set in I2C_SR1 or when the STOPF bit is cleared */
- if((flag1 & I2C_SR1_ADDR) || (flag1 & ~I2C_SR1_STOPF))
- {
- flag2 = I2Cx->SR2;
- }
- else
- {
- return ERROR;
- }
- flag2 = flag2 << 16;
-
- /* Get the last event value from I2C status register */
- lastevent = (flag1 | flag2) & FLAG_MASK;
-
- /* Check whether the last event contains the I2C_EVENT */
- if ((lastevent & I2C_EVENT) == I2C_EVENT)
- {
- /* SUCCESS: last event is equal to I2C_EVENT */
- status = SUCCESS;
- }
- else
- {
- /* ERROR: last event is different from I2C_EVENT */
- status = ERROR;
- }
- /* Return status */
- return status;
-}
-
-/*
- ===============================================================================
- 2. Advanced state monitoring
- ===============================================================================
- */
-
-/**
- * @brief Returns the last I2Cx Event.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- *
- * @note For detailed description of Events, please refer to section I2C_Events
- * in stm32f4xx_i2c.h file.
- *
- * @retval The last event
- */
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
-{
- uint32_t lastevent = 0;
- uint32_t flag1 = 0, flag2 = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Read the I2Cx status register */
- flag1 = I2Cx->SR1;
- flag2 = I2Cx->SR2;
- flag2 = flag2 << 16;
-
- /* Get the last event value from I2C status register */
- lastevent = (flag1 | flag2) & FLAG_MASK;
-
- /* Return status */
- return lastevent;
-}
-
-/*
- ===============================================================================
- 3. Flag-based state monitoring
- ===============================================================================
- */
-
-/**
- * @brief Checks whether the specified I2C flag is set or not.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
- * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
- * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
- * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
- * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
- * @arg I2C_FLAG_BUSY: Bus busy flag
- * @arg I2C_FLAG_MSL: Master/Slave flag
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
- * @arg I2C_FLAG_PECERR: PEC error in reception flag
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
- * @arg I2C_FLAG_AF: Acknowledge failure flag
- * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
- * @arg I2C_FLAG_BERR: Bus error flag
- * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
- * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
- * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
- * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
- * @arg I2C_FLAG_BTF: Byte transfer finished flag
- * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL"
- * Address matched flag (Slave mode)"ENDAD"
- * @arg I2C_FLAG_SB: Start bit flag (Master mode)
- * @retval The new state of I2C_FLAG (SET or RESET).
- */
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
- FlagStatus bitstatus = RESET;
- __IO uint32_t i2creg = 0, i2cxbase = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
-
- /* Get the I2Cx peripheral base address */
- i2cxbase = (uint32_t)I2Cx;
-
- /* Read flag register index */
- i2creg = I2C_FLAG >> 28;
-
- /* Get bit[23:0] of the flag */
- I2C_FLAG &= FLAG_MASK;
-
- if(i2creg != 0)
- {
- /* Get the I2Cx SR1 register address */
- i2cxbase += 0x14;
- }
- else
- {
- /* Flag in I2Cx SR2 Register */
- I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
- /* Get the I2Cx SR2 register address */
- i2cxbase += 0x18;
- }
-
- if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
- {
- /* I2C_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* I2C_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the I2C_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the I2Cx's pending flags.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
- * @arg I2C_FLAG_PECERR: PEC error in reception flag
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
- * @arg I2C_FLAG_AF: Acknowledge failure flag
- * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
- * @arg I2C_FLAG_BERR: Bus error flag
- *
- * @note STOPF (STOP detection) is cleared by software sequence: a read operation
- * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation
- * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
- * @note ADD10 (10-bit header sent) is cleared by software sequence: a read
- * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the
- * second byte of the address in DR register.
- * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read
- * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a
- * read/write to I2C_DR register (I2C_SendData()).
- * @note ADDR (Address sent) is cleared by software sequence: a read operation to
- * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to
- * I2C_SR2 register ((void)(I2Cx->SR2)).
- * @note SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
- * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
- * register (I2C_SendData()).
- *
- * @retval None
- */
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
- uint32_t flagpos = 0;
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
- /* Get the I2C flag position */
- flagpos = I2C_FLAG & FLAG_MASK;
- /* Clear the selected I2C flag */
- I2Cx->SR1 = (uint16_t)~flagpos;
-}
-
-/**
- * @brief Checks whether the specified I2C interrupt has occurred or not.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_IT: specifies the interrupt source to check.
- * This parameter can be one of the following values:
- * @arg I2C_IT_SMBALERT: SMBus Alert flag
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag
- * @arg I2C_IT_PECERR: PEC error in reception flag
- * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
- * @arg I2C_IT_AF: Acknowledge failure flag
- * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
- * @arg I2C_IT_BERR: Bus error flag
- * @arg I2C_IT_TXE: Data register empty flag (Transmitter)
- * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
- * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
- * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
- * @arg I2C_IT_BTF: Byte transfer finished flag
- * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL"
- * Address matched flag (Slave mode)"ENDAD"
- * @arg I2C_IT_SB: Start bit flag (Master mode)
- * @retval The new state of I2C_IT (SET or RESET).
- */
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_GET_IT(I2C_IT));
-
- /* Check if the interrupt source is enabled or not */
- enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ;
-
- /* Get bit[23:0] of the flag */
- I2C_IT &= FLAG_MASK;
-
- /* Check the status of the specified I2C flag */
- if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
- {
- /* I2C_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* I2C_IT is reset */
- bitstatus = RESET;
- }
- /* Return the I2C_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the I2Cx's interrupt pending bits.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg I2C_IT_SMBALERT: SMBus Alert interrupt
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
- * @arg I2C_IT_PECERR: PEC error in reception interrupt
- * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
- * @arg I2C_IT_AF: Acknowledge failure interrupt
- * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
- * @arg I2C_IT_BERR: Bus error interrupt
- *
- * @note STOPF (STOP detection) is cleared by software sequence: a read operation
- * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
- * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
- * @note ADD10 (10-bit header sent) is cleared by software sequence: a read
- * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second
- * byte of the address in I2C_DR register.
- * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read
- * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a
- * read/write to I2C_DR register (I2C_SendData()).
- * @note ADDR (Address sent) is cleared by software sequence: a read operation to
- * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to
- * I2C_SR2 register ((void)(I2Cx->SR2)).
- * @note SB (Start Bit) is cleared by software sequence: a read operation to
- * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
- * I2C_DR register (I2C_SendData()).
- * @retval None
- */
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
- uint32_t flagpos = 0;
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLEAR_IT(I2C_IT));
-
- /* Get the I2C flag position */
- flagpos = I2C_IT & FLAG_MASK;
-
- /* Clear the selected I2C flag */
- I2Cx->SR1 = (uint16_t)~flagpos;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_i2c.h b/底盘/底盘-old/底盘/Library/stm32f4xx_i2c.h
deleted file mode 100644
index 7ee4de1..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_i2c.h
+++ /dev/null
@@ -1,701 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_i2c.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the I2C firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_I2C_H
-#define __STM32F4xx_I2C_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup I2C
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief I2C Init structure definition
- */
-
-typedef struct
-{
- uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
- This parameter must be set to a value lower than 400kHz */
-
- uint16_t I2C_Mode; /*!< Specifies the I2C mode.
- This parameter can be a value of @ref I2C_mode */
-
- uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
- This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
-
- uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
- This parameter can be a 7-bit or 10-bit address. */
-
- uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
- This parameter can be a value of @ref I2C_acknowledgement */
-
- uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
- This parameter can be a value of @ref I2C_acknowledged_address */
-}I2C_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-
-/** @defgroup I2C_Exported_Constants
- * @{
- */
-#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
- ((PERIPH) == I2C2) || \
- ((PERIPH) == I2C3))
-/** @defgroup I2C_Digital_Filter
- * @{
- */
-
-#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
-/**
- * @}
- */
-
-
-/** @defgroup I2C_mode
- * @{
- */
-
-#define I2C_Mode_I2C ((uint16_t)0x0000)
-#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
-#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
-#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
- ((MODE) == I2C_Mode_SMBusDevice) || \
- ((MODE) == I2C_Mode_SMBusHost))
-/**
- * @}
- */
-
-/** @defgroup I2C_duty_cycle_in_fast_mode
- * @{
- */
-
-#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
-#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
-#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
- ((CYCLE) == I2C_DutyCycle_2))
-/**
- * @}
- */
-
-/** @defgroup I2C_acknowledgement
- * @{
- */
-
-#define I2C_Ack_Enable ((uint16_t)0x0400)
-#define I2C_Ack_Disable ((uint16_t)0x0000)
-#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
- ((STATE) == I2C_Ack_Disable))
-/**
- * @}
- */
-
-/** @defgroup I2C_transfer_direction
- * @{
- */
-
-#define I2C_Direction_Transmitter ((uint8_t)0x00)
-#define I2C_Direction_Receiver ((uint8_t)0x01)
-#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
- ((DIRECTION) == I2C_Direction_Receiver))
-/**
- * @}
- */
-
-/** @defgroup I2C_acknowledged_address
- * @{
- */
-
-#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
-#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
-#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
- ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
-/**
- * @}
- */
-
-/** @defgroup I2C_registers
- * @{
- */
-
-#define I2C_Register_CR1 ((uint8_t)0x00)
-#define I2C_Register_CR2 ((uint8_t)0x04)
-#define I2C_Register_OAR1 ((uint8_t)0x08)
-#define I2C_Register_OAR2 ((uint8_t)0x0C)
-#define I2C_Register_DR ((uint8_t)0x10)
-#define I2C_Register_SR1 ((uint8_t)0x14)
-#define I2C_Register_SR2 ((uint8_t)0x18)
-#define I2C_Register_CCR ((uint8_t)0x1C)
-#define I2C_Register_TRISE ((uint8_t)0x20)
-#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
- ((REGISTER) == I2C_Register_CR2) || \
- ((REGISTER) == I2C_Register_OAR1) || \
- ((REGISTER) == I2C_Register_OAR2) || \
- ((REGISTER) == I2C_Register_DR) || \
- ((REGISTER) == I2C_Register_SR1) || \
- ((REGISTER) == I2C_Register_SR2) || \
- ((REGISTER) == I2C_Register_CCR) || \
- ((REGISTER) == I2C_Register_TRISE))
-/**
- * @}
- */
-
-/** @defgroup I2C_NACK_position
- * @{
- */
-
-#define I2C_NACKPosition_Next ((uint16_t)0x0800)
-#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
-#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
- ((POSITION) == I2C_NACKPosition_Current))
-/**
- * @}
- */
-
-/** @defgroup I2C_SMBus_alert_pin_level
- * @{
- */
-
-#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
-#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
-#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
- ((ALERT) == I2C_SMBusAlert_High))
-/**
- * @}
- */
-
-/** @defgroup I2C_PEC_position
- * @{
- */
-
-#define I2C_PECPosition_Next ((uint16_t)0x0800)
-#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
-#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
- ((POSITION) == I2C_PECPosition_Current))
-/**
- * @}
- */
-
-/** @defgroup I2C_interrupts_definition
- * @{
- */
-
-#define I2C_IT_BUF ((uint16_t)0x0400)
-#define I2C_IT_EVT ((uint16_t)0x0200)
-#define I2C_IT_ERR ((uint16_t)0x0100)
-#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup I2C_interrupts_definition
- * @{
- */
-
-#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
-#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
-#define I2C_IT_PECERR ((uint32_t)0x01001000)
-#define I2C_IT_OVR ((uint32_t)0x01000800)
-#define I2C_IT_AF ((uint32_t)0x01000400)
-#define I2C_IT_ARLO ((uint32_t)0x01000200)
-#define I2C_IT_BERR ((uint32_t)0x01000100)
-#define I2C_IT_TXE ((uint32_t)0x06000080)
-#define I2C_IT_RXNE ((uint32_t)0x06000040)
-#define I2C_IT_STOPF ((uint32_t)0x02000010)
-#define I2C_IT_ADD10 ((uint32_t)0x02000008)
-#define I2C_IT_BTF ((uint32_t)0x02000004)
-#define I2C_IT_ADDR ((uint32_t)0x02000002)
-#define I2C_IT_SB ((uint32_t)0x02000001)
-
-#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
-
-#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
- ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
- ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
- ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
- ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
- ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
- ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
-/**
- * @}
- */
-
-/** @defgroup I2C_flags_definition
- * @{
- */
-
-/**
- * @brief SR2 register flags
- */
-
-#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
-#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
-#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
-#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
-#define I2C_FLAG_TRA ((uint32_t)0x00040000)
-#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
-#define I2C_FLAG_MSL ((uint32_t)0x00010000)
-
-/**
- * @brief SR1 register flags
- */
-
-#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
-#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
-#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
-#define I2C_FLAG_OVR ((uint32_t)0x10000800)
-#define I2C_FLAG_AF ((uint32_t)0x10000400)
-#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
-#define I2C_FLAG_BERR ((uint32_t)0x10000100)
-#define I2C_FLAG_TXE ((uint32_t)0x10000080)
-#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
-#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
-#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
-#define I2C_FLAG_BTF ((uint32_t)0x10000004)
-#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
-#define I2C_FLAG_SB ((uint32_t)0x10000001)
-
-#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
-
-#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
- ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
- ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
- ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
- ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
- ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
- ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
- ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
- ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
- ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
- ((FLAG) == I2C_FLAG_SB))
-/**
- * @}
- */
-
-/** @defgroup I2C_Events
- * @{
- */
-
-/**
- ===============================================================================
- I2C Master Events (Events grouped in order of communication)
- ===============================================================================
- */
-
-/**
- * @brief Communication start
- *
- * After sending the START condition (I2C_GenerateSTART() function) the master
- * has to wait for this event. It means that the Start condition has been correctly
- * released on the I2C bus (the bus is free, no other devices is communicating).
- *
- */
-/* --EV5 */
-#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
-
-/**
- * @brief Address Acknowledge
- *
- * After checking on EV5 (start condition correctly released on the bus), the
- * master sends the address of the slave(s) with which it will communicate
- * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
- * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
- * his address. If an acknowledge is sent on the bus, one of the following events will
- * be set:
- *
- * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
- * event is set.
- *
- * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
- * is set
- *
- * 3) In case of 10-Bit addressing mode, the master (just after generating the START
- * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
- * function). Then master should wait on EV9. It means that the 10-bit addressing
- * header has been correctly sent on the bus. Then master should send the second part of
- * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
- * should wait for event EV6.
- *
- */
-
-/* --EV6 */
-#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
-#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
-/* --EV9 */
-#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
-
-/**
- * @brief Communication events
- *
- * If a communication is established (START condition generated and slave address
- * acknowledged) then the master has to check on one of the following events for
- * communication procedures:
- *
- * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
- * the data received from the slave (I2C_ReceiveData() function).
- *
- * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
- * function) then to wait on event EV8 or EV8_2.
- * These two events are similar:
- * - EV8 means that the data has been written in the data register and is
- * being shifted out.
- * - EV8_2 means that the data has been physically shifted out and output
- * on the bus.
- * In most cases, using EV8 is sufficient for the application.
- * Using EV8_2 leads to a slower communication but ensure more reliable test.
- * EV8_2 is also more suitable than EV8 for testing on the last data transmission
- * (before Stop condition generation).
- *
- * @note In case the user software does not guarantee that this event EV7 is
- * managed before the current byte end of transfer, then user may check on EV7
- * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
- * In this case the communication may be slower.
- *
- */
-
-/* Master RECEIVER mode -----------------------------*/
-/* --EV7 */
-#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
-
-/* Master TRANSMITTER mode --------------------------*/
-/* --EV8 */
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
-/* --EV8_2 */
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
-
-
-/**
- ===============================================================================
- I2C Slave Events (Events grouped in order of communication)
- ===============================================================================
- */
-
-
-/**
- * @brief Communication start events
- *
- * Wait on one of these events at the start of the communication. It means that
- * the I2C peripheral detected a Start condition on the bus (generated by master
- * device) followed by the peripheral address. The peripheral generates an ACK
- * condition on the bus (if the acknowledge feature is enabled through function
- * I2C_AcknowledgeConfig()) and the events listed above are set :
- *
- * 1) In normal case (only one address managed by the slave), when the address
- * sent by the master matches the own address of the peripheral (configured by
- * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
- * (where XXX could be TRANSMITTER or RECEIVER).
- *
- * 2) In case the address sent by the master matches the second address of the
- * peripheral (configured by the function I2C_OwnAddress2Config() and enabled
- * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
- * (where XXX could be TRANSMITTER or RECEIVER) are set.
- *
- * 3) In case the address sent by the master is General Call (address 0x00) and
- * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
- * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
- *
- */
-
-/* --EV1 (all the events below are variants of EV1) */
-/* 1) Case of One Single Address managed by the slave */
-#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
-#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
-
-/* 2) Case of Dual address managed by the slave */
-#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
-#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
-
-/* 3) Case of General Call enabled for the slave */
-#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
-
-/**
- * @brief Communication events
- *
- * Wait on one of these events when EV1 has already been checked and:
- *
- * - Slave RECEIVER mode:
- * - EV2: When the application is expecting a data byte to be received.
- * - EV4: When the application is expecting the end of the communication: master
- * sends a stop condition and data transmission is stopped.
- *
- * - Slave Transmitter mode:
- * - EV3: When a byte has been transmitted by the slave and the application is expecting
- * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
- * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
- * used when the user software doesn't guarantee the EV3 is managed before the
- * current byte end of transfer.
- * - EV3_2: When the master sends a NACK in order to tell slave that data transmission
- * shall end (before sending the STOP condition). In this case slave has to stop sending
- * data bytes and expect a Stop condition on the bus.
- *
- * @note In case the user software does not guarantee that the event EV2 is
- * managed before the current byte end of transfer, then user may check on EV2
- * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
- * In this case the communication may be slower.
- *
- */
-
-/* Slave RECEIVER mode --------------------------*/
-/* --EV2 */
-#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
-/* --EV4 */
-#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
-
-/* Slave TRANSMITTER mode -----------------------*/
-/* --EV3 */
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
-/* --EV3_2 */
-#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
-
-/*
- ===============================================================================
- End of Events Description
- ===============================================================================
- */
-
-#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
- ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
- ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
- ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
- ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
- ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
- ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
- ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
- ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
- ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
- ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
-/**
- * @}
- */
-
-/** @defgroup I2C_own_address1
- * @{
- */
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
-/**
- * @}
- */
-
-/** @defgroup I2C_clock_speed
- * @{
- */
-
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the I2C configuration to the default reset state *****/
-void I2C_DeInit(I2C_TypeDef* I2Cx);
-
-/* Initialization and Configuration functions *********************************/
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter);
-void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
-void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-
-/* Data transfers functions ***************************************************/
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
-
-/* PEC management functions ***************************************************/
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
-
-/* DMA transfers management functions *****************************************/
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-
-/* Interrupts, events and flags management functions **************************/
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
-
-/*
- ===============================================================================
- I2C State Monitoring Functions
- ===============================================================================
- This I2C driver provides three different ways for I2C state monitoring
- depending on the application requirements and constraints:
-
-
- 1. Basic state monitoring (Using I2C_CheckEvent() function)
- -----------------------------------------------------------
- It compares the status registers (SR1 and SR2) content to a given event
- (can be the combination of one or more flags).
- It returns SUCCESS if the current status includes the given flags
- and returns ERROR if one or more flags are missing in the current status.
-
- - When to use
- - This function is suitable for most applications as well as for startup
- activity since the events are fully described in the product reference
- manual (RM0090).
- - It is also suitable for users who need to define their own events.
-
- - Limitations
- - If an error occurs (ie. error flags are set besides to the monitored
- flags), the I2C_CheckEvent() function may return SUCCESS despite
- the communication hold or corrupted real state.
- In this case, it is advised to use error interrupts to monitor
- the error events and handle them in the interrupt IRQ handler.
-
- Note
- For error management, it is advised to use the following functions:
- - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
- - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
- Where x is the peripheral instance (I2C1, I2C2 ...)
- - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
- I2Cx_ER_IRQHandler() function in order to determine which error occurred.
- - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
- and/or I2C_GenerateStop() in order to clear the error flag and source
- and return to correct communication status.
-
-
- 2. Advanced state monitoring (Using the function I2C_GetLastEvent())
- --------------------------------------------------------------------
- Using the function I2C_GetLastEvent() which returns the image of both status
- registers in a single word (uint32_t) (Status Register 2 value is shifted left
- by 16 bits and concatenated to Status Register 1).
-
- - When to use
- - This function is suitable for the same applications above but it
- allows to overcome the mentioned limitation of I2C_GetFlagStatus()
- function.
- - The returned value could be compared to events already defined in
- this file or to custom values defined by user.
- This function is suitable when multiple flags are monitored at the
- same time.
- - At the opposite of I2C_CheckEvent() function, this function allows
- user to choose when an event is accepted (when all events flags are
- set and no other flags are set or just when the needed flags are set
- like I2C_CheckEvent() function.
-
- - Limitations
- - User may need to define his own events.
- - Same remark concerning the error management is applicable for this
- function if user decides to check only regular communication flags
- (and ignores error flags).
-
-
- 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
- -----------------------------------------------------------------------
-
- Using the function I2C_GetFlagStatus() which simply returns the status of
- one single flag (ie. I2C_FLAG_RXNE ...).
-
- - When to use
- - This function could be used for specific applications or in debug
- phase.
- - It is suitable when only one flag checking is needed (most I2C
- events are monitored through multiple flags).
- - Limitations:
- - When calling this function, the Status register is accessed.
- Some flags are cleared when the status register is accessed.
- So checking the status of one Flag, may clear other ones.
- - Function may need to be called twice or more in order to monitor
- one single event.
- */
-
-/*
- ===============================================================================
- 1. Basic state monitoring
- ===============================================================================
- */
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
-/*
- ===============================================================================
- 2. Advanced state monitoring
- ===============================================================================
- */
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
-/*
- ===============================================================================
- 3. Flag-based state monitoring
- ===============================================================================
- */
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-
-
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_I2C_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_iwdg.c b/底盘/底盘-old/底盘/Library/stm32f4xx_iwdg.c
deleted file mode 100644
index aeb5412..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_iwdg.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_iwdg.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Independent watchdog (IWDG) peripheral:
- * + Prescaler and Counter configuration
- * + IWDG activation
- * + Flag management
- *
- @verbatim
- ===============================================================================
- ##### IWDG features #####
- ===============================================================================
- [..]
- The IWDG can be started by either software or hardware (configurable
- through option byte).
-
- The IWDG is clocked by its own dedicated low-speed clock (LSI) and
- thus stays active even if the main clock fails.
- Once the IWDG is started, the LSI is forced ON and cannot be disabled
- (LSI cannot be disabled too), and the counter starts counting down from
- the reset value of 0xFFF. When it reaches the end of count value (0x000)
- a system reset is generated.
- The IWDG counter should be reloaded at regular intervals to prevent
- an MCU reset.
-
- The IWDG is implemented in the VDD voltage domain that is still functional
- in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
-
- IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
- reset occurs.
-
- Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
- The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx
- devices provide the capability to measure the LSI frequency (LSI clock
- connected internally to TIM5 CH4 input capture). The measured value
- can be used to have an IWDG timeout with an acceptable accuracy.
- For more information, please refer to the STM32F4xx Reference manual
-
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable write access to IWDG_PR and IWDG_RLR registers using
- IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function
-
- (#) Configure the IWDG prescaler using IWDG_SetPrescaler() function
-
- (#) Configure the IWDG counter value using IWDG_SetReload() function.
- This value will be loaded in the IWDG counter each time the counter
- is reloaded, then the IWDG will start counting down from this value.
-
- (#) Start the IWDG using IWDG_Enable() function, when the IWDG is used
- in software mode (no need to enable the LSI, it will be enabled
- by hardware)
-
- (#) Then the application program must reload the IWDG counter at regular
- intervals during normal operation to prevent an MCU reset, using
- IWDG_ReloadCounter() function.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_iwdg.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup IWDG
- * @brief IWDG driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* KR register bit mask */
-#define KR_KEY_RELOAD ((uint16_t)0xAAAA)
-#define KR_KEY_ENABLE ((uint16_t)0xCCCC)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup IWDG_Private_Functions
- * @{
- */
-
-/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
- * @brief Prescaler and Counter configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Prescaler and Counter configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
- * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
- * This parameter can be one of the following values:
- * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
- * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
- * @retval None
- */
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
- IWDG->KR = IWDG_WriteAccess;
-}
-
-/**
- * @brief Sets IWDG Prescaler value.
- * @param IWDG_Prescaler: specifies the IWDG Prescaler value.
- * This parameter can be one of the following values:
- * @arg IWDG_Prescaler_4: IWDG prescaler set to 4
- * @arg IWDG_Prescaler_8: IWDG prescaler set to 8
- * @arg IWDG_Prescaler_16: IWDG prescaler set to 16
- * @arg IWDG_Prescaler_32: IWDG prescaler set to 32
- * @arg IWDG_Prescaler_64: IWDG prescaler set to 64
- * @arg IWDG_Prescaler_128: IWDG prescaler set to 128
- * @arg IWDG_Prescaler_256: IWDG prescaler set to 256
- * @retval None
- */
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
- IWDG->PR = IWDG_Prescaler;
-}
-
-/**
- * @brief Sets IWDG Reload value.
- * @param Reload: specifies the IWDG Reload value.
- * This parameter must be a number between 0 and 0x0FFF.
- * @retval None
- */
-void IWDG_SetReload(uint16_t Reload)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_RELOAD(Reload));
- IWDG->RLR = Reload;
-}
-
-/**
- * @brief Reloads IWDG counter with value defined in the reload register
- * (write access to IWDG_PR and IWDG_RLR registers disabled).
- * @param None
- * @retval None
- */
-void IWDG_ReloadCounter(void)
-{
- IWDG->KR = KR_KEY_RELOAD;
-}
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Group2 IWDG activation function
- * @brief IWDG activation function
- *
-@verbatim
- ===============================================================================
- ##### IWDG activation function #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
- * @param None
- * @retval None
- */
-void IWDG_Enable(void)
-{
- IWDG->KR = KR_KEY_ENABLE;
-}
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Group3 Flag management function
- * @brief Flag management function
- *
-@verbatim
- ===============================================================================
- ##### Flag management function #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the specified IWDG flag is set or not.
- * @param IWDG_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg IWDG_FLAG_PVU: Prescaler Value Update on going
- * @arg IWDG_FLAG_RVU: Reload Value Update on going
- * @retval The new state of IWDG_FLAG (SET or RESET).
- */
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_IWDG_FLAG(IWDG_FLAG));
- if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_iwdg.h b/底盘/底盘-old/底盘/Library/stm32f4xx_iwdg.h
deleted file mode 100644
index 972267b..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_iwdg.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_iwdg.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the IWDG
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_IWDG_H
-#define __STM32F4xx_IWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup IWDG
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup IWDG_Exported_Constants
- * @{
- */
-
-/** @defgroup IWDG_WriteAccess
- * @{
- */
-#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
-#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
-#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
- ((ACCESS) == IWDG_WriteAccess_Disable))
-/**
- * @}
- */
-
-/** @defgroup IWDG_prescaler
- * @{
- */
-#define IWDG_Prescaler_4 ((uint8_t)0x00)
-#define IWDG_Prescaler_8 ((uint8_t)0x01)
-#define IWDG_Prescaler_16 ((uint8_t)0x02)
-#define IWDG_Prescaler_32 ((uint8_t)0x03)
-#define IWDG_Prescaler_64 ((uint8_t)0x04)
-#define IWDG_Prescaler_128 ((uint8_t)0x05)
-#define IWDG_Prescaler_256 ((uint8_t)0x06)
-#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
- ((PRESCALER) == IWDG_Prescaler_8) || \
- ((PRESCALER) == IWDG_Prescaler_16) || \
- ((PRESCALER) == IWDG_Prescaler_32) || \
- ((PRESCALER) == IWDG_Prescaler_64) || \
- ((PRESCALER) == IWDG_Prescaler_128)|| \
- ((PRESCALER) == IWDG_Prescaler_256))
-/**
- * @}
- */
-
-/** @defgroup IWDG_Flag
- * @{
- */
-#define IWDG_FLAG_PVU ((uint16_t)0x0001)
-#define IWDG_FLAG_RVU ((uint16_t)0x0002)
-#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
-#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Prescaler and Counter configuration functions ******************************/
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
-void IWDG_SetReload(uint16_t Reload);
-void IWDG_ReloadCounter(void);
-
-/* IWDG activation function ***************************************************/
-void IWDG_Enable(void);
-
-/* Flag management function ***************************************************/
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_IWDG_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_lptim.c b/底盘/底盘-old/底盘/Library/stm32f4xx_lptim.c
deleted file mode 100644
index 12ebdff..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_lptim.c
+++ /dev/null
@@ -1,943 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_lptim.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Low Power Timer (LPT) peripheral:
- * + Initialization functions.
- * + Configuration functions.
- * + Interrupts and flags management functions.
- *
- * @verbatim
- *
-================================================================================
- ##### How to use this driver #####
-================================================================================
-
- Basic configuration:
- --------------------
- - Configure the clock source, the prescaler, the waveform shape and
- the output polarity by filling the "LPTIM_InitTypeDef" structure and
- calling LPTIM_Init.
- - If the ULPTIM source is selected as clock source, configure the digital
- Glitch filter by setting the number of consecutive samples
- to be detected by using LPTIM_ConfigClockGlitchFilter.
- - To select a software start use LPTIM_SelectSoftwareStart.
- - To select an external trigger for the start of the counter, configure
- the source and its active edge polarity by calling
- LPTIM_ConfigExternalTrigger. Configure the Digital Glitch filter for
- the external triggers by setting the number of consecutive samples
- to be detected by using LPTIM_ConfigTriggerGlitchFilter.
- - Select the operating mode of the peripheral by using
- LPTIM_SelectOperatingMode, 2 modes can be selected:
- + Continuous mode: the timer is free running, the timer is started
- from a trigger event and never stops until the timer is disabled
- + One shot mode: the timer is started from a trigger event and
- stops when reaching the auto-reload value.
- - Use LPTIM_SetAutoreloadValue to set the auto-reload value and
- LPTIM_SetCompareValue to set the compare value.
- - Configure the preload mode by using LPTIM_ConfigUpdate function. 2 modes
- are available:
- + The Autoreload and compare registers are updated immediately after
- APB write.
- + The Autoreload and compare registers are updated at the end of
- counter period.
- - Enable the peripheral by calling LPTIM_Cmd.
-
- Encoder mode:
- -------------
- - To select the encoder feature, use the function: LPTIM_SelectEncoderMode.
- - To select on which edge (Rising edge, falling edge or both edges)
- the counter is incremented, use LPTIM_SelectClockPolarity.
-
- Counter mode:
- -------------
- - Use LPTIM_SelectCounterMode to select the counting mode. In this mode
- the counter is incremented on each valid event on ULPTIM.
-
- Timeout function:
- -----------------
- In this case, the trigger will reset the timer. The first trigger event
- will start the timer, any successive trigger event will reset the counter
- and the timer restarts.
- - To active this feature use LPTIM_TimoutCmd.
-
- Interrupt configuration:
- ------------------------
- - Use LPTIM_ITConfig to configure an interruption.
- - Call LPTIM_GetFlagStatus to get a flag status.
- - Call LPTIM_GetITStatus to get an interrupt status.
- - Use LPTIM_ClearFlag to clear a flag.
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_lptim.h"
-
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup LPTIM
- * @brief LPTIM driver modules
- * @{
- */
-#if defined(STM32F410xx) || defined(STM32F413_423xx)
-/* External variables --------------------------------------------------------*/
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-
-#define CFGR_INIT_CLEAR_MASK ((uint32_t) 0xFFCFF1FE)
-#define CFGR_TRIG_AND_POL_CLEAR_MASK ((uint32_t) 0xFFF91FFF)
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup LPTIM_Private_Functions
- * @{
- */
-
-/** @defgroup LPTIM_Group1 Initialization functions
- * @brief Initialization functions
- *
-@verbatim
- ===============================================================================
- Initialization functions
- ===============================================================================
- This section provides functions allowing to:
- - Deinitialize the LPTimer
- - Initialize the Clock source, the Prescaler, the Ouput Waveform shape and Polarity
- - Initialize the member of LPTIM_InitStruct structer with default value
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the LPTIMx peripheral registers to their default reset values.
- * @param LPTIMx: where x can be 1.
- * @retval None
- *
- */
-void LPTIM_DeInit(LPTIM_TypeDef* LPTIMx)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
-
- /* Deinitializes the LPTIM1 peripheral */
- if(LPTIMx == LPTIM1)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_LPTIM1, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_LPTIM1, DISABLE);
- }
-}
-
-/**
- * @brief Initializes the LPTIMx peripheral according to the specified parameters
- * in the LPTIM_InitStruct.
- * @param LPTIMx: where x can be 1.
- * @param LPTIM_InitStruct: pointer to an LPTIM_InitTypeDef structure that contains
- * the configuration information for the specified LPTIM peripheral.
- * @retval None
- *
- * @note It is mandatory to disable the peripheral to use this function.
- */
-void LPTIM_Init(LPTIM_TypeDef* LPTIMx, LPTIM_InitTypeDef* LPTIM_InitStruct)
-{
- uint32_t tmpreg1 = 0;
-
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
- assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->LPTIM_ClockSource));
- assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->LPTIM_Prescaler));
- assert_param(IS_LPTIM_WAVEFORM(LPTIM_InitStruct->LPTIM_Waveform));
- assert_param(IS_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->LPTIM_OutputPolarity));
-
- /* Get the LPTIMx CFGR value */
- tmpreg1 = LPTIMx->CFGR;
-
- /* Clear CKSEL, PRESC, WAVE and WAVEPOL bits */
- tmpreg1 &= CFGR_INIT_CLEAR_MASK;
-
- /* Set or Reset CKSEL bit according to LPTIM_ClockSource value */
- /* Set or Reset PRESC bits according to LPTIM_Prescaler value */
- /* Set or Reset WAVE bit according to LPTIM_Waveform value */
- /* Set or Reset WAVEPOL bit according to LPTIM_OutputPolarity value */
- tmpreg1 |= (LPTIM_InitStruct->LPTIM_ClockSource | LPTIM_InitStruct->LPTIM_Prescaler
- |LPTIM_InitStruct->LPTIM_Waveform | LPTIM_InitStruct->LPTIM_OutputPolarity);
-
- /* Write to LPTIMx CFGR */
- LPTIMx->CFGR = tmpreg1;
-}
-
-/**
- * @brief Fills each LPTIM_InitStruct member with its default value.
- * @param LPTIM_InitStruct : pointer to a LPTIM_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void LPTIM_StructInit(LPTIM_InitTypeDef* LPTIM_InitStruct)
-{
- /* APB Clock/Low Power oscillators is selected as default Clock source*/
- LPTIM_InitStruct->LPTIM_ClockSource = LPTIM_ClockSource_APBClock_LPosc;
-
- /* High Polarity is selected as default polarity */
- LPTIM_InitStruct->LPTIM_OutputPolarity = LPTIM_OutputPolarity_High;
-
- /* DIV=1 is selected as default prescaler */
- LPTIM_InitStruct->LPTIM_Prescaler = LPTIM_Prescaler_DIV1;
-
- /* PWM/One pulse mode is selected as default Waveform shape */
- LPTIM_InitStruct->LPTIM_Waveform = LPTIM_Waveform_PWM_OnePulse;
-}
-
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Group2 Configuration functions
- * @brief Configuration functions
- *
-@verbatim
- ===============================================================================
- Configuration functions
- ===============================================================================
- This section provides functions allowing to configure the Low Power Timer:
- - Select the Clock source.
- - Configure the Glitch filter for the external clock and the external clock.
- - Configure the prescaler of the counter.
- - Select the Trigger source of the counter.
- - Configure the operating mode (Single or Continuous mode).
- - Select the Waveform shape (PWM/One Pulse or Set once) and polarity.
- - Enable or disable the Encoder mode and the Timeout function.
- - Write on the Autoreload and the Compare registers and configure the
- preload mode.
- - Get the Counter value.
- - Enable or disable the peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified LPTIM peripheral.
- * @param LPTIMx: where x can be 1.
- * @param NewState: new state of the LPTIMx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void LPTIM_Cmd(LPTIM_TypeDef* LPTIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- /* Set the ENABLE bit */
- LPTIMx->CR |= LPTIM_CR_ENABLE;
- }
- else
- {
- /* Reset the ENABLE bit */
- LPTIMx->CR &= ~(LPTIM_CR_ENABLE);
- }
-}
-
-/**
- * @brief Selects the Clock source of the LPTIM counter.
- * @param LPTIMx: where x can be 1.
- * @param LPTIM_ClockSource: the selected clock source.
- * This parameter can be:
- * @arg LPTIM_ClockSource_APBClock_LPosc : APB clock/LP oscillators selected
- * @arg LPTIM_ClockSource_ULPTIM: ULPTIM (external input) selected
- * @retval None
- *
- * @note It is mandatory to disable the peripheral to use this function.
- */
-void LPTIM_SelectClockSource(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_ClockSource)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
- assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_ClockSource));
-
- /* Clear the CKSEL bit */
- LPTIMx->CFGR &= ~(LPTIM_CFGR_CKSEL);
-
- /* Set or Reset the CKSEL bit */
- LPTIMx->CFGR |= LPTIM_ClockSource;
-}
-
-/**
- * @brief Configures the polarity of the edge to be used to count
- * if the ULPTIM input is selected.
- * @param LPTIMx: where x can be 1.
- * @param LPTIM_ClockPolarity: the selected clock polarity.
- * This parameter can be:
- * @arg LPTIM_ClockPolarity_RisingEdge : Counter Clock = LPTIM Clock / 1
- * @arg LPTIM_ClockPolarity_FallingEdge : Counter Clock = LPTIM Clock / 2
- * @arg LPTIM_ClockPolarity_BothEdges : Counter Clock = LPTIM Clock / 4
- * @retval None
- *
- * @note It is mandatory to disable the peripheral to use this function.
- */
-void LPTIM_SelectULPTIMClockPolarity(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_ClockPolarity)
-{
- uint32_t tmpreg1 = 0;
-
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
- assert_param(IS_LPTIM_CLOCK_POLARITY(LPTIM_ClockPolarity));
-
- /* Get the LPTIMx CFGR value */
- tmpreg1 = LPTIMx->CFGR;
-
- /* Clear the CKPOL bits */
- tmpreg1 &= ~(LPTIM_CFGR_CKPOL);
-
- /* Set or Reset the PRESC bits */
- tmpreg1 |= LPTIM_ClockPolarity;
-
- /* Write to LPTIMx CFGR */
- LPTIMx->CFGR = tmpreg1;
-}
-
-/**
- * @brief Configures the Clock Prescaler.
- * @param LPTIMx: where x can be 1.
- * @param LPTIM_Prescaler: the selected clock prescaler.
- * This parameter can be:
- * @arg LPTIM_Prescaler_DIV1 : Counter Clock = LPTIM Clock / 1
- * @arg LPTIM_Prescaler_DIV2 : Counter Clock = LPTIM Clock / 2
- * @arg LPTIM_Prescaler_DIV4 : Counter Clock = LPTIM Clock / 4
- * @arg LPTIM_Prescaler_DIV8 : Counter Clock = LPTIM Clock / 8
- * @arg LPTIM_Prescaler_DIV16 : Counter Clock = LPTIM Clock / 16
- * @arg LPTIM_Prescaler_DIV32 : Counter Clock = LPTIM Clock / 32
- * @arg LPTIM_Prescaler_DIV64 : Counter Clock = LPTIM Clock / 64
- * @arg LPTIM_Prescaler_DIV128 : Counter Clock = LPTIM Clock / 128
- * @retval None
- *
- * @note It is mandatory to disable the peripheral to use this function.
- */
-void LPTIM_ConfigPrescaler(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Prescaler)
-{
- uint32_t tmpreg1 = 0;
-
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
- assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_Prescaler));
-
- /* Get the LPTIMx CFGR value */
- tmpreg1 = LPTIMx->CFGR;
-
- /* Clear the PRESC bits */
- tmpreg1 &= ~(LPTIM_CFGR_PRESC);
-
- /* Set or Reset the PRESC bits */
- tmpreg1 |= LPTIM_Prescaler;
-
- /* Write to LPTIMx CFGR */
- LPTIMx->CFGR = tmpreg1;
-}
-
-/**
- * @brief Selects the trigger source for the counter and its polarity.
- * @param LPTIMx: where x can be 1.
- * @param LPTIM_ExtTRGSource: the selected external trigger.
- * This parameter can be:
- * @arg LPTIM_ExtTRGSource_Trig0 : ext_trig0
- * @arg LPTIM_ExtTRGSource_Trig1 : ext_trig1
- * @arg LPTIM_ExtTRGSource_Trig2 : ext_trig2
- * @arg LPTIM_ExtTRGSource_Trig3 : ext_trig3
- * @arg LPTIM_ExtTRGSource_Trig4 : ext_trig4
- * @arg LPTIM_ExtTRGSource_Trig5 : ext_trig5
- * @arg LPTIM_ExtTRGSource_Trig6 : ext_trig6
- * @arg LPTIM_ExtTRGSource_Trig7 : ext_trig7
- * @param LPTIM_ExtTRGPolarity: the selected external trigger.
- * This parameter can be:
- * @arg LPTIM_ExtTRGPolarity_RisingEdge : Rising edge polarity selected
- * @arg LPTIM_ExtTRGPolarity_FallingEdge : Falling edge polarity selected
- * @arg LPTIM_ExtTRGPolarity_BothEdges : Both edges polarity selected
- * @retval None
- *
- * @note It is mandatory to disable the peripheral to use this function.
- */
-void LPTIM_ConfigExternalTrigger(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_ExtTRGSource, uint32_t LPTIM_ExtTRGPolarity)
-{
- uint32_t tmpreg1 = 0;
-
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
- assert_param(IS_LPTIM_EXT_TRG_SOURCE(LPTIM_ExtTRGSource));
- assert_param(IS_LPTIM_EXT_TRG_POLARITY(LPTIM_ExtTRGPolarity));
-
- /* Get the LPTIMx CFGR value */
- tmpreg1 = LPTIMx->CFGR;
-
- /* Clear the TRIGEN and TRIGSEL bits */
- tmpreg1 &= CFGR_TRIG_AND_POL_CLEAR_MASK;
-
- /* Set or Reset the TRIGEN and TRIGSEL bits */
- tmpreg1 |= (LPTIM_ExtTRGSource | LPTIM_ExtTRGPolarity);
-
- /* Write to LPTIMx CFGR */
- LPTIMx->CFGR = tmpreg1;
-}
-
-/**
- * @brief Selects a software start of the counter.
- * @param LPTIMx: where x can be 1.
- * @retval None
- *
- * @note It is mandatory to disable the peripheral to use this function.
- */
-void LPTIM_SelectSoftwareStart(LPTIM_TypeDef* LPTIMx)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
-
- /* Reset the TRIGEN bits to allow a software start */
- LPTIMx->CFGR &= ~(LPTIM_CFGR_TRIGEN);
-}
-
-/**
- * @brief Configures the digital filter for trigger by determining the number of consecutive
- * samples at the specified level to detect a correct transition.
- * @param LPTIMx: where x can be 1.
- * @param LPTIM_TrigSampleTime: the number of samples to detect a valid transition.
- * This parameter can be:
- * @arg LPTIM_TrigSampleTime_DirectTransistion : Event is detected on input transitions
- * @arg LPTIM_TrigSampleTime_2Transistions : Event is detected after 2 consecutive samples at the active level
- * @arg LPTIM_TrigSampleTime_4Transistions : Event is detected after 4 consecutive samples at the active level
- * @arg LPTIM_TrigSampleTime_8Transistions : Event is detected after 8 consecutive samples at the active level
- * @retval None
- *
- * @note It is mandatory to disable the peripheral to use this function.
- * @note An auxiliary clock must be present to use this feature.
- */
-void LPTIM_ConfigTriggerGlitchFilter(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_TrigSampleTime)
-{
- uint32_t tmpreg1 = 0;
-
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
- assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(LPTIM_TrigSampleTime));
-
- /* Get the LPTIMx CFGR value */
- tmpreg1 = LPTIMx->CFGR;
-
- /* Clear the TRGFLT bits */
- tmpreg1 &= ~(LPTIM_CFGR_TRGFLT);
-
- /* Set or Reset the TRGFLT bits according to LPTIM_TrigSampleTime */
- tmpreg1 |= (LPTIM_TrigSampleTime);
-
- /* Write to LPTIMx CFGR */
- LPTIMx->CFGR = tmpreg1;
-}
-
-/**
- * @brief Configures the digital filter for the external clock by determining the number
- of consecutive samples at the specified level to detect a correct transition.
- * @param LPTIMx: where x can be 1.
- * @param LPTIM_ClockSampleTime: the number of samples to detect a valid transition.
- * This parameter can be:
- * @arg LPTIM_ClockSampleTime_DirectTransistion : Event is detected on input transitions
- * @arg LPTIM_ClockSampleTime_2Transistions : Event is detected after 2 consecutive samples at the active level
- * @arg LPTIM_ClockSampleTime_4Transistions : Event is detected after 4 consecutive samples at the active level
- * @arg LPTIM_ClockSampleTime_8Transistions : Event is detected after 8 consecutive samples at the active level
- * @retval None
- *
- * @note It is mandatory to disable the peripheral to use this function.
- * @note An auxiliary clock must be present to use this feature.
- */
-void LPTIM_ConfigClockGlitchFilter(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_ClockSampleTime)
-{
- uint32_t tmpreg1 = 0;
-
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
- assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(LPTIM_ClockSampleTime));
-
- /* Get the LPTIMx CFGR value */
- tmpreg1 = LPTIMx->CFGR;
-
- /* Clear the CKFLT bits */
- tmpreg1 &= ~(LPTIM_CFGR_CKFLT);
-
- /* Set or Reset the CKFLT bits according to LPTIM_ClockSampleTime */
- tmpreg1 |= LPTIM_ClockSampleTime;
-
- /* Write to LPTIMx CFGR */
- LPTIMx->CFGR = tmpreg1;
-}
-
-/**
- * @brief Selects an operating mode.
- * @param LPTIMx: where x can be 1.
- * @param LPTIM_Mode: the selected mode.
- * This parameter can be:
- * @arg LPTIM_Mode_Continuous : Timer starts in Continuous mode
- * @arg LPTIM_Mode_Single : Timer will starts in Single mode
- * @retval None
- */
-void LPTIM_SelectOperatingMode(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Mode)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
- assert_param(IS_LPTIM_MODE(LPTIM_Mode));
-
-
- if(LPTIM_Mode == LPTIM_Mode_Continuous)
- {
- /* Set the CNTSTRT to select the continuous start*/
- LPTIMx->CR |= LPTIM_Mode_Continuous;
- }
- else /*LPTIM_Mode_Single */
- {
- /* Set the SNGSTRT to select the continuous start*/
- LPTIMx->CR |= LPTIM_Mode_Single;
- }
-}
-
-/**
- * @brief Enables or disables the Timeout function.
- * @param LPTIMx: where x can be 1.
- * @param NewState: new state of the Timeout function.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- *
- * @note It is mandatory to disable the peripheral to use this function.
- */
-void LPTIM_TimoutCmd(LPTIM_TypeDef* LPTIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- /* Set the TIMOUT bit */
- LPTIMx->CFGR |= LPTIM_CFGR_TIMOUT;
- }
- else
- {
- /* Reset the TIMOUT bit */
- LPTIMx->CFGR &= ~(LPTIM_CFGR_TIMOUT);
- }
-}
-
-/**
- * @brief Configures the Waveform shape.
- * @param LPTIMx: where x can be 1.
- * @param LPTIM_Waveform: the selected waveform shape.
- * This parameter can be:
- * @arg LPTIM_Waveform_PWM_OnePulse : PWM/One Pulse is selected
- * @arg LPTIM_Waveform_SetOnce : Set once is selected
- * @retval None
- *
- * @note It is mandatory to disable the peripheral to use this function.
- */
-void LPTIM_ConfigWaveform(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Waveform)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
- assert_param(IS_LPTIM_WAVEFORM(LPTIM_Waveform));
-
- /* Clear the WAVE bit */
- LPTIMx->CFGR &= ~(LPTIM_CFGR_CKFLT);
-
- /* Set or Reset the WAVE bit according to LPTIM_Waveform */
- LPTIMx->CFGR |= (LPTIM_Waveform);
-}
-
-/**
- * @brief Configures the Autoreload and Compare registers update mode.
- * @param LPTIMx: where x can be 1.
- * @param LPTIM_Update: The selected update mode.
- * This parameter can be:
- * @arg LPTIM_Update_Immediate : Registers updated after APB write
- * @arg LPTIM_Update_EndOfPeriod : Registers updated at the end of current timer preload
- * @retval None
- *
- * @note It is mandatory to disable the peripheral to use this function.
- */
-void LPTIM_ConfigUpdate(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Update)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
- assert_param(IS_LPTIM_UPDATE(LPTIM_Update));
-
- /* Clear the PRELOAD bit */
- LPTIMx->CFGR &= ~(LPTIM_CFGR_PRELOAD);
-
- /* Set or Reset the PRELOAD bit according to LPTIM_Update */
- LPTIMx->CFGR |= (LPTIM_Update);
-}
-
-/**
- * @brief Writes the passed parameter in the Autoreload register.
- * @param LPTIMx: where x can be 1.
- * @param LPTIM_Autoreload: The Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF
- * @retval None
- */
-void LPTIM_SetAutoreloadValue(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Autoreload)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
- assert_param(IS_LPTIM_AUTORELOAD(LPTIM_Autoreload));
-
- /* Write LPTIM_Autoreload in Autoreload register */
- LPTIMx->ARR = LPTIM_Autoreload;
-}
-
-/**
- * @brief Writes the passed parameter in the Compare register.
- * @param LPTIMx: where x can be 1.
- * @param LPTIM_Compare: The Compare value.
- * This parameter must be a value between 0x0000 and 0xFFFF
- * @retval None
- */
-void LPTIM_SetCompareValue(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Compare)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
- assert_param(IS_LPTIM_COMPARE(LPTIM_Compare));
-
- /* Write LPTIM_Compare in Compare register */
- LPTIMx->CMP = LPTIM_Compare;
-}
-
-/**
- * @brief Enables or disables the Counter mode. When the Counter mode is enabled,
- * the counter is incremented each valid event on ULPTIM
- * @param LPTIMx: where x can be 1.
- * @param NewState: new state of the Counter mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- *
- * @note It is mandatory to disable the peripheral to use this function.
- */
-void LPTIM_SelectCounterMode(LPTIM_TypeDef* LPTIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- /* Set the COUNTMODE bit */
- LPTIMx->CFGR |= LPTIM_CFGR_COUNTMODE;
- }
- else
- {
- /* Reset the COUNTMODE bit */
- LPTIMx->CFGR &= ~(LPTIM_CFGR_COUNTMODE);
- }
-}
-
-/**
- * @brief Enables or disables the Encoder mode.
- * @param LPTIMx: where x can be 1.
- * @param NewState: New state of the encoder mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- *
- * @note It is mandatory to disable the peripheral to use this function.
- */
-void LPTIM_SelectEncoderMode(LPTIM_TypeDef* LPTIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- /* Set the ENC bit */
- LPTIMx->CFGR |= LPTIM_CFGR_ENC;
- }
- else
- {
- /* Reset the ENC bit */
- LPTIMx->CFGR &= ~(LPTIM_CFGR_ENC);
- }
-}
-
-/**
- * @brief Gets the LPTIMx counter value.
- * @param LPTIMx: where x can be 1.
- * @retval Counter Register value
- */
-uint32_t LPTIM_GetCounterValue(LPTIM_TypeDef* LPTIMx)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
-
- /* Get the Counter Register value */
- return LPTIMx->CNT;
-}
-
-/**
- * @brief Gets the LPTIMx Autoreload value.
- * @param LPTIMx: where x can be 1.
- * @retval Counter Register value
- */
-uint32_t LPTIM_GetAutoreloadValue(LPTIM_TypeDef* LPTIMx)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
-
- /* Get the Counter Register value */
- return LPTIMx->ARR;
-}
-
-/**
- * @brief Gets the LPTIMx Compare value.
- * @param LPTIMx: where x can be 1.
- * @retval Counter Register value
- */
-uint32_t LPTIM_GetCompareValue(LPTIM_TypeDef* LPTIMx)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
-
- /* Get the Counter Register value */
- return LPTIMx->CMP;
-}
-
-/**
- * @brief LPTIM Input 1 Remap.
- * @param LPTIMx: where x can be 1.
- * @param LPTIM_OPTR :
- * This Parameter can be :
- * @arg LPTIM_OP_PAD_AF : Port B5 on AF1 or Port C0 on AF1 for input timer
- * @arg LPTIM_OP_PAD_PA4 : Input remapped to Port A4
- * @arg RCC_LPTIM1CLKSOURCE_LSI : Input remapped to Port B9
- * @arg LPTIM_OP_TIM_DAC : Input coming from timer 6 output (for encoder mode)
- * @retval Counter Register value
- */
-void LPTIM_RemapConfig(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_OPTR)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
-
- /* Get the Counter Register value */
- LPTIMx->OR = LPTIM_OPTR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- Interrupts and flags management functions
- ===============================================================================
- This section provides functions allowing to configure the LPTIM Interrupts, get
- the status and clear flags bits.
-
- The LPTIM provides 7 Flags and Interrupts sources (2 flags and Interrupt sources
- are available only on LPTIM peripherals equipped with encoder mode interface)
-
- Flags and Interrupts sources:
- =============================
- 1. Compare match.
- 2. Auto-reload match.
- 3. External trigger event.
- 4. Autoreloaded register write completed.
- 5. Compare register write completed.
- 6. Direction change: from up to down [Available only for LPTIM peripheral with
- encoder mode module]
- 7. Direction change: from down to up [Available only for LPTIM peripheral with
- encoder mode module]
-
- - To enable a specific interrupt source, use "LPTIM_ITConfig" function.
- - To check if an interrupt was occurred, call "LPTIM_GetITStatus" function and read
- the returned value.
- - To get a flag status, call the "LPTIM_GetFlagStatus" function and read the returned
- value.
- - To clear a flag or an interrupt, use LPTIM_ClearFlag function with the
- corresponding flag (interrupt).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified LPTIM interrupts.
- * @param LPTIMx: where x can be 1.
- * @param LPTIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg LPTIM_IT_DOWN: Counter direction change up to down Interrupt source
- * @arg LPTIM_IT_UP: Counter direction change down to up Interrupt source
- * @arg LPTIM_IT_ARROK: Autoreload register update OK Interrupt source
- * @arg LPTIM_IT_CMPOK: Compare register update OK Interrupt source
- * @arg LPTIM_IT_EXTTRIG: External trigger edge event Interrupt source
- * @arg LPTIM_IT_ARRM: Autoreload match Interrupt source
- * @arg LPTIM_IT_CMPM: Compare match Interrupt source
- * @note LPTIM_IT_DOWN is available only for LPTIM1.
- * @note LPTIM_IT_UP is available only for LPTIM1.
- * @param NewState: new state of the TIM interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- *
- * @note It is mandatory to disable the peripheral to use this function.
- */
-void LPTIM_ITConfig(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_IT, FunctionalState NewState)
- {
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
- assert_param(IS_LPTIM_IT(LPTIM_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- /* Enable the Interrupt sources */
- LPTIMx->IER |= LPTIM_IT;
- }
- else
- {
- /* Disable the Interrupt sources */
- LPTIMx->IER &= ~(LPTIM_IT);
- }
-}
-
-/**
- * @brief Checks whether the specified LPTIM flag is set or not.
- * @param LPTIMx: where x can be 1.
- * @param LPTIM_FLAG: specifies the flag to check.
- * This parameter can be any combination of the following values:
- * @arg LPTIM_FLAG_DOWN: Counter direction change up Flag
- * @arg LPTIM_FLAG_UP: Counter direction change down to up Flag
- * @arg LPTIM_FLAG_ARROK: Autoreload register update OK Flag
- * @arg LPTIM_FLAG_CMPOK: Compare register update OK Flag
- * @arg LPTIM_FLAG_EXTTRIG: External trigger edge event Flag
- * @arg LPTIM_FLAG_ARRM: Autoreload match Flag
- * @arg LPTIM_FLAG_CMPM: Compare match Flag
- * @note LPTIM_Flag_DOWN is generated only for LPTIM1.
- * @note LPTIM_Flag_UP is generated only for LPTIM1.
- * @param NewState: new state of the TIM interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-FlagStatus LPTIM_GetFlagStatus(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_FLAG)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
- assert_param(IS_LPTIM_GET_FLAG(LPTIM_FLAG));
-
- if((LPTIMx->ISR & LPTIM_FLAG) != (RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the LPTIMx's pending flag.
- * @param LPTIMx: where x can be 1.
- * @param LPTIM_CLEARF: specifies the pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg LPTIM_CLEARF_DOWN: Counter direction change up Clear Flag
- * @arg LPTIM_CLEARF_UP: Counter direction change down to up Clear Flag
- * @arg LPTIM_CLEARF_ARROK: Autoreload register update OK Clear Flag
- * @arg LPTIM_CLEARF_CMPOK: Compare register update OK Clear Flag
- * @arg LPTIM_CLEARF_EXTTRIG: External trigger edge event Clear Flag
- * @arg LPTIM_CLEARF_ARRM: Autoreload match Clear Flag
- * @arg LPTIM_CLEARF_CMPM: Compare match Clear Flag
- * @note LPTIM_Flag_DOWN is generated only for LPTIM1.
- * @note LPTIM_Flag_UP is generated only for LPTIM1.
- * @retval None
- */
-void LPTIM_ClearFlag(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_CLEARF)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
- assert_param(IS_LPTIM_CLEAR_FLAG(LPTIM_CLEARF));
-
- /* Clear the IT pending Bit */
- LPTIMx->ICR |= LPTIM_CLEARF;
-}
-
-/**
- * @brief Check whether the specified LPTIM interrupt has occurred or not.
- * @param LPTIMx: where x can be 1.
- * @param LPTIM_IT: specifies the LPTIM interrupt source to check.
- * @arg LPTIM_IT_DOWN: Counter direction change up to down Interrupt source
- * @arg LPTIM_IT_UP: Counter direction change down to up Interrupt source
- * @arg LPTIM_IT_ARROK: Autoreload register update OK Interrupt source
- * @arg LPTIM_IT_CMPOK: Compare register update OK Interrupt source
- * @arg LPTIM_IT_EXTTRIG: External trigger edge event Interrupt source
- * @arg LPTIM_IT_ARRM: Autoreload match Interrupt source
- * @arg LPTIM_IT_CMPM: Compare match Interrupt source
- * @retval The new state of LPTIM_IT (SET or RESET).
- */
-ITStatus LPTIM_GetITStatus(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t itstatus = 0x0, itenable = 0x0;
-
- /* Check the parameters */
- assert_param(IS_LPTIM_ALL_PERIPH(LPTIMx));
- assert_param(IS_LPTIM_IT(LPTIM_IT));
-
- /* Get the Interrupt Status bit value */
- itstatus = LPTIMx->ISR & LPTIM_IT;
-
- /* Check if the Interrupt is enabled */
- itenable = LPTIMx->IER & LPTIM_IT;
-
- if((itstatus != RESET) && (itenable != RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* STM32F410xx || STM32F413_423xx */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_lptim.h b/底盘/底盘-old/底盘/Library/stm32f4xx_lptim.h
deleted file mode 100644
index e2dabc2..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_lptim.h
+++ /dev/null
@@ -1,378 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_lptim.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the LPTIM
- * firmware library
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4XX_LPTIM_H
-#define __STM32F4XX_LPTIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup LPTIM
- * @{
- */
-#if defined(STM32F410xx) || defined(STM32F413_423xx)
-/* Exported types ------------------------------------------------------------*/
-/**
- * @brief LPTIM Init structure definition
- * @note
- */
-typedef struct
-{
- uint32_t LPTIM_ClockSource; /*!< Selects the clock source.
- This parameter can be a value of @ref LPTIM_Clock_Source */
-
- uint32_t LPTIM_Prescaler; /*!< Specifies the timer clock Prescaler.
- This parameter can be a value of @ref LPTIM_Clock_Prescaler */
-
- uint32_t LPTIM_Waveform; /*!< Selects the output shape.
- This parameter can be a value of @ref LPTIM_Waveform_Shape */
-
- uint32_t LPTIM_OutputPolarity; /*!< Specifies the LPTIM Output pin polarity.
- This parameter can be a value of @ref LPTIM_Output_Polarity */
-}LPTIM_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup LPTIM_Exported_Constants
- * @{
- */
-
-#define IS_LPTIM_ALL_PERIPH(PERIPH) ((PERIPH) == LPTIM1)
-
-/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
- * @{
- */
-
-#define LPTIM_ClockSource_APBClock_LPosc ((uint32_t)0x00000000)
-#define LPTIM_ClockSource_ULPTIM ((uint32_t)0x00000001)
-#define IS_LPTIM_CLOCK_SOURCE(SOURCE) (((SOURCE) == LPTIM_ClockSource_ULPTIM) || \
- ((SOURCE) == LPTIM_ClockSource_APBClock_LPosc))
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
- * @{
- */
-#define LPTIM_Prescaler_DIV1 ((uint32_t)0x00000000)
-#define LPTIM_Prescaler_DIV2 ((uint32_t)0x00000200)
-#define LPTIM_Prescaler_DIV4 ((uint32_t)0x00000400)
-#define LPTIM_Prescaler_DIV8 ((uint32_t)0x00000600)
-#define LPTIM_Prescaler_DIV16 ((uint32_t)0x00000800)
-#define LPTIM_Prescaler_DIV32 ((uint32_t)0x00000A00)
-#define LPTIM_Prescaler_DIV64 ((uint32_t)0x00000C00)
-#define LPTIM_Prescaler_DIV128 ((uint32_t)0x00000E00)
-#define IS_LPTIM_CLOCK_PRESCALER(PRESCALER) (((PRESCALER) == LPTIM_Prescaler_DIV1) || \
- ((PRESCALER) == LPTIM_Prescaler_DIV2) || \
- ((PRESCALER) == LPTIM_Prescaler_DIV4) || \
- ((PRESCALER) == LPTIM_Prescaler_DIV8) || \
- ((PRESCALER) == LPTIM_Prescaler_DIV16) || \
- ((PRESCALER) == LPTIM_Prescaler_DIV32) || \
- ((PRESCALER) == LPTIM_Prescaler_DIV64) || \
- ((PRESCALER) == LPTIM_Prescaler_DIV128))
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Waveform_Shape LPTIM Waveform Shape
- * @{
- */
-#define LPTIM_Waveform_PWM_OnePulse ((uint32_t)0x00000000)
-#define LPTIM_Waveform_SetOnce ((uint32_t)0x00100000)
-#define IS_LPTIM_WAVEFORM(WAVE) (((WAVE) == LPTIM_Waveform_SetOnce) || \
- ((WAVE) == LPTIM_Waveform_PWM_OnePulse))
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
- * @{
- */
-#define LPTIM_OutputPolarity_High ((uint32_t)0x00000000)
-#define LPTIM_OutputPolarity_Low ((uint32_t)0x00200000)
-#define IS_LPTIM_OUTPUT_POLARITY(POLARITY) (((POLARITY) == LPTIM_OutputPolarity_Low ) || \
- ((POLARITY) == LPTIM_OutputPolarity_High))
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
- * @{
- */
-#define LPTIM_ClockPolarity_RisingEdge ((uint32_t)0x00000000)
-#define LPTIM_ClockPolarity_FallingEdge ((uint32_t)0x00000002)
-#define LPTIM_ClockPolarity_BothEdges ((uint32_t)0x00000004)
-#define IS_LPTIM_CLOCK_POLARITY(POLARITY) (((POLARITY) == LPTIM_ClockPolarity_RisingEdge ) || \
- ((POLARITY) == LPTIM_ClockPolarity_FallingEdge ) || \
- ((POLARITY) == LPTIM_ClockPolarity_BothEdges))
-/**
- * @}
- */
-
-/** @defgroup LPTIM_External_Trigger_Source LPTIM External Trigger Source
- * @{
- */
-#define LPTIM_ExtTRGSource_0 ((uint32_t)0x00000000)
-#define LPTIM_ExtTRGSource_1 ((uint32_t)0x00002000)
-#define LPTIM_ExtTRGSource_2 ((uint32_t)0x00004000)
-#define LPTIM_ExtTRGSource_3 ((uint32_t)0x00006000)
-#define LPTIM_ExtTRGSource_4 ((uint32_t)0x00008000)
-#define LPTIM_ExtTRGSource_5 ((uint32_t)0x0000A000)
-#define LPTIM_ExtTRGSource_6 ((uint32_t)0x0000C000)
-#define LPTIM_ExtTRGSource_7 ((uint32_t)0x0000E000)
-#define IS_LPTIM_EXT_TRG_SOURCE(TRIG) (((TRIG) == LPTIM_ExtTRGSource_0) || \
- ((TRIG) == LPTIM_ExtTRGSource_1) || \
- ((TRIG) == LPTIM_ExtTRGSource_2) || \
- ((TRIG) == LPTIM_ExtTRGSource_3) || \
- ((TRIG) == LPTIM_ExtTRGSource_4) || \
- ((TRIG) == LPTIM_ExtTRGSource_5) || \
- ((TRIG) == LPTIM_ExtTRGSource_6) || \
- ((TRIG) == LPTIM_ExtTRGSource_7))
-/**
- * @}
- */
-
-/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
- * @{
- */
-#define LPTIM_ExtTRGPolarity_RisingEdge ((uint32_t)0x00020000)
-#define LPTIM_ExtTRGPolarity_FallingEdge ((uint32_t)0x00040000)
-#define LPTIM_ExtTRGPolarity_BothEdges ((uint32_t)0x00060000)
-#define IS_LPTIM_EXT_TRG_POLARITY(POLAR) (((POLAR) == LPTIM_ExtTRGPolarity_RisingEdge) || \
- ((POLAR) == LPTIM_ExtTRGPolarity_FallingEdge) || \
- ((POLAR) == LPTIM_ExtTRGPolarity_BothEdges))
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
- * @{
- */
-#define LPTIM_ClockSampleTime_DirectTransistion ((uint32_t)0x00000000)
-#define LPTIM_ClockSampleTime_2Transistions ((uint32_t)0x00000008)
-#define LPTIM_ClockSampleTime_4Transistions ((uint32_t)0x00000010)
-#define LPTIM_ClockSampleTime_8Transistions ((uint32_t)0x00000018)
-#define IS_LPTIM_CLOCK_SAMPLE_TIME(SAMPLETIME) (((SAMPLETIME) == LPTIM_ClockSampleTime_DirectTransistion) || \
- ((SAMPLETIME) == LPTIM_ClockSampleTime_2Transistions) || \
- ((SAMPLETIME) == LPTIM_ClockSampleTime_4Transistions) || \
- ((SAMPLETIME) == LPTIM_ClockSampleTime_8Transistions))
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
- * @{
- */
-#define LPTIM_TrigSampleTime_DirectTransistion ((uint32_t)0x00000000)
-#define LPTIM_TrigSampleTime_2Transistions ((uint32_t)0x00000040)
-#define LPTIM_TrigSampleTime_4Transistions ((uint32_t)0x00000080)
-#define LPTIM_TrigSampleTime_8Transistions ((uint32_t)0x000000C0)
-#define IS_LPTIM_TRIG_SAMPLE_TIME(SAMPLETIME) (((SAMPLETIME) == LPTIM_TrigSampleTime_DirectTransistion) || \
- ((SAMPLETIME) == LPTIM_TrigSampleTime_2Transistions) || \
- ((SAMPLETIME) == LPTIM_TrigSampleTime_4Transistions) || \
- ((SAMPLETIME) == LPTIM_TrigSampleTime_8Transistions))
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Operating_Mode LPTIM Operating Mode
- * @{
- */
-#define LPTIM_Mode_Continuous ((uint32_t)0x00000004)
-#define LPTIM_Mode_Single ((uint32_t)0x00000002)
-#define IS_LPTIM_MODE(MODE) (((MODE) == LPTIM_Mode_Continuous) || \
- ((MODE) == LPTIM_Mode_Single))
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Updating_Register LPTIM Updating Register
- * @{
- */
-#define LPTIM_Update_Immediate ((uint32_t)0x00000000)
-#define LPTIM_Update_EndOfPeriod ((uint32_t)0x00400000)
-#define IS_LPTIM_UPDATE(UPDATE) (((UPDATE) == LPTIM_Update_Immediate) || \
- ((UPDATE) == LPTIM_Update_EndOfPeriod))
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
- * @{
- */
-#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE
-#define LPTIM_IT_UP LPTIM_IER_UPIE
-#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE
-#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
-#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
-#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE
-#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE
-#define IS_LPTIM_IT(IT) (((IT) == LPTIM_IT_DOWN) || \
- ((IT) == LPTIM_IT_UP) || \
- ((IT) == LPTIM_IT_ARROK) || \
- ((IT) == LPTIM_IT_CMPOK) || \
- ((IT) == LPTIM_IT_EXTTRIG) || \
- ((IT) == LPTIM_IT_ARRM) || \
- ((IT) == LPTIM_IT_CMPM))
-
-#define IS_LPTIM_GET_IT(IT) (((IT) == LPTIM_IT_DOWN) || \
- ((IT) == LPTIM_IT_UP) || \
- ((IT) == LPTIM_IT_ARROK) || \
- ((IT) == LPTIM_IT_CMPOK) || \
- ((IT) == LPTIM_IT_EXTTRIG) || \
- ((IT) == LPTIM_IT_ARRM) || \
- ((IT) == LPTIM_IT_CMPM))
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Flag_Definition LPTIM Flag Definition
- * @{
- */
-#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
-#define LPTIM_FLAG_UP LPTIM_ISR_UP
-#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
-#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
-#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
-#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
-#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM
-#define IS_LPTIM_GET_FLAG(FLAG) (((FLAG) == LPTIM_FLAG_DOWN) || \
- ((FLAG) == LPTIM_FLAG_UP) || \
- ((FLAG) == LPTIM_FLAG_ARROK) || \
- ((FLAG) == LPTIM_FLAG_CMPOK) || \
- ((FLAG) == LPTIM_FLAG_EXTTRIG) || \
- ((FLAG) == LPTIM_FLAG_ARRM) || \
- ((FLAG) == LPTIM_FLAG_CMPM))
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Clear_Flag_Definition LPTIM Clear Flag Definition
- * @{
- */
-#define LPTIM_CLEAR_DOWN LPTIM_ICR_DOWNCF
-#define LPTIM_CLEAR_UP LPTIM_ICR_UPCF
-#define LPTIM_CLEAR_ARROK LPTIM_ICR_ARROKCF
-#define LPTIM_CLEAR_CMPOK LPTIM_ICR_CMPOKCF
-#define LPTIM_CLEAR_EXTTRIG LPTIM_ICR_EXTTRIGCF
-#define LPTIM_CLEAR_ARRM LPTIM_ICR_ARRMCF
-#define LPTIM_CLEAR_CMPM LPTIM_ICR_CMPMCF
-#define IS_LPTIM_CLEAR_FLAG(CLEARF) (((CLEARF) == LPTIM_CLEAR_DOWN) || \
- ((CLEARF) == LPTIM_CLEAR_UP) || \
- ((CLEARF) == LPTIM_CLEAR_ARROK) || \
- ((CLEARF) == LPTIM_CLEAR_CMPOK) || \
- ((CLEARF) == LPTIM_CLEAR_EXTTRIG) || \
- ((CLEARF) == LPTIM_CLEAR_ARRM ) || \
- ((CLEARF) == LPTIM_CLEAR_CMPM))
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Autorelaod_Value LPTIM Autorelaod Value
- * @{
- */
-#define IS_LPTIM_AUTORELOAD(AUTORELOAD) ((AUTORELOAD) <= 0x0000FFFF)
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Compare_Value LPTIM Compare Value
- * @{
- */
-#define IS_LPTIM_COMPARE(COMPARE) ((COMPARE) <= 0x0000FFFF)
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Option_Register_Definition LPTIM Option Register Definition
- * @{
- */
-#define LPTIM_OP_PAD_AF ((uint32_t)0x00000000)
-#define LPTIM_OP_PAD_PA4 LPTIM_OR_OR_0
-#define LPTIM_OP_PAD_PB9 LPTIM_OR_OR_1
-#define LPTIM_OP_TIM_DAC LPTIM_OR_OR
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Initialization functions ***************************************************/
-void LPTIM_DeInit(LPTIM_TypeDef* LPTIMx);
-void LPTIM_Init(LPTIM_TypeDef* LPTIMx, LPTIM_InitTypeDef* LPTIM_InitStruct);
-void LPTIM_StructInit(LPTIM_InitTypeDef* LPTIM_InitStruct);
-
-/* Configuration functions ****************************************************/
-void LPTIM_Cmd(LPTIM_TypeDef* LPTIMx, FunctionalState NewState);
-void LPTIM_SelectClockSource(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_ClockSource);
-void LPTIM_SelectULPTIMClockPolarity(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_ClockPolarity);
-void LPTIM_ConfigPrescaler(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Prescaler);
-void LPTIM_ConfigExternalTrigger(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_ExtTRGSource, uint32_t LPTIM_ExtTRGPolarity);
-void LPTIM_SelectSoftwareStart(LPTIM_TypeDef* LPTIMx);
-void LPTIM_ConfigTriggerGlitchFilter(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_TrigSampleTime);
-void LPTIM_ConfigClockGlitchFilter(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_ClockSampleTime);
-void LPTIM_SelectOperatingMode(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Mode);
-void LPTIM_TimoutCmd(LPTIM_TypeDef* LPTIMx, FunctionalState NewState);
-void LPTIM_ConfigWaveform(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Waveform);
-void LPTIM_ConfigUpdate(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Update);
-void LPTIM_SetAutoreloadValue(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Autoreload);
-void LPTIM_SetCompareValue(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Compare);
-void LPTIM_SelectCounterMode(LPTIM_TypeDef* LPTIMx, FunctionalState NewState);
-void LPTIM_SelectEncoderMode(LPTIM_TypeDef* LPTIMx, FunctionalState NewState);
-void LPTIM_RemapConfig(LPTIM_TypeDef* LPTIMx,uint32_t LPTIM_OPTR);
-uint32_t LPTIM_GetCounterValue(LPTIM_TypeDef* LPTIMx);
-uint32_t LPTIM_GetAutoreloadValue(LPTIM_TypeDef* LPTIMx);
-uint32_t LPTIM_GetCompareValue(LPTIM_TypeDef* LPTIMx);
-
-/* Interrupts and flags management functions **********************************/
-void LPTIM_ITConfig(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_IT, FunctionalState NewState);
-FlagStatus LPTIM_GetFlagStatus(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_FLAG);
-void LPTIM_ClearFlag(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_CLEARF);
-ITStatus LPTIM_GetITStatus(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_IT);
-
-#endif /* STM32F410xx || STM32F413_423xx */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_LPTIM_H */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_ltdc.c b/底盘/底盘-old/底盘/Library/stm32f4xx_ltdc.c
deleted file mode 100644
index 9f2b722..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_ltdc.c
+++ /dev/null
@@ -1,1102 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_ltdc.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the LTDC controller (LTDC) peripheral:
- * + Initialization and configuration
- * + Interrupts and flags management
- *
- * @verbatim
-
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable LTDC clock using
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_LTDC, ENABLE) function.
- (#) Configures LTDC
- (++) Configure the required Pixel clock following the panel datasheet
- (++) Configure the Synchronous timings: VSYNC, HSYNC, Vertical and
- Horizontal back proch, active data area and the front proch
- timings
- (++) Configure the synchronous signals and clock polarity in the
- LTDC_GCR register
- (#) Configures Layer1/2 parameters
- (++) The Layer window horizontal and vertical position in the LTDC_LxWHPCR and
- LTDC_WVPCR registers. The layer window must be in the active data area.
- (++) The pixel input format in the LTDC_LxPFCR register
- (++) The color frame buffer start address in the LTDC_LxCFBAR register
- (++) The line length and pitch of the color frame buffer in the
- LTDC_LxCFBLR register
- (++) The number of lines of the color frame buffer in
- the LTDC_LxCFBLNR register
- (++) if needed, load the CLUT with the RGB values and the address
- in the LTDC_LxCLUTWR register
- (++) If needed, configure the default color and the blending factors
- respectively in the LTDC_LxDCCR and LTDC_LxBFCR registers
-
- (++) If needed, Dithering and color keying can be enabled respectively
- in the LTDC_GCR and LTDC_LxCKCR registers. It can be also enabled
- on the fly.
- (#) Enable Layer1/2 and if needed the CLUT in the LTDC_LxCR register
-
- (#) Reload the shadow registers to active register through
- the LTDC_SRCR register.
- -@- All layer parameters can be modified on the fly except the CLUT.
- The new configuration has to be either reloaded immediately
- or during vertical blanking period by configuring the LTDC_SRCR register.
- (#) Call the LTDC_Cmd() to enable the LTDC controller.
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_ltdc.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup LTDC
- * @brief LTDC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-#define GCR_MASK ((uint32_t)0x0FFE888F) /* LTDC GCR Mask */
-
-
-/** @defgroup LTDC_Private_Functions
- * @{
- */
-
-/** @defgroup LTDC_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the LTDC
- (+) Enable or Disable Dither
- (+) Define the position of the line interrupt
- (+) reload layers registers with new parameters
- (+) Initialize and configure layer1 and layer2
- (+) Set and configure the color keying functionality
- (+) Configure and Enables or disables CLUT
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the LTDC peripheral registers to their default reset
- * values.
- * @param None
- * @retval None
- */
-
-void LTDC_DeInit(void)
-{
- /* Enable LTDC reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_LTDC, ENABLE);
- /* Release LTDC from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_LTDC, DISABLE);
-}
-
-/**
- * @brief Initializes the LTDC peripheral according to the specified parameters
- * in the LTDC_InitStruct.
- * @note This function can be used only when the LTDC is disabled.
- * @param LTDC_InitStruct: pointer to a LTDC_InitTypeDef structure that contains
- * the configuration information for the specified LTDC peripheral.
- * @retval None
- */
-
-void LTDC_Init(LTDC_InitTypeDef* LTDC_InitStruct)
-{
- uint32_t horizontalsync = 0;
- uint32_t accumulatedHBP = 0;
- uint32_t accumulatedactiveW = 0;
- uint32_t totalwidth = 0;
- uint32_t backgreen = 0;
- uint32_t backred = 0;
-
- /* Check function parameters */
- assert_param(IS_LTDC_HSYNC(LTDC_InitStruct->LTDC_HorizontalSync));
- assert_param(IS_LTDC_VSYNC(LTDC_InitStruct->LTDC_VerticalSync));
- assert_param(IS_LTDC_AHBP(LTDC_InitStruct->LTDC_AccumulatedHBP));
- assert_param(IS_LTDC_AVBP(LTDC_InitStruct->LTDC_AccumulatedVBP));
- assert_param(IS_LTDC_AAH(LTDC_InitStruct->LTDC_AccumulatedActiveH));
- assert_param(IS_LTDC_AAW(LTDC_InitStruct->LTDC_AccumulatedActiveW));
- assert_param(IS_LTDC_TOTALH(LTDC_InitStruct->LTDC_TotalHeigh));
- assert_param(IS_LTDC_TOTALW(LTDC_InitStruct->LTDC_TotalWidth));
- assert_param(IS_LTDC_HSPOL(LTDC_InitStruct->LTDC_HSPolarity));
- assert_param(IS_LTDC_VSPOL(LTDC_InitStruct->LTDC_VSPolarity));
- assert_param(IS_LTDC_DEPOL(LTDC_InitStruct->LTDC_DEPolarity));
- assert_param(IS_LTDC_PCPOL(LTDC_InitStruct->LTDC_PCPolarity));
- assert_param(IS_LTDC_BackBlueValue(LTDC_InitStruct->LTDC_BackgroundBlueValue));
- assert_param(IS_LTDC_BackGreenValue(LTDC_InitStruct->LTDC_BackgroundGreenValue));
- assert_param(IS_LTDC_BackRedValue(LTDC_InitStruct->LTDC_BackgroundRedValue));
-
- /* Sets Synchronization size */
- LTDC->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
- horizontalsync = (LTDC_InitStruct->LTDC_HorizontalSync << 16);
- LTDC->SSCR |= (horizontalsync | LTDC_InitStruct->LTDC_VerticalSync);
-
- /* Sets Accumulated Back porch */
- LTDC->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
- accumulatedHBP = (LTDC_InitStruct->LTDC_AccumulatedHBP << 16);
- LTDC->BPCR |= (accumulatedHBP | LTDC_InitStruct->LTDC_AccumulatedVBP);
-
- /* Sets Accumulated Active Width */
- LTDC->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
- accumulatedactiveW = (LTDC_InitStruct->LTDC_AccumulatedActiveW << 16);
- LTDC->AWCR |= (accumulatedactiveW | LTDC_InitStruct->LTDC_AccumulatedActiveH);
-
- /* Sets Total Width */
- LTDC->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
- totalwidth = (LTDC_InitStruct->LTDC_TotalWidth << 16);
- LTDC->TWCR |= (totalwidth | LTDC_InitStruct->LTDC_TotalHeigh);
-
- LTDC->GCR &= (uint32_t)GCR_MASK;
- LTDC->GCR |= (uint32_t)(LTDC_InitStruct->LTDC_HSPolarity | LTDC_InitStruct->LTDC_VSPolarity | \
- LTDC_InitStruct->LTDC_DEPolarity | LTDC_InitStruct->LTDC_PCPolarity);
-
- /* sets the background color value */
- backgreen = (LTDC_InitStruct->LTDC_BackgroundGreenValue << 8);
- backred = (LTDC_InitStruct->LTDC_BackgroundRedValue << 16);
-
- LTDC->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
- LTDC->BCCR |= (backred | backgreen | LTDC_InitStruct->LTDC_BackgroundBlueValue);
-}
-
-/**
- * @brief Fills each LTDC_InitStruct member with its default value.
- * @param LTDC_InitStruct: pointer to a LTDC_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-
-void LTDC_StructInit(LTDC_InitTypeDef* LTDC_InitStruct)
-{
- /*--------------- Reset LTDC init structure parameters values ----------------*/
- LTDC_InitStruct->LTDC_HSPolarity = LTDC_HSPolarity_AL; /*!< Initialize the LTDC_HSPolarity member */
- LTDC_InitStruct->LTDC_VSPolarity = LTDC_VSPolarity_AL; /*!< Initialize the LTDC_VSPolarity member */
- LTDC_InitStruct->LTDC_DEPolarity = LTDC_DEPolarity_AL; /*!< Initialize the LTDC_DEPolarity member */
- LTDC_InitStruct->LTDC_PCPolarity = LTDC_PCPolarity_IPC; /*!< Initialize the LTDC_PCPolarity member */
- LTDC_InitStruct->LTDC_HorizontalSync = 0x00; /*!< Initialize the LTDC_HorizontalSync member */
- LTDC_InitStruct->LTDC_VerticalSync = 0x00; /*!< Initialize the LTDC_VerticalSync member */
- LTDC_InitStruct->LTDC_AccumulatedHBP = 0x00; /*!< Initialize the LTDC_AccumulatedHBP member */
- LTDC_InitStruct->LTDC_AccumulatedVBP = 0x00; /*!< Initialize the LTDC_AccumulatedVBP member */
- LTDC_InitStruct->LTDC_AccumulatedActiveW = 0x00; /*!< Initialize the LTDC_AccumulatedActiveW member */
- LTDC_InitStruct->LTDC_AccumulatedActiveH = 0x00; /*!< Initialize the LTDC_AccumulatedActiveH member */
- LTDC_InitStruct->LTDC_TotalWidth = 0x00; /*!< Initialize the LTDC_TotalWidth member */
- LTDC_InitStruct->LTDC_TotalHeigh = 0x00; /*!< Initialize the LTDC_TotalHeigh member */
- LTDC_InitStruct->LTDC_BackgroundRedValue = 0x00; /*!< Initialize the LTDC_BackgroundRedValue member */
- LTDC_InitStruct->LTDC_BackgroundGreenValue = 0x00; /*!< Initialize the LTDC_BackgroundGreenValue member */
- LTDC_InitStruct->LTDC_BackgroundBlueValue = 0x00; /*!< Initialize the LTDC_BackgroundBlueValue member */
-}
-
-/**
- * @brief Enables or disables the LTDC Controller.
- * @param NewState: new state of the LTDC peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-
-void LTDC_Cmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable LTDC by setting LTDCEN bit */
- LTDC->GCR |= (uint32_t)LTDC_GCR_LTDCEN;
- }
- else
- {
- /* Disable LTDC by clearing LTDCEN bit */
- LTDC->GCR &= ~(uint32_t)LTDC_GCR_LTDCEN;
- }
-}
-
-/**
- * @brief Enables or disables Dither.
- * @param NewState: new state of the Dither.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-
-void LTDC_DitherCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Dither by setting DTEN bit */
- LTDC->GCR |= (uint32_t)LTDC_GCR_DTEN;
- }
- else
- {
- /* Disable Dither by clearing DTEN bit */
- LTDC->GCR &= ~(uint32_t)LTDC_GCR_DTEN;
- }
-}
-
-/**
- * @brief Get the dither RGB width.
- * @param LTDC_RGB_InitStruct: pointer to a LTDC_RGBTypeDef structure that contains
- * the Dither RGB width.
- * @retval None
- */
-
-LTDC_RGBTypeDef LTDC_GetRGBWidth(void)
-{
- LTDC_RGBTypeDef LTDC_RGB_InitStruct;
-
- LTDC->GCR &= (uint32_t)GCR_MASK;
-
- LTDC_RGB_InitStruct.LTDC_BlueWidth = (uint32_t)((LTDC->GCR >> 4) & 0x7);
- LTDC_RGB_InitStruct.LTDC_GreenWidth = (uint32_t)((LTDC->GCR >> 8) & 0x7);
- LTDC_RGB_InitStruct.LTDC_RedWidth = (uint32_t)((LTDC->GCR >> 12) & 0x7);
-
- return LTDC_RGB_InitStruct;
-}
-
-/**
- * @brief Fills each LTDC_RGBStruct member with its default value.
- * @param LTDC_RGB_InitStruct: pointer to a LTDC_RGBTypeDef structure which will
- * be initialized.
- * @retval None
- */
-
-void LTDC_RGBStructInit(LTDC_RGBTypeDef* LTDC_RGB_InitStruct)
-{
- LTDC_RGB_InitStruct->LTDC_BlueWidth = 0x02;
- LTDC_RGB_InitStruct->LTDC_GreenWidth = 0x02;
- LTDC_RGB_InitStruct->LTDC_RedWidth = 0x02;
-}
-
-
-/**
- * @brief Define the position of the line interrupt .
- * @param LTDC_LIPositionConfig: Line Interrupt Position.
- * @retval None
- */
-
-void LTDC_LIPConfig(uint32_t LTDC_LIPositionConfig)
-{
- /* Check the parameters */
- assert_param(IS_LTDC_LIPOS(LTDC_LIPositionConfig));
-
- /* Sets the Line Interrupt position */
- LTDC->LIPCR = (uint32_t)LTDC_LIPositionConfig;
-}
-
-/**
- * @brief reload layers registers with new parameters
- * @param LTDC_Reload: specifies the type of reload.
- * This parameter can be one of the following values:
- * @arg LTDC_IMReload: Vertical blanking reload.
- * @arg LTDC_VBReload: Immediate reload.
- * @retval None
- */
-
-void LTDC_ReloadConfig(uint32_t LTDC_Reload)
-{
- /* Check the parameters */
- assert_param(IS_LTDC_RELOAD(LTDC_Reload));
-
- /* Sets the Reload type */
- LTDC->SRCR = (uint32_t)LTDC_Reload;
-}
-
-
-/**
- * @brief Initializes the LTDC Layer according to the specified parameters
- * in the LTDC_LayerStruct.
- * @note This function can be used only when the LTDC is disabled.
- * @param LTDC_layerx: Select the layer to be configured, this parameter can be
- * one of the following values: LTDC_Layer1, LTDC_Layer2
- * @param LTDC_LayerStruct: pointer to a LTDC_LayerTypeDef structure that contains
- * the configuration information for the specified LTDC peripheral.
- * @retval None
- */
-
-void LTDC_LayerInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_Layer_InitTypeDef* LTDC_Layer_InitStruct)
-{
-
- uint32_t whsppos = 0;
- uint32_t wvsppos = 0;
- uint32_t dcgreen = 0;
- uint32_t dcred = 0;
- uint32_t dcalpha = 0;
- uint32_t cfbp = 0;
-
-/* Check the parameters */
- assert_param(IS_LTDC_Pixelformat(LTDC_Layer_InitStruct->LTDC_PixelFormat));
- assert_param(IS_LTDC_BlendingFactor1(LTDC_Layer_InitStruct->LTDC_BlendingFactor_1));
- assert_param(IS_LTDC_BlendingFactor2(LTDC_Layer_InitStruct->LTDC_BlendingFactor_2));
- assert_param(IS_LTDC_HCONFIGST(LTDC_Layer_InitStruct->LTDC_HorizontalStart));
- assert_param(IS_LTDC_HCONFIGSP(LTDC_Layer_InitStruct->LTDC_HorizontalStop));
- assert_param(IS_LTDC_VCONFIGST(LTDC_Layer_InitStruct->LTDC_VerticalStart));
- assert_param(IS_LTDC_VCONFIGSP(LTDC_Layer_InitStruct->LTDC_VerticalStop));
- assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorBlue));
- assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorGreen));
- assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorRed));
- assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorAlpha));
- assert_param(IS_LTDC_CFBP(LTDC_Layer_InitStruct->LTDC_CFBPitch));
- assert_param(IS_LTDC_CFBLL(LTDC_Layer_InitStruct->LTDC_CFBLineLength));
- assert_param(IS_LTDC_CFBLNBR(LTDC_Layer_InitStruct->LTDC_CFBLineNumber));
-
- /* Configures the horizontal start and stop position */
- whsppos = LTDC_Layer_InitStruct->LTDC_HorizontalStop << 16;
- LTDC_Layerx->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
- LTDC_Layerx->WHPCR = (LTDC_Layer_InitStruct->LTDC_HorizontalStart | whsppos);
-
- /* Configures the vertical start and stop position */
- wvsppos = LTDC_Layer_InitStruct->LTDC_VerticalStop << 16;
- LTDC_Layerx->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
- LTDC_Layerx->WVPCR = (LTDC_Layer_InitStruct->LTDC_VerticalStart | wvsppos);
-
- /* Specifies the pixel format */
- LTDC_Layerx->PFCR &= ~(LTDC_LxPFCR_PF);
- LTDC_Layerx->PFCR = (LTDC_Layer_InitStruct->LTDC_PixelFormat);
-
- /* Configures the default color values */
- dcgreen = (LTDC_Layer_InitStruct->LTDC_DefaultColorGreen << 8);
- dcred = (LTDC_Layer_InitStruct->LTDC_DefaultColorRed << 16);
- dcalpha = (LTDC_Layer_InitStruct->LTDC_DefaultColorAlpha << 24);
- LTDC_Layerx->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);
- LTDC_Layerx->DCCR = (LTDC_Layer_InitStruct->LTDC_DefaultColorBlue | dcgreen | \
- dcred | dcalpha);
-
- /* Specifies the constant alpha value */
- LTDC_Layerx->CACR &= ~(LTDC_LxCACR_CONSTA);
- LTDC_Layerx->CACR = (LTDC_Layer_InitStruct->LTDC_ConstantAlpha);
-
- /* Specifies the blending factors */
- LTDC_Layerx->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
- LTDC_Layerx->BFCR = (LTDC_Layer_InitStruct->LTDC_BlendingFactor_1 | LTDC_Layer_InitStruct->LTDC_BlendingFactor_2);
-
- /* Configures the color frame buffer start address */
- LTDC_Layerx->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
- LTDC_Layerx->CFBAR = (LTDC_Layer_InitStruct->LTDC_CFBStartAdress);
-
- /* Configures the color frame buffer pitch in byte */
- cfbp = (LTDC_Layer_InitStruct->LTDC_CFBPitch << 16);
- LTDC_Layerx->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
- LTDC_Layerx->CFBLR = (LTDC_Layer_InitStruct->LTDC_CFBLineLength | cfbp);
-
- /* Configures the frame buffer line number */
- LTDC_Layerx->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR);
- LTDC_Layerx->CFBLNR = (LTDC_Layer_InitStruct->LTDC_CFBLineNumber);
-
-}
-
-/**
- * @brief Fills each LTDC_Layer_InitStruct member with its default value.
- * @param LTDC_Layer_InitStruct: pointer to a LTDC_LayerTypeDef structure which will
- * be initialized.
- * @retval None
- */
-
-void LTDC_LayerStructInit(LTDC_Layer_InitTypeDef * LTDC_Layer_InitStruct)
-{
- /*--------------- Reset Layer structure parameters values -------------------*/
-
- /*!< Initialize the horizontal limit member */
- LTDC_Layer_InitStruct->LTDC_HorizontalStart = 0x00;
- LTDC_Layer_InitStruct->LTDC_HorizontalStop = 0x00;
-
- /*!< Initialize the vertical limit member */
- LTDC_Layer_InitStruct->LTDC_VerticalStart = 0x00;
- LTDC_Layer_InitStruct->LTDC_VerticalStop = 0x00;
-
- /*!< Initialize the pixel format member */
- LTDC_Layer_InitStruct->LTDC_PixelFormat = LTDC_Pixelformat_ARGB8888;
-
- /*!< Initialize the constant alpha value */
- LTDC_Layer_InitStruct->LTDC_ConstantAlpha = 0xFF;
-
- /*!< Initialize the default color values */
- LTDC_Layer_InitStruct->LTDC_DefaultColorBlue = 0x00;
- LTDC_Layer_InitStruct->LTDC_DefaultColorGreen = 0x00;
- LTDC_Layer_InitStruct->LTDC_DefaultColorRed = 0x00;
- LTDC_Layer_InitStruct->LTDC_DefaultColorAlpha = 0x00;
-
- /*!< Initialize the blending factors */
- LTDC_Layer_InitStruct->LTDC_BlendingFactor_1 = LTDC_BlendingFactor1_PAxCA;
- LTDC_Layer_InitStruct->LTDC_BlendingFactor_2 = LTDC_BlendingFactor2_PAxCA;
-
- /*!< Initialize the frame buffer start address */
- LTDC_Layer_InitStruct->LTDC_CFBStartAdress = 0x00;
-
- /*!< Initialize the frame buffer pitch and line length */
- LTDC_Layer_InitStruct->LTDC_CFBLineLength = 0x00;
- LTDC_Layer_InitStruct->LTDC_CFBPitch = 0x00;
-
- /*!< Initialize the frame buffer line number */
- LTDC_Layer_InitStruct->LTDC_CFBLineNumber = 0x00;
-}
-
-
-/**
- * @brief Enables or disables the LTDC_Layer Controller.
- * @param LTDC_layerx: Select the layer to be configured, this parameter can be
- * one of the following values: LTDC_Layer1, LTDC_Layer2
- * @param NewState: new state of the LTDC_Layer peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-
-void LTDC_LayerCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable LTDC_Layer by setting LEN bit */
- LTDC_Layerx->CR |= (uint32_t)LTDC_LxCR_LEN;
- }
- else
- {
- /* Disable LTDC_Layer by clearing LEN bit */
- LTDC_Layerx->CR &= ~(uint32_t)LTDC_LxCR_LEN;
- }
-}
-
-
-/**
- * @brief Get the current position.
- * @param LTDC_Pos_InitStruct: pointer to a LTDC_PosTypeDef structure that contains
- * the current position.
- * @retval None
- */
-
-LTDC_PosTypeDef LTDC_GetPosStatus(void)
-{
- LTDC_PosTypeDef LTDC_Pos_InitStruct;
-
- LTDC->CPSR &= ~(LTDC_CPSR_CYPOS | LTDC_CPSR_CXPOS);
-
- LTDC_Pos_InitStruct.LTDC_POSX = (uint32_t)(LTDC->CPSR >> 16);
- LTDC_Pos_InitStruct.LTDC_POSY = (uint32_t)(LTDC->CPSR & 0xFFFF);
-
- return LTDC_Pos_InitStruct;
-}
-
-/**
- * @brief Fills each LTDC_Pos_InitStruct member with its default value.
- * @param LTDC_Pos_InitStruct: pointer to a LTDC_PosTypeDef structure which will
- * be initialized.
- * @retval None
- */
-
-void LTDC_PosStructInit(LTDC_PosTypeDef* LTDC_Pos_InitStruct)
-{
- LTDC_Pos_InitStruct->LTDC_POSX = 0x00;
- LTDC_Pos_InitStruct->LTDC_POSY = 0x00;
-}
-
-/**
- * @brief Checks whether the specified LTDC's flag is set or not.
- * @param LTDC_CD: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg LTDC_CD_VDES: vertical data enable current status.
- * @arg LTDC_CD_HDES: horizontal data enable current status.
- * @arg LTDC_CD_VSYNC: Vertical Synchronization current status.
- * @arg LTDC_CD_HSYNC: Horizontal Synchronization current status.
- * @retval The new state of LTDC_CD (SET or RESET).
- */
-
-FlagStatus LTDC_GetCDStatus(uint32_t LTDC_CD)
-{
- FlagStatus bitstatus;
-
- /* Check the parameters */
- assert_param(IS_LTDC_GET_CD(LTDC_CD));
-
- if ((LTDC->CDSR & LTDC_CD) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Set and configure the color keying.
- * @param LTDC_colorkeying_InitStruct: pointer to a LTDC_ColorKeying_InitTypeDef
- * structure that contains the color keying configuration.
- * @param LTDC_layerx: Select the layer to be configured, this parameter can be
- * one of the following values: LTDC_Layer1, LTDC_Layer2
- * @retval None
- */
-
-void LTDC_ColorKeyingConfig(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct, FunctionalState NewState)
-{
- uint32_t ckgreen = 0;
- uint32_t ckred = 0;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_LTDC_CKEYING(LTDC_colorkeying_InitStruct->LTDC_ColorKeyBlue));
- assert_param(IS_LTDC_CKEYING(LTDC_colorkeying_InitStruct->LTDC_ColorKeyGreen));
- assert_param(IS_LTDC_CKEYING(LTDC_colorkeying_InitStruct->LTDC_ColorKeyRed));
-
- if (NewState != DISABLE)
- {
- /* Enable LTDC color keying by setting COLKEN bit */
- LTDC_Layerx->CR |= (uint32_t)LTDC_LxCR_COLKEN;
-
- /* Sets the color keying values */
- ckgreen = (LTDC_colorkeying_InitStruct->LTDC_ColorKeyGreen << 8);
- ckred = (LTDC_colorkeying_InitStruct->LTDC_ColorKeyRed << 16);
- LTDC_Layerx->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
- LTDC_Layerx->CKCR |= (LTDC_colorkeying_InitStruct->LTDC_ColorKeyBlue | ckgreen | ckred);
- }
- else
- {
- /* Disable LTDC color keying by clearing COLKEN bit */
- LTDC_Layerx->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
- }
-
- /* Reload shadow register */
- LTDC->SRCR = LTDC_IMReload;
-}
-
-/**
- * @brief Fills each LTDC_colorkeying_InitStruct member with its default value.
- * @param LTDC_colorkeying_InitStruct: pointer to a LTDC_ColorKeying_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-
-void LTDC_ColorKeyingStructInit(LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct)
-{
- /*!< Initialize the color keying values */
- LTDC_colorkeying_InitStruct->LTDC_ColorKeyBlue = 0x00;
- LTDC_colorkeying_InitStruct->LTDC_ColorKeyGreen = 0x00;
- LTDC_colorkeying_InitStruct->LTDC_ColorKeyRed = 0x00;
-}
-
-
-/**
- * @brief Enables or disables CLUT.
- * @param NewState: new state of CLUT.
- * @param LTDC_layerx: Select the layer to be configured, this parameter can be
- * one of the following values: LTDC_Layer1, LTDC_Layer2
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-
-void LTDC_CLUTCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable CLUT by setting CLUTEN bit */
- LTDC_Layerx->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
- }
- else
- {
- /* Disable CLUT by clearing CLUTEN bit */
- LTDC_Layerx->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
- }
-
- /* Reload shadow register */
- LTDC->SRCR = LTDC_IMReload;
-}
-
-/**
- * @brief configure the CLUT.
- * @param LTDC_CLUT_InitStruct: pointer to a LTDC_CLUT_InitTypeDef structure that contains
- * the CLUT configuration.
- * @param LTDC_layerx: Select the layer to be configured, this parameter can be
- * one of the following values: LTDC_Layer1, LTDC_Layer2
- * @retval None
- */
-
-void LTDC_CLUTInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct)
-{
- uint32_t green = 0;
- uint32_t red = 0;
- uint32_t clutadd = 0;
-
- /* Check the parameters */
- assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_CLUTAdress));
- assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_RedValue));
- assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_GreenValue));
- assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_BlueValue));
-
- /* Specifies the CLUT address and RGB value */
- green = (LTDC_CLUT_InitStruct->LTDC_GreenValue << 8);
- red = (LTDC_CLUT_InitStruct->LTDC_RedValue << 16);
- clutadd = (LTDC_CLUT_InitStruct->LTDC_CLUTAdress << 24);
- LTDC_Layerx->CLUTWR = (clutadd | LTDC_CLUT_InitStruct->LTDC_BlueValue | \
- green | red);
-}
-
-/**
- * @brief Fills each LTDC_CLUT_InitStruct member with its default value.
- * @param LTDC_CLUT_InitStruct: pointer to a LTDC_CLUT_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-
-void LTDC_CLUTStructInit(LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct)
-{
- /*!< Initialize the CLUT address and RGB values */
- LTDC_CLUT_InitStruct->LTDC_CLUTAdress = 0x00;
- LTDC_CLUT_InitStruct->LTDC_BlueValue = 0x00;
- LTDC_CLUT_InitStruct->LTDC_GreenValue = 0x00;
- LTDC_CLUT_InitStruct->LTDC_RedValue = 0x00;
-}
-
-
-/**
- * @brief reconfigure the layer position.
- * @param OffsetX: horizontal offset from start active width .
- * @param OffsetY: vertical offset from start active height.
- * @param LTDC_layerx: Select the layer to be configured, this parameter can be
- * one of the following values: LTDC_Layer1, LTDC_Layer2
- * @retval Reload of the shadow registers values must be applied after layer
- * position reconfiguration.
- */
-
-void LTDC_LayerPosition(LTDC_Layer_TypeDef* LTDC_Layerx, uint16_t OffsetX, uint16_t OffsetY)
-{
-
- uint32_t tempreg, temp;
- uint32_t horizontal_start;
- uint32_t horizontal_stop;
- uint32_t vertical_start;
- uint32_t vertical_stop;
-
- LTDC_Layerx->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
- LTDC_Layerx->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
-
- /* Reconfigures the horizontal and vertical start position */
- tempreg = LTDC->BPCR;
- horizontal_start = (tempreg >> 16) + 1 + OffsetX;
- vertical_start = (tempreg & 0xFFFF) + 1 + OffsetY;
-
- /* Reconfigures the horizontal and vertical stop position */
- /* Get the number of byte per pixel */
-
- tempreg = LTDC_Layerx->PFCR;
-
- if (tempreg == LTDC_Pixelformat_ARGB8888)
- {
- temp = 4;
- }
- else if (tempreg == LTDC_Pixelformat_RGB888)
- {
- temp = 3;
- }
- else if ((tempreg == LTDC_Pixelformat_ARGB4444) ||
- (tempreg == LTDC_Pixelformat_RGB565) ||
- (tempreg == LTDC_Pixelformat_ARGB1555) ||
- (tempreg == LTDC_Pixelformat_AL88))
- {
- temp = 2;
- }
- else
- {
- temp = 1;
- }
-
- tempreg = LTDC_Layerx->CFBLR;
- horizontal_stop = (((tempreg & 0x1FFF) - 3)/temp) + horizontal_start - 1;
-
- tempreg = LTDC_Layerx->CFBLNR;
- vertical_stop = (tempreg & 0x7FF) + vertical_start - 1;
-
- LTDC_Layerx->WHPCR = horizontal_start | (horizontal_stop << 16);
- LTDC_Layerx->WVPCR = vertical_start | (vertical_stop << 16);
-}
-
-/**
- * @brief reconfigure constant alpha.
- * @param ConstantAlpha: constant alpha value.
- * @param LTDC_layerx: Select the layer to be configured, this parameter can be
- * one of the following values: LTDC_Layer1, LTDC_Layer2
- * @retval Reload of the shadow registers values must be applied after constant
- * alpha reconfiguration.
- */
-
-void LTDC_LayerAlpha(LTDC_Layer_TypeDef* LTDC_Layerx, uint8_t ConstantAlpha)
-{
- /* reconfigure the constant alpha value */
- LTDC_Layerx->CACR = ConstantAlpha;
-}
-
-/**
- * @brief reconfigure layer address.
- * @param Address: The color frame buffer start address.
- * @param LTDC_layerx: Select the layer to be configured, this parameter can be
- * one of the following values: LTDC_Layer1, LTDC_Layer2
- * @retval Reload of the shadow registers values must be applied after layer
- * address reconfiguration.
- */
-
-void LTDC_LayerAddress(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Address)
-{
- /* Reconfigures the color frame buffer start address */
- LTDC_Layerx->CFBAR = Address;
-}
-
-/**
- * @brief reconfigure layer size.
- * @param Width: layer window width.
- * @param Height: layer window height.
- * @param LTDC_layerx: Select the layer to be configured, this parameter can be
- * one of the following values: LTDC_Layer1, LTDC_Layer2
- * @retval Reload of the shadow registers values must be applied after layer
- * size reconfiguration.
- */
-
-void LTDC_LayerSize(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Width, uint32_t Height)
-{
-
- uint8_t temp;
- uint32_t tempreg;
- uint32_t horizontal_start;
- uint32_t horizontal_stop;
- uint32_t vertical_start;
- uint32_t vertical_stop;
-
- tempreg = LTDC_Layerx->PFCR;
-
- if (tempreg == LTDC_Pixelformat_ARGB8888)
- {
- temp = 4;
- }
- else if (tempreg == LTDC_Pixelformat_RGB888)
- {
- temp = 3;
- }
- else if ((tempreg == LTDC_Pixelformat_ARGB4444) || \
- (tempreg == LTDC_Pixelformat_RGB565) || \
- (tempreg == LTDC_Pixelformat_ARGB1555) || \
- (tempreg == LTDC_Pixelformat_AL88))
- {
- temp = 2;
- }
- else
- {
- temp = 1;
- }
-
- /* update horizontal and vertical stop */
- tempreg = LTDC_Layerx->WHPCR;
- horizontal_start = (tempreg & 0x1FFF);
- horizontal_stop = Width + horizontal_start - 1;
-
- tempreg = LTDC_Layerx->WVPCR;
- vertical_start = (tempreg & 0x1FFF);
- vertical_stop = Height + vertical_start - 1;
-
- LTDC_Layerx->WHPCR = horizontal_start | (horizontal_stop << 16);
- LTDC_Layerx->WVPCR = vertical_start | (vertical_stop << 16);
-
- /* Reconfigures the color frame buffer pitch in byte */
- LTDC_Layerx->CFBLR = ((Width * temp) << 16) | ((Width * temp) + 3);
-
- /* Reconfigures the frame buffer line number */
- LTDC_Layerx->CFBLNR = Height;
-
-}
-
-/**
- * @brief reconfigure layer pixel format.
- * @param PixelFormat: reconfigure the pixel format, this parameter can be
- * one of the following values:@ref LTDC_Pixelformat.
- * @param LTDC_layerx: Select the layer to be configured, this parameter can be
- * one of the following values: LTDC_Layer1, LTDC_Layer2
- * @retval Reload of the shadow registers values must be applied after layer
- * pixel format reconfiguration.
- */
-
-void LTDC_LayerPixelFormat(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t PixelFormat)
-{
-
- uint8_t temp;
- uint32_t tempreg;
-
- tempreg = LTDC_Layerx->PFCR;
-
- if (tempreg == LTDC_Pixelformat_ARGB8888)
- {
- temp = 4;
- }
- else if (tempreg == LTDC_Pixelformat_RGB888)
- {
- temp = 3;
- }
- else if ((tempreg == LTDC_Pixelformat_ARGB4444) || \
- (tempreg == LTDC_Pixelformat_RGB565) || \
- (tempreg == LTDC_Pixelformat_ARGB1555) || \
- (tempreg == LTDC_Pixelformat_AL88))
- {
- temp = 2;
- }
- else
- {
- temp = 1;
- }
-
- tempreg = (LTDC_Layerx->CFBLR >> 16);
- tempreg = (tempreg / temp);
-
- if (PixelFormat == LTDC_Pixelformat_ARGB8888)
- {
- temp = 4;
- }
- else if (PixelFormat == LTDC_Pixelformat_RGB888)
- {
- temp = 3;
- }
- else if ((PixelFormat == LTDC_Pixelformat_ARGB4444) || \
- (PixelFormat == LTDC_Pixelformat_RGB565) || \
- (PixelFormat == LTDC_Pixelformat_ARGB1555) || \
- (PixelFormat == LTDC_Pixelformat_AL88))
- {
- temp = 2;
- }
- else
- {
- temp = 1;
- }
-
- /* Reconfigures the color frame buffer pitch in byte */
- LTDC_Layerx->CFBLR = ((tempreg * temp) << 16) | ((tempreg * temp) + 3);
-
- /* Reconfigures the color frame buffer start address */
- LTDC_Layerx->PFCR = PixelFormat;
-
-}
-
-/**
- * @}
- */
-
-/** @defgroup LTDC_Group2 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure the LTDC Interrupts
- and to get the status and clear flags and Interrupts pending bits.
-
- [..] The LTDC provides 4 Interrupts sources and 4 Flags
-
- *** Flags ***
- =============
- [..]
- (+) LTDC_FLAG_LI: Line Interrupt flag.
- (+) LTDC_FLAG_FU: FIFO Underrun Interrupt flag.
- (+) LTDC_FLAG_TERR: Transfer Error Interrupt flag.
- (+) LTDC_FLAG_RR: Register Reload interrupt flag.
-
- *** Interrupts ***
- ==================
- [..]
- (+) LTDC_IT_LI: Line Interrupt is generated when a programmed line
- is reached. The line interrupt position is programmed in
- the LTDC_LIPR register.
- (+) LTDC_IT_FU: FIFO Underrun interrupt is generated when a pixel is requested
- from an empty layer FIFO
- (+) LTDC_IT_TERR: Transfer Error interrupt is generated when an AHB bus
- error occurs during data transfer.
- (+) LTDC_IT_RR: Register Reload interrupt is generated when the shadow
- registers reload was performed during the vertical blanking
- period.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified LTDC's interrupts.
- * @param LTDC_IT: specifies the LTDC interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg LTDC_IT_LI: Line Interrupt Enable.
- * @arg LTDC_IT_FU: FIFO Underrun Interrupt Enable.
- * @arg LTDC_IT_TERR: Transfer Error Interrupt Enable.
- * @arg LTDC_IT_RR: Register Reload interrupt enable.
- * @param NewState: new state of the specified LTDC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void LTDC_ITConfig(uint32_t LTDC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_LTDC_IT(LTDC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- LTDC->IER |= LTDC_IT;
- }
- else
- {
- LTDC->IER &= (uint32_t)~LTDC_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified LTDC's flag is set or not.
- * @param LTDC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg LTDC_FLAG_LI: Line Interrupt flag.
- * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag.
- * @arg LTDC_FLAG_TERR: Transfer Error Interrupt flag.
- * @arg LTDC_FLAG_RR: Register Reload interrupt flag.
- * @retval The new state of LTDC_FLAG (SET or RESET).
- */
-FlagStatus LTDC_GetFlagStatus(uint32_t LTDC_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_LTDC_FLAG(LTDC_FLAG));
-
- if ((LTDC->ISR & LTDC_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the LTDC's pending flags.
- * @param LTDC_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg LTDC_FLAG_LI: Line Interrupt flag.
- * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag.
- * @arg LTDC_FLAG_TERR: Transfer Error Interrupt flag.
- * @arg LTDC_FLAG_RR: Register Reload interrupt flag.
- * @retval None
- */
-void LTDC_ClearFlag(uint32_t LTDC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_LTDC_FLAG(LTDC_FLAG));
-
- /* Clear the corresponding LTDC flag */
- LTDC->ICR = (uint32_t)LTDC_FLAG;
-}
-
-/**
- * @brief Checks whether the specified LTDC's interrupt has occurred or not.
- * @param LTDC_IT: specifies the LTDC interrupts sources to check.
- * This parameter can be one of the following values:
- * @arg LTDC_IT_LI: Line Interrupt Enable.
- * @arg LTDC_IT_FU: FIFO Underrun Interrupt Enable.
- * @arg LTDC_IT_TERR: Transfer Error Interrupt Enable.
- * @arg LTDC_IT_RR: Register Reload interrupt Enable.
- * @retval The new state of the LTDC_IT (SET or RESET).
- */
-ITStatus LTDC_GetITStatus(uint32_t LTDC_IT)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_LTDC_IT(LTDC_IT));
-
- if ((LTDC->ISR & LTDC_IT) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- if (((LTDC->IER & LTDC_IT) != (uint32_t)RESET) && (bitstatus != (uint32_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-
-/**
- * @brief Clears the LTDC's interrupt pending bits.
- * @param LTDC_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg LTDC_IT_LIE: Line Interrupt.
- * @arg LTDC_IT_FUIE: FIFO Underrun Interrupt.
- * @arg LTDC_IT_TERRIE: Transfer Error Interrupt.
- * @arg LTDC_IT_RRIE: Register Reload interrupt.
- * @retval None
- */
-void LTDC_ClearITPendingBit(uint32_t LTDC_IT)
-{
- /* Check the parameters */
- assert_param(IS_LTDC_IT(LTDC_IT));
-
- /* Clear the corresponding LTDC Interrupt */
- LTDC->ICR = (uint32_t)LTDC_IT;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_ltdc.h b/底盘/底盘-old/底盘/Library/stm32f4xx_ltdc.h
deleted file mode 100644
index 52087a8..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_ltdc.h
+++ /dev/null
@@ -1,495 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_ltdc.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the LTDC firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LTDC_H
-#define __STM32F4xx_LTDC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup LTDC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief LTDC Init structure definition
- */
-
-typedef struct
-{
- uint32_t LTDC_HSPolarity; /*!< configures the horizontal synchronization polarity.
- This parameter can be one value of @ref LTDC_HSPolarity */
-
- uint32_t LTDC_VSPolarity; /*!< configures the vertical synchronization polarity.
- This parameter can be one value of @ref LTDC_VSPolarity */
-
- uint32_t LTDC_DEPolarity; /*!< configures the data enable polarity. This parameter can
- be one of value of @ref LTDC_DEPolarity */
-
- uint32_t LTDC_PCPolarity; /*!< configures the pixel clock polarity. This parameter can
- be one of value of @ref LTDC_PCPolarity */
-
- uint32_t LTDC_HorizontalSync; /*!< configures the number of Horizontal synchronization
- width. This parameter must range from 0x000 to 0xFFF. */
-
- uint32_t LTDC_VerticalSync; /*!< configures the number of Vertical synchronization
- height. This parameter must range from 0x000 to 0x7FF. */
-
- uint32_t LTDC_AccumulatedHBP; /*!< configures the accumulated horizontal back porch width.
- This parameter must range from LTDC_HorizontalSync to 0xFFF. */
-
- uint32_t LTDC_AccumulatedVBP; /*!< configures the accumulated vertical back porch height.
- This parameter must range from LTDC_VerticalSync to 0x7FF. */
-
- uint32_t LTDC_AccumulatedActiveW; /*!< configures the accumulated active width. This parameter
- must range from LTDC_AccumulatedHBP to 0xFFF. */
-
- uint32_t LTDC_AccumulatedActiveH; /*!< configures the accumulated active height. This parameter
- must range from LTDC_AccumulatedVBP to 0x7FF. */
-
- uint32_t LTDC_TotalWidth; /*!< configures the total width. This parameter
- must range from LTDC_AccumulatedActiveW to 0xFFF. */
-
- uint32_t LTDC_TotalHeigh; /*!< configures the total height. This parameter
- must range from LTDC_AccumulatedActiveH to 0x7FF. */
-
- uint32_t LTDC_BackgroundRedValue; /*!< configures the background red value.
- This parameter must range from 0x00 to 0xFF. */
-
- uint32_t LTDC_BackgroundGreenValue; /*!< configures the background green value.
- This parameter must range from 0x00 to 0xFF. */
-
- uint32_t LTDC_BackgroundBlueValue; /*!< configures the background blue value.
- This parameter must range from 0x00 to 0xFF. */
-} LTDC_InitTypeDef;
-
-/**
- * @brief LTDC Layer structure definition
- */
-
-typedef struct
-{
- uint32_t LTDC_HorizontalStart; /*!< Configures the Window Horizontal Start Position.
- This parameter must range from 0x000 to 0xFFF. */
-
- uint32_t LTDC_HorizontalStop; /*!< Configures the Window Horizontal Stop Position.
- This parameter must range from 0x0000 to 0xFFFF. */
-
- uint32_t LTDC_VerticalStart; /*!< Configures the Window vertical Start Position.
- This parameter must range from 0x000 to 0xFFF. */
-
- uint32_t LTDC_VerticalStop; /*!< Configures the Window vaertical Stop Position.
- This parameter must range from 0x0000 to 0xFFFF. */
-
- uint32_t LTDC_PixelFormat; /*!< Specifies the pixel format. This parameter can be
- one of value of @ref LTDC_Pixelformat */
-
- uint32_t LTDC_ConstantAlpha; /*!< Specifies the constant alpha used for blending.
- This parameter must range from 0x00 to 0xFF. */
-
- uint32_t LTDC_DefaultColorBlue; /*!< Configures the default blue value.
- This parameter must range from 0x00 to 0xFF. */
-
- uint32_t LTDC_DefaultColorGreen; /*!< Configures the default green value.
- This parameter must range from 0x00 to 0xFF. */
-
- uint32_t LTDC_DefaultColorRed; /*!< Configures the default red value.
- This parameter must range from 0x00 to 0xFF. */
-
- uint32_t LTDC_DefaultColorAlpha; /*!< Configures the default alpha value.
- This parameter must range from 0x00 to 0xFF. */
-
- uint32_t LTDC_BlendingFactor_1; /*!< Select the blending factor 1. This parameter
- can be one of value of @ref LTDC_BlendingFactor1 */
-
- uint32_t LTDC_BlendingFactor_2; /*!< Select the blending factor 2. This parameter
- can be one of value of @ref LTDC_BlendingFactor2 */
-
- uint32_t LTDC_CFBStartAdress; /*!< Configures the color frame buffer address */
-
- uint32_t LTDC_CFBLineLength; /*!< Configures the color frame buffer line length.
- This parameter must range from 0x0000 to 0x1FFF. */
-
- uint32_t LTDC_CFBPitch; /*!< Configures the color frame buffer pitch in bytes.
- This parameter must range from 0x0000 to 0x1FFF. */
-
- uint32_t LTDC_CFBLineNumber; /*!< Specifies the number of line in frame buffer.
- This parameter must range from 0x000 to 0x7FF. */
-} LTDC_Layer_InitTypeDef;
-
-/**
- * @brief LTDC Position structure definition
- */
-typedef struct
-{
- uint32_t LTDC_POSX; /*!< Current X Position */
- uint32_t LTDC_POSY; /*!< Current Y Position */
-} LTDC_PosTypeDef;
-
-/**
- * @brief LTDC RGB structure definition
- */
-typedef struct
-{
- uint32_t LTDC_BlueWidth; /*!< Blue width */
- uint32_t LTDC_GreenWidth; /*!< Green width */
- uint32_t LTDC_RedWidth; /*!< Red width */
-} LTDC_RGBTypeDef;
-
-/**
- * @brief LTDC Color Keying structure definition
- */
-typedef struct
-{
- uint32_t LTDC_ColorKeyBlue; /*!< Configures the color key blue value.
- This parameter must range from 0x00 to 0xFF. */
-
- uint32_t LTDC_ColorKeyGreen; /*!< Configures the color key green value.
- This parameter must range from 0x00 to 0xFF. */
-
- uint32_t LTDC_ColorKeyRed; /*!< Configures the color key red value.
- This parameter must range from 0x00 to 0xFF. */
-} LTDC_ColorKeying_InitTypeDef;
-
-/**
- * @brief LTDC CLUT structure definition
- */
-typedef struct
-{
- uint32_t LTDC_CLUTAdress; /*!< Configures the CLUT address.
- This parameter must range from 0x00 to 0xFF. */
-
- uint32_t LTDC_BlueValue; /*!< Configures the blue value.
- This parameter must range from 0x00 to 0xFF. */
-
- uint32_t LTDC_GreenValue; /*!< Configures the green value.
- This parameter must range from 0x00 to 0xFF. */
-
- uint32_t LTDC_RedValue; /*!< Configures the red value.
- This parameter must range from 0x00 to 0xFF. */
-} LTDC_CLUT_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup LTDC_Exported_Constants
- * @{
- */
-
-/** @defgroup LTDC_SYNC
- * @{
- */
-
-#define LTDC_HorizontalSYNC ((uint32_t)0x00000FFF)
-#define LTDC_VerticalSYNC ((uint32_t)0x000007FF)
-
-#define IS_LTDC_HSYNC(HSYNC) ((HSYNC) <= LTDC_HorizontalSYNC)
-#define IS_LTDC_VSYNC(VSYNC) ((VSYNC) <= LTDC_VerticalSYNC)
-#define IS_LTDC_AHBP(AHBP) ((AHBP) <= LTDC_HorizontalSYNC)
-#define IS_LTDC_AVBP(AVBP) ((AVBP) <= LTDC_VerticalSYNC)
-#define IS_LTDC_AAW(AAW) ((AAW) <= LTDC_HorizontalSYNC)
-#define IS_LTDC_AAH(AAH) ((AAH) <= LTDC_VerticalSYNC)
-#define IS_LTDC_TOTALW(TOTALW) ((TOTALW) <= LTDC_HorizontalSYNC)
-#define IS_LTDC_TOTALH(TOTALH) ((TOTALH) <= LTDC_VerticalSYNC)
-/**
- * @}
- */
-
-/** @defgroup LTDC_HSPolarity
- * @{
- */
-#define LTDC_HSPolarity_AL ((uint32_t)0x00000000) /*!< Horizontal Synchronization is active low. */
-#define LTDC_HSPolarity_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */
-
-#define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPolarity_AL) || \
- ((HSPOL) == LTDC_HSPolarity_AH))
-/**
- * @}
- */
-
-/** @defgroup LTDC_VSPolarity
- * @{
- */
-#define LTDC_VSPolarity_AL ((uint32_t)0x00000000) /*!< Vertical Synchronization is active low. */
-#define LTDC_VSPolarity_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */
-
-#define IS_LTDC_VSPOL(VSPOL) (((VSPOL) == LTDC_VSPolarity_AL) || \
- ((VSPOL) == LTDC_VSPolarity_AH))
-/**
- * @}
- */
-
-/** @defgroup LTDC_DEPolarity
- * @{
- */
-#define LTDC_DEPolarity_AL ((uint32_t)0x00000000) /*!< Data Enable, is active low. */
-#define LTDC_DEPolarity_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */
-
-#define IS_LTDC_DEPOL(DEPOL) (((DEPOL) == LTDC_VSPolarity_AL) || \
- ((DEPOL) == LTDC_DEPolarity_AH))
-/**
- * @}
- */
-
-/** @defgroup LTDC_PCPolarity
- * @{
- */
-#define LTDC_PCPolarity_IPC ((uint32_t)0x00000000) /*!< input pixel clock. */
-#define LTDC_PCPolarity_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */
-
-#define IS_LTDC_PCPOL(PCPOL) (((PCPOL) == LTDC_PCPolarity_IPC) || \
- ((PCPOL) == LTDC_PCPolarity_IIPC))
-/**
- * @}
- */
-
-/** @defgroup LTDC_Reload
- * @{
- */
-#define LTDC_IMReload LTDC_SRCR_IMR /*!< Immediately Reload. */
-#define LTDC_VBReload LTDC_SRCR_VBR /*!< Vertical Blanking Reload. */
-
-#define IS_LTDC_RELOAD(RELOAD) (((RELOAD) == LTDC_IMReload) || \
- ((RELOAD) == LTDC_VBReload))
-/**
- * @}
- */
-
-/** @defgroup LTDC_Back_Color
- * @{
- */
-#define LTDC_Back_Color ((uint32_t)0x000000FF)
-
-#define IS_LTDC_BackBlueValue(BBLUE) ((BBLUE) <= LTDC_Back_Color)
-#define IS_LTDC_BackGreenValue(BGREEN) ((BGREEN) <= LTDC_Back_Color)
-#define IS_LTDC_BackRedValue(BRED) ((BRED) <= LTDC_Back_Color)
-/**
- * @}
- */
-
-/** @defgroup LTDC_Position
- * @{
- */
-#define LTDC_POS_CY LTDC_CPSR_CYPOS
-#define LTDC_POS_CX LTDC_CPSR_CXPOS
-
-#define IS_LTDC_GET_POS(POS) (((POS) <= LTDC_POS_CY))
-/**
- * @}
- */
-
-/** @defgroup LTDC_LIPosition
- * @{
- */
-#define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF)
-/**
- * @}
- */
-
-/** @defgroup LTDC_CurrentStatus
- * @{
- */
-#define LTDC_CD_VDES LTDC_CDSR_VDES
-#define LTDC_CD_HDES LTDC_CDSR_HDES
-#define LTDC_CD_VSYNC LTDC_CDSR_VSYNCS
-#define LTDC_CD_HSYNC LTDC_CDSR_HSYNCS
-
-#define IS_LTDC_GET_CD(CD) (((CD) == LTDC_CD_VDES) || ((CD) == LTDC_CD_HDES) || \
- ((CD) == LTDC_CD_VSYNC) || ((CD) == LTDC_CD_HSYNC))
-/**
- * @}
- */
-
-/** @defgroup LTDC_Interrupts
- * @{
- */
-#define LTDC_IT_LI LTDC_IER_LIE
-#define LTDC_IT_FU LTDC_IER_FUIE
-#define LTDC_IT_TERR LTDC_IER_TERRIE
-#define LTDC_IT_RR LTDC_IER_RRIE
-
-#define IS_LTDC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF0) == 0x00) && ((IT) != 0x00))
-
-/**
- * @}
- */
-
-/** @defgroup LTDC_Flag
- * @{
- */
-#define LTDC_FLAG_LI LTDC_ISR_LIF
-#define LTDC_FLAG_FU LTDC_ISR_FUIF
-#define LTDC_FLAG_TERR LTDC_ISR_TERRIF
-#define LTDC_FLAG_RR LTDC_ISR_RRIF
-
-#define IS_LTDC_FLAG(FLAG) (((FLAG) == LTDC_FLAG_LI) || ((FLAG) == LTDC_FLAG_FU) || \
- ((FLAG) == LTDC_FLAG_TERR) || ((FLAG) == LTDC_FLAG_RR))
-/**
- * @}
- */
-
-/** @defgroup LTDC_Pixelformat
- * @{
- */
-#define LTDC_Pixelformat_ARGB8888 ((uint32_t)0x00000000)
-#define LTDC_Pixelformat_RGB888 ((uint32_t)0x00000001)
-#define LTDC_Pixelformat_RGB565 ((uint32_t)0x00000002)
-#define LTDC_Pixelformat_ARGB1555 ((uint32_t)0x00000003)
-#define LTDC_Pixelformat_ARGB4444 ((uint32_t)0x00000004)
-#define LTDC_Pixelformat_L8 ((uint32_t)0x00000005)
-#define LTDC_Pixelformat_AL44 ((uint32_t)0x00000006)
-#define LTDC_Pixelformat_AL88 ((uint32_t)0x00000007)
-
-#define IS_LTDC_Pixelformat(Pixelformat) (((Pixelformat) == LTDC_Pixelformat_ARGB8888) || ((Pixelformat) == LTDC_Pixelformat_RGB888) || \
- ((Pixelformat) == LTDC_Pixelformat_RGB565) || ((Pixelformat) == LTDC_Pixelformat_ARGB1555) || \
- ((Pixelformat) == LTDC_Pixelformat_ARGB4444) || ((Pixelformat) == LTDC_Pixelformat_L8) || \
- ((Pixelformat) == LTDC_Pixelformat_AL44) || ((Pixelformat) == LTDC_Pixelformat_AL88))
-
-/**
- * @}
- */
-
-/** @defgroup LTDC_BlendingFactor1
- * @{
- */
-#define LTDC_BlendingFactor1_CA ((uint32_t)0x00000400)
-#define LTDC_BlendingFactor1_PAxCA ((uint32_t)0x00000600)
-
-#define IS_LTDC_BlendingFactor1(BlendingFactor1) (((BlendingFactor1) == LTDC_BlendingFactor1_CA) || ((BlendingFactor1) == LTDC_BlendingFactor1_PAxCA))
-/**
- * @}
- */
-
-/** @defgroup LTDC_BlendingFactor2
- * @{
- */
-#define LTDC_BlendingFactor2_CA ((uint32_t)0x00000005)
-#define LTDC_BlendingFactor2_PAxCA ((uint32_t)0x00000007)
-
-#define IS_LTDC_BlendingFactor2(BlendingFactor2) (((BlendingFactor2) == LTDC_BlendingFactor2_CA) || ((BlendingFactor2) == LTDC_BlendingFactor2_PAxCA))
-/**
- * @}
- */
-
-/** @defgroup LTDC_LAYER_Config
- * @{
- */
-#define LTDC_STOPPosition ((uint32_t)0x0000FFFF)
-#define LTDC_STARTPosition ((uint32_t)0x00000FFF)
-
-#define LTDC_DefaultColorConfig ((uint32_t)0x000000FF)
-#define LTDC_ColorFrameBuffer ((uint32_t)0x00001FFF)
-#define LTDC_LineNumber ((uint32_t)0x000007FF)
-
-#define IS_LTDC_HCONFIGST(HCONFIGST) ((HCONFIGST) <= LTDC_STARTPosition)
-#define IS_LTDC_HCONFIGSP(HCONFIGSP) ((HCONFIGSP) <= LTDC_STOPPosition)
-#define IS_LTDC_VCONFIGST(VCONFIGST) ((VCONFIGST) <= LTDC_STARTPosition)
-#define IS_LTDC_VCONFIGSP(VCONFIGSP) ((VCONFIGSP) <= LTDC_STOPPosition)
-
-#define IS_LTDC_DEFAULTCOLOR(DEFAULTCOLOR) ((DEFAULTCOLOR) <= LTDC_DefaultColorConfig)
-
-#define IS_LTDC_CFBP(CFBP) ((CFBP) <= LTDC_ColorFrameBuffer)
-#define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_ColorFrameBuffer)
-
-#define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LineNumber)
-/**
- * @}
- */
-
-/** @defgroup LTDC_colorkeying_Config
- * @{
- */
-#define LTDC_colorkeyingConfig ((uint32_t)0x000000FF)
-
-#define IS_LTDC_CKEYING(CKEYING) ((CKEYING) <= LTDC_colorkeyingConfig)
-/**
- * @}
- */
-
-/** @defgroup LTDC_CLUT_Config
- * @{
- */
-
-#define LTDC_CLUTWR ((uint32_t)0x000000FF)
-
-#define IS_LTDC_CLUTWR(CLUTWR) ((CLUTWR) <= LTDC_CLUTWR)
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/* Function used to set the LTDC configuration to the default reset state *****/
-void LTDC_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void LTDC_Init(LTDC_InitTypeDef* LTDC_InitStruct);
-void LTDC_StructInit(LTDC_InitTypeDef* LTDC_InitStruct);
-void LTDC_Cmd(FunctionalState NewState);
-void LTDC_DitherCmd(FunctionalState NewState);
-LTDC_RGBTypeDef LTDC_GetRGBWidth(void);
-void LTDC_RGBStructInit(LTDC_RGBTypeDef* LTDC_RGB_InitStruct);
-void LTDC_LIPConfig(uint32_t LTDC_LIPositionConfig);
-void LTDC_ReloadConfig(uint32_t LTDC_Reload);
-void LTDC_LayerInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_Layer_InitTypeDef* LTDC_Layer_InitStruct);
-void LTDC_LayerStructInit(LTDC_Layer_InitTypeDef * LTDC_Layer_InitStruct);
-void LTDC_LayerCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState);
-LTDC_PosTypeDef LTDC_GetPosStatus(void);
-void LTDC_PosStructInit(LTDC_PosTypeDef* LTDC_Pos_InitStruct);
-FlagStatus LTDC_GetCDStatus(uint32_t LTDC_CD);
-void LTDC_ColorKeyingConfig(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct, FunctionalState NewState);
-void LTDC_ColorKeyingStructInit(LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct);
-void LTDC_CLUTCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState);
-void LTDC_CLUTInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct);
-void LTDC_CLUTStructInit(LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct);
-void LTDC_LayerPosition(LTDC_Layer_TypeDef* LTDC_Layerx, uint16_t OffsetX, uint16_t OffsetY);
-void LTDC_LayerAlpha(LTDC_Layer_TypeDef* LTDC_Layerx, uint8_t ConstantAlpha);
-void LTDC_LayerAddress(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Address);
-void LTDC_LayerSize(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Width, uint32_t Height);
-void LTDC_LayerPixelFormat(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t PixelFormat);
-
-/* Interrupts and flags management functions **********************************/
-void LTDC_ITConfig(uint32_t LTDC_IT, FunctionalState NewState);
-FlagStatus LTDC_GetFlagStatus(uint32_t LTDC_FLAG);
-void LTDC_ClearFlag(uint32_t LTDC_FLAG);
-ITStatus LTDC_GetITStatus(uint32_t LTDC_IT);
-void LTDC_ClearITPendingBit(uint32_t LTDC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_LTDC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_pwr.c b/底盘/底盘-old/底盘/Library/stm32f4xx_pwr.c
deleted file mode 100644
index 1eb8154..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_pwr.c
+++ /dev/null
@@ -1,1045 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_pwr.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Power Controller (PWR) peripheral:
- * + Backup Domain Access
- * + PVD configuration
- * + WakeUp pin configuration
- * + Main and Backup Regulators configuration
- * + FLASH Power Down configuration
- * + Low Power modes configuration
- * + Flags management
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_pwr.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup PWR
- * @brief PWR driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* --------- PWR registers bit address in the alias region ---------- */
-#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
-
-/* --- CR Register ---*/
-
-/* Alias word address of DBP bit */
-#define CR_OFFSET (PWR_OFFSET + 0x00)
-#define DBP_BitNumber 0x08
-#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
-
-/* Alias word address of PVDE bit */
-#define PVDE_BitNumber 0x04
-#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
-
-/* Alias word address of FPDS bit */
-#define FPDS_BitNumber 0x09
-#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
-
-/* Alias word address of PMODE bit */
-#define PMODE_BitNumber 0x0E
-#define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
-
-/* Alias word address of ODEN bit */
-#define ODEN_BitNumber 0x10
-#define CR_ODEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODEN_BitNumber * 4))
-
-/* Alias word address of ODSWEN bit */
-#define ODSWEN_BitNumber 0x11
-#define CR_ODSWEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4))
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
-/* Alias word address of MRUDS bit */
-#define MRUDS_BitNumber 0x0B
-#define CR_MRUDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRUDS_BitNumber * 4))
-
-/* Alias word address of LPUDS bit */
-#define LPUDS_BitNumber 0x0A
-#define CR_LPUDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LPUDS_BitNumber * 4))
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx */
-
-#if defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG) || defined(STM32F413_423xx)
-/* Alias word address of MRLVDS bit */
-#define MRLVDS_BitNumber 0x0B
-#define CR_MRLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRLVDS_BitNumber * 4))
-
-/* Alias word address of LPLVDS bit */
-#define LPLVDS_BitNumber 0x0A
-#define CR_LPLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LPLVDS_BitNumber * 4))
-#endif /* STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG || STM32F413_423xx */
-
-/* --- CSR Register ---*/
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
-/* Alias word address of EWUP bit */
-#define CSR_OFFSET (PWR_OFFSET + 0x04)
-#define EWUP_BitNumber 0x08
-#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */
-
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-/* Alias word address of EWUP2 bit */
-#define CSR_OFFSET (PWR_OFFSET + 0x04)
-#define EWUP1_BitNumber 0x08
-#define CSR_EWUP1_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP1_BitNumber * 4))
-#define EWUP2_BitNumber 0x07
-#define CSR_EWUP2_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP2_BitNumber * 4))
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
-#define EWUP3_BitNumber 0x06
-#define CSR_EWUP3_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP2_BitNumber * 4))
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
-
-/* Alias word address of BRE bit */
-#define BRE_BitNumber 0x09
-#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
-
-/* ------------------ PWR registers bit mask ------------------------ */
-
-/* CR register bit mask */
-#define CR_DS_MASK ((uint32_t)0xFFFFF3FC)
-#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
-#define CR_VOS_MASK ((uint32_t)0xFFFF3FFF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup PWR_Private_Functions
- * @{
- */
-
-/** @defgroup PWR_Group1 Backup Domain Access function
- * @brief Backup Domain Access function
- *
-@verbatim
- ===============================================================================
- ##### Backup Domain Access function #####
- ===============================================================================
- [..]
- After reset, the backup domain (RTC registers, RTC backup data
- registers and backup SRAM) is protected against possible unwanted
- write accesses.
- To enable access to the RTC Domain and RTC registers, proceed as follows:
- (+) Enable the Power Controller (PWR) APB1 interface clock using the
- RCC_APB1PeriphClockCmd() function.
- (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the PWR peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void PWR_DeInit(void)
-{
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
-}
-
-/**
- * @brief Enables or disables access to the backup domain (RTC registers, RTC
- * backup data registers and backup SRAM).
- * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
- * Backup Domain Access should be kept enabled.
- * @param NewState: new state of the access to the backup domain.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_BackupAccessCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group2 PVD configuration functions
- * @brief PVD configuration functions
- *
-@verbatim
- ===============================================================================
- ##### PVD configuration functions #####
- ===============================================================================
- [..]
- (+) The PVD is used to monitor the VDD power supply by comparing it to a
- threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
- (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
- than the PVD threshold. This event is internally connected to the EXTI
- line16 and can generate an interrupt if enabled through the EXTI registers.
- (+) The PVD is stopped in Standby mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
- * @param PWR_PVDLevel: specifies the PVD detection level
- * This parameter can be one of the following values:
- * @arg PWR_PVDLevel_0
- * @arg PWR_PVDLevel_1
- * @arg PWR_PVDLevel_2
- * @arg PWR_PVDLevel_3
- * @arg PWR_PVDLevel_4
- * @arg PWR_PVDLevel_5
- * @arg PWR_PVDLevel_6
- * @arg PWR_PVDLevel_7
- * @note Refer to the electrical characteristics of your device datasheet for
- * more details about the voltage threshold corresponding to each
- * detection level.
- * @retval None
- */
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
-
- tmpreg = PWR->CR;
-
- /* Clear PLS[7:5] bits */
- tmpreg &= CR_PLS_MASK;
-
- /* Set PLS[7:5] bits according to PWR_PVDLevel value */
- tmpreg |= PWR_PVDLevel;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Power Voltage Detector(PVD).
- * @param NewState: new state of the PVD.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_PVDCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group3 WakeUp pin configuration functions
- * @brief WakeUp pin configuration functions
- *
-@verbatim
- ===============================================================================
- ##### WakeUp pin configuration functions #####
- ===============================================================================
- [..]
- (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
- forced in input pull down configuration and is active on rising edges.
- (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
- (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13
- (++) For STM32F410xx/STM32F412xG/STM32F413_423xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01
-@endverbatim
- * @{
- */
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
-/**
- * @brief Enables or disables the WakeUp Pin functionality.
- * @param NewState: new state of the WakeUp Pin functionality.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_WakeUpPinCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
-}
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
-
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-/**
- * @brief Enables or disables the WakeUp Pin functionality.
- * @param PWR_WakeUpPinx: specifies the WakeUp Pin.
- * This parameter can be one of the following values:
- * @arg PWR_WakeUp_Pin1: WKUP1 pin is used for wakeup from Standby mode.
- * @arg PWR_WakeUp_Pin2: WKUP2 pin is used for wakeup from Standby mode.
- * @arg PWR_WakeUp_Pin3: WKUP3 pin is used for wakeup from Standby mode.(only for STM32F410xx, STM32F412xG and STM32F413_423xx Devices)
- * @param NewState: new state of the WakeUp Pin functionality.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPinx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_PWR_WAKEUP_PIN(NewState));
- if(PWR_WakeUpPinx == PWR_WakeUp_Pin1) /* PWR_WakeUp_Pin1 */
- {
- *(__IO uint32_t *) CSR_EWUP1_BB = (uint32_t)NewState;
- }
-#if defined(STM32F410xx)|| defined(STM32F412xG) || defined(STM32F413_423xx)
- else if(PWR_WakeUpPinx == PWR_WakeUp_Pin3) /* PWR_WakeUp_Pin3 */
- {
- *(__IO uint32_t *) CSR_EWUP3_BB = (uint32_t)NewState;
- }
-#endif /* STM32F410xx */
- else /* PWR_WakeUp_Pin2 */
- {
- *(__IO uint32_t *) CSR_EWUP2_BB = (uint32_t)NewState;
- }
-}
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group4 Main and Backup Regulators configuration functions
- * @brief Main and Backup Regulators configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Main and Backup Regulators configuration functions #####
- ===============================================================================
- [..]
- (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
- the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
- retained even in Standby or VBAT mode when the low power backup regulator
- is enabled. It can be considered as an internal EEPROM when VBAT is
- always present. You can use the PWR_BackupRegulatorCmd() function to
- enable the low power backup regulator and use the PWR_GetFlagStatus
- (PWR_FLAG_BRR) to check if it is ready or not.
-
- (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
- the backup SRAM is powered from VDD which replaces the VBAT power supply to
- save battery life.
-
- (+) The backup SRAM is not mass erased by an tamper event. It is read
- protected to prevent confidential data, such as cryptographic private
- key, from being accessed. The backup SRAM can be erased only through
- the Flash interface when a protection level change from level 1 to
- level 0 is requested.
- -@- Refer to the description of Read protection (RDP) in the reference manual.
-
- (+) The main internal regulator can be configured to have a tradeoff between
- performance and power consumption when the device does not operate at
- the maximum frequency.
- (+) For STM32F405xx/407xx and STM32F415xx/417xx Devices, the regulator can be
- configured on the fly through PWR_MainRegulatorModeConfig() function which
- configure VOS bit in PWR_CR register:
- (++) When this bit is set (Regulator voltage output Scale 1 mode selected)
- the System frequency can go up to 168 MHz.
- (++) When this bit is reset (Regulator voltage output Scale 2 mode selected)
- the System frequency can go up to 144 MHz.
-
- (+) For STM32F42xxx/43xxx Devices, the regulator can be configured through
- PWR_MainRegulatorModeConfig() function which configure VOS[1:0] bits in
- PWR_CR register:
- which configure VOS[1:0] bits in PWR_CR register:
- (++) When VOS[1:0] = 11 (Regulator voltage output Scale 1 mode selected)
- the System frequency can go up to 168 MHz.
- (++) When VOS[1:0] = 10 (Regulator voltage output Scale 2 mode selected)
- the System frequency can go up to 144 MHz.
- (++) When VOS[1:0] = 01 (Regulator voltage output Scale 3 mode selected)
- the System frequency can go up to 120 MHz.
-
- (+) For STM32F42xxx/43xxx Devices, the scale can be modified only when the PLL
- is OFF and the HSI or HSE clock source is selected as system clock.
- The new value programmed is active only when the PLL is ON.
- When the PLL is OFF, the voltage scale 3 is automatically selected.
- Refer to the datasheets for more details.
-
- (+) For STM32F42xxx/43xxx Devices, in Run mode: the main regulator has
- 2 operating modes available:
- (++) Normal mode: The CPU and core logic operate at maximum frequency at a given
- voltage scaling (scale 1, scale 2 or scale 3)
- (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
- higher frequency than the normal mode for a given voltage scaling (scale 1,
- scale 2 or scale 3). This mode is enabled through PWR_OverDriveCmd() function and
- PWR_OverDriveSWCmd() function, to enter or exit from Over-drive mode please follow
- the sequence described in Reference manual.
-
- (+) For STM32F42xxx/43xxx Devices, in Stop mode: the main regulator or low power regulator
- supplies a low power voltage to the 1.2V domain, thus preserving the content of registers
- and internal SRAM. 2 operating modes are available:
- (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
- available when the main regulator or the low power regulator is used in Scale 3 or
- low voltage mode.
- (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
- available when the main regulator or the low power regulator is in low voltage mode.
- This mode is enabled through PWR_UnderDriveCmd() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the Backup Regulator.
- * @param NewState: new state of the Backup Regulator.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_BackupRegulatorCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the main internal regulator output voltage.
- * @param PWR_Regulator_Voltage: specifies the regulator output voltage to achieve
- * a tradeoff between performance and power consumption when the device does
- * not operate at the maximum frequency (refer to the datasheets for more details).
- * This parameter can be one of the following values:
- * @arg PWR_Regulator_Voltage_Scale1: Regulator voltage output Scale 1 mode,
- * System frequency up to 168 MHz.
- * @arg PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode,
- * System frequency up to 144 MHz.
- * @arg PWR_Regulator_Voltage_Scale3: Regulator voltage output Scale 3 mode,
- * System frequency up to 120 MHz (only for STM32F42xxx/43xxx devices)
- * @retval None
- */
-void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage));
-
- tmpreg = PWR->CR;
-
- /* Clear VOS[15:14] bits */
- tmpreg &= CR_VOS_MASK;
-
- /* Set VOS[15:14] bits according to PWR_Regulator_Voltage value */
- tmpreg |= PWR_Regulator_Voltage;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Over-Drive.
- *
- * @note This function can be used only for STM32F42xxx/STM3243xxx devices.
- * This mode allows the CPU and the core logic to operate at a higher frequency
- * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
- *
- * @note It is recommended to enter or exit Over-drive mode when the application is not running
- * critical tasks and when the system clock source is either HSI or HSE.
- * During the Over-drive switch activation, no peripheral clocks should be enabled.
- * The peripheral clocks must be enabled once the Over-drive mode is activated.
- *
- * @param NewState: new state of the Over Drive mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_OverDriveCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Set/Reset the ODEN bit to enable/disable the Over Drive mode */
- *(__IO uint32_t *) CR_ODEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the Over-Drive switching.
- *
- * @note This function can be used only for STM32F42xxx/STM3243xxx devices.
- *
- * @param NewState: new state of the Over Drive switching mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_OverDriveSWCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Set/Reset the ODSWEN bit to enable/disable the Over Drive switching mode */
- *(__IO uint32_t *) CR_ODSWEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the Under-Drive mode.
- *
- * @note This function can be used only for STM32F42xxx/STM3243xxx devices.
- * @note This mode is enabled only with STOP low power mode.
- * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
- * mode is only available when the main regulator or the low power regulator
- * is in low voltage mode
- *
- * @note If the Under-drive mode was enabled, it is automatically disabled after
- * exiting Stop mode.
- * When the voltage regulator operates in Under-drive mode, an additional
- * startup delay is induced when waking up from Stop mode.
- *
- * @param NewState: new state of the Under Drive mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_UnderDriveCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the UDEN[1:0] bits to enable the Under Drive mode */
- PWR->CR |= (uint32_t)PWR_CR_UDEN;
- }
- else
- {
- /* Reset the UDEN[1:0] bits to disable the Under Drive mode */
- PWR->CR &= (uint32_t)(~PWR_CR_UDEN);
- }
-}
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
-/**
- * @brief Enables or disables the Main Regulator under drive mode.
- *
- * @note This mode is only available for STM32F427_437xx/STM32F429_439xx/STM32F446xx devices.
- *
- * @param NewState: new state of the Main Regulator Under Drive mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_MainRegulatorUnderDriveCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- *(__IO uint32_t *) CR_MRUDS_BB = (uint32_t)ENABLE;
- }
- else
- {
- *(__IO uint32_t *) CR_MRUDS_BB = (uint32_t)DISABLE;
- }
-}
-
-/**
- * @brief Enables or disables the Low Power Regulator under drive mode.
- *
- * @note This mode is only available for STM32F427_437xx/STM32F429_439xx/STM32F446xx devices.
- *
- * @param NewState: new state of the Low Power Regulator Under Drive mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_LowRegulatorUnderDriveCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- *(__IO uint32_t *) CR_LPUDS_BB = (uint32_t)ENABLE;
- }
- else
- {
- *(__IO uint32_t *) CR_LPUDS_BB = (uint32_t)DISABLE;
- }
-}
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx */
-
-#if defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG) || defined(STM32F413_423xx)
-/**
- * @brief Enables or disables the Main Regulator low voltage mode.
- *
- * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412xG/STM32F413_423xx devices.
- *
- * @param NewState: new state of the Main Regulator Low Voltage mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE;
- }
- else
- {
- *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE;
- }
-}
-
-/**
- * @brief Enables or disables the Low Power Regulator low voltage mode.
- *
- * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412xG/STM32F413_423xx devices.
- *
- * @param NewState: new state of the Low Power Regulator Low Voltage mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE;
- }
- else
- {
- *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE;
- }
-}
-#endif /* STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG || STM32F413_423xx */
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group5 FLASH Power Down configuration functions
- * @brief FLASH Power Down configuration functions
- *
-@verbatim
- ===============================================================================
- ##### FLASH Power Down configuration functions #####
- ===============================================================================
- [..]
- (+) By setting the FPDS bit in the PWR_CR register by using the
- PWR_FlashPowerDownCmd() function, the Flash memory also enters power
- down mode when the device enters Stop mode. When the Flash memory
- is in power down mode, an additional startup delay is incurred when
- waking up from Stop mode.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the Flash Power Down in STOP mode.
- * @param NewState: new state of the Flash power mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_FlashPowerDownCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group6 Low Power modes configuration functions
- * @brief Low Power modes configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Low Power modes configuration functions #####
- ===============================================================================
- [..]
- The devices feature 3 low-power modes:
- (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
- (+) Stop mode: all clocks are stopped, regulator running, regulator
- in low power mode
- (+) Standby mode: 1.2V domain powered off.
-
- *** Sleep mode ***
- ==================
- [..]
- (+) Entry:
- (++) The Sleep mode is entered by using the __WFI() or __WFE() functions.
- (+) Exit:
- (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
- controller (NVIC) can wake up the device from Sleep mode.
-
- *** Stop mode ***
- =================
- [..]
- In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
- and the HSE RC oscillators are disabled. Internal SRAM and register contents
- are preserved.
- The voltage regulator can be configured either in normal or low-power mode.
- To minimize the consumption In Stop mode, FLASH can be powered off before
- entering the Stop mode. It can be switched on again by software after exiting
- the Stop mode using the PWR_FlashPowerDownCmd() function.
-
- (+) Entry:
- (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_MainRegulator_ON)
- function with:
- (+++) Main regulator ON.
- (+++) Low Power regulator ON.
- (+) Exit:
- (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
-
- *** Standby mode ***
- ====================
- [..]
- The Standby mode allows to achieve the lowest power consumption. It is based
- on the Cortex-M4 deepsleep mode, with the voltage regulator disabled.
- The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
- the HSE oscillator are also switched off. SRAM and register contents are lost
- except for the RTC registers, RTC backup registers, backup SRAM and Standby
- circuitry.
-
- The voltage regulator is OFF.
-
- (+) Entry:
- (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
- (+) Exit:
- (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
- tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
-
- *** Auto-wakeup (AWU) from low-power mode ***
- =============================================
- [..]
- The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
- Wakeup event, a tamper event, a time-stamp event, or a comparator event,
- without depending on an external interrupt (Auto-wakeup mode).
-
- (#) RTC auto-wakeup (AWU) from the Stop mode
-
- (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
- (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
- or Event modes) using the EXTI_Init() function.
- (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
- (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
- and RTC_AlarmCmd() functions.
- (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
- is necessary to:
- (+++) Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt
- or Event modes) using the EXTI_Init() function.
- (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
- function
- (+++) Configure the RTC to detect the tamper or time stamp event using the
- RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
- functions.
- (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
- (+++) Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt
- or Event modes) using the EXTI_Init() function.
- (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
- (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
- RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
-
- (#) RTC auto-wakeup (AWU) from the Standby mode
-
- (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
- (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
- (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
- and RTC_AlarmCmd() functions.
- (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
- is necessary to:
- (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
- function
- (+++) Configure the RTC to detect the tamper or time stamp event using the
- RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
- functions.
- (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
- (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
- (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
- RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enters STOP mode.
- *
- * @note In Stop mode, all I/O pins keep the same state as in Run mode.
- * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
- * the HSI RC oscillator is selected as system clock.
- * @note When the voltage regulator operates in low power mode, an additional
- * startup delay is incurred when waking up from Stop mode.
- * By keeping the internal regulator ON during Stop mode, the consumption
- * is higher although the startup time is reduced.
- *
- * @param PWR_Regulator: specifies the regulator state in STOP mode.
- * This parameter can be one of the following values:
- * @arg PWR_MainRegulator_ON: STOP mode with regulator ON
- * @arg PWR_LowPowerRegulator_ON: STOP mode with low power regulator ON
- * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
- * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
- * @retval None
- */
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR(PWR_Regulator));
- assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
-
- /* Select the regulator state in STOP mode ---------------------------------*/
- tmpreg = PWR->CR;
- /* Clear PDDS and LPDS bits */
- tmpreg &= CR_DS_MASK;
-
- /* Set LPDS, MRLVDS and LPLVDS bits according to PWR_Regulator value */
- tmpreg |= PWR_Regulator;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
- /* Select STOP mode entry --------------------------------------------------*/
- if(PWR_STOPEntry == PWR_STOPEntry_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __WFE();
- }
- /* Reset SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-}
-
-/**
- * @brief Enters in Under-Drive STOP mode.
- *
- * @note This mode is only available for STM32F42xxx/STM3243xxx devices.
- *
- * @note This mode can be selected only when the Under-Drive is already active
- *
- * @note In Stop mode, all I/O pins keep the same state as in Run mode.
- * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
- * the HSI RC oscillator is selected as system clock.
- * @note When the voltage regulator operates in low power mode, an additional
- * startup delay is incurred when waking up from Stop mode.
- * By keeping the internal regulator ON during Stop mode, the consumption
- * is higher although the startup time is reduced.
- *
- * @param PWR_Regulator: specifies the regulator state in STOP mode.
- * This parameter can be one of the following values:
- * @arg PWR_MainRegulator_UnderDrive_ON: Main Regulator in under-drive mode
- * and Flash memory in power-down when the device is in Stop under-drive mode
- * @arg PWR_LowPowerRegulator_UnderDrive_ON: Low Power Regulator in under-drive mode
- * and Flash memory in power-down when the device is in Stop under-drive mode
- * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
- * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
- * @retval None
- */
-void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR_UNDERDRIVE(PWR_Regulator));
- assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
-
- /* Select the regulator state in STOP mode ---------------------------------*/
- tmpreg = PWR->CR;
- /* Clear PDDS and LPDS bits */
- tmpreg &= CR_DS_MASK;
-
- /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
- tmpreg |= PWR_Regulator;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
- /* Select STOP mode entry --------------------------------------------------*/
- if(PWR_STOPEntry == PWR_STOPEntry_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __WFE();
- }
- /* Reset SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-}
-
-/**
- * @brief Enters STANDBY mode.
- * @note In Standby mode, all I/O pins are high impedance except for:
- * - Reset pad (still available)
- * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
- * Alarm out, or RTC clock calibration out.
- * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
- * - WKUP pin 1 (PA0) if enabled.
- * @note The Wakeup flag (WUF) need to be cleared at application level before to call this function
- * @param None
- * @retval None
- */
-void PWR_EnterSTANDBYMode(void)
-{
- /* Select STANDBY mode */
- PWR->CR |= PWR_CR_PDDS;
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
- /* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM )
- __force_stores();
-#endif
- /* Request Wait For Interrupt */
- __WFI();
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group7 Flags management functions
- * @brief Flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the specified PWR flag is set or not.
- * @param PWR_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
- * was received from the WKUP pin or from the RTC alarm (Alarm A
- * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
- * An additional wakeup event is detected if the WKUP pin is enabled
- * (by setting the EWUP bit) when the WKUP pin level is already high.
- * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
- * resumed from StandBy mode.
- * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
- * by the PWR_PVDCmd() function. The PVD is stopped by Standby mode
- * For this reason, this bit is equal to 0 after Standby or reset
- * until the PVDE bit is set.
- * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
- * when the device wakes up from Standby mode or by a system reset
- * or power reset.
- * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
- * scaling output selection is ready.
- * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
- * is ready (STM32F42xxx/43xxx devices)
- * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
- * switching is ready (STM32F42xxx/43xxx devices)
- * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
- * is enabled in Stop mode (STM32F42xxx/43xxx devices)
- * @retval The new state of PWR_FLAG (SET or RESET).
- */
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
-
- if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the PWR's pending flags.
- * @param PWR_FLAG: specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag
- * @arg PWR_FLAG_SB: StandBy flag
- * @arg PWR_FLAG_UDRDY: Under-drive ready flag (STM32F42xxx/43xxx devices)
- * @retval None
- */
-void PWR_ClearFlag(uint32_t PWR_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
-
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
- if (PWR_FLAG != PWR_FLAG_UDRDY)
- {
- PWR->CR |= PWR_FLAG << 2;
- }
- else
- {
- PWR->CSR |= PWR_FLAG_UDRDY;
- }
-#endif /* STM32F427_437xx || STM32F429_439xx */
-
-#if defined (STM32F40_41xxx) || defined (STM32F401xx) || defined (STM32F410xx) || defined (STM32F411xE) || defined(STM32F412xG) || defined(STM32F413_423xx)
- PWR->CR |= PWR_FLAG << 2;
-#endif /* STM32F40_41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG || STM32F413_423xx */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_pwr.h b/底盘/底盘-old/底盘/Library/stm32f4xx_pwr.h
deleted file mode 100644
index 92d3d5d..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_pwr.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_pwr.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the PWR firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_PWR_H
-#define __STM32F4xx_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup PWR
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Constants
- * @{
- */
-
-/** @defgroup PWR_PVD_detection_level
- * @{
- */
-#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
-#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
-#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
-#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3
-#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4
-#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5
-#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6
-#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7
-
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
- ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
- ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
- ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
-/**
- * @}
- */
-
-
-/** @defgroup PWR_Regulator_state_in_STOP_mode
- * @{
- */
-#define PWR_MainRegulator_ON ((uint32_t)0x00000000)
-#define PWR_LowPowerRegulator_ON PWR_CR_LPDS
-
-/* --- PWR_Legacy ---*/
-#define PWR_Regulator_ON PWR_MainRegulator_ON
-#define PWR_Regulator_LowPower PWR_LowPowerRegulator_ON
-
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MainRegulator_ON) || \
- ((REGULATOR) == PWR_LowPowerRegulator_ON))
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Regulator_state_in_UnderDrive_mode
- * @{
- */
-#define PWR_MainRegulator_UnderDrive_ON PWR_CR_MRUDS
-#define PWR_LowPowerRegulator_UnderDrive_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
-
-#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MainRegulator_UnderDrive_ON) || \
- ((REGULATOR) == PWR_LowPowerRegulator_UnderDrive_ON))
-
-/**
- * @}
- */
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-/** @defgroup PWR_Wake_Up_Pin
- * @{
- */
-#define PWR_WakeUp_Pin1 ((uint32_t)0x00)
-#define PWR_WakeUp_Pin2 ((uint32_t)0x01)
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
-#define PWR_WakeUp_Pin3 ((uint32_t)0x02)
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */
-
-#if defined(STM32F446xx)
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUp_Pin1) || \
- ((PIN) == PWR_WakeUp_Pin2))
-#else /* STM32F410xx || STM32F412xG */
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUp_Pin1) || ((PIN) == PWR_WakeUp_Pin2) || \
- ((PIN) == PWR_WakeUp_Pin3))
-#endif /* STM32F446xx */
-/**
- * @}
- */
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
-
-/** @defgroup PWR_STOP_mode_entry
- * @{
- */
-#define PWR_STOPEntry_WFI ((uint8_t)0x01)
-#define PWR_STOPEntry_WFE ((uint8_t)0x02)
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
-/**
- * @}
- */
-
-/** @defgroup PWR_Regulator_Voltage_Scale
- * @{
- */
-#define PWR_Regulator_Voltage_Scale1 ((uint32_t)0x0000C000)
-#define PWR_Regulator_Voltage_Scale2 ((uint32_t)0x00008000)
-#define PWR_Regulator_Voltage_Scale3 ((uint32_t)0x00004000)
-#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || \
- ((VOLTAGE) == PWR_Regulator_Voltage_Scale2) || \
- ((VOLTAGE) == PWR_Regulator_Voltage_Scale3))
-/**
- * @}
- */
-
-/** @defgroup PWR_Flag
- * @{
- */
-#define PWR_FLAG_WU PWR_CSR_WUF
-#define PWR_FLAG_SB PWR_CSR_SBF
-#define PWR_FLAG_PVDO PWR_CSR_PVDO
-#define PWR_FLAG_BRR PWR_CSR_BRR
-#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
-#define PWR_FLAG_ODRDY PWR_CSR_ODRDY
-#define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY
-#define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY
-
-/* --- FLAG Legacy ---*/
-#define PWR_FLAG_REGRDY PWR_FLAG_VOSRDY
-
-#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
- ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \
- ((FLAG) == PWR_FLAG_VOSRDY) || ((FLAG) == PWR_FLAG_ODRDY) || \
- ((FLAG) == PWR_FLAG_ODSWRDY) || ((FLAG) == PWR_FLAG_UDRDY))
-
-
-#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
- ((FLAG) == PWR_FLAG_UDRDY))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the PWR configuration to the default reset state ******/
-void PWR_DeInit(void);
-
-/* Backup Domain Access function **********************************************/
-void PWR_BackupAccessCmd(FunctionalState NewState);
-
-/* PVD configuration functions ************************************************/
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
-void PWR_PVDCmd(FunctionalState NewState);
-
-/* WakeUp pins configuration functions ****************************************/
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
-void PWR_WakeUpPinCmd(FunctionalState NewState);
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) ||defined(STM32F446xx)
-void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPinx, FunctionalState NewState);
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
-/* Main and Backup Regulators configuration functions *************************/
-void PWR_BackupRegulatorCmd(FunctionalState NewState);
-void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage);
-void PWR_OverDriveCmd(FunctionalState NewState);
-void PWR_OverDriveSWCmd(FunctionalState NewState);
-void PWR_UnderDriveCmd(FunctionalState NewState);
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
-void PWR_MainRegulatorUnderDriveCmd(FunctionalState NewState);
-void PWR_LowRegulatorUnderDriveCmd(FunctionalState NewState);
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx */
-
-#if defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG) || defined(STM32F413_423xx)
-void PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState);
-void PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState);
-#endif /* STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG || STM32F413_423xx */
-
-/* FLASH Power Down configuration functions ***********************************/
-void PWR_FlashPowerDownCmd(FunctionalState NewState);
-
-/* Low Power modes configuration functions ************************************/
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
-void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
-void PWR_EnterSTANDBYMode(void);
-
-/* Flags management functions *************************************************/
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
-void PWR_ClearFlag(uint32_t PWR_FLAG);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_PWR_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_qspi.c b/底盘/底盘-old/底盘/Library/stm32f4xx_qspi.c
deleted file mode 100644
index ff501f9..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_qspi.c
+++ /dev/null
@@ -1,903 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_qspi.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Serial peripheral interface (QSPI):
- * + Initialization and Configuration
- * + Indirect Data Read/Write functions
- * + Memory Mapped Mode Data Read functions
- * + Automatic Polling functions
- * + DMA transfers management
- * + Interrupts and flags management
- *
- * @verbatim
- *
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable peripheral clock using RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_QSPI,ENABLE);
- function.
-
- (#) Enable CLK, BK1_IO0, BK1_IO1, BK1_IO2, BK1_IO3, BK1_NCS, BK2_IO0,
- BK2_IO1, BK2_IO2, BK2_IO3 and BK2_NCS GPIO clocks using
- RCC_AHB1PeriphClockCmd() function.
-
- (#) Peripherals alternate function:
- (++) Connect the pin to the desired peripherals' Alternate
- Function (AF) using GPIO_PinAFConfig() function.
- (++) Configure the desired pin in alternate function by:
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
- (++) Select the type, pull-up/pull-down and output speed via
- GPIO_PuPd, GPIO_OType and GPIO_Speed members.
- (++) Call GPIO_Init() function.
-
- (#) Program the Flash Size, CS High Time, Sample Shift, Prescaler, Clock Mode
- values using the QSPI_Init() function.
-
- (#) Enable QSPI using QSPI_Cmd() function.
-
- (#) Set QSPI Data Length using QSPI_SetDataLength() function.
-
- (#) Configure the FIFO threshold using QSPI_SetFIFOThreshold() to select
- at which threshold the FTF event is generated.
-
- (#) Enable the NVIC and the corresponding interrupt using the function
- QSPI_ITConfig() if you need to use interrupt mode.
-
- (#) When using the DMA mode
- (++) Configure the DMA using DMA_Init() function.
- (++) Active the needed channel Request using SPI_I2S_DMACmd() function.
-
- (#) Enable the SPI using the QSPI_DMACmd() function.
-
- (#) Enable the DMA using the DMA_Cmd() function when using DMA mode.
-
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_qspi.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup QSPI
- * @brief QSPI driver modules
- * @{
- */
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define QSPI_CR_CLEAR_MASK 0x00FFFFCF
-#define QSPI_DCR_CLEAR_MASK 0xFFE0F7FE
-#define QSPI_CCR_CLEAR_MASK 0x90800000
-#define QSPI_PIR_CLEAR_MASK 0xFFFF0000
-#define QSPI_LPTR_CLEAR_MASK 0xFFFF0000
-#define QSPI_CCR_CLEAR_INSTRUCTION_MASK 0xFFFFFF00
-#define QSPI_CCR_CLEAR_DCY_MASK 0xFFC3FFFF
-#define QSPI_CR_CLEAR_FIFOTHRESHOLD_MASK 0xFFFFF0FF
-#define QSPI_CR_INTERRUPT_MASK 0x001F0000
-#define QSPI_SR_INTERRUPT_MASK 0x0000001F
-#define QSPI_FSR_INTERRUPT_MASK 0x0000001B
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-
-/* Initialization and Configuration functions *********************************/
-
-/** @defgroup _Private_Functions
- * @{
- */
-
-/** @defgroup _Group1 Function Group1 Name
- * @brief Function group1 name description (copied from the header file)
- *
-@verbatim
- ===============================================================================
- ##### < Function group1 name (copied from the header file)
- Note: do not use "Peripheral" or "PPP" word in the function group name > #####
- ===============================================================================
-
- [..] < OPTIONAL:
- Add here the most important information to know about the IP features
- covered by this group of function.
-
- For system IPs, this section contains how to use this group API.
- >
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the QSPI peripheral registers to their default
- * reset values.
- * @param None
- * @retval None
- */
-void QSPI_DeInit(void)
-{
- /* Enable QSPI reset state */
- RCC_AHB3PeriphResetCmd(RCC_AHB3Periph_QSPI, ENABLE);
- /* Release QSPI from reset state */
- RCC_AHB3PeriphResetCmd(RCC_AHB3Periph_QSPI, DISABLE);
-}
-
-/**
- * @brief Fills each QSPI_InitStruct member with its default value.
- * @param QSPI_InitStruct: pointer to a QSPI_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void QSPI_StructInit(QSPI_InitTypeDef* QSPI_InitStruct)
-{
-/*--------- Reset QSPI init structure parameters default values ------------*/
- /* Initialize the QSPI_SShift member */
- QSPI_InitStruct->QSPI_SShift = QSPI_SShift_NoShift ;
- /* Initialize the QSPI_Prescaler member */
- QSPI_InitStruct->QSPI_Prescaler = 0 ;
- /* Initialize the QSPI_CKMode member */
- QSPI_InitStruct->QSPI_CKMode = QSPI_CKMode_Mode0 ;
- /* Initialize the QSPI_CSHTime member */
- QSPI_InitStruct->QSPI_CSHTime = QSPI_CSHTime_1Cycle ;
- /* Initialize the QSPI_FSize member */
- QSPI_InitStruct->QSPI_FSize = 0 ;
- /* Initialize the QSPI_FSelect member */
- QSPI_InitStruct->QSPI_FSelect = QSPI_FSelect_1 ;
- /* Initialize the QSPI_DFlash member */
- QSPI_InitStruct->QSPI_DFlash = QSPI_DFlash_Disable ;
-}
-
-/**
- * @brief Fills each QSPI_ComConfig_InitStruct member with its default value.
- * @param QSPI_ComConfig_InitStruct: pointer to a QSPI_ComConfig_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void QSPI_ComConfig_StructInit(QSPI_ComConfig_InitTypeDef* QSPI_ComConfig_InitStruct)
-{
-/*--------- Reset QSPI ComConfig init structure parameters default values ------------*/
-
-/* Set QSPI Communication configuration structure parameters default values */
- /* Initialize the QSPI_ComConfig_DDRMode member */
- QSPI_ComConfig_InitStruct->QSPI_ComConfig_DDRMode = QSPI_ComConfig_DDRMode_Disable ;
- /* Initialize the QSPI_ComConfig_DHHC member */
- QSPI_ComConfig_InitStruct->QSPI_ComConfig_DHHC = QSPI_ComConfig_DHHC_Disable ;
- /* Initialize the QSPI_ComConfig_SIOOMode member */
- QSPI_ComConfig_InitStruct->QSPI_ComConfig_SIOOMode = QSPI_ComConfig_SIOOMode_Disable ;
- /* Initialize the QSPI_ComConfig_FMode member */
- QSPI_ComConfig_InitStruct->QSPI_ComConfig_FMode = QSPI_ComConfig_FMode_Indirect_Write ;
- /* Initialize the QSPI_ComConfig_DMode member */
- QSPI_ComConfig_InitStruct->QSPI_ComConfig_DMode = QSPI_ComConfig_DMode_NoData ;
- /* Initialize the QSPI_ComConfig_DummyCycles member */
- QSPI_ComConfig_InitStruct->QSPI_ComConfig_DummyCycles = 0 ;
- /* Initialize the QSPI_ComConfig_ABSize member */
- QSPI_ComConfig_InitStruct->QSPI_ComConfig_ABSize = QSPI_ComConfig_ABSize_8bit ;
- /* Initialize the QSPI_ComConfig_ABMode member */
- QSPI_ComConfig_InitStruct->QSPI_ComConfig_ABMode = QSPI_ComConfig_ABMode_NoAlternateByte ;
- /* Initialize the QSPI_ComConfig_ADSize member */
- QSPI_ComConfig_InitStruct->QSPI_ComConfig_ADSize = QSPI_ComConfig_ADSize_8bit ;
- /* Initialize the QSPI_ComConfig_ADMode member */
- QSPI_ComConfig_InitStruct->QSPI_ComConfig_ADMode = QSPI_ComConfig_ADMode_NoAddress ;
- /* Initialize the QSPI_ComConfig_IMode member */
- QSPI_ComConfig_InitStruct->QSPI_ComConfig_IMode = QSPI_ComConfig_IMode_NoInstruction ;
- /* Initialize the QSPI_ComConfig_Ins member */
- QSPI_ComConfig_InitStruct->QSPI_ComConfig_Ins = 0 ;
-}
-
-/**
- * @brief Initializes the QSPI peripheral according to the specified
- * parameters in the QSPI_InitStruct.
- * @param QSPI_InitStruct: pointer to a QSPI_InitTypeDef structure that
- * contains the configuration information for the specified QSPI peripheral.
- * @retval None
- */
-void QSPI_Init(QSPI_InitTypeDef* QSPI_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the QSPI parameters */
- assert_param(IS_QSPI_SSHIFT(QSPI_InitStruct->QSPI_SShift));
- assert_param(IS_QSPI_PRESCALER(QSPI_InitStruct->QSPI_Prescaler));
- assert_param(IS_QSPI_CKMODE(QSPI_InitStruct->QSPI_CKMode));
- assert_param(IS_QSPI_CSHTIME(QSPI_InitStruct->QSPI_CSHTime));
- assert_param(IS_QSPI_FSIZE(QSPI_InitStruct->QSPI_FSize));
- assert_param(IS_QSPI_FSEL(QSPI_InitStruct->QSPI_FSelect));
- assert_param(IS_QSPI_DFM(QSPI_InitStruct->QSPI_DFlash));
-
- /*------------------------ QSPI CR Configuration ------------------------*/
- /* Get the QUADSPI CR1 value */
- tmpreg = QUADSPI->CR;
- /* Clear PRESCALER and SSHIFT bits */
- tmpreg &= QSPI_CR_CLEAR_MASK;
- /* Configure QUADSPI: Prescaler and Sample Shift */
- tmpreg |= (uint32_t)(((QSPI_InitStruct->QSPI_Prescaler)<<24)
- |(QSPI_InitStruct->QSPI_SShift)
- |(QSPI_InitStruct->QSPI_FSelect)
- |(QSPI_InitStruct->QSPI_DFlash));
- /* Write to QUADSPI CR */
- QUADSPI->CR = tmpreg;
-
- /*------------------------ QUADSPI DCR Configuration ------------------------*/
- /* Get the QUADSPI DCR value */
- tmpreg = QUADSPI->DCR;
- /* Clear FSIZE, CSHT and CKMODE bits */
- tmpreg &= QSPI_DCR_CLEAR_MASK;
- /* Configure QSPI: Flash Size, Chip Select High Time and Clock Mode */
- tmpreg |= (uint32_t)(((QSPI_InitStruct->QSPI_FSize)<<16)
- |(QSPI_InitStruct->QSPI_CSHTime)
- |(QSPI_InitStruct->QSPI_CKMode));
- /* Write to QSPI DCR */
- QUADSPI->DCR = tmpreg;
-}
-
-/**
- * @brief Initializes the QSPI CCR according to the specified
- * parameters in the QSPI_ComConfig_InitStruct.
- * @param QSPI_ComConfig_InitStruct: pointer to a QSPI_ComConfig_InitTypeDef structure that
- * contains the communication configuration informations about QSPI peripheral.
- * @retval None
- */
-void QSPI_ComConfig_Init(QSPI_ComConfig_InitTypeDef* QSPI_ComConfig_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the QSPI Communication Control parameters */
- assert_param(IS_QSPI_FMODE (QSPI_ComConfig_InitStruct->QSPI_ComConfig_FMode));
- assert_param(IS_QSPI_SIOOMODE (QSPI_ComConfig_InitStruct->QSPI_ComConfig_SIOOMode));
- assert_param(IS_QSPI_DMODE (QSPI_ComConfig_InitStruct->QSPI_ComConfig_DMode));
- assert_param(IS_QSPI_DCY (QSPI_ComConfig_InitStruct->QSPI_ComConfig_DummyCycles));
- assert_param(IS_QSPI_ABSIZE (QSPI_ComConfig_InitStruct->QSPI_ComConfig_ABSize));
- assert_param(IS_QSPI_ABMODE (QSPI_ComConfig_InitStruct->QSPI_ComConfig_ABMode));
- assert_param(IS_QSPI_ADSIZE (QSPI_ComConfig_InitStruct->QSPI_ComConfig_ADSize));
- assert_param(IS_QSPI_ADMODE (QSPI_ComConfig_InitStruct->QSPI_ComConfig_ADMode));
- assert_param(IS_QSPI_IMODE (QSPI_ComConfig_InitStruct->QSPI_ComConfig_IMode));
- assert_param(IS_QSPI_INSTRUCTION (QSPI_ComConfig_InitStruct->QSPI_ComConfig_Ins));
- assert_param(IS_QSPI_DDRMODE (QSPI_ComConfig_InitStruct->QSPI_ComConfig_DDRMode));
- assert_param(IS_QSPI_DHHC (QSPI_ComConfig_InitStruct->QSPI_ComConfig_DHHC));
-
- /*------------------------ QUADSPI CCR Configuration ------------------------*/
- /* Get the QUADSPI CCR value */
- tmpreg = QUADSPI->CCR;
- /* Clear FMODE Mode bits */
- tmpreg &= QSPI_CCR_CLEAR_MASK;
- /* Configure QUADSPI: CCR Configuration */
- tmpreg |= (uint32_t)( (QSPI_ComConfig_InitStruct->QSPI_ComConfig_FMode)
- | (QSPI_ComConfig_InitStruct->QSPI_ComConfig_DDRMode)
- | (QSPI_ComConfig_InitStruct->QSPI_ComConfig_DHHC)
- | (QSPI_ComConfig_InitStruct->QSPI_ComConfig_SIOOMode)
- | (QSPI_ComConfig_InitStruct->QSPI_ComConfig_DMode)
- | (QSPI_ComConfig_InitStruct->QSPI_ComConfig_ABSize)
- | (QSPI_ComConfig_InitStruct->QSPI_ComConfig_ABMode)
- | (QSPI_ComConfig_InitStruct->QSPI_ComConfig_ADSize)
- | (QSPI_ComConfig_InitStruct->QSPI_ComConfig_ADMode)
- | (QSPI_ComConfig_InitStruct->QSPI_ComConfig_IMode)
- | (QSPI_ComConfig_InitStruct->QSPI_ComConfig_Ins)
- |((QSPI_ComConfig_InitStruct->QSPI_ComConfig_DummyCycles)<<18));
- /* Write to QUADSPI DCR */
- QUADSPI->CCR = tmpreg;
-}
-
-/**
- * @brief Enables or disables QSPI peripheral.
- * @param NewState: new state of the QSPI peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void QSPI_Cmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable QSPI peripheral */
- QUADSPI->CR |= QUADSPI_CR_EN;
- }
- else
- {
- /* Disable QSPI peripheral */
- QUADSPI->CR &= ~ QUADSPI_CR_EN;
- }
-}
-
-/**
- * @brief Configure the QSPI Automatic Polling Mode.
- * @param QSPI_Match: Value to be compared with the masked status register to get a match.
- * This parameter can be any value between 0x00000000 and 0xFFFFFFFF.
- * @param QSPI_Mask: Mask to be applied to the status bytes received in polling mode..
- * This parameter can be any value between 0x00000000 and 0xFFFFFFFF.
- * @param QSPI_Match_Mode: indicates which method should be used for determining a match during
- * automatic polling mode.
- * This parameter can be any value of :
- * @arg QSPI_PMM_AND: AND match mode- SMF is set if all the unmasked bits received from the flash match
- * the corresponding bits in the match register
- * @arg QSPI_PMM_OR: OR match mode- SMF is set if any one of the unmasked bits received from the flash
- matches its corresponding bit in the match register.
- * @note This function is used only in Automatic Polling Mode
- * @retval None
- */
-void QSPI_AutoPollingMode_Config(uint32_t QSPI_Match, uint32_t QSPI_Mask , uint32_t QSPI_Match_Mode)
-{
- /* Check the parameters */
- assert_param(IS_QSPI_PMM(QSPI_Match_Mode));
-
- if ((QUADSPI->SR & QUADSPI_SR_BUSY) == RESET)
- /* Device is not Busy */
- {
- /* Set the Match Register */
- QUADSPI->PSMAR = QSPI_Match ;
-
- /* Set the Mask Register */
- QUADSPI->PSMKR = QSPI_Mask ;
-
- /* Set the Polling Match Mode */
- if(QSPI_Match_Mode)
- /* OR Match Mode */
- {
- /* Set the PMM bit */
- QUADSPI->CR |= QUADSPI_CR_PMM;
- }
- else
- /* AND Match Mode */
- {
- /* Reset the PMM bit */
- QUADSPI->CR &= ~ QUADSPI_CR_PMM;
- }
- }
-}
-
-/**
- * @brief Sets the number of CLK cycle between two read during automatic polling phases.
- * @param QSPI_Interval: The number of CLK cycle between two read during automatic polling phases.
- * This parameter can be any value of between 0x0000 and 0xFFFF
- * @note This function is used only in Automatic Polling Mode
- * @retval None
- */
-void QSPI_AutoPollingMode_SetInterval(uint32_t QSPI_Interval)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_QSPI_PIR(QSPI_Interval));
-
- if ((QUADSPI->SR & QUADSPI_SR_BUSY) == RESET)
- /* Device is not Busy */
- {
- /* Read the PIR Register */
- tmpreg = QUADSPI->PIR ;
- /* Clear Polling interval Bits */
- tmpreg &= QSPI_PIR_CLEAR_MASK ;
- /* Set the QSPI Polling Interval Bits */
- tmpreg |= QSPI_Interval;
- /* Write the PIR Register */
- QUADSPI->PIR = tmpreg;
- }
-}
-
-/**
- * @brief Sets the value of the Timeout in Memory Mapped mode
- * @param QSPI_Timeout: This field indicates how many CLK cycles QSPI waits after the
- * FIFO becomes full until it raises nCS, putting the flash memory
- * in a lowerconsumption state.
- * This parameter can be any value of between 0x0000 and 0xFFFF
- * @note This function is used only in Memory Mapped Mode
- * @retval None
- */
-void QSPI_MemoryMappedMode_SetTimeout(uint32_t QSPI_Timeout)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_QSPI_TIMEOUT(QSPI_Timeout));
-
- if ((QUADSPI->SR & QUADSPI_SR_BUSY) == RESET)
- /* Device is not Busy */
- {
- /* Read the LPTR Register */
- tmpreg = QUADSPI->LPTR ;
- /* Clear Timeout Bits */
- tmpreg &= QSPI_LPTR_CLEAR_MASK ;
- /* Set Timeout Bits */
- tmpreg |= QSPI_Timeout;
- /* Write the LPTR Register */
- QUADSPI->LPTR = tmpreg;
- }
-}
-
-/**
- * @brief Sets the value of the Address
- * @param QSPI_Address: Address to be send to the external flash memory.
- * This parameter can be any value of between 0x00000000 and 0xFFFFFFFF
- * @note This function is used only in Indirect Mode
- * @retval None
- */
-void QSPI_SetAddress(uint32_t QSPI_Address)
-{
- if((QUADSPI->SR & QUADSPI_SR_BUSY) == RESET)
- /* Device is not Busy */
- {
- /* Write the AR Register */
- QUADSPI->AR = QSPI_Address;
- }
-}
-
-/**
- * @brief Sets the value of the Alternate Bytes
- * @param QSPI_AlternateByte: Optional data to be send to the external QSPI device right after the address.
- * This parameter can be any value of between 0x00000000 and 0xFFFFFFFF
- * @note This function is used only in Indirect Mode
- * @retval None
- */
-void QSPI_SetAlternateByte(uint32_t QSPI_AlternateByte)
-{
- if((QUADSPI->SR & QUADSPI_SR_BUSY) == RESET)
- /* Device is not Busy */
- {
- /* Write the ABR Register */
- QUADSPI->ABR = QSPI_AlternateByte;
- }
-}
-
-/**
- * @brief Sets the FIFO Threshold
- * @param QSPI_FIFOThres: Defines, in indirect mode, the threshold number
- * of bytes in the FIFO which will cause the FIFO Threshold Flag
- * FTF to be set.
- * This parameter can be any value of between 0x00 and 0x0F
- * @retval None
- */
-void QSPI_SetFIFOThreshold(uint32_t QSPI_FIFOThreshold)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_QSPI_FIFOTHRESHOLD(QSPI_FIFOThreshold));
-
- /* Read the CR Register */
- tmpreg = QUADSPI->CR ;
- /* Clear FIFO Threshold Bits */
- tmpreg &= QSPI_CR_CLEAR_FIFOTHRESHOLD_MASK ;
- /* Set FIFO Threshold Bits */
- tmpreg |= (QSPI_FIFOThreshold << 8);
- /* Write the CR Register */
- QUADSPI->CR = tmpreg;
-}
-
-/**
- * @brief Sets number of Bytes to be transferred
- * @param QSPI_DataLength: Number of data to be retrieved (value+1)
- * in indirect and status-polling modes. A value no greater than 3
- * (indicating 4 bytes) should be used for status-polling mode.
- * All 1s in indirect mode means undefined length, where QSPI will
- * continue until the end of memory, as defined by FSIZE
- * This parameter can be any value of between 0x00000000 and 0xFFFFFFFF
- * 0x0000_0000: 1 byte is to be transferred
- * 0x0000_0001: 2 bytes are to be transferred
- * 0x0000_0002: 3 bytes are to be transferred
- * 0x0000_0003: 4 bytes are to be transferred
- * ...
- * 0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred
- * 0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred
- * 0xFFFF_FFFF: undefined length -- all bytes until the end of flash memory (as defined
- * by FSIZE) are to be transferred
- * @note This function is not used in Memory Mapped Mode.
- * @retval None
- */
-void QSPI_SetDataLength(uint32_t QSPI_DataLength)
-{
- if ((QUADSPI->SR & QUADSPI_SR_BUSY) == RESET)
- /* Device is not Busy */
- {
- /* Write the DLR Register */
- QUADSPI->DLR = QSPI_DataLength;
- }
-}
-
-/**
- * @brief Enables or disables The Timeout Counter.
- * @param NewState: new state of the Timeout Counter.
- * This parameter can be: ENABLE or DISABLE.
- * @note This function is used only in Memory Mapped Mode.
- * @retval None
- */
-void QSPI_TimeoutCounterCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if ((QUADSPI->SR & QUADSPI_SR_BUSY) == RESET)
- /* Device is not Busy */
- {
- if (NewState != DISABLE)
- {
- /* Enable Timeout Counter */
- QUADSPI->CR |= QUADSPI_CR_TCEN;
- }
- else
- {
- /* Disable Timeout Counter */
- QUADSPI->CR &= ~ QUADSPI_CR_TCEN;
- }
- }
-}
-
-/**
- * @brief Enables or disables Automatic Polling Mode Stop when a match occurs.
- * @param NewState: new state of the Automatic Polling Mode Stop.
- * This parameter can be: ENABLE or DISABLE.
- * @note This function is used only in Automatic Polling Mode.
- * @retval None
- */
-void QSPI_AutoPollingModeStopCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if ((QUADSPI->SR & QUADSPI_SR_BUSY) == RESET)
- /* Device is not Busy */
- {
- if (NewState != DISABLE)
- {
- /* Enable Automatic Polling Mode Stop */
- QUADSPI->CR |= QUADSPI_CR_APMS;
- }
- else
- {
- /* Disable Automatic Polling Mode Stop */
- QUADSPI->CR &= ~ QUADSPI_CR_APMS;
- }
- }
-}
-
-/**
- * @brief Abort the on-going command sequence.
- * @param None
- * @retval None
- */
-void QSPI_AbortRequest(void)
-{
- /* Enable the ABORT request bit in CR */
- QUADSPI->CR |= QUADSPI_CR_ABORT;
-}
-
-/* Data transfers functions ***************************************************/
-
-/**
- * @brief Transmits a 8bit Data through the QSPI peripheral.
- * @param Data: Data to be transmitted.
- * @retval None
- */
-void QSPI_SendData8(uint8_t Data)
-{
- uint32_t quadspibase = 0;
-
- quadspibase = (uint32_t)QUADSPI;
- quadspibase += 0x20;
-
- *(__IO uint8_t *) quadspibase = Data;
-}
-
-/**
- * @brief Transmits a 16bit Data through the QSPI peripheral.
- * @param Data: Data to be transmitted.
- * @retval None
- */
-void QSPI_SendData16(uint16_t Data)
-{
- uint32_t quadspibase = 0;
-
- quadspibase = (uint32_t)QUADSPI;
- quadspibase += 0x20;
-
- *(__IO uint16_t *) quadspibase = Data;
-}
-
-/**
- * @brief Transmits a 32bit Data through the QSPI peripheral.
- * @param Data: Data to be transmitted.
- * @retval None
- */
-void QSPI_SendData32(uint32_t Data)
-{
- QUADSPI->DR = Data;
-}
-
-/**
- * @brief Returns the most recent received 8bit data by the QSPI peripheral.
- * @retval The value of the received data.
- */
-uint8_t QSPI_ReceiveData8(void)
-{
- uint32_t quadspibase = 0;
-
- quadspibase = (uint32_t)QUADSPI;
- quadspibase += 0x20;
-
- return *(__IO uint8_t *) quadspibase;
-}
-
-/**
- * @brief Returns the most recent received 16bit data by the QSPI peripheral.
- * @retval The value of the received data.
- */
-uint16_t QSPI_ReceiveData16(void)
-{
- uint32_t quadspibase = 0;
-
- quadspibase = (uint32_t)QUADSPI;
- quadspibase += 0x20;
-
- return *(__IO uint16_t *) quadspibase;
-}
-
-/**
- * @brief Returns the most recent received 32bit data by the QSPI peripheral.
- * @retval The value of the received data.
- */
-uint32_t QSPI_ReceiveData32(void)
-{
- return QUADSPI->DR;
-}
-
-/* DMA transfers management functions *****************************************/
-
-/**
- * @brief Enables or disables DMA for Indirect Mode.
- * @param NewState: new state of the Timeout Counter.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void QSPI_DMACmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable DMA */
- QUADSPI->CR |= QUADSPI_CR_DMAEN;
- }
- else
- {
- /* Disable DMA */
- QUADSPI->CR &= ~ QUADSPI_CR_DMAEN;
- }
-}
-
-/* Interrupts and flags management functions **********************************/
-
-/**
- * @brief Enables or disables the specified QSPI interrupts.
- * @param QSPI_IT: specifies the QSPI interrupt source to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg QSPI_IT_TO: Timeout interrupt
- * @arg QSPI_IT_SM: Status Match interrupt
- * @arg QSPI_IT_FT: FIFO Threshold
- * @arg QSPI_IT_TC: Transfer Complete
- * @arg QSPI_IT_TE: Transfer Error
- * @param NewState: new state of the specified QSPI interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void QSPI_ITConfig(uint32_t QSPI_IT, FunctionalState NewState)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_QSPI_IT(QSPI_IT));
-
- /* Read the CR Register */
- tmpreg = QUADSPI->CR ;
-
- if(NewState != DISABLE)
- {
- /* Enable the selected QSPI interrupt */
- tmpreg |= (uint32_t)(QSPI_IT & QSPI_CR_INTERRUPT_MASK);
- }
- else
- {
- /* Disable the selected QSPI interrupt */
- tmpreg &= ~(uint32_t)(QSPI_IT & QSPI_CR_INTERRUPT_MASK);
- }
- /* Write the CR Register */
- QUADSPI->CR = tmpreg ;
-}
-
-/**
- * @brief Returns the current QSPI FIFO filled level.
- * @retval Number of valid bytes which are being held in the FIFO.
- * 0x00 : FIFO is empty
- * 0x1F : FIFO is full
- */
-uint32_t QSPI_GetFIFOLevel(void)
-{
- /* Get the QSPI FIFO level bits */
- return ((QUADSPI->SR & QUADSPI_SR_FLEVEL)>> 8);
-}
-
-/**
- * @brief Returns the QSPI functional mode.
- * @param None
- * @retval QSPI Functional Mode .The returned value can be one of the following:
- * - 0x00000000: QSPI_FMode_Indirect_Write
- * - 0x04000000: QSPI_FMode_Indirect_Read
- * - 0x08000000: QSPI_FMode_AutoPolling
- * - 0x0C000000: QSPI_FMode_MemoryMapped
- */
-uint32_t QSPI_GetFMode(void)
-{
- /* Return the QSPI_FMode */
- return (QUADSPI->CCR & QUADSPI_CCR_FMODE);
-}
-
-/**
- * @brief Checks whether the specified QSPI flag is set or not.
- * @param QSPI_FLAG: specifies the QSPI flag to check.
- * This parameter can be one of the following values:
- * @arg QSPI_FLAG_TO: Timeout interrupt flag
- * @arg QSPI_FLAG_SM: Status Match interrupt flag
- * @arg QSPI_FLAG_FT: FIFO Threshold flag
- * @arg QSPI_FLAG_TC: Transfer Complete flag
- * @arg QSPI_FLAG_TE: Transfer Error flag
- * @arg QSPI_FLAG_BUSY: Busy flag
- * @retval The new state of QSPI_FLAG (SET or RESET).
- */
-FlagStatus QSPI_GetFlagStatus(uint32_t QSPI_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_QSPI_GET_FLAG(QSPI_FLAG));
-
- /* Check the status of the specified QSPI flag */
- if((QUADSPI->SR & QSPI_FLAG) != RESET)
- {
- /* QSPI_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* QSPI_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the QSPI_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the QSPI flag.
- * @param QSPI_FLAG: specifies the QSPI flag to clear.
- * This parameter can be one of the following values:
- * @arg QSPI_FLAG_TO: Timeout interrupt flag
- * @arg QSPI_FLAG_SM: Status Match interrupt flag
- * @arg QSPI_FLAG_TC: Transfer Complete flag
- * @arg QSPI_FLAG_TE: Transfer Error flag
- * @retval None
- */
-void QSPI_ClearFlag(uint32_t QSPI_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_QSPI_CLEAR_FLAG(QSPI_FLAG));
-
- /* Clear the selected QSPI flags */
- QUADSPI->FCR = QSPI_FLAG;
-}
-
-/**
- * @brief Checks whether the specified QSPI interrupt has occurred or not.
- * @param QSPI_IT: specifies the QSPI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg QSPI_IT_TO: Timeout interrupt
- * @arg QSPI_IT_SM: Status Match interrupt
- * @arg QSPI_IT_FT: FIFO Threshold
- * @arg QSPI_IT_TC: Transfer Complete
- * @arg QSPI_IT_TE: Transfer Error
- * @retval The new state of QSPI_IT (SET or RESET).
- */
-ITStatus QSPI_GetITStatus(uint32_t QSPI_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t tmpcreg = 0, tmpsreg = 0;
-
- /* Check the parameters */
- assert_param(IS_QSPI_IT(QSPI_IT));
-
- /* Read the QUADSPI CR */
- tmpcreg = QUADSPI->CR;
- tmpcreg &= (uint32_t)(QSPI_IT & QSPI_CR_INTERRUPT_MASK);
-
- /* Read the QUADSPI SR */
- tmpsreg = QUADSPI->SR;
- tmpsreg &= (uint32_t)(QSPI_IT & QSPI_SR_INTERRUPT_MASK);
-
- /* Check the status of the specified QSPI interrupt */
- if((tmpcreg != RESET) && (tmpsreg != RESET))
- {
- /* QSPI_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* QSPI_IT is reset */
- bitstatus = RESET;
- }
- /* Return the QSPI_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the QSPI's interrupt pending bits.
- * @param QSPI_IT: specifies the QSPI pending bit to clear.
- * This parameter can be one of the following values:
- * @arg QSPI_IT_TO: Timeout interrupt
- * @arg QSPI_IT_SM: Status Match interrupt
- * @arg QSPI_IT_TC: Transfer Complete
- * @arg QSPI_IT_TE: Transfer Error
- * @retval None
- */
-void QSPI_ClearITPendingBit(uint32_t QSPI_IT)
-{
- /* Check the parameters */
- assert_param(IS_QSPI_CLEAR_IT(QSPI_IT));
-
- QUADSPI->FCR = (uint32_t)(QSPI_IT & QSPI_FSR_INTERRUPT_MASK);
-}
-
-/**
- * @brief Enables or disables QSPI Dual Flash Mode.
- * @param NewState: new state of the QSPI Dual Flash Mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void QSPI_DualFlashMode_Cmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable QSPI Dual Flash Mode */
- QUADSPI->CR |= QUADSPI_CR_DFM;
- }
- else
- {
- /* Disable QSPI Dual Flash Mode */
- QUADSPI->CR &= ~ QUADSPI_CR_DFM;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_qspi.h b/底盘/底盘-old/底盘/Library/stm32f4xx_qspi.h
deleted file mode 100644
index 45bbdb2..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_qspi.h
+++ /dev/null
@@ -1,485 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_qspi.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the QSPI
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4XX_QUADSPI_H
-#define __STM32F4XX_QUADSPI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup QSPI
- * @{
- */
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief QSPI Communication Configuration Init structure definition
- */
-
-typedef struct
-{
-
- uint32_t QSPI_ComConfig_FMode; /* Specifies the Functional Mode
- This parameter can be a value of @ref QSPI_ComConfig_Functional_Mode*/
-
- uint32_t QSPI_ComConfig_DDRMode; /* Specifies the Double Data Rate Mode
- This parameter can be a value of @ref QSPI_ComConfig_DoubleDataRateMode*/
-
- uint32_t QSPI_ComConfig_DHHC; /* Specifies the Delay Half Hclk Cycle
- This parameter can be a value of @ref QSPI_ComConfig_DelayHalfHclkCycle*/
-
- uint32_t QSPI_ComConfig_SIOOMode; /* Specifies the Send Instruction Only Once Mode
- This parameter can be a value of @ref QSPI_ComConfig_SendInstructionOnlyOnceMode*/
-
- uint32_t QSPI_ComConfig_DMode; /* Specifies the Data Mode
- This parameter can be a value of @ref QSPI_ComConfig_DataMode*/
-
- uint32_t QSPI_ComConfig_DummyCycles; /* Specifies the Number of Dummy Cycles.
- This parameter can be a number between 0x00 and 0x1F */
-
- uint32_t QSPI_ComConfig_ABSize; /* Specifies the Alternate Bytes Size
- This parameter can be a value of @ref QSPI_ComConfig_AlternateBytesSize*/
-
- uint32_t QSPI_ComConfig_ABMode; /* Specifies the Alternate Bytes Mode
- This parameter can be a value of @ref QSPI_ComConfig_AlternateBytesMode*/
-
- uint32_t QSPI_ComConfig_ADSize; /* Specifies the Address Size
- This parameter can be a value of @ref QSPI_ComConfig_AddressSize*/
-
- uint32_t QSPI_ComConfig_ADMode; /* Specifies the Address Mode
- This parameter can be a value of @ref QSPI_ComConfig_AddressMode*/
-
- uint32_t QSPI_ComConfig_IMode; /* Specifies the Instruction Mode
- This parameter can be a value of @ref QSPI_ComConfig_InstructionMode*/
-
- uint32_t QSPI_ComConfig_Ins; /* Specifies the Instruction Mode
- This parameter can be a value of @ref QSPI_ComConfig_Instruction*/
-
-}QSPI_ComConfig_InitTypeDef;
-
-/**
- * @brief QSPI Init structure definition
- */
-
-typedef struct
-{
- uint32_t QSPI_SShift; /* Specifies the Sample Shift
- This parameter can be a value of @ref QSPI_Sample_Shift*/
-
- uint32_t QSPI_Prescaler; /* Specifies the prescaler value used to divide the QSPI clock.
- This parameter can be a number between 0x00 and 0xFF */
-
- uint32_t QSPI_CKMode; /* Specifies the Clock Mode
- This parameter can be a value of @ref QSPI_Clock_Mode*/
-
- uint32_t QSPI_CSHTime; /* Specifies the Chip Select High Time
- This parameter can be a value of @ref QSPI_ChipSelectHighTime*/
-
- uint32_t QSPI_FSize; /* Specifies the Flash Size.
- QSPI_FSize+1 is effectively the number of address bits required to address the flash memory.
- The flash capacity can be up to 4GB (addressed using 32 bits) in indirect mode, but the
- addressable space in memory-mapped mode is limited to 512MB
- This parameter can be a number between 0x00 and 0x1F */
- uint32_t QSPI_FSelect; /* Specifies the Flash which will be used,
- This parameter can be a value of @ref QSPI_Fash_Select*/
- uint32_t QSPI_DFlash; /* Specifies the Dual Flash Mode State
- This parameter can be a value of @ref QSPI_Dual_Flash*/
-}QSPI_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup QSPI_Exported_Constants
- * @{
- */
-
-/** @defgroup QSPI_Sample_Shift
- * @{
- */
-#define QSPI_SShift_NoShift ((uint32_t)0x00000000)
-#define QSPI_SShift_HalfCycleShift ((uint32_t)QUADSPI_CR_SSHIFT)
-#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SShift_NoShift) || ((SSHIFT) == QSPI_SShift_HalfCycleShift))
-/* Legacy Defines */
-#define QUADSPI_CR_SSHIFT_0 QUADSPI_CR_SSHIFT
-/**
- * @}
- */
-
-/** @defgroup QSPI_Prescaler
- * @{
- */
-#define IS_QSPI_PRESCALER(PRESCALER) (((PRESCALER) <= 0xFF))
-/**
- * @}
- */
-
-/** @defgroup QSPI_Clock_Mode
- * @{
- */
-#define QSPI_CKMode_Mode0 ((uint32_t)0x00000000)
-#define QSPI_CKMode_Mode3 ((uint32_t)QUADSPI_DCR_CKMODE)
-#define IS_QSPI_CKMODE(CKMode) (((CKMode) == QSPI_CKMode_Mode0) || ((CKMode) == QSPI_CKMode_Mode3))
-/**
- * @}
- */
-
-/** @defgroup QSPI_ChipSelectHighTime
- * @{
- */
-#define QSPI_CSHTime_1Cycle ((uint32_t)0x00000000)
-#define QSPI_CSHTime_2Cycle ((uint32_t)QUADSPI_DCR_CSHT_0)
-#define QSPI_CSHTime_3Cycle ((uint32_t)QUADSPI_DCR_CSHT_1)
-#define QSPI_CSHTime_4Cycle ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1)
-#define QSPI_CSHTime_5Cycle ((uint32_t)QUADSPI_DCR_CSHT_2)
-#define QSPI_CSHTime_6Cycle ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0)
-#define QSPI_CSHTime_7Cycle ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1)
-#define QSPI_CSHTime_8Cycle ((uint32_t)QUADSPI_DCR_CSHT)
-#define IS_QSPI_CSHTIME(CSHTIME) (((CSHTIME) == QSPI_CSHTime_1Cycle) || \
- ((CSHTIME) == QSPI_CSHTime_2Cycle) || \
- ((CSHTIME) == QSPI_CSHTime_3Cycle) || \
- ((CSHTIME) == QSPI_CSHTime_4Cycle) || \
- ((CSHTIME) == QSPI_CSHTime_5Cycle) || \
- ((CSHTIME) == QSPI_CSHTime_6Cycle) || \
- ((CSHTIME) == QSPI_CSHTime_7Cycle) || \
- ((CSHTIME) == QSPI_CSHTime_8Cycle))
-/**
- * @}
- */
-
-/** @defgroup QSPI_Flash_Size
- * @{
- */
-#define IS_QSPI_FSIZE(FSIZE) (((FSIZE) <= 0x1F))
-/**
- * @}
- */
-
-/** @defgroup QSPI_Fash_Select
- * @{
- */
-#define QSPI_FSelect_1 ((uint32_t)0x00000000)
-#define QSPI_FSelect_2 ((uint32_t)QUADSPI_CR_FSEL)
-#define IS_QSPI_FSEL(FLA) (((FLA) == QSPI_FSelect_1) || ((FLA) == QSPI_FSelect_2))
-/**
- * @}
- */
-
-/** @defgroup QSPI_Dual_Flash
- * @{
- */
-#define QSPI_DFlash_Disable ((uint32_t)0x00000000)
-#define QSPI_DFlash_Enable ((uint32_t)QUADSPI_CR_DFM)
-#define IS_QSPI_DFM(FLA) (((FLA) == QSPI_DFlash_Enable) || ((FLA) == QSPI_DFlash_Disable))
-/**
- * @}
- */
-
-/** @defgroup QSPI_ComConfig_Functional_Mode
- * @{
- */
-#define QSPI_ComConfig_FMode_Indirect_Write ((uint32_t)0x00000000)
-#define QSPI_ComConfig_FMode_Indirect_Read ((uint32_t)QUADSPI_CCR_FMODE_0)
-#define QSPI_ComConfig_FMode_Auto_Polling ((uint32_t)QUADSPI_CCR_FMODE_1)
-#define QSPI_ComConfig_FMode_Memory_Mapped ((uint32_t)QUADSPI_CCR_FMODE)
-#define IS_QSPI_FMODE(FMODE) (((FMODE) == QSPI_ComConfig_FMode_Indirect_Write) || \
- ((FMODE) == QSPI_ComConfig_FMode_Indirect_Read) || \
- ((FMODE) == QSPI_ComConfig_FMode_Auto_Polling) || \
- ((FMODE) == QSPI_ComConfig_FMode_Memory_Mapped))
-/**
- * @}
- */
-
-/** @defgroup QSPI_ComConfig_DoubleDataRateMode
- * @{
- */
-#define QSPI_ComConfig_DDRMode_Disable ((uint32_t)0x00000000)
-#define QSPI_ComConfig_DDRMode_Enable ((uint32_t)QUADSPI_CCR_DDRM)
-#define IS_QSPI_DDRMODE(DDRMODE) (((DDRMODE) == QSPI_ComConfig_DDRMode_Disable) || \
- ((DDRMODE) == QSPI_ComConfig_DDRMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup QSPI_ComConfig_DelayHalfHclkCycle
- * @{
- */
-#define QSPI_ComConfig_DHHC_Disable ((uint32_t)0x00000000)
-#define QSPI_ComConfig_DHHC_Enable ((uint32_t)QUADSPI_CCR_DHHC)
-#define IS_QSPI_DHHC(DHHC) (((DHHC) == QSPI_ComConfig_DHHC_Disable) || \
- ((DHHC) == QSPI_ComConfig_DHHC_Enable))
-/**
- * @}
- */
-
-/** @defgroup QSPI_ComConfig_SendInstructionOnlyOnceMode
- * @{
- */
-#define QSPI_ComConfig_SIOOMode_Disable ((uint32_t)0x00000000)
-#define QSPI_ComConfig_SIOOMode_Enable ((uint32_t)QUADSPI_CCR_SIOO)
-#define IS_QSPI_SIOOMODE(SIOOMODE) (((SIOOMODE) == QSPI_ComConfig_SIOOMode_Disable) || \
- ((SIOOMODE) == QSPI_ComConfig_SIOOMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup QSPI_ComConfig_DataMode
- * @{
- */
-#define QSPI_ComConfig_DMode_NoData ((uint32_t)0x00000000)
-#define QSPI_ComConfig_DMode_1Line ((uint32_t)QUADSPI_CCR_DMODE_0)
-#define QSPI_ComConfig_DMode_2Line ((uint32_t)QUADSPI_CCR_DMODE_1)
-#define QSPI_ComConfig_DMode_4Line ((uint32_t)QUADSPI_CCR_DMODE)
-#define IS_QSPI_DMODE(DMODE) (((DMODE) == QSPI_ComConfig_DMode_NoData) || \
- ((DMODE) == QSPI_ComConfig_DMode_1Line) || \
- ((DMODE) == QSPI_ComConfig_DMode_2Line) || \
- ((DMODE) == QSPI_ComConfig_DMode_4Line))
-/**
- * @}
- */
-
-/** @defgroup QSPI_ComConfig_AlternateBytesSize
- * @{
- */
-#define QSPI_ComConfig_ABSize_8bit ((uint32_t)0x00000000)
-#define QSPI_ComConfig_ABSize_16bit ((uint32_t)QUADSPI_CCR_ABSIZE_0)
-#define QSPI_ComConfig_ABSize_24bit ((uint32_t)QUADSPI_CCR_ABSIZE_1)
-#define QSPI_ComConfig_ABSize_32bit ((uint32_t)QUADSPI_CCR_ABSIZE)
-#define IS_QSPI_ABSIZE(ABSIZE) (((ABSIZE) == QSPI_ComConfig_ABSize_8bit) || \
- ((ABSIZE) == QSPI_ComConfig_ABSize_16bit) || \
- ((ABSIZE) == QSPI_ComConfig_ABSize_24bit) || \
- ((ABSIZE) == QSPI_ComConfig_ABSize_32bit))
-/**
- * @}
- */
-
-/** @defgroup QSPI_ComConfig_AlternateBytesMode
- * @{
- */
-#define QSPI_ComConfig_ABMode_NoAlternateByte ((uint32_t)0x00000000)
-#define QSPI_ComConfig_ABMode_1Line ((uint32_t)QUADSPI_CCR_ABMODE_0)
-#define QSPI_ComConfig_ABMode_2Line ((uint32_t)QUADSPI_CCR_ABMODE_1)
-#define QSPI_ComConfig_ABMode_4Line ((uint32_t)QUADSPI_CCR_ABMODE)
-#define IS_QSPI_ABMODE(ABMODE) (((ABMODE) == QSPI_ComConfig_ABMode_NoAlternateByte) || \
- ((ABMODE) == QSPI_ComConfig_ABMode_1Line) || \
- ((ABMODE) == QSPI_ComConfig_ABMode_2Line) || \
- ((ABMODE) == QSPI_ComConfig_ABMode_4Line))
-/**
- * @}
- */
-
-/** @defgroup QSPI_ComConfig_AddressSize
- * @{
- */
-#define QSPI_ComConfig_ADSize_8bit ((uint32_t)0x00000000)
-#define QSPI_ComConfig_ADSize_16bit ((uint32_t)QUADSPI_CCR_ADSIZE_0)
-#define QSPI_ComConfig_ADSize_24bit ((uint32_t)QUADSPI_CCR_ADSIZE_1)
-#define QSPI_ComConfig_ADSize_32bit ((uint32_t)QUADSPI_CCR_ADSIZE)
-#define IS_QSPI_ADSIZE(ADSIZE) (((ADSIZE) == QSPI_ComConfig_ADSize_8bit) || \
- ((ADSIZE) == QSPI_ComConfig_ADSize_16bit) || \
- ((ADSIZE) == QSPI_ComConfig_ADSize_24bit) || \
- ((ADSIZE) == QSPI_ComConfig_ADSize_32bit))
-/**
- * @}
- */
-
-/** @defgroup QSPI_ComConfig_AddressMode
- * @{
- */
-#define QSPI_ComConfig_ADMode_NoAddress ((uint32_t)0x00000000)
-#define QSPI_ComConfig_ADMode_1Line ((uint32_t)QUADSPI_CCR_ADMODE_0)
-#define QSPI_ComConfig_ADMode_2Line ((uint32_t)QUADSPI_CCR_ADMODE_1)
-#define QSPI_ComConfig_ADMode_4Line ((uint32_t)QUADSPI_CCR_ADMODE)
-#define IS_QSPI_ADMODE(ADMODE) (((ADMODE) == QSPI_ComConfig_ADMode_NoAddress) || \
- ((ADMODE) == QSPI_ComConfig_ADMode_1Line) || \
- ((ADMODE) == QSPI_ComConfig_ADMode_2Line) || \
- ((ADMODE) == QSPI_ComConfig_ADMode_4Line))
-/**
- * @}
- */
-
-/** @defgroup QSPI_ComConfig_InstructionMode
- * @{
- */
-#define QSPI_ComConfig_IMode_NoInstruction ((uint32_t)0x00000000)
-#define QSPI_ComConfig_IMode_1Line ((uint32_t)QUADSPI_CCR_IMODE_0)
-#define QSPI_ComConfig_IMode_2Line ((uint32_t)QUADSPI_CCR_IMODE_1)
-#define QSPI_ComConfig_IMode_4Line ((uint32_t)QUADSPI_CCR_IMODE)
-#define IS_QSPI_IMODE(IMODE) (((IMODE) == QSPI_ComConfig_IMode_NoInstruction) || \
- ((IMODE) == QSPI_ComConfig_IMode_1Line) || \
- ((IMODE) == QSPI_ComConfig_IMode_2Line) || \
- ((IMODE) == QSPI_ComConfig_IMode_4Line))
-/**
- * @}
- */
-
-/** @defgroup QSPI_ComConfig_Instruction
- * @{
- */
-#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup QSPI_InterruptsDefinition
- * @{
- */
-#define QSPI_IT_TO (uint32_t)(QUADSPI_CR_TOIE | QUADSPI_SR_TOF)
-#define QSPI_IT_SM (uint32_t)(QUADSPI_CR_SMIE | QUADSPI_SR_SMF)
-#define QSPI_IT_FT (uint32_t)(QUADSPI_CR_FTIE | QUADSPI_SR_FTF)
-#define QSPI_IT_TC (uint32_t)(QUADSPI_CR_TCIE | QUADSPI_SR_TCF)
-#define QSPI_IT_TE (uint32_t)(QUADSPI_CR_TEIE | QUADSPI_SR_TEF)
-#define IS_QSPI_IT(IT) ((((IT) & 0xFFE0FFE0) == 0) && ((IT) != 0))
-#define IS_QSPI_CLEAR_IT(IT) ((((IT) & 0xFFE4FFE4) == 0) && ((IT) != 0))
-/**
- * @}
- */
-
-/** @defgroup QSPI_FlagsDefinition
- * @{
- */
-#define QSPI_FLAG_TO QUADSPI_SR_TOF
-#define QSPI_FLAG_SM QUADSPI_SR_SMF
-#define QSPI_FLAG_FT QUADSPI_SR_FTF
-#define QSPI_FLAG_TC QUADSPI_SR_TCF
-#define QSPI_FLAG_TE QUADSPI_SR_TEF
-#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY
-#define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_TO) || ((FLAG) == QSPI_FLAG_SM) || \
- ((FLAG) == QSPI_FLAG_FT) || ((FLAG) == QSPI_FLAG_TC) || \
- ((FLAG) == QSPI_FLAG_TE) || ((FLAG) == QSPI_FLAG_BUSY))
-#define IS_QSPI_CLEAR_FLAG(FLAG) (((FLAG) == QSPI_FLAG_TO) || ((FLAG) == QSPI_FLAG_SM) || \
- ((FLAG) == QSPI_FLAG_TC) || ((FLAG) == QSPI_FLAG_TE))
-
-/**
- * @}
- */
-
-/** @defgroup QSPI_Polling_Match_Mode
- * @{
- */
-#define QSPI_PMM_AND ((uint32_t)0x00000000)
-#define QSPI_PMM_OR ((uint32_t)QUADSPI_CR_PMM)
-#define IS_QSPI_PMM(PMM) (((PMM) == QSPI_PMM_AND) || ((PMM) == QSPI_PMM_OR))
-/**
- * @}
- */
-
-/** @defgroup QSPI_Polling_Interval
- * @{
- */
-#define IS_QSPI_PIR(PIR) ((PIR) <= QUADSPI_PIR_INTERVAL)
-/**
- * @}
- */
-
-/** @defgroup QSPI_Timeout
- * @{
- */
-#define IS_QSPI_TIMEOUT(TIMEOUT) ((TIMEOUT) <= QUADSPI_LPTR_TIMEOUT)
-/**
- * @}
- */
-
-/** @defgroup QSPI_DummyCycle
- * @{
- */
-#define IS_QSPI_DCY(DCY) ((DCY) <= 0x1F)
-/**
- * @}
- */
-
-/** @defgroup QSPI_FIFOThreshold
- * @{
- */
-#define IS_QSPI_FIFOTHRESHOLD(FIFOTHRESHOLD) ((FIFOTHRESHOLD) <= 0x0F)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Initialization and Configuration functions *********************************/
-void QSPI_DeInit(void);
-void QSPI_Init(QSPI_InitTypeDef* QSPI_InitStruct);
-void QSPI_StructInit(QSPI_InitTypeDef* QSPI_InitStruct);
-void QSPI_ComConfig_Init(QSPI_ComConfig_InitTypeDef* QSPI_ComConfig_InitStruct);
-void QSPI_ComConfig_StructInit(QSPI_ComConfig_InitTypeDef* QSPI_ComConfig_InitStruct);
-void QSPI_Cmd(FunctionalState NewState);
-void QSPI_AutoPollingMode_Config(uint32_t QSPI_Match, uint32_t QSPI_Mask , uint32_t QSPI_Match_Mode);
-void QSPI_AutoPollingMode_SetInterval(uint32_t QSPI_Interval);
-void QSPI_MemoryMappedMode_SetTimeout(uint32_t QSPI_Timeout);
-void QSPI_SetAddress(uint32_t QSPI_Address);
-void QSPI_SetAlternateByte(uint32_t QSPI_AlternateByte);
-void QSPI_SetFIFOThreshold(uint32_t QSPI_FIFOThreshold);
-void QSPI_SetDataLength(uint32_t QSPI_DataLength);
-void QSPI_TimeoutCounterCmd(FunctionalState NewState);
-void QSPI_AutoPollingModeStopCmd(FunctionalState NewState);
-void QSPI_AbortRequest(void);
-void QSPI_DualFlashMode_Cmd(FunctionalState NewState);
-
-/* Data transfers functions ***************************************************/
-void QSPI_SendData8(uint8_t Data);
-void QSPI_SendData16(uint16_t Data);
-void QSPI_SendData32(uint32_t Data);
-uint8_t QSPI_ReceiveData8(void);
-uint16_t QSPI_ReceiveData16(void);
-uint32_t QSPI_ReceiveData32(void);
-
-/* DMA transfers management functions *****************************************/
-void QSPI_DMACmd(FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void QSPI_ITConfig(uint32_t QSPI_IT, FunctionalState NewState);
-uint32_t QSPI_GetFIFOLevel(void);
-FlagStatus QSPI_GetFlagStatus(uint32_t QSPI_FLAG);
-void QSPI_ClearFlag(uint32_t QSPI_FLAG);
-ITStatus QSPI_GetITStatus(uint32_t QSPI_IT);
-void QSPI_ClearITPendingBit(uint32_t QSPI_IT);
-uint32_t QSPI_GetFMode(void);
-
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4XX_QUADSPI_H */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_rcc.c b/底盘/底盘-old/底盘/Library/stm32f4xx_rcc.c
deleted file mode 100644
index 7bd9355..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_rcc.c
+++ /dev/null
@@ -1,3184 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_rcc.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Reset and clock control (RCC) peripheral:
- * + Internal/external clocks, PLL, CSS and MCO configuration
- * + System, AHB and APB busses clocks configuration
- * + Peripheral clocks configuration
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### RCC specific features #####
- ===============================================================================
- [..]
- After reset the device is running from Internal High Speed oscillator
- (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
- and I-Cache are disabled, and all peripherals are off except internal
- SRAM, Flash and JTAG.
- (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
- all peripherals mapped on these busses are running at HSI speed.
- (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
- (+) All GPIOs are in input floating state, except the JTAG pins which
- are assigned to be used for debug purpose.
- [..]
- Once the device started from reset, the user application has to:
- (+) Configure the clock source to be used to drive the System clock
- (if the application needs higher frequency/performance)
- (+) Configure the System clock frequency and Flash settings
- (+) Configure the AHB and APB busses prescalers
- (+) Enable the clock for the peripheral(s) to be used
- (+) Configure the clock source(s) for peripherals which clocks are not
- derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup RCC
- * @brief RCC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ------------ RCC registers bit address in the alias region ----------- */
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
-/* --- CR Register ---*/
-/* Alias word address of HSION bit */
-#define CR_OFFSET (RCC_OFFSET + 0x00)
-#define HSION_BitNumber 0x00
-#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
-/* Alias word address of CSSON bit */
-#define CSSON_BitNumber 0x13
-#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
-/* Alias word address of PLLON bit */
-#define PLLON_BitNumber 0x18
-#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
-/* Alias word address of PLLI2SON bit */
-#define PLLI2SON_BitNumber 0x1A
-#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
-
-/* Alias word address of PLLSAION bit */
-#define PLLSAION_BitNumber 0x1C
-#define CR_PLLSAION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
-
-/* --- CFGR Register ---*/
-/* Alias word address of I2SSRC bit */
-#define CFGR_OFFSET (RCC_OFFSET + 0x08)
-#define I2SSRC_BitNumber 0x17
-#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
-
-/* --- BDCR Register ---*/
-/* Alias word address of RTCEN bit */
-#define BDCR_OFFSET (RCC_OFFSET + 0x70)
-#define RTCEN_BitNumber 0x0F
-#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
-/* Alias word address of BDRST bit */
-#define BDRST_BitNumber 0x10
-#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
-
-/* --- CSR Register ---*/
-/* Alias word address of LSION bit */
-#define CSR_OFFSET (RCC_OFFSET + 0x74)
-#define LSION_BitNumber 0x00
-#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
-
-/* --- DCKCFGR Register ---*/
-/* Alias word address of TIMPRE bit */
-#define DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
-#define TIMPRE_BitNumber 0x18
-#define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
-
-/* --- CFGR Register ---*/
-#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
- #if defined(STM32F410xx)
-/* Alias word address of MCO1EN bit */
-#define RCC_MCO1EN_BIT_NUMBER 0x8
-#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO1EN_BIT_NUMBER * 4))
-
-/* Alias word address of MCO2EN bit */
-#define RCC_MCO2EN_BIT_NUMBER 0x9
-#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO2EN_BIT_NUMBER * 4))
-#endif /* STM32F410xx */
-/* ---------------------- RCC registers bit mask ------------------------ */
-/* CFGR register bit mask */
-#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF)
-#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF)
-
-/* RCC Flag Mask */
-#define FLAG_MASK ((uint8_t)0x1F)
-
-/* CR register byte 3 (Bits[23:16]) base address */
-#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)
-
-/* CIR register byte 2 (Bits[15:8]) base address */
-#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
-
-/* CIR register byte 3 (Bits[23:16]) base address */
-#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
-
-/* BDCR register base address */
-#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RCC_Private_Functions
- * @{
- */
-
-/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
- * @brief Internal and external clocks, PLL, CSS and MCO configuration functions
- *
-@verbatim
- ===================================================================================
- ##### Internal and external clocks, PLL, CSS and MCO configuration functions #####
- ===================================================================================
- [..]
- This section provide functions allowing to configure the internal/external clocks,
- PLLs, CSS and MCO pins.
-
- (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
- the PLL as System clock source.
-
- (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
- clock source.
-
- (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
- through the PLL as System clock source. Can be used also as RTC clock source.
-
- (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
-
- (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
- (++) The first output is used to generate the high speed system clock (up to 168 MHz)
- (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
- the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
-
- (#) PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve
- high-quality audio performance on the I2S interface or SAI interface in case
- of STM32F429x/439x devices.
-
- (#) PLLSAI clocked by (HSI or HSE), used to generate an accurate clock to SAI
- interface and LCD TFT controller available only for STM32F42xxx/43xxx/446xx/469xx/479xx devices.
-
- (#) CSS (Clock security system), once enable and if a HSE clock failure occurs
- (HSE used directly or through PLL as System clock source), the System clock
- is automatically switched to HSI and an interrupt is generated if enabled.
- The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
- exception vector.
-
- (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
- clock (through a configurable prescaler) on PA8 pin.
-
- (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
- clock (through a configurable prescaler) on PC9 pin.
- @endverbatim
- * @{
- */
-
-/**
- * @brief Resets the RCC clock configuration to the default reset state.
- * @note The default reset state of the clock configuration is given below:
- * - HSI ON and used as system clock source
- * - HSE, PLL and PLLI2S OFF
- * - AHB, APB1 and APB2 prescaler set to 1.
- * - CSS, MCO1 and MCO2 OFF
- * - All interrupts disabled
- * @note This function doesn't modify the configuration of the
- * - Peripheral clocks
- * - LSI, LSE and RTC clocks
- * @param None
- * @retval None
- */
-void RCC_DeInit(void)
-{
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
-
- /* Reset HSEON, CSSON, PLLON, PLLI2S and PLLSAI(STM32F42xxx/43xxx/446xx/469xx/479xx devices) bits */
- RCC->CR &= (uint32_t)0xEAF6FFFF;
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x24003010;
-
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F413_423xx) || defined(STM32F469_479xx)
- /* Reset PLLI2SCFGR register */
- RCC->PLLI2SCFGR = 0x20003000;
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx || STM32F413_423xx || STM32F469_479xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
- /* Reset PLLSAICFGR register, only available for STM32F42xxx/43xxx/446xx/469xx/479xx devices */
- RCC->PLLSAICFGR = 0x24003000;
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-
- /* Disable Timers clock prescalers selection, only available for STM32F42/43xxx and STM32F413_423xx devices */
- RCC->DCKCFGR = 0x00000000;
-
-#if defined(STM32F410xx) || defined(STM32F413_423xx)
- /* Disable LPTIM and FMPI2C clock prescalers selection, only available for STM32F410xx and STM32F413_423xx devices */
- RCC->DCKCFGR2 = 0x00000000;
-#endif /* STM32F410xx || STM32F413_423xx */
-}
-
-/**
- * @brief Configures the External High Speed oscillator (HSE).
- * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
- * software should wait on HSERDY flag to be set indicating that HSE clock
- * is stable and can be used to clock the PLL and/or system clock.
- * @note HSE state can not be changed if it is used directly or through the
- * PLL as system clock. In this case, you have to select another source
- * of the system clock then change the HSE state (ex. disable it).
- * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
- * @note This function reset the CSSON bit, so if the Clock security system(CSS)
- * was previously enabled you have to enable it again after calling this
- * function.
- * @param RCC_HSE: specifies the new state of the HSE.
- * This parameter can be one of the following values:
- * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
- * 6 HSE oscillator clock cycles.
- * @arg RCC_HSE_ON: turn ON the HSE oscillator
- * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
- * @retval None
- */
-void RCC_HSEConfig(uint8_t RCC_HSE)
-{
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_HSE));
-
- /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
- *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;
-
- /* Set the new HSE configuration -------------------------------------------*/
- *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
-}
-
-/**
- * @brief Waits for HSE start-up.
- * @note This functions waits on HSERDY flag to be set and return SUCCESS if
- * this flag is set, otherwise returns ERROR if the timeout is reached
- * and this flag is not set. The timeout value is defined by the constant
- * HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending
- * on the HSE crystal used in your application.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: HSE oscillator is stable and ready to use
- * - ERROR: HSE oscillator not yet ready
- */
-ErrorStatus RCC_WaitForHSEStartUp(void)
-{
- __IO uint32_t startupcounter = 0;
- ErrorStatus status = ERROR;
- FlagStatus hsestatus = RESET;
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
- startupcounter++;
- } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET));
-
- if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
- {
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
- return (status);
-}
-
-/**
- * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI RC.
- * @param HSICalibrationValue: specifies the calibration trimming value.
- * This parameter must be a number between 0 and 0x1F.
- * @retval None
- */
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
-
- tmpreg = RCC->CR;
-
- /* Clear HSITRIM[4:0] bits */
- tmpreg &= ~RCC_CR_HSITRIM;
-
- /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
- tmpreg |= (uint32_t)HSICalibrationValue << 3;
-
- /* Store the new value */
- RCC->CR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Internal High Speed oscillator (HSI).
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
- * It is used (enabled by hardware) as system clock source after startup
- * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
- * of the HSE used directly or indirectly as system clock (if the Clock
- * Security System CSS is enabled).
- * @note HSI can not be stopped if it is used as system clock source. In this case,
- * you have to select another source of the system clock then stop the HSI.
- * @note After enabling the HSI, the application software should wait on HSIRDY
- * flag to be set indicating that HSI clock is stable and can be used as
- * system clock source.
- * @param NewState: new state of the HSI.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
- * clock cycles.
- * @retval None
- */
-void RCC_HSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the External Low Speed oscillator (LSE).
- * @note As the LSE is in the Backup domain and write access is denied to
- * this domain after reset, you have to enable write access using
- * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
- * (to be done once after reset).
- * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
- * software should wait on LSERDY flag to be set indicating that LSE clock
- * is stable and can be used to clock the RTC.
- * @param RCC_LSE: specifies the new state of the LSE.
- * This parameter can be one of the following values:
- * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
- * 6 LSE oscillator clock cycles.
- * @arg RCC_LSE_ON: turn ON the LSE oscillator
- * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
- * @retval None
- */
-void RCC_LSEConfig(uint8_t RCC_LSE)
-{
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_LSE));
-
- /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
- /* Reset LSEON bit */
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
-
- /* Reset LSEBYP bit */
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
-
- /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
- switch (RCC_LSE)
- {
- case RCC_LSE_ON:
- /* Set LSEON bit */
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
- break;
- case RCC_LSE_Bypass:
- /* Set LSEBYP and LSEON bits */
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Enables or disables the Internal Low Speed oscillator (LSI).
- * @note After enabling the LSI, the application software should wait on
- * LSIRDY flag to be set indicating that LSI clock is stable and can
- * be used to clock the IWDG and/or the RTC.
- * @note LSI can not be disabled if the IWDG is running.
- * @param NewState: new state of the LSI.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
- * clock cycles.
- * @retval None
- */
-void RCC_LSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
-}
-
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-/**
- * @brief Configures the main PLL clock source, multiplication and division factors.
- * @note This function must be used only when the main PLL is disabled.
- *
- * @param RCC_PLLSource: specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
- * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
- * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
- *
- * @param PLLM: specifies the division factor for PLL VCO input clock
- * This parameter must be a number between 0 and 63.
- * @note You have to set the PLLM parameter correctly to ensure that the VCO input
- * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
- * of 2 MHz to limit PLL jitter.
- *
- * @param PLLN: specifies the multiplication factor for PLL VCO output clock
- * This parameter must be a number between 50 and 432.
- * @note You have to set the PLLN parameter correctly to ensure that the VCO
- * output frequency is between 100 and 432 MHz.
- *
- * @param PLLP: specifies the division factor for main system clock (SYSCLK)
- * This parameter must be a number in the range {2, 4, 6, or 8}.
- * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
- * the System clock frequency.
- *
- * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
- * This parameter must be a number between 4 and 15.
- *
- * @param PLLR: specifies the division factor for I2S, SAI, SYSTEM, SPDIF in STM32F446xx devices
- * This parameter must be a number between 2 and 7.
- *
- * @note If the USB OTG FS is used in your application, you have to set the
- * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
- * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
- * correctly.
- *
- * @retval None
- */
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR)
-{
- /* Check the parameters */
- assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
- assert_param(IS_RCC_PLLM_VALUE(PLLM));
- assert_param(IS_RCC_PLLN_VALUE(PLLN));
- assert_param(IS_RCC_PLLP_VALUE(PLLP));
- assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
- assert_param(IS_RCC_PLLR_VALUE(PLLR));
-
- RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
- (PLLQ << 24) | (PLLR << 28);
-}
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
-/**
- * @brief Configures the main PLL clock source, multiplication and division factors.
- * @note This function must be used only when the main PLL is disabled.
- *
- * @param RCC_PLLSource: specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
- * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
- * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
- *
- * @param PLLM: specifies the division factor for PLL VCO input clock
- * This parameter must be a number between 0 and 63.
- * @note You have to set the PLLM parameter correctly to ensure that the VCO input
- * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
- * of 2 MHz to limit PLL jitter.
- *
- * @param PLLN: specifies the multiplication factor for PLL VCO output clock
- * This parameter must be a number between 50 and 432.
- * @note You have to set the PLLN parameter correctly to ensure that the VCO
- * output frequency is between 100 and 432 MHz.
- *
- * @param PLLP: specifies the division factor for main system clock (SYSCLK)
- * This parameter must be a number in the range {2, 4, 6, or 8}.
- * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
- * the System clock frequency.
- *
- * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
- * This parameter must be a number between 4 and 15.
- * @note If the USB OTG FS is used in your application, you have to set the
- * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
- * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
- * correctly.
- *
- * @retval None
- */
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
-{
- /* Check the parameters */
- assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
- assert_param(IS_RCC_PLLM_VALUE(PLLM));
- assert_param(IS_RCC_PLLN_VALUE(PLLN));
- assert_param(IS_RCC_PLLP_VALUE(PLLP));
- assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
-
- RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
- (PLLQ << 24);
-}
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
-
-/**
- * @brief Enables or disables the main PLL.
- * @note After enabling the main PLL, the application software should wait on
- * PLLRDY flag to be set indicating that PLL clock is stable and can
- * be used as system clock source.
- * @note The main PLL can not be disabled if it is used as system clock source
- * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
- * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_PLLCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
-}
-
-#if defined(STM32F40_41xxx) || defined(STM32F401xx)
-/**
- * @brief Configures the PLLI2S clock multiplication and division factors.
- *
- * @note This function can be used only for STM32F405xx/407xx, STM32F415xx/417xx
- * or STM32F401xx devices.
- *
- * @note This function must be used only when the PLLI2S is disabled.
- * @note PLLI2S clock source is common with the main PLL (configured in
- * RCC_PLLConfig function )
- *
- * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
- * This parameter must be a number between 50 and 432.
- * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
- * output frequency is between 100 and 432 MHz.
- *
- * @param PLLI2SR: specifies the division factor for I2S clock
- * This parameter must be a number between 2 and 7.
- * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
- * on the I2S clock frequency.
- *
- * @retval None
- */
-void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
-{
- /* Check the parameters */
- assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
- assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));
-
- RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);
-}
-#endif /* STM32F40_41xxx || STM32F401xx */
-
-#if defined(STM32F411xE)
-/**
- * @brief Configures the PLLI2S clock multiplication and division factors.
- *
- * @note This function can be used only for STM32F411xE devices.
- *
- * @note This function must be used only when the PLLI2S is disabled.
- * @note PLLI2S clock source is common with the main PLL (configured in
- * RCC_PLLConfig function )
- *
- * @param PLLI2SM: specifies the division factor for PLLI2S VCO input clock
- * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
- * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
- * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
- * of 2 MHz to limit PLLI2S jitter.
- *
- * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
- * This parameter must be a number between 50 and 432.
- * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
- * output frequency is between 100 and 432 MHz.
- *
- * @param PLLI2SR: specifies the division factor for I2S clock
- * This parameter must be a number between 2 and 7.
- * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
- * on the I2S clock frequency.
- *
- * @retval None
- */
-void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM)
-{
- /* Check the parameters */
- assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
- assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SM));
- assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));
-
- RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28) | PLLI2SM;
-}
-#endif /* STM32F411xE */
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
-/**
- * @brief Configures the PLLI2S clock multiplication and division factors.
- *
- * @note This function can be used only for STM32F42xxx/43xxx devices
- *
- * @note This function must be used only when the PLLI2S is disabled.
- * @note PLLI2S clock source is common with the main PLL (configured in
- * RCC_PLLConfig function )
- *
- * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
- * This parameter must be a number between 50 and 432.
- * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
- * output frequency is between 100 and 432 MHz.
- *
- * @param PLLI2SQ: specifies the division factor for SAI1 clock
- * This parameter must be a number between 2 and 15.
- *
- * @param PLLI2SR: specifies the division factor for I2S clock
- * This parameter must be a number between 2 and 7.
- * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
- * on the I2S clock frequency.
- *
- * @retval None
- */
-void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR)
-{
- /* Check the parameters */
- assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
- assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SQ));
- assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));
-
- RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SQ << 24) | (PLLI2SR << 28);
-}
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
-
-#if defined(STM32F412xG ) || defined(STM32F413_423xx) || defined(STM32F446xx)
-/**
- * @brief Configures the PLLI2S clock multiplication and division factors.
- *
- * @note This function can be used only for STM32F446xx devices
- *
- * @note This function must be used only when the PLLI2S is disabled.
- * @note PLLI2S clock source is common with the main PLL (configured in
- * RCC_PLLConfig function )
- *
- * @param PLLI2SM: specifies the division factor for PLLI2S VCO input clock
- * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
- * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
- * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
- * of 2 MHz to limit PLLI2S jitter.
- *
- * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
- * This parameter must be a number between 50 and 432.
- * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
- * output frequency is between 100 and 432 MHz.
- *
- * @param PLLI2SP: specifies the division factor for PLL 48Mhz clock output
- * This parameter must be a number in the range {2, 4, 6, or 8}.
- *
- * @param PLLI2SQ: specifies the division factor for SAI1 clock
- * This parameter must be a number between 2 and 15.
- *
- * @param PLLI2SR: specifies the division factor for I2S clock
- * This parameter must be a number between 2 and 7.
- * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
- * on the I2S clock frequency.
- * @note the PLLI2SR parameter is only available with STM32F42xxx/43xxx devices.
- *
- * @retval None
- */
-void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR)
-{
- /* Check the parameters */
- assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SM));
- assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
- assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SP));
- assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SQ));
- assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));
-
- RCC->PLLI2SCFGR = PLLI2SM | (PLLI2SN << 6) | (((PLLI2SP >> 1) -1) << 16) | (PLLI2SQ << 24) | (PLLI2SR << 28);
-}
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
-
-/**
- * @brief Enables or disables the PLLI2S.
- * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
- * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_PLLI2SCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState;
-}
-
-#if defined(STM32F469_479xx)
-/**
- * @brief Configures the PLLSAI clock multiplication and division factors.
- *
- * @note This function can be used only for STM32F469_479xx devices
- *
- * @note This function must be used only when the PLLSAI is disabled.
- * @note PLLSAI clock source is common with the main PLL (configured in
- * RCC_PLLConfig function )
- *
- * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock
- * This parameter must be a number between 50 and 432.
- * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
- * output frequency is between 100 and 432 MHz.
- *
- * @param PLLSAIP: specifies the division factor for PLL 48Mhz clock output
- * This parameter must be a number in the range {2, 4, 6, or 8}..
- *
- * @param PLLSAIQ: specifies the division factor for SAI1 clock
- * This parameter must be a number between 2 and 15.
- *
- * @param PLLSAIR: specifies the division factor for LTDC clock
- * This parameter must be a number between 2 and 7.
- *
- * @retval None
- */
-void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR)
-{
- /* Check the parameters */
- assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIN));
- assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIP));
- assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIQ));
- assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIR));
-
- RCC->PLLSAICFGR = (PLLSAIN << 6) | (((PLLSAIP >> 1) -1) << 16) | (PLLSAIQ << 24) | (PLLSAIR << 28);
-}
-#endif /* STM32F469_479xx */
-
-#if defined(STM32F446xx)
-/**
- * @brief Configures the PLLSAI clock multiplication and division factors.
- *
- * @note This function can be used only for STM32F446xx devices
- *
- * @note This function must be used only when the PLLSAI is disabled.
- * @note PLLSAI clock source is common with the main PLL (configured in
- * RCC_PLLConfig function )
- *
- * @param PLLSAIM: specifies the division factor for PLLSAI VCO input clock
- * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
- * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
- * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
- * of 2 MHz to limit PLLSAI jitter.
- *
- * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock
- * This parameter must be a number between 50 and 432.
- * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
- * output frequency is between 100 and 432 MHz.
- *
- * @param PLLSAIP: specifies the division factor for PLL 48Mhz clock output
- * This parameter must be a number in the range {2, 4, 6, or 8}.
- *
- * @param PLLSAIQ: specifies the division factor for SAI1 clock
- * This parameter must be a number between 2 and 15.
- *
- * @retval None
- */
-void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ)
-{
- /* Check the parameters */
- assert_param(IS_RCC_PLLSAIM_VALUE(PLLSAIM));
- assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIN));
- assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIP));
- assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIQ));
-
- RCC->PLLSAICFGR = PLLSAIM | (PLLSAIN << 6) | (((PLLSAIP >> 1) -1) << 16) | (PLLSAIQ << 24);
-}
-#endif /* STM32F446xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
-/**
- * @brief Configures the PLLSAI clock multiplication and division factors.
- *
- * @note This function can be used only for STM32F42xxx/43xxx devices
- *
- * @note This function must be used only when the PLLSAI is disabled.
- * @note PLLSAI clock source is common with the main PLL (configured in
- * RCC_PLLConfig function )
- *
- * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock
- * This parameter must be a number between 50 and 432.
- * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
- * output frequency is between 100 and 432 MHz.
- *
- * @param PLLSAIQ: specifies the division factor for SAI1 clock
- * This parameter must be a number between 2 and 15.
- *
- * @param PLLSAIR: specifies the division factor for LTDC clock
- * This parameter must be a number between 2 and 7.
- *
- * @retval None
- */
-void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR)
-{
- /* Check the parameters */
- assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIN));
- assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIR));
- assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIQ));
-
- RCC->PLLSAICFGR = (PLLSAIN << 6) | (PLLSAIQ << 24) | (PLLSAIR << 28);
-}
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
-
-/**
- * @brief Enables or disables the PLLSAI.
- *
- * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices
- *
- * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
- * @param NewState: new state of the PLLSAI. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_PLLSAICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) CR_PLLSAION_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the Clock Security System.
- * @note If a failure is detected on the HSE oscillator clock, this oscillator
- * is automatically disabled and an interrupt is generated to inform the
- * software about the failure (Clock Security System Interrupt, CSSI),
- * allowing the MCU to perform rescue operations. The CSSI is linked to
- * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
- * @param NewState: new state of the Clock Security System.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Selects the clock source to output on MCO1 pin(PA8).
- * @note PA8 should be configured in alternate function mode.
- * @param RCC_MCO1Source: specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source
- * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source
- * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source
- * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source
- * @param RCC_MCO1Div: specifies the MCO1 prescaler.
- * This parameter can be one of the following values:
- * @arg RCC_MCO1Div_1: no division applied to MCO1 clock
- * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock
- * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock
- * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock
- * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock
- * @retval None
- */
-void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source));
- assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div));
-
- tmpreg = RCC->CFGR;
-
- /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */
- tmpreg &= CFGR_MCO1_RESET_MASK;
-
- /* Select MCO1 clock source and prescaler */
- tmpreg |= RCC_MCO1Source | RCC_MCO1Div;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-
-#if defined(STM32F410xx)
- RCC_MCO1Cmd(ENABLE);
-#endif /* STM32F410xx */
-}
-
-/**
- * @brief Selects the clock source to output on MCO2 pin(PC9).
- * @note PC9 should be configured in alternate function mode.
- * @param RCC_MCO2Source: specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source
- * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
- * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410xx devices
- * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source
- * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source
- * @param RCC_MCO2Div: specifies the MCO2 prescaler.
- * This parameter can be one of the following values:
- * @arg RCC_MCO2Div_1: no division applied to MCO2 clock
- * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock
- * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock
- * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock
- * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock
- * @note For STM32F410xx devices to output I2SCLK clock on MCO2 you should have
- * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
- * @retval None
- */
-void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source));
- assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div));
-
- tmpreg = RCC->CFGR;
-
- /* Clear MCO2 and MCO2PRE[2:0] bits */
- tmpreg &= CFGR_MCO2_RESET_MASK;
-
- /* Select MCO2 clock source and prescaler */
- tmpreg |= RCC_MCO2Source | RCC_MCO2Div;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-
-#if defined(STM32F410xx)
- RCC_MCO2Cmd(ENABLE);
-#endif /* STM32F410xx */
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
- * @brief System, AHB and APB busses clocks configuration functions
- *
-@verbatim
- ===============================================================================
- ##### System, AHB and APB busses clocks configuration functions #####
- ===============================================================================
- [..]
- This section provide functions allowing to configure the System, AHB, APB1 and
- APB2 busses clocks.
-
- (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
- HSE and PLL.
- The AHB clock (HCLK) is derived from System clock through configurable
- prescaler and used to clock the CPU, memory and peripherals mapped
- on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
- from AHB clock through configurable prescalers and used to clock
- the peripherals mapped on these busses. You can use
- "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
-
- -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
- (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
- from an external clock mapped on the I2S_CKIN pin.
- You have to use RCC_I2SCLKConfig() function to configure this clock.
- (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
- divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd()
- functions to configure this clock.
- (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
- to work correctly, while the SDIO require a frequency equal or lower than
- to 48. This clock is derived of the main PLL through PLLQ divider.
- (+@) IWDG clock which is always the LSI clock.
-
- (#) For STM32F405xx/407xx and STM32F415xx/417xx devices, the maximum frequency
- of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending
- on the device voltage range, the maximum frequency should be adapted accordingly:
- +-------------------------------------------------------------------------------------+
- | Latency | HCLK clock frequency (MHz) |
- | |---------------------------------------------------------------------|
- | | voltage range | voltage range | voltage range | voltage range |
- | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
- |---------------|----------------|----------------|-----------------|-----------------|
- |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
- |---------------|----------------|----------------|-----------------|-----------------|
- |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
- |---------------|----------------|----------------|-----------------|-----------------|
- |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160|
- +---------------|----------------|----------------|-----------------|-----------------+
- (#) For STM32F42xxx/43xxx/469xx/479xx devices, the maximum frequency of the SYSCLK and HCLK is 180 MHz,
- PCLK2 90 MHz and PCLK1 45 MHz. Depending on the device voltage range, the maximum
- frequency should be adapted accordingly:
- +-------------------------------------------------------------------------------------+
- | Latency | HCLK clock frequency (MHz) |
- | |---------------------------------------------------------------------|
- | | voltage range | voltage range | voltage range | voltage range |
- | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
- |---------------|----------------|----------------|-----------------|-----------------|
- |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
- |---------------|----------------|----------------|-----------------|-----------------|
- |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
- |---------------|----------------|----------------|-----------------|-----------------|
- |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160|
- |---------------|----------------|----------------|-----------------|-----------------|
- |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168|
- +-------------------------------------------------------------------------------------+
-
- (#) For STM32F401xx devices, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
- PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum
- frequency should be adapted accordingly:
- +-------------------------------------------------------------------------------------+
- | Latency | HCLK clock frequency (MHz) |
- | |---------------------------------------------------------------------|
- | | voltage range | voltage range | voltage range | voltage range |
- | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
- |---------------|----------------|----------------|-----------------|-----------------|
- |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 |
- +-------------------------------------------------------------------------------------+
-
- (#) For STM32F410xx/STM32F411xE devices, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
- PCLK2 100 MHz and PCLK1 50 MHz. Depending on the device voltage range, the maximum
- frequency should be adapted accordingly:
- +-------------------------------------------------------------------------------------+
- | Latency | HCLK clock frequency (MHz) |
- | |---------------------------------------------------------------------|
- | | voltage range | voltage range | voltage range | voltage range |
- | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
- |---------------|----------------|----------------|-----------------|-----------------|
- |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |1WS(2CPU cycle)|30 < HCLK <= 64 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |2WS(3CPU cycle)|64 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |3WS(4CPU cycle)|90 < HCLK <= 100|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |4WS(5CPU cycle)| NA |96 < HCLK <= 100|72 < HCLK <= 90 |64 < HCLK <= 80 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 100 |80 < HCLK <= 96 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |6WS(7CPU cycle)| NA | NA | NA |96 < HCLK <= 100 |
- +-------------------------------------------------------------------------------------+
-
- -@- On STM32F405xx/407xx and STM32F415xx/417xx devices:
- (++) when VOS = '0', the maximum value of fHCLK = 144MHz.
- (++) when VOS = '1', the maximum value of fHCLK = 168MHz.
- [..]
- On STM32F42xxx/43xxx/469xx/479xx devices:
- (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 120MHz.
- (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 144MHz.
- (++) when VOS[1:0] = '0x11', the maximum value of f is 168MHz
- [..]
- On STM32F401x devices:
- (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 64MHz.
- (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 84MHz.
- On STM32F410xx/STM32F411xE devices:
- (++) when VOS[1:0] = '0x01' the maximum value of fHCLK is 64MHz.
- (++) when VOS[1:0] = '0x10' the maximum value of fHCLK is 84MHz.
- (++) when VOS[1:0] = '0x11' the maximum value of fHCLK is 100MHz.
-
- You can use PWR_MainRegulatorModeConfig() function to control VOS bits.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the system clock (SYSCLK).
- * @note The HSI is used (enabled by hardware) as system clock source after
- * startup from Reset, wake-up from STOP and STANDBY mode, or in case
- * of failure of the HSE used directly or indirectly as system clock
- * (if the Clock Security System CSS is enabled).
- * @note A switch from one clock source to another occurs only if the target
- * clock source is ready (clock stable after startup delay or PLL locked).
- * If a clock source which is not yet ready is selected, the switch will
- * occur when the clock source will be ready.
- * You can use RCC_GetSYSCLKSource() function to know which clock is
- * currently used as system clock source.
- * @param RCC_SYSCLKSource: specifies the clock source used as system clock.
- * This parameter can be one of the following values:
- * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
- * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
- * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source (RCC_SYSCLKSource_PLLPCLK for STM32F446xx devices)
- * @arg RCC_SYSCLKSource_PLLRCLK: PLL R selected as system clock source only for STM32F412xG, STM32F413_423xx and STM32F446xx devices
- * @retval None
- */
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
-
- tmpreg = RCC->CFGR;
-
- /* Clear SW[1:0] bits */
- tmpreg &= ~RCC_CFGR_SW;
-
- /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
- tmpreg |= RCC_SYSCLKSource;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Returns the clock source used as system clock.
- * @param None
- * @retval The clock source used as system clock. The returned value can be one
- * of the following:
- * - 0x00: HSI used as system clock
- * - 0x04: HSE used as system clock
- * - 0x08: PLL used as system clock (PLL P for STM32F446xx devices)
- * - 0x0C: PLL R used as system clock (only for STM32F412xG, STM32F413_423xx and STM32F446xx devices)
- */
-uint8_t RCC_GetSYSCLKSource(void)
-{
- return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
-}
-
-/**
- * @brief Configures the AHB clock (HCLK).
- * @note Depending on the device voltage range, the software has to set correctly
- * these bits to ensure that HCLK not exceed the maximum allowed frequency
- * (for more details refer to section above
- * "CPU, AHB and APB busses clocks configuration functions")
- * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
- * the system clock (SYSCLK).
- * This parameter can be one of the following values:
- * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
- * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
- * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
- * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
- * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
- * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
- * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
- * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
- * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
- * @retval None
- */
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_HCLK(RCC_SYSCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear HPRE[3:0] bits */
- tmpreg &= ~RCC_CFGR_HPRE;
-
- /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
- tmpreg |= RCC_SYSCLK;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Configures the Low Speed APB clock (PCLK1).
- * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
- * the AHB clock (HCLK).
- * This parameter can be one of the following values:
- * @arg RCC_HCLK_Div1: APB1 clock = HCLK
- * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
- * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
- * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
- * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
- * @retval None
- */
-void RCC_PCLK1Config(uint32_t RCC_HCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PCLK(RCC_HCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear PPRE1[2:0] bits */
- tmpreg &= ~RCC_CFGR_PPRE1;
-
- /* Set PPRE1[2:0] bits according to RCC_HCLK value */
- tmpreg |= RCC_HCLK;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Configures the High Speed APB clock (PCLK2).
- * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
- * the AHB clock (HCLK).
- * This parameter can be one of the following values:
- * @arg RCC_HCLK_Div1: APB2 clock = HCLK
- * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
- * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
- * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
- * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
- * @retval None
- */
-void RCC_PCLK2Config(uint32_t RCC_HCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PCLK(RCC_HCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear PPRE2[2:0] bits */
- tmpreg &= ~RCC_CFGR_PPRE2;
-
- /* Set PPRE2[2:0] bits according to RCC_HCLK value */
- tmpreg |= RCC_HCLK << 3;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK,
- * PCLK1 and PCLK2.
- *
- * @note The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
- * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
- * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- * @note (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
- * 16 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- * @note (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
- * 25 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * @note The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
- * the clocks frequencies.
- *
- * @note This function can be used by the user application to compute the
- * baudrate for the communication peripherals or configure other parameters.
- * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
- * must be called to update the structure's field. Otherwise, any
- * configuration based on this function will be incorrect.
- *
- * @retval None
- */
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
-{
- uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
- uint32_t pllr = 2;
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock source */
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock source */
- RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
- break;
- case 0x08: /* PLL P used as system clock source */
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
- SYSCLK = PLL_VCO / PLLP
- */
- pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-
- if (pllsource != 0)
- {
- /* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
- else
- {
- /* HSI used as PLL clock source */
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
-
- pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
- RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
- break;
-
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
- case 0x0C: /* PLL R used as system clock source */
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
- SYSCLK = PLL_VCO / PLLR
- */
- pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-
- if (pllsource != 0)
- {
- /* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
- else
- {
- /* HSI used as PLL clock source */
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
-
- pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >>28) + 1 ) *2;
- RCC_Clocks->SYSCLK_Frequency = pllvco/pllr;
- break;
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
-
- default:
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- }
- /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/
-
- /* Get HCLK prescaler */
- tmp = RCC->CFGR & RCC_CFGR_HPRE;
- tmp = tmp >> 4;
- presc = APBAHBPrescTable[tmp];
- /* HCLK clock frequency */
- RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
-
- /* Get PCLK1 prescaler */
- tmp = RCC->CFGR & RCC_CFGR_PPRE1;
- tmp = tmp >> 10;
- presc = APBAHBPrescTable[tmp];
- /* PCLK1 clock frequency */
- RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-
- /* Get PCLK2 prescaler */
- tmp = RCC->CFGR & RCC_CFGR_PPRE2;
- tmp = tmp >> 13;
- presc = APBAHBPrescTable[tmp];
- /* PCLK2 clock frequency */
- RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group3 Peripheral clocks configuration functions
- * @brief Peripheral clocks configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral clocks configuration functions #####
- ===============================================================================
- [..] This section provide functions allowing to configure the Peripheral clocks.
-
- (#) The RTC clock which is derived from the LSI, LSE or HSE clock divided
- by 2 to 31.
-
- (#) After restart from Reset or wakeup from STANDBY, all peripherals are off
- except internal SRAM, Flash and JTAG. Before to start using a peripheral
- you have to enable its interface clock. You can do this using
- RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
-
- (#) To reset the peripherals configuration (to the default state after device reset)
- you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and
- RCC_APB1PeriphResetCmd() functions.
-
- (#) To further reduce power consumption in SLEEP mode the peripheral clocks
- can be disabled prior to executing the WFI or WFE instructions.
- You can do this using RCC_AHBPeriphClockLPModeCmd(),
- RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the RTC clock (RTCCLK).
- * @note As the RTC clock configuration bits are in the Backup domain and write
- * access is denied to this domain after reset, you have to enable write
- * access using PWR_BackupAccessCmd(ENABLE) function before to configure
- * the RTC clock source (to be done once after reset).
- * @note Once the RTC clock is configured it can't be changed unless the
- * Backup domain is reset using RCC_BackupResetCmd() function, or by
- * a Power On Reset (POR).
- *
- * @param RCC_RTCCLKSource: specifies the RTC clock source.
- * This parameter can be one of the following values:
- * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
- * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
- * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected
- * as RTC clock, where x:[2,31]
- *
- * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
- * work in STOP and STANDBY modes, and can be used as wakeup source.
- * However, when the HSE clock is used as RTC clock source, the RTC
- * cannot be used in STOP and STANDBY modes.
- * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
- * RTC clock source).
- *
- * @retval None
- */
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
-
- if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300)
- { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
- tmpreg = RCC->CFGR;
-
- /* Clear RTCPRE[4:0] bits */
- tmpreg &= ~RCC_CFGR_RTCPRE;
-
- /* Configure HSE division factor for RTC clock */
- tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF);
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
- }
-
- /* Select the RTC clock source */
- RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF);
-}
-
-/**
- * @brief Enables or disables the RTC clock.
- * @note This function must be used only after the RTC clock source was selected
- * using the RCC_RTCCLKConfig function.
- * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_RTCCLKCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Forces or releases the Backup domain reset.
- * @note This function resets the RTC peripheral (including the backup registers)
- * and the RTC clock source selection in RCC_CSR register.
- * @note The BKPSRAM is not affected by this reset.
- * @param NewState: new state of the Backup domain reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_BackupResetCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
-}
-
-#if defined (STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-/**
- * @brief Configures the I2S clock source (I2SCLK).
- * @note This function must be called before enabling the I2S APB clock.
- *
- * @param RCC_I2SAPBx: specifies the APBx I2S clock source.
- * This parameter can be one of the following values:
- * @arg RCC_I2SBus_APB1: I2S peripheral instance is on APB1 Bus
- * @arg RCC_I2SBus_APB2: I2S peripheral instance is on APB2 Bus
- *
- * @param RCC_I2SCLKSource: specifies the I2S clock source.
- * This parameter can be one of the following values:
- * @arg RCC_I2SCLKSource_PLLI2S: PLLI2S clock used as I2S clock source
- * @arg RCC_I2SCLKSource_Ext: External clock mapped on the I2S_CKIN pin
- * used as I2S clock source
- * @arg RCC_I2SCLKSource_PLL: PLL clock used as I2S clock source
- * @arg RCC_I2SCLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as I2S clock source
- * @retval None
- */
-void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
- assert_param(IS_RCC_I2S_APBx(RCC_I2SAPBx));
-
- if(RCC_I2SAPBx == RCC_I2SBus_APB1)
- {
- /* Clear APB1 I2Sx clock source selection bits */
- RCC->DCKCFGR &= ~RCC_DCKCFGR_I2S1SRC;
- /* Set new APB1 I2Sx clock source*/
- RCC->DCKCFGR |= RCC_I2SCLKSource;
- }
- else
- {
- /* Clear APB2 I2Sx clock source selection bits */
- RCC->DCKCFGR &= ~RCC_DCKCFGR_I2S2SRC;
- /* Set new APB2 I2Sx clock source */
- RCC->DCKCFGR |= (RCC_I2SCLKSource << 2);
- }
-}
-#if defined(STM32F446xx)
-/**
- * @brief Configures the SAIx clock source (SAIxCLK).
- * @note This function must be called before enabling the SAIx APB clock.
- *
- * @param RCC_SAIInstance: specifies the SAIx clock source.
- * This parameter can be one of the following values:
- * @arg RCC_SAIInstance_SAI1: SAI1 clock source selection
- * @arg RCC_SAIInstance_SAI2: SAI2 clock source selections
- *
- * @param RCC_SAICLKSource: specifies the SAI clock source.
- * This parameter can be one of the following values:
- * @arg RCC_SAICLKSource_PLLSAI: PLLSAI clock used as SAI clock source
- * @arg RCC_SAICLKSource_PLLI2S: PLLI2S clock used as SAI clock source
- * @arg RCC_SAICLKSource_PLL: PLL clock used as SAI clock source
- * @arg RCC_SAICLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source
- * @retval None
- */
-void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_SAICLK_SOURCE(RCC_SAICLKSource));
- assert_param(IS_RCC_SAI_INSTANCE(RCC_SAIInstance));
-
- if(RCC_SAIInstance == RCC_SAIInstance_SAI1)
- {
- /* Clear SAI1 clock source selection bits */
- RCC->DCKCFGR &= ~RCC_DCKCFGR_SAI1SRC;
- /* Set new SAI1 clock source */
- RCC->DCKCFGR |= RCC_SAICLKSource;
- }
- else
- {
- /* Clear SAI2 clock source selection bits */
- RCC->DCKCFGR &= ~RCC_DCKCFGR_SAI2SRC;
- /* Set new SAI2 clock source */
- RCC->DCKCFGR |= (RCC_SAICLKSource << 2);
- }
-}
-#endif /* STM32F446xx */
-
-#if defined(STM32F413_423xx)
-/**
- * @brief Configures SAI1BlockA clock source selection.
- * @note This function must be called before enabling PLLSAI, PLLI2S and
- * the SAI clock.
- * @param RCC_SAIBlockACLKSource: specifies the SAI Block A clock source.
- * This parameter can be one of the following values:
- * @arg RCC_SAIACLKSource_PLLI2SR: PLLI2SR clock used as SAI clock source
- * @arg RCC_SAIACLKSource_PLLI2S: PLLI2S clock used as SAI clock source
- * @arg RCC_SAIACLKSource_PLL: PLL clock used as SAI clock source
- * @arg RCC_SAIACLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source
- * @retval None
- */
-void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource));
-
- tmpreg = RCC->DCKCFGR;
-
- /* Clear RCC_DCKCFGR_SAI1ASRC[1:0] bits */
- tmpreg &= ~RCC_DCKCFGR_SAI1ASRC;
-
- /* Set SAI Block A source selection value */
- tmpreg |= RCC_SAIBlockACLKSource;
-
- /* Store the new value */
- RCC->DCKCFGR = tmpreg;
-}
-
-/**
- * @brief Configures SAI1BlockB clock source selection.
- * @note This function must be called before enabling PLLSAI, PLLI2S and
- * the SAI clock.
- * @param RCC_SAIBlockBCLKSource: specifies the SAI Block B clock source.
- * This parameter can be one of the following values:
- * @arg RCC_SAIBCLKSource_PLLI2SR: PLLI2SR clock used as SAI clock source
- * @arg RCC_SAIBCLKSource_PLLI2S: PLLI2S clock used as SAI clock source
- * @arg RCC_SAIBCLKSource_PLL: PLL clock used as SAI clock source
- * @arg RCC_SAIBCLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source
- * @retval None
- */
-void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource));
-
- tmpreg = RCC->DCKCFGR;
-
- /* Clear RCC_DCKCFGR_SAI1ASRC[1:0] bits */
- tmpreg &= ~RCC_DCKCFGR_SAI1BSRC;
-
- /* Set SAI Block B source selection value */
- tmpreg |= RCC_SAIBlockBCLKSource;
-
- /* Store the new value */
- RCC->DCKCFGR = tmpreg;
-}
-#endif /* STM32F413_423xx */
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
-
-#if defined(STM32F410xx)
-/**
- * @brief Configures the I2S clock source (I2SCLK).
- * @note This function must be called before enabling the I2S clock.
- *
- * @param RCC_I2SCLKSource: specifies the I2S clock source.
- * This parameter can be one of the following values:
- * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
- * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
- * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
- * @retval None
- */
-void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
-
- /* Clear I2Sx clock source selection bits */
- RCC->DCKCFGR &= ~RCC_DCKCFGR_I2SSRC;
- /* Set new I2Sx clock source*/
- RCC->DCKCFGR |= RCC_I2SCLKSource;
-}
-#endif /* STM32F410xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
-/**
- * @brief Configures the I2S clock source (I2SCLK).
- * @note This function must be called before enabling the I2S APB clock.
- * @param RCC_I2SCLKSource: specifies the I2S clock source.
- * This parameter can be one of the following values:
- * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
- * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin
- * used as I2S clock source
- * @retval None
- */
-void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
-
- *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
-}
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
-/**
- * @brief Configures SAI1BlockA clock source selection.
- *
- * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices.
- *
- * @note This function must be called before enabling PLLSAI, PLLI2S and
- * the SAI clock.
- * @param RCC_SAIBlockACLKSource: specifies the SAI Block A clock source.
- * This parameter can be one of the following values:
- * @arg RCC_SAIACLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
- * as SAI1 Block A clock
- * @arg RCC_SAIACLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
- * as SAI1 Block A clock
- * @arg RCC_SAIACLKSource_Ext: External clock mapped on the I2S_CKIN pin
- * used as SAI1 Block A clock
- * @retval None
- */
-void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource));
-
- tmpreg = RCC->DCKCFGR;
-
- /* Clear RCC_DCKCFGR_SAI1ASRC[1:0] bits */
- tmpreg &= ~RCC_DCKCFGR_SAI1ASRC;
-
- /* Set SAI Block A source selection value */
- tmpreg |= RCC_SAIBlockACLKSource;
-
- /* Store the new value */
- RCC->DCKCFGR = tmpreg;
-}
-
-/**
- * @brief Configures SAI1BlockB clock source selection.
- *
- * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices.
- *
- * @note This function must be called before enabling PLLSAI, PLLI2S and
- * the SAI clock.
- * @param RCC_SAIBlockBCLKSource: specifies the SAI Block B clock source.
- * This parameter can be one of the following values:
- * @arg RCC_SAIBCLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
- * as SAI1 Block B clock
- * @arg RCC_SAIBCLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
- * as SAI1 Block B clock
- * @arg RCC_SAIBCLKSource_Ext: External clock mapped on the I2S_CKIN pin
- * used as SAI1 Block B clock
- * @retval None
- */
-void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource));
-
- tmpreg = RCC->DCKCFGR;
-
- /* Clear RCC_DCKCFGR_SAI1BSRC[1:0] bits */
- tmpreg &= ~RCC_DCKCFGR_SAI1BSRC;
-
- /* Set SAI Block B source selection value */
- tmpreg |= RCC_SAIBlockBCLKSource;
-
- /* Store the new value */
- RCC->DCKCFGR = tmpreg;
-}
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
-
-/**
- * @brief Configures the SAI clock Divider coming from PLLI2S.
- *
- * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices.
- *
- * @note This function must be called before enabling the PLLI2S.
- *
- * @param RCC_PLLI2SDivQ: specifies the PLLI2S division factor for SAI1 clock .
- * This parameter must be a number between 1 and 32.
- * SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ
- *
- * @retval None
- */
-void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(RCC_PLLI2SDivQ));
-
- tmpreg = RCC->DCKCFGR;
-
- /* Clear PLLI2SDIVQ[4:0] bits */
- tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVQ);
-
- /* Set PLLI2SDIVQ values */
- tmpreg |= (RCC_PLLI2SDivQ - 1);
-
- /* Store the new value */
- RCC->DCKCFGR = tmpreg;
-}
-
-/**
- * @brief Configures the SAI clock Divider coming from PLLSAI.
- *
- * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices.
- *
- * @note This function must be called before enabling the PLLSAI.
- *
- * @param RCC_PLLSAIDivQ: specifies the PLLSAI division factor for SAI1 clock .
- * This parameter must be a number between 1 and 32.
- * SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ
- *
- * @retval None
- */
-void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(RCC_PLLSAIDivQ));
-
- tmpreg = RCC->DCKCFGR;
-
- /* Clear PLLI2SDIVQ[4:0] and PLLSAIDIVQ[4:0] bits */
- tmpreg &= ~(RCC_DCKCFGR_PLLSAIDIVQ);
-
- /* Set PLLSAIDIVQ values */
- tmpreg |= ((RCC_PLLSAIDivQ - 1) << 8);
-
- /* Store the new value */
- RCC->DCKCFGR = tmpreg;
-}
-
-#if defined(STM32F413_423xx)
-/**
- * @brief Configures the SAI clock Divider coming from PLLI2S.
- *
- * @note This function can be used only for STM32F413_423xx
- *
- * @param RCC_PLLI2SDivR: specifies the PLLI2S division factor for SAI1 clock.
- * This parameter must be a number between 1 and 32.
- * SAI1 clock frequency = f(PLLI2SR) / RCC_PLLI2SDivR
- * @retval None
- */
-void RCC_SAIPLLI2SRClkDivConfig(uint32_t RCC_PLLI2SDivR)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PLLI2S_DIVR_VALUE(RCC_PLLI2SDivR));
-
- tmpreg = RCC->DCKCFGR;
-
- /* Clear PLLI2SDIVR[4:0] bits */
- tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVR);
-
- /* Set PLLI2SDIVR values */
- tmpreg |= (RCC_PLLI2SDivR-1);
-
- /* Store the new value */
- RCC->DCKCFGR = tmpreg;
-}
-
-/**
- * @brief Configures the SAI clock Divider coming from PLL.
- *
- * @note This function can be used only for STM32F413_423xx
- *
- * @note This function must be called before enabling the PLLSAI.
- *
- * @param RCC_PLLDivR: specifies the PLL division factor for SAI1 clock.
- * This parameter must be a number between 1 and 32.
- * SAI1 clock frequency = f(PLLR) / RCC_PLLDivR
- *
- * @retval None
- */
-void RCC_SAIPLLRClkDivConfig(uint32_t RCC_PLLDivR)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PLL_DIVR_VALUE(RCC_PLLDivR));
-
- tmpreg = RCC->DCKCFGR;
-
- /* Clear PLLDIVR[12:8] */
- tmpreg &= ~(RCC_DCKCFGR_PLLDIVR);
-
- /* Set PLLDivR values */
- tmpreg |= ((RCC_PLLDivR - 1 ) << 8);
-
- /* Store the new value */
- RCC->DCKCFGR = tmpreg;
-}
-#endif /* STM32F413_423xx */
-
-/**
- * @brief Configures the LTDC clock Divider coming from PLLSAI.
- *
- * @note The LTDC peripheral is only available with STM32F42xxx/43xxx/446xx/469xx/479xx Devices.
- *
- * @note This function must be called before enabling the PLLSAI.
- *
- * @param RCC_PLLSAIDivR: specifies the PLLSAI division factor for LTDC clock .
- * LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR
- * This parameter can be one of the following values:
- * @arg RCC_PLLSAIDivR_Div2: LTDC clock = f(PLLSAI_R)/2
- * @arg RCC_PLLSAIDivR_Div4: LTDC clock = f(PLLSAI_R)/4
- * @arg RCC_PLLSAIDivR_Div8: LTDC clock = f(PLLSAI_R)/8
- * @arg RCC_PLLSAIDivR_Div16: LTDC clock = f(PLLSAI_R)/16
- *
- * @retval None
- */
-void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PLLSAI_DIVR_VALUE(RCC_PLLSAIDivR));
-
- tmpreg = RCC->DCKCFGR;
-
- /* Clear PLLSAIDIVR[2:0] bits */
- tmpreg &= ~RCC_DCKCFGR_PLLSAIDIVR;
-
- /* Set PLLSAIDIVR values */
- tmpreg |= RCC_PLLSAIDivR;
-
- /* Store the new value */
- RCC->DCKCFGR = tmpreg;
-}
-
-#if defined(STM32F412xG) || defined(STM32F413_423xx)
-/**
- * @brief Configures the DFSDM clock source (DFSDMCLK).
- * @note This function must be called before enabling the DFSDM APB clock.
- * @param RCC_DFSDMCLKSource: specifies the DFSDM clock source.
- * This parameter can be one of the following values:
- * @arg RCC_DFSDMCLKSource_APB: APB clock used as DFSDM clock source.
- * @arg RCC_DFSDMCLKSource_SYS: System clock used as DFSDM clock source.
- *
- * @retval None
- */
-void RCC_DFSDM1CLKConfig(uint32_t RCC_DFSDMCLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_DFSDM1CLK_SOURCE(RCC_DFSDMCLKSource));
-
- tmpreg = RCC->DCKCFGR;
-
- /* Clear CKDFSDM-SEL bit */
- tmpreg &= ~RCC_DCKCFGR_CKDFSDM1SEL;
-
- /* Set CKDFSDM-SEL bit according to RCC_DFSDMCLKSource value */
- tmpreg |= (RCC_DFSDMCLKSource << 31) ;
-
- /* Store the new value */
- RCC->DCKCFGR = tmpreg;
-}
-
-/**
- * @brief Configures the DFSDM Audio clock source (DFSDMACLK).
- * @note This function must be called before enabling the DFSDM APB clock.
- * @param RCC_DFSDM1ACLKSource: specifies the DFSDM clock source.
- * This parameter can be one of the following values:
- * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1: APB clock used as DFSDM clock source.
- * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2: System clock used as DFSDM clock source.
- *
- * @retval None
- */
-void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDM1ACLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_DFSDMACLK_SOURCE(RCC_DFSDM1ACLKSource));
-
- tmpreg = RCC->DCKCFGR;
-
- /* Clear CKDFSDMA SEL bit */
- tmpreg &= ~RCC_DCKCFGR_CKDFSDM1ASEL;
-
- /* Set CKDFSDM-SEL bt according to RCC_DFSDMCLKSource value */
- tmpreg |= RCC_DFSDM1ACLKSource;
-
- /* Store the new value */
- RCC->DCKCFGR = tmpreg;
-}
-
-#if defined(STM32F413_423xx)
-/**
- * @brief Configures the DFSDM Audio clock source (DFSDMACLK).
- * @note This function must be called before enabling the DFSDM APB clock.
- * @param RCC_DFSDM2ACLKSource: specifies the DFSDM clock source.
- * This parameter can be one of the following values:
- * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1: APB clock used as DFSDM clock source.
- * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2: System clock used as DFSDM clock source.
- *
- * @retval None
- */
-void RCC_DFSDM2ACLKConfig(uint32_t RCC_DFSDMACLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_DFSDMCLK_SOURCE(RCC_DFSDMACLKSource));
-
- tmpreg = RCC->DCKCFGR;
-
- /* Clear CKDFSDMA SEL bit */
- tmpreg &= ~RCC_DCKCFGR_CKDFSDM1ASEL;
-
- /* Set CKDFSDM-SEL bt according to RCC_DFSDMCLKSource value */
- tmpreg |= RCC_DFSDMACLKSource;
-
- /* Store the new value */
- RCC->DCKCFGR = tmpreg;
-}
-#endif /* STM32F413_423xx */
-#endif /* STM32F412xG || STM32F413_423xx */
-
-/**
- * @brief Configures the Timers clocks prescalers selection.
- *
- * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.
- *
- * @param RCC_TIMCLKPrescaler : specifies the Timers clocks prescalers selection
- * This parameter can be one of the following values:
- * @arg RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is
- * equal to HPRE if PPREx is corresponding to division by 1 or 2,
- * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
- * division by 4 or more.
- *
- * @arg RCC_TIMPrescActivated: The Timers kernels clocks prescaler is
- * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
- * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
- * to division by 8 or more.
- * @retval None
- */
-void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler)
-{
- /* Check the parameters */
- assert_param(IS_RCC_TIMCLK_PRESCALER(RCC_TIMCLKPrescaler));
-
- *(__IO uint32_t *) DCKCFGR_TIMPRE_BB = RCC_TIMCLKPrescaler;
-}
-
-/**
- * @brief Enables or disables the AHB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
- * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
- * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
- * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
- * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
- * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
- * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
- * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices)
- * @arg RCC_AHB1Periph_CRC: CRC clock
- * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
- * @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock
- * @arg RCC_AHB1Periph_DMA1: DMA1 clock
- * @arg RCC_AHB1Periph_DMA2: DMA2 clock
- * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
- * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
- * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
- * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
- * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
- * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
- * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph));
-
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->AHB1ENR |= RCC_AHB1Periph;
- }
- else
- {
- RCC->AHB1ENR &= ~RCC_AHB1Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB2Periph_DCMI: DCMI clock
- * @arg RCC_AHB2Periph_CRYP: CRYP clock
- * @arg RCC_AHB2Periph_HASH: HASH clock
- * @arg RCC_AHB2Periph_RNG: RNG clock
- * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB2ENR |= RCC_AHB2Periph;
- }
- else
- {
- RCC->AHB2ENR &= ~RCC_AHB2Periph;
- }
-}
-
-#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-/**
- * @brief Enables or disables the AHB3 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
- * This parameter must be:
- * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG/STM32F413_423xx/STM32F429x/439x devices)
- * - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices)
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB3ENR |= RCC_AHB3Periph;
- }
- else
- {
- RCC->AHB3ENR &= ~RCC_AHB3Periph;
- }
-}
-#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-/**
- * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2: TIM2 clock
- * @arg RCC_APB1Periph_TIM3: TIM3 clock
- * @arg RCC_APB1Periph_TIM4: TIM4 clock
- * @arg RCC_APB1Periph_TIM5: TIM5 clock
- * @arg RCC_APB1Periph_TIM6: TIM6 clock
- * @arg RCC_APB1Periph_TIM7: TIM7 clock
- * @arg RCC_APB1Periph_TIM12: TIM12 clock
- * @arg RCC_APB1Periph_TIM13: TIM13 clock
- * @arg RCC_APB1Periph_TIM14: TIM14 clock
- * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices)
- * @arg RCC_APB1Periph_WWDG: WWDG clock
- * @arg RCC_APB1Periph_SPI2: SPI2 clock
- * @arg RCC_APB1Periph_SPI3: SPI3 clock
- * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices)
- * @arg RCC_APB1Periph_USART2: USART2 clock
- * @arg RCC_APB1Periph_USART3: USART3 clock
- * @arg RCC_APB1Periph_UART4: UART4 clock
- * @arg RCC_APB1Periph_UART5: UART5 clock
- * @arg RCC_APB1Periph_I2C1: I2C1 clock
- * @arg RCC_APB1Periph_I2C2: I2C2 clock
- * @arg RCC_APB1Periph_I2C3: I2C3 clock
- * @arg RCC_APB1Periph_FMPI2C1:FMPI2C1 clock
- * @arg RCC_APB1Periph_CAN1: CAN1 clock
- * @arg RCC_APB1Periph_CAN2: CAN2 clock
- * @arg RCC_APB1Periph_CEC: CEC clock (STM32F446xx devices)
- * @arg RCC_APB1Periph_PWR: PWR clock
- * @arg RCC_APB1Periph_DAC: DAC clock
- * @arg RCC_APB1Periph_UART7: UART7 clock
- * @arg RCC_APB1Periph_UART8: UART8 clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB1ENR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1ENR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_TIM1: TIM1 clock
- * @arg RCC_APB2Periph_TIM8: TIM8 clock
- * @arg RCC_APB2Periph_USART1: USART1 clock
- * @arg RCC_APB2Periph_USART6: USART6 clock
- * @arg RCC_APB2Periph_ADC1: ADC1 clock
- * @arg RCC_APB2Periph_ADC2: ADC2 clock
- * @arg RCC_APB2Periph_ADC3: ADC3 clock
- * @arg RCC_APB2Periph_SDIO: SDIO clock
- * @arg RCC_APB2Periph_SPI1: SPI1 clock
- * @arg RCC_APB2Periph_SPI4: SPI4 clock
- * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
- * @arg RCC_APB2Periph_EXTIT: EXTIIT clock
- * @arg RCC_APB2Periph_TIM9: TIM9 clock
- * @arg RCC_APB2Periph_TIM10: TIM10 clock
- * @arg RCC_APB2Periph_TIM11: TIM11 clock
- * @arg RCC_APB2Periph_SPI5: SPI5 clock
- * @arg RCC_APB2Periph_SPI6: SPI6 clock
- * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices)
- * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices)
- * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
- * @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices)
- * @arg RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices)
- * @arg RCC_APB2Periph_DFSDM2: DFSDM2 Clock (STM32F413_423xx Devices)
- * @arg RCC_APB2Periph_UART9: UART9 Clock (STM32F413_423xx Devices)
- * @arg RCC_APB2Periph_UART10: UART10 Clock (STM32F413_423xx Devices)
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB2ENR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2ENR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Forces or releases AHB1 peripheral reset.
- * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
- * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
- * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
- * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
- * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
- * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
- * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
- * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxxdevices)
- * @arg RCC_AHB1Periph_CRC: CRC clock
- * @arg RCC_AHB1Periph_DMA1: DMA1 clock
- * @arg RCC_AHB1Periph_DMA2: DMA2 clock
- * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
- * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
- * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
- * @arg RCC_AHB1Periph_RNG: RNG clock for STM32F410xx devices
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB1RSTR |= RCC_AHB1Periph;
- }
- else
- {
- RCC->AHB1RSTR &= ~RCC_AHB1Periph;
- }
-}
-
-/**
- * @brief Forces or releases AHB2 peripheral reset.
- * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB2Periph_DCMI: DCMI clock
- * @arg RCC_AHB2Periph_CRYP: CRYP clock
- * @arg RCC_AHB2Periph_HASH: HASH clock
- * @arg RCC_AHB2Periph_RNG: RNG clock for STM32F40_41xxx/STM32F412xG/STM32F413_423xx/STM32F427_437xx/STM32F429_439xx/STM32F469_479xx devices
- * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB2RSTR |= RCC_AHB2Periph;
- }
- else
- {
- RCC->AHB2RSTR &= ~RCC_AHB2Periph;
- }
-}
-
-#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-/**
- * @brief Forces or releases AHB3 peripheral reset.
- * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset.
- * This parameter must be:
- * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG, STM32F413_423xx and STM32F429x/439x devices)
- * - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F446xx/STM32F469_479xx devices)
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB3RSTR |= RCC_AHB3Periph;
- }
- else
- {
- RCC->AHB3RSTR &= ~RCC_AHB3Periph;
- }
-}
-#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-/**
- * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2: TIM2 clock
- * @arg RCC_APB1Periph_TIM3: TIM3 clock
- * @arg RCC_APB1Periph_TIM4: TIM4 clock
- * @arg RCC_APB1Periph_TIM5: TIM5 clock
- * @arg RCC_APB1Periph_TIM6: TIM6 clock
- * @arg RCC_APB1Periph_TIM7: TIM7 clock
- * @arg RCC_APB1Periph_TIM12: TIM12 clock
- * @arg RCC_APB1Periph_TIM13: TIM13 clock
- * @arg RCC_APB1Periph_TIM14: TIM14 clock
- * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices)
- * @arg RCC_APB1Periph_WWDG: WWDG clock
- * @arg RCC_APB1Periph_SPI2: SPI2 clock
- * @arg RCC_APB1Periph_SPI3: SPI3 clock
- * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices)
- * @arg RCC_APB1Periph_USART2: USART2 clock
- * @arg RCC_APB1Periph_USART3: USART3 clock
- * @arg RCC_APB1Periph_UART4: UART4 clock
- * @arg RCC_APB1Periph_UART5: UART5 clock
- * @arg RCC_APB1Periph_I2C1: I2C1 clock
- * @arg RCC_APB1Periph_I2C2: I2C2 clock
- * @arg RCC_APB1Periph_I2C3: I2C3 clock
- * @arg RCC_APB1Periph_FMPI2C1:FMPI2C1 clock
- * @arg RCC_APB1Periph_CAN1: CAN1 clock
- * @arg RCC_APB1Periph_CAN2: CAN2 clock
- * @arg RCC_APB1Periph_CEC: CEC clock(STM32F446xx devices)
- * @arg RCC_APB1Periph_PWR: PWR clock
- * @arg RCC_APB1Periph_DAC: DAC clock
- * @arg RCC_APB1Periph_UART7: UART7 clock
- * @arg RCC_APB1Periph_UART8: UART8 clock
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->APB1RSTR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1RSTR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @brief Forces or releases High Speed APB (APB2) peripheral reset.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_TIM1: TIM1 clock
- * @arg RCC_APB2Periph_TIM8: TIM8 clock
- * @arg RCC_APB2Periph_USART1: USART1 clock
- * @arg RCC_APB2Periph_USART6: USART6 clock
- * @arg RCC_APB2Periph_ADC1: ADC1 clock
- * @arg RCC_APB2Periph_ADC2: ADC2 clock
- * @arg RCC_APB2Periph_ADC3: ADC3 clock
- * @arg RCC_APB2Periph_SDIO: SDIO clock
- * @arg RCC_APB2Periph_SPI1: SPI1 clock
- * @arg RCC_APB2Periph_SPI4: SPI4 clock
- * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
- * @arg RCC_APB2Periph_TIM9: TIM9 clock
- * @arg RCC_APB2Periph_TIM10: TIM10 clock
- * @arg RCC_APB2Periph_TIM11: TIM11 clock
- * @arg RCC_APB2Periph_SPI5: SPI5 clock
- * @arg RCC_APB2Periph_SPI6: SPI6 clock
- * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices)
- * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices)
- * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
- * @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices)
- * @arg RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices)
- * @arg RCC_APB2Periph_DFSDM2: DFSDM2 Clock (STM32F413_423xx Devices)
- * @arg RCC_APB2Periph_UART9: UART9 Clock (STM32F413_423xx Devices)
- * @arg RCC_APB2Periph_UART10: UART10 Clock (STM32F413_423xx Devices)
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->APB2RSTR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2RSTR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
- * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
- * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
- * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
- * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
- * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
- * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
- * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices)
- * @arg RCC_AHB1Periph_CRC: CRC clock
- * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
- * @arg RCC_AHB1Periph_DMA1: DMA1 clock
- * @arg RCC_AHB1Periph_DMA2: DMA2 clock
- * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
- * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
- * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
- * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
- * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
- * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
- * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->AHB1LPENR |= RCC_AHB1Periph;
- }
- else
- {
- RCC->AHB1LPENR &= ~RCC_AHB1Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB2Periph_DCMI: DCMI clock
- * @arg RCC_AHB2Periph_CRYP: CRYP clock
- * @arg RCC_AHB2Periph_HASH: HASH clock
- * @arg RCC_AHB2Periph_RNG: RNG clock
- * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->AHB2LPENR |= RCC_AHB2Periph;
- }
- else
- {
- RCC->AHB2LPENR &= ~RCC_AHB2Periph;
- }
-}
-
-#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-/**
- * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
- * This parameter must be:
- * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG/STM32F413_423xx/STM32F429x/439x devices)
- * - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices)
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->AHB3LPENR |= RCC_AHB3Periph;
- }
- else
- {
- RCC->AHB3LPENR &= ~RCC_AHB3Periph;
- }
-}
-#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-/**
- * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2: TIM2 clock
- * @arg RCC_APB1Periph_TIM3: TIM3 clock
- * @arg RCC_APB1Periph_TIM4: TIM4 clock
- * @arg RCC_APB1Periph_TIM5: TIM5 clock
- * @arg RCC_APB1Periph_TIM6: TIM6 clock
- * @arg RCC_APB1Periph_TIM7: TIM7 clock
- * @arg RCC_APB1Periph_TIM12: TIM12 clock
- * @arg RCC_APB1Periph_TIM13: TIM13 clock
- * @arg RCC_APB1Periph_TIM14: TIM14 clock
- * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices)
- * @arg RCC_APB1Periph_WWDG: WWDG clock
- * @arg RCC_APB1Periph_SPI2: SPI2 clock
- * @arg RCC_APB1Periph_SPI3: SPI3 clock
- * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices)
- * @arg RCC_APB1Periph_USART2: USART2 clock
- * @arg RCC_APB1Periph_USART3: USART3 clock
- * @arg RCC_APB1Periph_UART4: UART4 clock
- * @arg RCC_APB1Periph_UART5: UART5 clock
- * @arg RCC_APB1Periph_I2C1: I2C1 clock
- * @arg RCC_APB1Periph_I2C2: I2C2 clock
- * @arg RCC_APB1Periph_I2C3: I2C3 clock
- * @arg RCC_APB1Periph_FMPI2C1: FMPI2C1 clock
- * @arg RCC_APB1Periph_CAN1: CAN1 clock
- * @arg RCC_APB1Periph_CAN2: CAN2 clock
- * @arg RCC_APB1Periph_CEC: CEC clock (STM32F446xx devices)
- * @arg RCC_APB1Periph_PWR: PWR clock
- * @arg RCC_APB1Periph_DAC: DAC clock
- * @arg RCC_APB1Periph_UART7: UART7 clock
- * @arg RCC_APB1Periph_UART8: UART8 clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->APB1LPENR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1LPENR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_TIM1: TIM1 clock
- * @arg RCC_APB2Periph_TIM8: TIM8 clock
- * @arg RCC_APB2Periph_USART1: USART1 clock
- * @arg RCC_APB2Periph_USART6: USART6 clock
- * @arg RCC_APB2Periph_ADC1: ADC1 clock
- * @arg RCC_APB2Periph_ADC2: ADC2 clock
- * @arg RCC_APB2Periph_ADC3: ADC3 clock
- * @arg RCC_APB2Periph_SDIO: SDIO clock
- * @arg RCC_APB2Periph_SPI1: SPI1 clock
- * @arg RCC_APB2Periph_SPI4: SPI4 clock
- * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
- * @arg RCC_APB2Periph_EXTIT: EXTIIT clock
- * @arg RCC_APB2Periph_TIM9: TIM9 clock
- * @arg RCC_APB2Periph_TIM10: TIM10 clock
- * @arg RCC_APB2Periph_TIM11: TIM11 clock
- * @arg RCC_APB2Periph_SPI5: SPI5 clock
- * @arg RCC_APB2Periph_SPI6: SPI6 clock
- * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices)
- * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices)
- * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
- * @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices)
- * @arg RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices)
- * @arg RCC_APB2Periph_DFSDM2: DFSDM2 Clock (STM32F413_423xx Devices)
- * @arg RCC_APB2Periph_UART9: UART9 Clock (STM32F413_423xx Devices)
- * @arg RCC_APB2Periph_UART10: UART10 Clock (STM32F413_423xx Devices)
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->APB2LPENR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2LPENR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Configures the External Low Speed oscillator mode (LSE mode).
- * @note This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469_479xx devices.
- * @param Mode: specifies the LSE mode.
- * This parameter can be one of the following values:
- * @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode.
- * @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode.
- * @retval None
- */
-void RCC_LSEModeConfig(uint8_t RCC_Mode)
-{
- /* Check the parameters */
- assert_param(IS_RCC_LSE_MODE(RCC_Mode));
-
- if(RCC_Mode == RCC_LSE_HIGHDRIVE_MODE)
- {
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
- }
- else
- {
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
- }
-}
-
-#if defined(STM32F410xx) || defined(STM32F413_423xx)
-/**
- * @brief Configures the LPTIM1 clock Source.
- * @note This feature is only available for STM32F410xx devices.
- * @param RCC_ClockSource: specifies the LPTIM1 clock Source.
- * This parameter can be one of the following values:
- * @arg RCC_LPTIM1CLKSOURCE_PCLK: LPTIM1 clock from APB1 selected.
- * @arg RCC_LPTIM1CLKSOURCE_HSI: LPTIM1 clock from HSI selected.
- * @arg RCC_LPTIM1CLKSOURCE_LSI: LPTIM1 clock from LSI selected.
- * @arg RCC_LPTIM1CLKSOURCE_LSE: LPTIM1 clock from LSE selected.
- * @retval None
- */
-void RCC_LPTIM1ClockSourceConfig(uint32_t RCC_ClockSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_LPTIM1_CLOCKSOURCE(RCC_ClockSource));
-
- /* Clear LPTIM1 clock source selection source bits */
- RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_LPTIM1SEL;
- /* Set new LPTIM1 clock source */
- RCC->DCKCFGR2 |= RCC_ClockSource;
-}
-#endif /* STM32F410xx || STM32F413_423xx */
-
-#if defined(STM32F469_479xx)
-/**
- * @brief Configures the DSI clock Source.
- * @note This feature is only available for STM32F469_479xx devices.
- * @param RCC_ClockSource: specifies the DSI clock Source.
- * This parameter can be one of the following values:
- * @arg RCC_DSICLKSource_PHY: DSI-PHY used as DSI byte lane clock source (usual case).
- * @arg RCC_DSICLKSource_PLLR: PLL_R used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode).
- * @retval None
- */
-void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_DSI_CLOCKSOURCE(RCC_ClockSource));
-
- if(RCC_ClockSource == RCC_DSICLKSource_PLLR)
- {
- SET_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL);
- }
- else
- {
- CLEAR_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL);
- }
-}
-#endif /* STM32F469_479xx */
-
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-/**
- * @brief Configures the 48MHz clock Source.
- * @note This feature is only available for STM32F446xx/STM32F469_479xx devices.
- * @param RCC_ClockSource: specifies the 48MHz clock Source.
- * This parameter can be one of the following values:
- * @arg RCC_48MHZCLKSource_PLL: 48MHz from PLL selected.
- * @arg RCC_48MHZCLKSource_PLLSAI: 48MHz from PLLSAI selected.
- * @arg RCC_CK48CLKSOURCE_PLLI2SQ : 48MHz from PLLI2SQ
- * @retval None
- */
-void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_48MHZ_CLOCKSOURCE(RCC_ClockSource));
-#if defined(STM32F469_479xx)
- if(RCC_ClockSource == RCC_48MHZCLKSource_PLLSAI)
- {
- SET_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL);
- }
- else
- {
- CLEAR_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL);
- }
-#elif defined(STM32F446xx)
- if(RCC_ClockSource == RCC_48MHZCLKSource_PLLSAI)
- {
- SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL);
- }
- else
- {
- CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL);
- }
-#elif defined(STM32F412xG) || defined(STM32F413_423xx)
- if(RCC_ClockSource == RCC_CK48CLKSOURCE_PLLI2SQ)
- {
- SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL);
- }
- else
- {
- CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL);
- }
-#else
-#endif /* STM32F469_479xx */
-}
-
-/**
- * @brief Configures the SDIO clock Source.
- * @note This feature is only available for STM32F469_479xx/STM32F446xx devices.
- * @param RCC_ClockSource: specifies the SDIO clock Source.
- * This parameter can be one of the following values:
- * @arg RCC_SDIOCLKSource_48MHZ: 48MHz clock selected.
- * @arg RCC_SDIOCLKSource_SYSCLK: system clock selected.
- * @retval None
- */
-void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_SDIO_CLOCKSOURCE(RCC_ClockSource));
-#if defined(STM32F469_479xx)
- if(RCC_ClockSource == RCC_SDIOCLKSource_SYSCLK)
- {
- SET_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL);
- }
- else
- {
- CLEAR_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL);
- }
-#elif defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
- if(RCC_ClockSource == RCC_SDIOCLKSource_SYSCLK)
- {
- SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL);
- }
- else
- {
- CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL);
- }
-#else
-#endif /* STM32F469_479xx */
-}
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F446xx)
-/**
- * @brief Enables or disables the AHB1 clock gating for the specified IPs.
- * @note This feature is only available for STM32F446xx devices.
- * @param RCC_AHB1ClockGating: specifies the AHB1 clock gating.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB1ClockGating_APB1Bridge: AHB1 to APB1 clock
- * @arg RCC_AHB1ClockGating_APB2Bridge: AHB1 to APB2 clock
- * @arg RCC_AHB1ClockGating_CM4DBG: Cortex M4 ETM clock
- * @arg RCC_AHB1ClockGating_SPARE: Spare clock
- * @arg RCC_AHB1ClockGating_SRAM: SRAM controller clock
- * @arg RCC_AHB1ClockGating_FLITF: Flash interface clock
- * @arg RCC_AHB1ClockGating_RCC: RCC clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB1_CLOCKGATING(RCC_AHB1ClockGating));
-
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->CKGATENR &= ~RCC_AHB1ClockGating;
- }
- else
- {
- RCC->CKGATENR |= RCC_AHB1ClockGating;
- }
-}
-
-/**
- * @brief Configures the SPDIFRX clock Source.
- * @note This feature is only available for STM32F446xx devices.
- * @param RCC_ClockSource: specifies the SPDIFRX clock Source.
- * This parameter can be one of the following values:
- * @arg RCC_SPDIFRXCLKSource_PLLR: SPDIFRX clock from PLL_R selected.
- * @arg RCC_SPDIFRXCLKSource_PLLI2SP: SPDIFRX clock from PLLI2S_P selected.
- * @retval None
- */
-void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_SPDIFRX_CLOCKSOURCE(RCC_ClockSource));
-
- if(RCC_ClockSource == RCC_SPDIFRXCLKSource_PLLI2SP)
- {
- SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL);
- }
- else
- {
- CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL);
- }
-}
-
-/**
- * @brief Configures the CEC clock Source.
- * @note This feature is only available for STM32F446xx devices.
- * @param RCC_ClockSource: specifies the CEC clock Source.
- * This parameter can be one of the following values:
- * @arg RCC_CECCLKSource_HSIDiv488: CEC clock from HSI/488 selected.
- * @arg RCC_CECCLKSource_LSE: CEC clock from LSE selected.
- * @retval None
- */
-void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_CEC_CLOCKSOURCE(RCC_ClockSource));
-
- if(RCC_ClockSource == RCC_CECCLKSource_LSE)
- {
- SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL);
- }
- else
- {
- CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL);
- }
-}
-#endif /* STM32F446xx */
-
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-/**
- * @brief Configures the FMPI2C1 clock Source.
- * @note This feature is only available for STM32F446xx devices.
- * @param RCC_ClockSource: specifies the FMPI2C1 clock Source.
- * This parameter can be one of the following values:
- * @arg RCC_FMPI2C1CLKSource_APB1: FMPI2C1 clock from APB1 selected.
- * @arg RCC_FMPI2C1CLKSource_SYSCLK: FMPI2C1 clock from Sytem clock selected.
- * @arg RCC_FMPI2C1CLKSource_HSI: FMPI2C1 clock from HSI selected.
- * @retval None
- */
-void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_FMPI2C1_CLOCKSOURCE(RCC_ClockSource));
-
- /* Clear FMPI2C1 clock source selection source bits */
- RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_FMPI2C1SEL;
- /* Set new FMPI2C1 clock source */
- RCC->DCKCFGR2 |= RCC_ClockSource;
-}
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
-/**
- * @}
- */
-
-#if defined(STM32F410xx)
-/**
- * @brief Enables or disables the MCO1.
- * @param NewState: new state of the MCO1.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_MCO1Cmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the MCO2.
- * @param NewState: new state of the MCO2.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_MCO2Cmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = (uint32_t)NewState;
-}
-#endif /* STM32F410xx */
-
-/** @defgroup RCC_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified RCC interrupts.
- * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: main PLL ready interrupt
- * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
- * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)
- * @param NewState: new state of the specified RCC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_IT(RCC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
- }
- else
- {
- /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified RCC flag is set or not.
- * @param RCC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
- * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
- * @arg RCC_FLAG_PLLRDY: main PLL clock ready
- * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
- * @arg RCC_FLAG_PLLSAIRDY: PLLSAI clock ready (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)
- * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
- * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
- * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset
- * @arg RCC_FLAG_PINRST: Pin reset
- * @arg RCC_FLAG_PORRST: POR/PDR reset
- * @arg RCC_FLAG_SFTRST: Software reset
- * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
- * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
- * @arg RCC_FLAG_LPWRRST: Low Power reset
- * @retval The new state of RCC_FLAG (SET or RESET).
- */
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
-{
- uint32_t tmp = 0;
- uint32_t statusreg = 0;
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_FLAG(RCC_FLAG));
-
- /* Get the RCC register index */
- tmp = RCC_FLAG >> 5;
- if (tmp == 1) /* The flag to check is in CR register */
- {
- statusreg = RCC->CR;
- }
- else if (tmp == 2) /* The flag to check is in BDCR register */
- {
- statusreg = RCC->BDCR;
- }
- else /* The flag to check is in CSR register */
- {
- statusreg = RCC->CSR;
- }
-
- /* Get the flag position */
- tmp = RCC_FLAG & FLAG_MASK;
- if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the RCC reset flags.
- * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
- * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
- * @param None
- * @retval None
- */
-void RCC_ClearFlag(void)
-{
- /* Set RMVF bit to clear the reset flags */
- RCC->CSR |= RCC_CSR_RMVF;
-}
-
-/**
- * @brief Checks whether the specified RCC interrupt has occurred or not.
- * @param RCC_IT: specifies the RCC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: main PLL ready interrupt
- * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
- * @arg RCC_IT_PLLSAIRDY: PLLSAI clock ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)
- * @arg RCC_IT_CSS: Clock Security System interrupt
- * @retval The new state of RCC_IT (SET or RESET).
- */
-ITStatus RCC_GetITStatus(uint8_t RCC_IT)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_GET_IT(RCC_IT));
-
- /* Check the status of the specified RCC interrupt */
- if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the RCC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the RCC's interrupt pending bits.
- * @param RCC_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: main PLL ready interrupt
- * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
- * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)
- * @arg RCC_IT_CSS: Clock Security System interrupt
- * @retval None
- */
-void RCC_ClearITPendingBit(uint8_t RCC_IT)
-{
- /* Check the parameters */
- assert_param(IS_RCC_CLEAR_IT(RCC_IT));
-
- /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
- pending bits */
- *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_rcc.h b/底盘/底盘-old/底盘/Library/stm32f4xx_rcc.h
deleted file mode 100644
index 3c986b3..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_rcc.h
+++ /dev/null
@@ -1,1058 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_rcc.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the RCC firmware library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_RCC_H
-#define __STM32F4xx_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup RCC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-typedef struct
-{
- uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */
- uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */
- uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
- uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */
-}RCC_ClocksTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Constants
- * @{
- */
-
-/** @defgroup RCC_HSE_configuration
- * @{
- */
-#define RCC_HSE_OFF ((uint8_t)0x00)
-#define RCC_HSE_ON ((uint8_t)0x01)
-#define RCC_HSE_Bypass ((uint8_t)0x05)
-#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
- ((HSE) == RCC_HSE_Bypass))
-/**
- * @}
- */
-
-/** @defgroup RCC_LSE_Dual_Mode_Selection
- * @{
- */
-#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
-#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
-#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \
- ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
-/**
- * @}
- */
-
-/** @defgroup RCC_PLLSAIDivR_Factor
- * @{
- */
-#define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000)
-#define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000)
-#define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000)
-#define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000)
-#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\
- ((VALUE) == RCC_PLLSAIDivR_Div4) ||\
- ((VALUE) == RCC_PLLSAIDivR_Div8) ||\
- ((VALUE) == RCC_PLLSAIDivR_Div16))
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Clock_Source
- * @{
- */
-#define RCC_PLLSource_HSI ((uint32_t)0x00000000)
-#define RCC_PLLSource_HSE ((uint32_t)0x00400000)
-#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
- ((SOURCE) == RCC_PLLSource_HSE))
-#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
-#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
-#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
-#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
-
-#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
-#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
-#define IS_RCC_PLLI2SM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
-#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
-#if defined(STM32F446xx)
-#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
-#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
-#elif defined(STM32F412xG) || defined(STM32F413_423xx)
-#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
-#else
-#endif /* STM32F446xx */
-#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
-#if defined(STM32F446xx) || defined(STM32F469_479xx)
-#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
-#endif /* STM32F446xx || STM32F469_479xx */
-#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
-#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
-
-#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
-#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
-
-#if defined(STM32F413_423xx)
-#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
-#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
-#endif /* STM32F413_423xx */
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source
- * @{
- */
-
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
-#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
-#define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002)
-#define RCC_SYSCLKSource_PLLRCLK ((uint32_t)0x00000003)
-#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
- ((SOURCE) == RCC_SYSCLKSource_HSE) || \
- ((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \
- ((SOURCE) == RCC_SYSCLKSource_PLLRCLK))
-/* Add legacy definition */
-#define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK
-#endif /* STM32F446xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
-#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
-#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
-#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
-#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
- ((SOURCE) == RCC_SYSCLKSource_HSE) || \
- ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Clock_Source
- * @{
- */
-#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
-#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
-#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
-#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
-#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
-#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
-#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
-#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
-#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
-#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
- ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
- ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
- ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
- ((HCLK) == RCC_SYSCLK_Div512))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_APB2_Clock_Source
- * @{
- */
-#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
-#define RCC_HCLK_Div2 ((uint32_t)0x00001000)
-#define RCC_HCLK_Div4 ((uint32_t)0x00001400)
-#define RCC_HCLK_Div8 ((uint32_t)0x00001800)
-#define RCC_HCLK_Div16 ((uint32_t)0x00001C00)
-#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
- ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
- ((PCLK) == RCC_HCLK_Div16))
-/**
- * @}
- */
-
-/** @defgroup RCC_Interrupt_Source
- * @{
- */
-#define RCC_IT_LSIRDY ((uint8_t)0x01)
-#define RCC_IT_LSERDY ((uint8_t)0x02)
-#define RCC_IT_HSIRDY ((uint8_t)0x04)
-#define RCC_IT_HSERDY ((uint8_t)0x08)
-#define RCC_IT_PLLRDY ((uint8_t)0x10)
-#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
-#define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
-#define RCC_IT_CSS ((uint8_t)0x80)
-
-#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
-#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
- ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
- ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
- ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY))
-#define IS_RCC_CLEAR_IT(IT)((IT) != 0x00)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LSE_Configuration
- * @{
- */
-#define RCC_LSE_OFF ((uint8_t)0x00)
-#define RCC_LSE_ON ((uint8_t)0x01)
-#define RCC_LSE_Bypass ((uint8_t)0x04)
-#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
- ((LSE) == RCC_LSE_Bypass))
-/**
- * @}
- */
-
-/** @defgroup RCC_RTC_Clock_Source
- * @{
- */
-#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
-#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
-#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)
-#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)
-#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300)
-#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)
-#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)
-#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)
-#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)
-#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)
-#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)
-#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)
-#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)
-#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)
-#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)
-#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)
-#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)
-#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)
-#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)
-#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)
-#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)
-#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)
-#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300)
-#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)
-#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)
-#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)
-#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)
-#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)
-#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)
-#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)
-#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)
-#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)
-#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
- ((SOURCE) == RCC_RTCCLKSource_LSI) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
-/**
- * @}
- */
-
-#if defined(STM32F410xx) || defined(STM32F413_423xx)
-/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
- * @{
- */
-#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
-#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
-#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
-#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
-
-#define IS_RCC_LPTIM1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \
- ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
-/* Legacy Defines */
-#define IS_RCC_LPTIM1_SOURCE IS_RCC_LPTIM1_CLOCKSOURCE
-
-#if defined(STM32F410xx)
-/**
- * @}
- */
-
-/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source
- * @{
- */
-#define RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000)
-#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
-#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
-#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) || ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) || \
- ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
-/**
- * @}
- */
-#endif /* STM32F413_423xx */
-#endif /* STM32F410xx || STM32F413_423xx */
-
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-/** @defgroup RCC_I2S_Clock_Source
- * @{
- */
-#define RCC_I2SCLKSource_PLLI2S ((uint32_t)0x00)
-#define RCC_I2SCLKSource_Ext ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
-#define RCC_I2SCLKSource_PLL ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
-#define RCC_I2SCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_I2S1SRC_0 | RCC_DCKCFGR_I2S1SRC_1)
-
-#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSource_PLLI2S) || ((SOURCE) == RCC_I2SCLKSource_Ext) || \
- ((SOURCE) == RCC_I2SCLKSource_PLL) || ((SOURCE) == RCC_I2SCLKSource_HSI_HSE))
-/**
- * @}
- */
-
-/** @defgroup RCC_I2S_APBBus
- * @{
- */
-#define RCC_I2SBus_APB1 ((uint8_t)0x00)
-#define RCC_I2SBus_APB2 ((uint8_t)0x01)
-#define IS_RCC_I2S_APBx(BUS) (((BUS) == RCC_I2SBus_APB1) || ((BUS) == RCC_I2SBus_APB2))
-/**
- * @}
- */
-#if defined(STM32F446xx)
-/** @defgroup RCC_SAI_Clock_Source
- * @{
- */
-#define RCC_SAICLKSource_PLLSAI ((uint32_t)0x00)
-#define RCC_SAICLKSource_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
-#define RCC_SAICLKSource_PLL ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
-#define RCC_SAICLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1SRC_0 | RCC_DCKCFGR_SAI1SRC_1)
-
-#define IS_RCC_SAICLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAICLKSource_PLLSAI) || ((SOURCE) == RCC_SAICLKSource_PLLI2S) || \
- ((SOURCE) == RCC_SAICLKSource_PLL) || ((SOURCE) == RCC_SAICLKSource_HSI_HSE))
-/**
- * @}
- */
-
-/** @defgroup RCC_SAI_Instance
- * @{
- */
-#define RCC_SAIInstance_SAI1 ((uint8_t)0x00)
-#define RCC_SAIInstance_SAI2 ((uint8_t)0x01)
-#define IS_RCC_SAI_INSTANCE(BUS) (((BUS) == RCC_SAIInstance_SAI1) || ((BUS) == RCC_SAIInstance_SAI2))
-/**
- * @}
- */
-#endif /* STM32F446xx */
-#if defined(STM32F413_423xx)
-
-/** @defgroup RCC_SAI_BlockA_Clock_Source
- * @{
- */
-#define RCC_SAIACLKSource_PLLI2S_R ((uint32_t)0x00000000)
-#define RCC_SAIACLKSource_I2SCKIN ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0)
-#define RCC_SAIACLKSource_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1)
-#define RCC_SAIACLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 | RCC_DCKCFGR_SAI1ASRC_1)
-
-#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S_R) || ((SOURCE) == RCC_SAIACLKSource_I2SCKIN) || \
- ((SOURCE) == RCC_SAIACLKSource_PLLR) || ((SOURCE) == RCC_SAIACLKSource_HSI_HSE))
-/**
- * @}
- */
-
-/** @defgroup RCC_SAI_BlockB_Clock_Source
- * @{
- */
-#define RCC_SAIBCLKSource_PLLI2S_R ((uint32_t)0x00000000)
-#define RCC_SAIBCLKSource_I2SCKIN ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0)
-#define RCC_SAIBCLKSource_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1)
-#define RCC_SAIBCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 | RCC_DCKCFGR_SAI1BSRC_1)
-
-#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S_R) || ((SOURCE) == RCC_SAIBCLKSource_I2SCKIN) || \
- ((SOURCE) == RCC_SAIBCLKSource_PLLR) || ((SOURCE) == RCC_SAIBCLKSource_HSI_HSE))
-/**
- * @}
- */
-#endif /* STM32F413_423xx */
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
-/** @defgroup RCC_I2S_Clock_Source
- * @{
- */
-#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00)
-#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
-
-#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
-/**
- * @}
- */
-
-/** @defgroup RCC_SAI_BlockA_Clock_Source
- * @{
- */
-#define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000)
-#define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000)
-#define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000)
-
-#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\
- ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\
- ((SOURCE) == RCC_SAIACLKSource_Ext))
-/**
- * @}
- */
-
-/** @defgroup RCC_SAI_BlockB_Clock_Source
- * @{
- */
-#define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000)
-#define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000)
-#define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000)
-
-#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\
- ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\
- ((SOURCE) == RCC_SAIBCLKSource_Ext))
-/**
- * @}
- */
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */
-
-/** @defgroup RCC_TIM_PRescaler_Selection
- * @{
- */
-#define RCC_TIMPrescDesactivated ((uint8_t)0x00)
-#define RCC_TIMPrescActivated ((uint8_t)0x01)
-
-#define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated))
-/**
- * @}
- */
-
-#if defined(STM32F469_479xx)
-/** @defgroup RCC_DSI_Clock_Source_Selection
- * @{
- */
-#define RCC_DSICLKSource_PHY ((uint8_t)0x00)
-#define RCC_DSICLKSource_PLLR ((uint8_t)0x01)
-#define IS_RCC_DSI_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_DSICLKSource_PHY) || \
- ((CLKSOURCE) == RCC_DSICLKSource_PLLR))
-/**
- * @}
- */
-#endif /* STM32F469_479xx */
-
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-/** @defgroup RCC_SDIO_Clock_Source_Selection
- * @{
- */
-#define RCC_SDIOCLKSource_48MHZ ((uint8_t)0x00)
-#define RCC_SDIOCLKSource_SYSCLK ((uint8_t)0x01)
-#define IS_RCC_SDIO_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SDIOCLKSource_48MHZ) || \
- ((CLKSOURCE) == RCC_SDIOCLKSource_SYSCLK))
-/**
- * @}
- */
-
-
-/** @defgroup RCC_48MHZ_Clock_Source_Selection
- * @{
- */
-#if defined(STM32F446xx) || defined(STM32F469_479xx)
-#define RCC_48MHZCLKSource_PLL ((uint8_t)0x00)
-#define RCC_48MHZCLKSource_PLLSAI ((uint8_t)0x01)
-#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_48MHZCLKSource_PLL) || \
- ((CLKSOURCE) == RCC_48MHZCLKSource_PLLSAI))
-#endif /* STM32F446xx || STM32F469_479xx */
-#if defined(STM32F412xG) || defined(STM32F413_423xx)
-#define RCC_CK48CLKSOURCE_PLLQ ((uint8_t)0x00)
-#define RCC_CK48CLKSOURCE_PLLI2SQ ((uint8_t)0x01) /* Only for STM32F412xG and STM32F413_423xx Devices */
-#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLQ) || \
- ((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLI2SQ))
-#endif /* STM32F412xG || STM32F413_423xx */
-/**
- * @}
- */
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F446xx)
-/** @defgroup RCC_SPDIFRX_Clock_Source_Selection
- * @{
- */
-#define RCC_SPDIFRXCLKSource_PLLR ((uint8_t)0x00)
-#define RCC_SPDIFRXCLKSource_PLLI2SP ((uint8_t)0x01)
-#define IS_RCC_SPDIFRX_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLR) || \
- ((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLI2SP))
-/**
- * @}
- */
-
-/** @defgroup RCC_CEC_Clock_Source_Selection
- * @{
- */
-#define RCC_CECCLKSource_HSIDiv488 ((uint8_t)0x00)
-#define RCC_CECCLKSource_LSE ((uint8_t)0x01)
-#define IS_RCC_CEC_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CECCLKSource_HSIDiv488) || \
- ((CLKSOURCE) == RCC_CECCLKSource_LSE))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB1_ClockGating
- * @{
- */
-#define RCC_AHB1ClockGating_APB1Bridge ((uint32_t)0x00000001)
-#define RCC_AHB1ClockGating_APB2Bridge ((uint32_t)0x00000002)
-#define RCC_AHB1ClockGating_CM4DBG ((uint32_t)0x00000004)
-#define RCC_AHB1ClockGating_SPARE ((uint32_t)0x00000008)
-#define RCC_AHB1ClockGating_SRAM ((uint32_t)0x00000010)
-#define RCC_AHB1ClockGating_FLITF ((uint32_t)0x00000020)
-#define RCC_AHB1ClockGating_RCC ((uint32_t)0x00000040)
-
-#define IS_RCC_AHB1_CLOCKGATING(PERIPH) ((((PERIPH) & 0xFFFFFF80) == 0x00) && ((PERIPH) != 0x00))
-
-/**
- * @}
- */
-#endif /* STM32F446xx */
-
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-/** @defgroup RCC_FMPI2C1_Clock_Source
- * @{
- */
-#define RCC_FMPI2C1CLKSource_APB1 ((uint32_t)0x00)
-#define RCC_FMPI2C1CLKSource_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
-#define RCC_FMPI2C1CLKSource_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
-
-#define IS_RCC_FMPI2C1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSource_APB1) || ((SOURCE) == RCC_FMPI2C1CLKSource_SYSCLK) || \
- ((SOURCE) == RCC_FMPI2C1CLKSource_HSI))
-/**
- * @}
- */
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
-
-#if defined(STM32F412xG) || defined(STM32F413_423xx)
-/** @defgroup RCC_DFSDM_Clock_Source
- * @{
- */
-#define RCC_DFSDMCLKSource_APB ((uint8_t)0x00)
-#define RCC_DFSDMCLKSource_SYS ((uint8_t)0x01)
-#define IS_RCC_DFSDMCLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDMCLKSource_APB) || ((SOURCE) == RCC_DFSDMCLKSource_SYS))
-
-/* Legacy Defines */
-#define RCC_DFSDM1CLKSource_APB RCC_DFSDMCLKSource_APB
-#define RCC_DFSDM1CLKSource_SYS RCC_DFSDMCLKSource_SYS
-#define IS_RCC_DFSDM1CLK_SOURCE IS_RCC_DFSDMCLK_SOURCE
-/**
- * @}
- */
-
-/** @defgroup RCC_DFSDM_Audio_Clock_Source RCC DFSDM Audio Clock Source
- * @{
- */
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000)
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
-#define IS_RCC_DFSDM1ACLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1) || ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2))
-
-/* Legacy Defines */
-#define IS_RCC_DFSDMACLK_SOURCE IS_RCC_DFSDM1ACLK_SOURCE
-/**
- * @}
- */
-
-#if defined(STM32F413_423xx)
-/** @defgroup RCC_DFSDM_Audio_Clock_Source RCC DFSDM Audio Clock Source
- * @{
- */
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000)
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL)
-#define IS_RCC_DFSDM2ACLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1) || ((SOURCE) == RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2))
-/**
- * @}
- */
-#endif /* STM32F413_423xx */
-#endif /* STM32F412xG || STM32F413_423xx */
-
-/** @defgroup RCC_AHB1_Peripherals
- * @{
- */
-#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)
-#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)
-#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)
-#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)
-#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)
-#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)
-#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)
-#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)
-#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
-#define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200)
-#define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400)
-#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
-#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
-#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
-#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)
-#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)
-#define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000)
-#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)
-#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
-#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
-#define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000)
-#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
-#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)
-#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)
-#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
-#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
-#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
-#if defined(STM32F410xx)
-#define RCC_AHB1Periph_RNG ((uint32_t)0x80000000)
-#endif /* STM32F410xx */
-#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x010BE800) == 0x00) && ((PERIPH) != 0x00))
-#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0x51FE800) == 0x00) && ((PERIPH) != 0x00))
-#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x01106800) == 0x00) && ((PERIPH) != 0x00))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB2_Peripherals
- * @{
- */
-#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)
-#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)
-#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
-#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
-#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040)
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
-#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)
-#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB3_Peripherals
- * @{
- */
-#if defined(STM32F40_41xxx)
-#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
-#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
-#endif /* STM32F40_41xxx */
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx)
-#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
-#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
-#endif /* STM32F427_437xx || STM32F429_439xx */
-
-#if defined(STM32F446xx) || defined(STM32F469_479xx)
-#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
-#define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002)
-#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
-#endif /* STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F412xG) || defined(STM32F413_423xx)
-#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
-#define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002)
-#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
-#endif /* STM32F412xG || STM32F413_423xx */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Peripherals
- * @{
- */
-#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
-#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
-#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
-#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
-#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
-#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
-#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
-#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
-#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
-#if defined(STM32F410xx) || defined(STM32F413_423xx)
-#define RCC_APB1Periph_LPTIM1 ((uint32_t)0x00000200)
-#endif /* STM32F410xx || STM32F413_423xx */
-#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
-#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
-#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
-#if defined(STM32F446xx)
-#define RCC_APB1Periph_SPDIFRX ((uint32_t)0x00010000)
-#endif /* STM32F446xx */
-#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
-#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
-#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
-#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
-#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
-#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
-#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-#define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000)
-#endif /* STM32F410xx || STM32F446xx || STM32F413_423xx*/
-#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
-#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
-#if defined(STM32F413_423xx)
-#define RCC_APB1Periph_CAN3 ((uint32_t)0x08000000)
-#endif /* STM32F413_423xx */
-#if defined(STM32F446xx)
-#define RCC_APB1Periph_CEC ((uint32_t)0x08000000)
-#endif /* STM32F446xx */
-#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
-#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
-#define RCC_APB1Periph_UART7 ((uint32_t)0x40000000)
-#define RCC_APB1Periph_UART8 ((uint32_t)0x80000000)
-#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Peripherals
- * @{
- */
-#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)
-#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)
-#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)
-#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)
-#define RCC_APB2Periph_ADC ((uint32_t)0x00000100)
-#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)
-#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)
-#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)
-#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)
-#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
-#define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000)
-#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
-#define RCC_APB2Periph_EXTIT ((uint32_t)0x00008000)
-#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)
-#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)
-#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
-#define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000)
-#define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000)
-#define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000)
-#if defined(STM32F446xx) || defined(STM32F469_479xx)
-#define RCC_APB2Periph_SAI2 ((uint32_t)0x00800000)
-#endif /* STM32F446xx || STM32F469_479xx */
-#define RCC_APB2Periph_LTDC ((uint32_t)0x04000000)
-#if defined(STM32F469_479xx)
-#define RCC_APB2Periph_DSI ((uint32_t)0x08000000)
-#endif /* STM32F469_479xx */
-#if defined(STM32F412xG) || defined(STM32F413_423xx)
-#define RCC_APB2Periph_DFSDM1 ((uint32_t)0x01000000)
-#endif /* STM32F412xG || STM32F413_423xx */
-#if defined(STM32F413_423xx)
-#define RCC_APB2Periph_DFSDM2 ((uint32_t)0x02000000)
-#define RCC_APB2Periph_UART9 ((uint32_t)0x02000040)
-#define RCC_APB2Periph_UART10 ((uint32_t)0x00000080)
-#endif /* STM32F413_423xx */
-
-/* Legacy Defines */
-#define RCC_APB2Periph_DFSDM RCC_APB2Periph_DFSDM1
-
-#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF008000C) == 0x00) && ((PERIPH) != 0x00))
-#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xF208860C) == 0x00) && ((PERIPH) != 0x00))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_MCO1_Clock_Source_Prescaler
- * @{
- */
-#define RCC_MCO1Source_HSI ((uint32_t)0x00000000)
-#define RCC_MCO1Source_LSE ((uint32_t)0x00200000)
-#define RCC_MCO1Source_HSE ((uint32_t)0x00400000)
-#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000)
-#define RCC_MCO1Div_1 ((uint32_t)0x00000000)
-#define RCC_MCO1Div_2 ((uint32_t)0x04000000)
-#define RCC_MCO1Div_3 ((uint32_t)0x05000000)
-#define RCC_MCO1Div_4 ((uint32_t)0x06000000)
-#define RCC_MCO1Div_5 ((uint32_t)0x07000000)
-#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
- ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
-
-#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
- ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
- ((DIV) == RCC_MCO1Div_5))
-/**
- * @}
- */
-
-/** @defgroup RCC_MCO2_Clock_Source_Prescaler
- * @{
- */
-#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)
-#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000)
-#define RCC_MCO2Source_HSE ((uint32_t)0x80000000)
-#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)
-#define RCC_MCO2Div_1 ((uint32_t)0x00000000)
-#define RCC_MCO2Div_2 ((uint32_t)0x20000000)
-#define RCC_MCO2Div_3 ((uint32_t)0x28000000)
-#define RCC_MCO2Div_4 ((uint32_t)0x30000000)
-#define RCC_MCO2Div_5 ((uint32_t)0x38000000)
-#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
- ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
-
-#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
- ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
- ((DIV) == RCC_MCO2Div_5))
-/**
- * @}
- */
-
-/** @defgroup RCC_Flag
- * @{
- */
-#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
-#define RCC_FLAG_HSERDY ((uint8_t)0x31)
-#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
-#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
-#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D)
-#define RCC_FLAG_LSERDY ((uint8_t)0x41)
-#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
-#define RCC_FLAG_BORRST ((uint8_t)0x79)
-#define RCC_FLAG_PINRST ((uint8_t)0x7A)
-#define RCC_FLAG_PORRST ((uint8_t)0x7B)
-#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
-#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
-#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
-#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
-
-#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
- ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
- ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
- ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
- ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
- ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \
- ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY))
-
-#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the RCC clock configuration to the default reset state */
-void RCC_DeInit(void);
-
-/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
-void RCC_HSEConfig(uint8_t RCC_HSE);
-ErrorStatus RCC_WaitForHSEStartUp(void);
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
-void RCC_HSICmd(FunctionalState NewState);
-void RCC_LSEConfig(uint8_t RCC_LSE);
-void RCC_LSICmd(FunctionalState NewState);
-
-void RCC_PLLCmd(FunctionalState NewState);
-
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR);
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
-
-void RCC_PLLI2SCmd(FunctionalState NewState);
-
-#if defined(STM32F40_41xxx) || defined(STM32F401xx)
-void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
-#endif /* STM32F40_41xxx || STM32F401xx */
-#if defined(STM32F411xE)
-void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM);
-#endif /* STM32F411xE */
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
-void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR);
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR);
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
-
-void RCC_PLLSAICmd(FunctionalState NewState);
-#if defined(STM32F469_479xx)
-void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR);
-#endif /* STM32F469_479xx */
-#if defined(STM32F446xx)
-void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ);
-#endif /* STM32F446xx */
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
-void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
-
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
-void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
-void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
-
-/* System, AHB and APB busses clocks configuration functions ******************/
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
-uint8_t RCC_GetSYSCLKSource(void);
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
-void RCC_PCLK1Config(uint32_t RCC_HCLK);
-void RCC_PCLK2Config(uint32_t RCC_HCLK);
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
-
-/* Peripheral clocks configuration functions **********************************/
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
-void RCC_RTCCLKCmd(FunctionalState NewState);
-void RCC_BackupResetCmd(FunctionalState NewState);
-
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource);
-#if defined(STM32F446xx)
-void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource);
-#endif /* STM32F446xx */
-#if defined(STM32F413_423xx)
-void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);
-void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
-#endif /* STM32F413_423xx */
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
-void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
-void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);
-void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
-
-void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ);
-void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ);
-
-#if defined(STM32F413_423xx)
-void RCC_SAIPLLI2SRClkDivConfig(uint32_t RCC_PLLI2SDivR);
-void RCC_SAIPLLRClkDivConfig(uint32_t RCC_PLLDivR);
-#endif /* STM32F413_423xx */
-
-void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR);
-void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);
-
-void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
-void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
-void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-
-void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
-void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
-void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-
-void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
-void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
-void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
-void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-
-/* Features available only for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469_479xx devices */
-void RCC_LSEModeConfig(uint8_t RCC_Mode);
-
-/* Features available only for STM32F469_479xx devices */
-#if defined(STM32F469_479xx)
-void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource);
-#endif /* STM32F469_479xx */
-
-/* Features available only for STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices */
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource);
-void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource);
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
-
-/* Features available only for STM32F446xx devices */
-#if defined(STM32F446xx)
-void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState);
-void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource);
-void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource);
-#endif /* STM32F446xx */
-
-/* Features available only for STM32F410xx/STM32F412xG/STM32F446xx devices */
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource);
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
-
-/* Features available only for STM32F410xx devices */
-#if defined(STM32F410xx) || defined(STM32F413_423xx)
-void RCC_LPTIM1ClockSourceConfig(uint32_t RCC_ClockSource);
-#if defined(STM32F410xx)
-void RCC_MCO1Cmd(FunctionalState NewState);
-void RCC_MCO2Cmd(FunctionalState NewState);
-#endif /* STM32F410xx */
-#endif /* STM32F410xx || STM32F413_423xx */
-
-#if defined(STM32F412xG) || defined(STM32F413_423xx)
-void RCC_DFSDMCLKConfig(uint32_t RCC_DFSDMCLKSource);
-void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDM1ACLKSource);
-#if defined(STM32F413_423xx)
-void RCC_DFSDM2ACLKConfig(uint32_t RCC_DFSDMACLKSource);
-#endif /* STM32F413_423xx */
-/* Legacy Defines */
-#define RCC_DFSDM1CLKConfig RCC_DFSDMCLKConfig
-#endif /* STM32F412xG || STM32F413_423xx */
-/* Interrupts and flags management functions **********************************/
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
-void RCC_ClearFlag(void);
-ITStatus RCC_GetITStatus(uint8_t RCC_IT);
-void RCC_ClearITPendingBit(uint8_t RCC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_RCC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_rng.c b/底盘/底盘-old/底盘/Library/stm32f4xx_rng.c
deleted file mode 100644
index b1ec183..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_rng.c
+++ /dev/null
@@ -1,398 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_rng.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Random Number Generator (RNG) peripheral:
- * + Initialization and Configuration
- * + Get 32 bit Random number
- * + Interrupts and flags management
- *
-@verbatim
-
- ===================================================================
- ##### How to use this driver #####
- ===================================================================
- [..]
- (#) Enable The RNG controller clock using
- RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function.
-
- (#) Activate the RNG peripheral using RNG_Cmd() function.
-
- (#) Wait until the 32 bit Random number Generator contains a valid random data
- (using polling/interrupt mode). For more details, refer to "Interrupts and
- flags management functions" module description.
-
- (#) Get the 32 bit Random number using RNG_GetRandomNumber() function
-
- (#) To get another 32 bit Random number, go to step 3.
-
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup RNG
- * @brief RNG driver modules
- * @{
- */
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RNG_Private_Functions
- * @{
- */
-
-/** @defgroup RNG_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to
- (+) Initialize the RNG peripheral
- (+) Enable or disable the RNG peripheral
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initializes the RNG peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void RNG_DeInit(void)
-{
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
- /* Enable RNG reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, ENABLE);
-
- /* Release RNG from reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, DISABLE);
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
-#if defined(STM32F410xx)
- /* Enable RNG reset state */
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_RNG, ENABLE);
-
- /* Release RNG from reset state */
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_RNG, DISABLE);
-#endif /* STM32F410xx*/
-}
-
-/**
- * @brief Enables or disables the RNG peripheral.
- * @param NewState: new state of the RNG peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RNG_Cmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the RNG */
- RNG->CR |= RNG_CR_RNGEN;
- }
- else
- {
- /* Disable the RNG */
- RNG->CR &= ~RNG_CR_RNGEN;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup RNG_Group2 Get 32 bit Random number function
- * @brief Get 32 bit Random number function
- *
-
-@verbatim
- ===============================================================================
- ##### Get 32 bit Random number function #####
- ===============================================================================
- [..] This section provides a function allowing to get the 32 bit Random number
-
- (@) Before to call this function you have to wait till DRDY flag is set,
- using RNG_GetFlagStatus(RNG_FLAG_DRDY) function.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Returns a 32-bit random number.
- *
- * @note Before to call this function you have to wait till DRDY (data ready)
- * flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function.
- * @note Each time the Random number data is read (using RNG_GetRandomNumber()
- * function), the RNG_FLAG_DRDY flag is automatically cleared.
- * @note In the case of a seed error, the generation of random numbers is
- * interrupted for as long as the SECS bit is '1'. If a number is
- * available in the RNG_DR register, it must not be used because it may
- * not have enough entropy. In this case, it is recommended to clear the
- * SEIS bit(using RNG_ClearFlag(RNG_FLAG_SECS) function), then disable
- * and enable the RNG peripheral (using RNG_Cmd() function) to
- * reinitialize and restart the RNG.
- * @note In the case of a clock error, the RNG is no more able to generate
- * random numbers because the PLL48CLK clock is not correct. User have
- * to check that the clock controller is correctly configured to provide
- * the RNG clock and clear the CEIS bit (using RNG_ClearFlag(RNG_FLAG_CECS)
- * function) . The clock error has no impact on the previously generated
- * random numbers, and the RNG_DR register contents can be used.
- *
- * @param None
- * @retval 32-bit random number.
- */
-uint32_t RNG_GetRandomNumber(void)
-{
- /* Return the 32 bit random number from the DR register */
- return RNG->DR;
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup RNG_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure the RNG Interrupts and
- to get the status and clear flags and Interrupts pending bits.
-
- [..] The RNG provides 3 Interrupts sources and 3 Flags:
-
- *** Flags : ***
- ===============
- [..]
- (#) RNG_FLAG_DRDY : In the case of the RNG_DR register contains valid
- random data. it is cleared by reading the valid data(using
- RNG_GetRandomNumber() function).
-
- (#) RNG_FLAG_CECS : In the case of a seed error detection.
-
- (#) RNG_FLAG_SECS : In the case of a clock error detection.
-
- *** Interrupts ***
- ==================
- [..] If enabled, an RNG interrupt is pending :
-
- (#) In the case of the RNG_DR register contains valid random data.
- This interrupt source is cleared once the RNG_DR register has been read
- (using RNG_GetRandomNumber() function) until a new valid value is
- computed; or
- (#) In the case of a seed error : One of the following faulty sequences has
- been detected:
- (++) More than 64 consecutive bits at the same value (0 or 1)
- (++) More than 32 consecutive alternance of 0 and 1 (0101010101...01)
- This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI)
- function; or
- (#) In the case of a clock error : the PLL48CLK (RNG peripheral clock source)
- was not correctly detected (fPLL48CLK< fHCLK/16). This interrupt source is
- cleared using RNG_ClearITPendingBit(RNG_IT_CEI) function.
- -@- note In this case, User have to check that the clock controller is
- correctly configured to provide the RNG clock.
-
- *** Managing the RNG controller events : ***
- ============================================
- [..] The user should identify which mode will be used in his application to manage
- the RNG controller events: Polling mode or Interrupt mode.
-
- (#) In the Polling Mode it is advised to use the following functions:
- (++) RNG_GetFlagStatus() : to check if flags events occur.
- (++) RNG_ClearFlag() : to clear the flags events.
-
- -@@- RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only
- by reading the Random number data.
-
- (#) In the Interrupt Mode it is advised to use the following functions:
- (++) RNG_ITConfig() : to enable or disable the interrupt source.
- (++) RNG_GetITStatus() : to check if Interrupt occurs.
- (++) RNG_ClearITPendingBit() : to clear the Interrupt pending Bit
- (corresponding Flag).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the RNG interrupt.
- * @note The RNG provides 3 interrupt sources,
- * - Computed data is ready event (DRDY), and
- * - Seed error Interrupt (SEI) and
- * - Clock error Interrupt (CEI),
- * all these interrupts sources are enabled by setting the IE bit in
- * CR register. However, each interrupt have its specific status bit
- * (see RNG_GetITStatus() function) and clear bit except the DRDY event
- * (see RNG_ClearITPendingBit() function).
- * @param NewState: new state of the RNG interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RNG_ITConfig(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the RNG interrupt */
- RNG->CR |= RNG_CR_IE;
- }
- else
- {
- /* Disable the RNG interrupt */
- RNG->CR &= ~RNG_CR_IE;
- }
-}
-
-/**
- * @brief Checks whether the specified RNG flag is set or not.
- * @param RNG_FLAG: specifies the RNG flag to check.
- * This parameter can be one of the following values:
- * @arg RNG_FLAG_DRDY: Data Ready flag.
- * @arg RNG_FLAG_CECS: Clock Error Current flag.
- * @arg RNG_FLAG_SECS: Seed Error Current flag.
- * @retval The new state of RNG_FLAG (SET or RESET).
- */
-FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_RNG_GET_FLAG(RNG_FLAG));
-
- /* Check the status of the specified RNG flag */
- if ((RNG->SR & RNG_FLAG) != (uint8_t)RESET)
- {
- /* RNG_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* RNG_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the RNG_FLAG status */
- return bitstatus;
-}
-
-
-/**
- * @brief Clears the RNG flags.
- * @param RNG_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg RNG_FLAG_CECS: Clock Error Current flag.
- * @arg RNG_FLAG_SECS: Seed Error Current flag.
- * @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag() function.
- * This flag is cleared only by reading the Random number data (using
- * RNG_GetRandomNumber() function).
- * @retval None
- */
-void RNG_ClearFlag(uint8_t RNG_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_RNG_CLEAR_FLAG(RNG_FLAG));
- /* Clear the selected RNG flags */
- RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4);
-}
-
-/**
- * @brief Checks whether the specified RNG interrupt has occurred or not.
- * @param RNG_IT: specifies the RNG interrupt source to check.
- * This parameter can be one of the following values:
- * @arg RNG_IT_CEI: Clock Error Interrupt.
- * @arg RNG_IT_SEI: Seed Error Interrupt.
- * @retval The new state of RNG_IT (SET or RESET).
- */
-ITStatus RNG_GetITStatus(uint8_t RNG_IT)
-{
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_RNG_GET_IT(RNG_IT));
-
- /* Check the status of the specified RNG interrupt */
- if ((RNG->SR & RNG_IT) != (uint8_t)RESET)
- {
- /* RNG_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* RNG_IT is reset */
- bitstatus = RESET;
- }
- /* Return the RNG_IT status */
- return bitstatus;
-}
-
-
-/**
- * @brief Clears the RNG interrupt pending bit(s).
- * @param RNG_IT: specifies the RNG interrupt pending bit(s) to clear.
- * This parameter can be any combination of the following values:
- * @arg RNG_IT_CEI: Clock Error Interrupt.
- * @arg RNG_IT_SEI: Seed Error Interrupt.
- * @retval None
- */
-void RNG_ClearITPendingBit(uint8_t RNG_IT)
-{
- /* Check the parameters */
- assert_param(IS_RNG_IT(RNG_IT));
-
- /* Clear the selected RNG interrupt pending bit */
- RNG->SR = (uint8_t)~RNG_IT;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F429_439xx || STM32F469_479xx */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_rng.h b/底盘/底盘-old/底盘/Library/stm32f4xx_rng.h
deleted file mode 100644
index 41883a5..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_rng.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_rng.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the Random
- * Number Generator(RNG) firmware library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_RNG_H
-#define __STM32F4xx_RNG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup RNG
- * @{
- */
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RNG_Exported_Constants
- * @{
- */
-
-/** @defgroup RNG_flags_definition
- * @{
- */
-#define RNG_FLAG_DRDY ((uint8_t)0x0001) /*!< Data ready */
-#define RNG_FLAG_CECS ((uint8_t)0x0002) /*!< Clock error current status */
-#define RNG_FLAG_SECS ((uint8_t)0x0004) /*!< Seed error current status */
-
-#define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \
- ((RNG_FLAG) == RNG_FLAG_CECS) || \
- ((RNG_FLAG) == RNG_FLAG_SECS))
-#define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \
- ((RNG_FLAG) == RNG_FLAG_SECS))
-/**
- * @}
- */
-
-/** @defgroup RNG_interrupts_definition
- * @{
- */
-#define RNG_IT_CEI ((uint8_t)0x20) /*!< Clock error interrupt */
-#define RNG_IT_SEI ((uint8_t)0x40) /*!< Seed error interrupt */
-
-#define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00))
-#define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the RNG configuration to the default reset state *****/
-void RNG_DeInit(void);
-
-/* Configuration function *****************************************************/
-void RNG_Cmd(FunctionalState NewState);
-
-/* Get 32 bit Random number function ******************************************/
-uint32_t RNG_GetRandomNumber(void);
-
-/* Interrupts and flags management functions **********************************/
-void RNG_ITConfig(FunctionalState NewState);
-FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG);
-void RNG_ClearFlag(uint8_t RNG_FLAG);
-ITStatus RNG_GetITStatus(uint8_t RNG_IT);
-void RNG_ClearITPendingBit(uint8_t RNG_IT);
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F429_439xx || STM32F469_479xx */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_RNG_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_rtc.c b/底盘/底盘-old/底盘/Library/stm32f4xx_rtc.c
deleted file mode 100644
index 586bc23..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_rtc.c
+++ /dev/null
@@ -1,2757 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_rtc.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Real-Time Clock (RTC) peripheral:
- * + Initialization
- * + Calendar (Time and Date) configuration
- * + Alarms (Alarm A and Alarm B) configuration
- * + WakeUp Timer configuration
- * + Daylight Saving configuration
- * + Output pin Configuration
- * + Coarse digital Calibration configuration
- * + Smooth digital Calibration configuration
- * + TimeStamp configuration
- * + Tampers configuration
- * + Backup Data Registers configuration
- * + Shift control synchronisation
- * + RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration
- * + Interrupts and flags management
- *
-@verbatim
-
- ===================================================================
- ##### Backup Domain Operating Condition #####
- ===================================================================
- [..] The real-time clock (RTC), the RTC backup registers, and the backup
- SRAM (BKP SRAM) can be powered from the VBAT voltage when the main
- VDD supply is powered off.
- To retain the content of the RTC backup registers, backup SRAM, and supply
- the RTC when VDD is turned off, VBAT pin can be connected to an optional
- standby voltage supplied by a battery or by another source.
-
- [..] To allow the RTC to operate even when the main digital supply (VDD) is turned
- off, the VBAT pin powers the following blocks:
- (#) The RTC
- (#) The LSE oscillator
- (#) The backup SRAM when the low power backup regulator is enabled
- (#) PC13 to PC15 I/Os, plus PI8 I/O (when available)
-
- [..] When the backup domain is supplied by VDD (analog switch connected to VDD),
- the following functions are available:
- (#) PC14 and PC15 can be used as either GPIO or LSE pins
- (#) PC13 can be used as a GPIO or as the RTC_AF1 pin
- (#) PI8 can be used as a GPIO or as the RTC_AF2 pin
-
- [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT
- because VDD is not present), the following functions are available:
- (#) PC14 and PC15 can be used as LSE pins only
- (#) PC13 can be used as the RTC_AF1 pin
- (#) PI8 can be used as the RTC_AF2 pin
-
-
- ##### Backup Domain Reset #####
- ===================================================================
- [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
- to their reset values. The BKPSRAM is not affected by this reset. The only
- way of resetting the BKPSRAM is through the Flash interface by requesting
- a protection level change from 1 to 0.
- [..] A backup domain reset is generated when one of the following events occurs:
- (#) Software reset, triggered by setting the BDRST bit in the
- RCC Backup domain control register (RCC_BDCR). You can use the
- RCC_BackupResetCmd().
- (#) VDD or VBAT power on, if both supplies have previously been powered off.
-
-
- ##### Backup Domain Access #####
- ===================================================================
- [..] After reset, the backup domain (RTC registers, RTC backup data
- registers and backup SRAM) is protected against possible unwanted write
- accesses.
- [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
- (+) Enable the Power Controller (PWR) APB1 interface clock using the
- RCC_APB1PeriphClockCmd() function.
- (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function.
- (+) Select the RTC clock source using the RCC_RTCCLKConfig() function.
- (+) Enable RTC Clock using the RCC_RTCCLKCmd() function.
-
-
- ##### How to use RTC Driver #####
- ===================================================================
- [..]
- (+) Enable the RTC domain access (see description in the section above)
- (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
- format using the RTC_Init() function.
-
- *** Time and Date configuration ***
- ===================================
- [..]
- (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime()
- and RTC_SetDate() functions.
- (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() functions.
- (+) Use the RTC_DayLightSavingConfig() function to add or sub one
- hour to the RTC Calendar.
-
- *** Alarm configuration ***
- ===========================
- [..]
- (+) To configure the RTC Alarm use the RTC_SetAlarm() function.
- (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function
- (+) To read the RTC Alarm, use the RTC_GetAlarm() function.
- (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.
-
- *** RTC Wakeup configuration ***
- ================================
- [..]
- (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()
- function.
- (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() function
- (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function
- (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter()
- function.
-
- *** Outputs configuration ***
- =============================
- [..] The RTC has 2 different outputs:
- (+) AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B
- and WaKeUp signals. To output the selected RTC signal on RTC_AF1 pin, use the
- RTC_OutputConfig() function.
- (+) AFO_CALIB: this output is 512Hz signal or 1Hz. To output the RTC Clock on
- RTC_AF1 pin, use the RTC_CalibOutputCmd() function.
-
- *** Smooth digital Calibration configuration ***
- ================================================
- [..]
- (+) Configure the RTC Original Digital Calibration Value and the corresponding
- calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig()
- function.
-
- *** Coarse digital Calibration configuration ***
- ================================================
- [..]
- (+) Configure the RTC Coarse Calibration Value and the corresponding
- sign using the RTC_CoarseCalibConfig() function.
- (+) Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() function
-
- *** TimeStamp configuration ***
- ===============================
- [..]
- (+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp using the RTC
- _TimeStampCmd() function.
- (+) To read the RTC TimeStamp Time and Date register, use the RTC_GetTimeStamp()
- function.
- (+) To read the RTC TimeStamp SubSecond register, use the
- RTC_GetTimeStampSubSecond() function.
- (+) The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13)
- or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in
- RTC_TAFCR register. You can use the RTC_TamperPinSelection() function to
- select the corresponding pin.
-
- *** Tamper configuration ***
- ============================
- [..]
- (+) Enable the RTC Tamper using the RTC_TamperCmd() function.
- (+) Configure the Tamper filter count using RTC_TamperFilterConfig()
- function.
- (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper
- filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig()
- function.
- (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()
- function.
- (+) Configure the Tamper precharge or discharge duration using
- RTC_TamperPinsPrechargeDuration() function.
- (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.
- (+) Enable the Time stamp on Tamper detection event using
- TC_TSOnTamperDetecCmd() function.
- (+) The TIMESTAMP alternate function can be mapped to either RTC_AF1
- or RTC_AF2 depending on the value of the TSINSEL bit in the RTC_TAFCR
- register. You can use the RTC_TimeStampPinSelection() function to select
- the corresponding pin.
-
- *** Backup Data Registers configuration ***
- ===========================================
- [..]
- (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()
- function.
- (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()
- function.
-
-
- ##### RTC and low power modes #####
- ===================================================================
- [..] The MCU can be woken up from a low power mode by an RTC alternate
- function.
- [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
- RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
- These RTC alternate functions can wake up the system from the Stop and
- Standby lowpower modes.
- [..] The system can also wake up from low power modes without depending
- on an external interrupt (Auto-wakeup mode), by using the RTC alarm
- or the RTC wakeup events.
- [..] The RTC provides a programmable time base for waking up from the
- Stop or Standby mode at regular intervals.
- Wakeup from STOP and Standby modes is possible only when the RTC clock source
- is LSE or LSI.
-
-
- ##### Selection of RTC_AF1 alternate functions #####
- ===================================================================
- [..] The RTC_AF1 pin (PC13) can be used for the following purposes:
- (+) AFO_ALARM output
- (+) AFO_CALIB output
- (+) AFI_TAMPER
- (+) AFI_TIMESTAMP
-
- [..]
- +-------------------------------------------------------------------------------------------------------------+
- | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE |
- | configuration | ENABLED | ENABLED | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM |
- | and function | | | | | selection | selection |Configuration |
- |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- | Alarm out | | | | | Don't | Don't | |
- | output OD | 1 |Don't care|Don't care | Don't care | care | care | 0 |
- |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- | Alarm out | | | | | Don't | Don't | |
- | output PP | 1 |Don't care|Don't care | Don't care | care | care | 1 |
- |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- | Calibration out | | | | | Don't | Don't | |
- | output PP | 0 | 1 |Don't care | Don't care | care | care | Don't care |
- |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- | TAMPER input | | | | | | Don't | |
- | floating | 0 | 0 | 1 | 0 | 0 | care | Don't care |
- |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- | TIMESTAMP and | | | | | | | |
- | TAMPER input | 0 | 0 | 1 | 1 | 0 | 0 | Don't care |
- | floating | | | | | | | |
- |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- | TIMESTAMP input | | | | | Don't | | |
- | floating | 0 | 0 | 0 | 1 | care | 0 | Don't care |
- |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- | Standard GPIO | 0 | 0 | 0 | 0 | Don't care | Don't care | Don't care |
- +-------------------------------------------------------------------------------------------------------------+
-
-
- ##### Selection of RTC_AF2 alternate functions #####
- ===================================================================
- [..] The RTC_AF2 pin (PI8) can be used for the following purposes:
- (+) AFI_TAMPER
- (+) AFI_TIMESTAMP
- [..]
- +---------------------------------------------------------------------------------------+
- | Pin |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE |
- | configuration | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM |
- | and function | | | selection | selection |Configuration |
- |-----------------|-----------|--------------|------------|--------------|--------------|
- | TAMPER input | | | | Don't | |
- | floating | 1 | 0 | 1 | care | Don't care |
- |-----------------|-----------|--------------|------------|--------------|--------------|
- | TIMESTAMP and | | | | | |
- | TAMPER input | 1 | 1 | 1 | 1 | Don't care |
- | floating | | | | | |
- |-----------------|-----------|--------------|------------|--------------|--------------|
- | TIMESTAMP input | | | Don't | | |
- | floating | 0 | 1 | care | 1 | Don't care |
- |-----------------|-----------|--------------|------------|--------------|--------------|
- | Standard GPIO | 0 | 0 | Don't care | Don't care | Don't care |
- +---------------------------------------------------------------------------------------+
-
-
-@endverbatim
-
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_rtc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup RTC
- * @brief RTC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* Masks Definition */
-#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
-#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
-#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
-#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
-#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
- RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
- RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
- RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
- RTC_FLAG_TAMP2F | RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
-
-#define INITMODE_TIMEOUT ((uint32_t) 0x00010000)
-#define SYNCHRO_TIMEOUT ((uint32_t) 0x00020000)
-#define RECALPF_TIMEOUT ((uint32_t) 0x00020000)
-#define SHPF_TIMEOUT ((uint32_t) 0x00001000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static uint8_t RTC_ByteToBcd2(uint8_t Value);
-static uint8_t RTC_Bcd2ToByte(uint8_t Value);
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RTC_Private_Functions
- * @{
- */
-
-/** @defgroup RTC_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
-
- [..] This section provide functions allowing to initialize and configure the RTC
- Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers
- Write protection, enter and exit the RTC initialization mode, RTC registers
- synchronization check and reference clock detection enable.
-
- (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is
- split into 2 programmable prescalers to minimize power consumption.
- (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
- (++) When both prescalers are used, it is recommended to configure the
- asynchronous prescaler to a high value to minimize consumption.
-
- (#) All RTC registers are Write protected. Writing to the RTC registers
- is enabled by writing a key into the Write Protection register, RTC_WPR.
-
- (#) To Configure the RTC Calendar, user application should enter initialization
- mode. In this mode, the calendar counter is stopped and its value can be
- updated. When the initialization sequence is complete, the calendar restarts
- counting after 4 RTCCLK cycles.
-
- (#) To read the calendar through the shadow registers after Calendar initialization,
- calendar update or after wakeup from low power modes the software must first
- clear the RSF flag. The software must then wait until it is set again before
- reading the calendar, which means that the calendar registers have been
- correctly copied into the RTC_TR and RTC_DR shadow registers.
- The RTC_WaitForSynchro() function implements the above software sequence
- (RSF clear and RSF check).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the RTC registers to their default reset values.
- * @note This function doesn't reset the RTC Clock source and RTC Backup Data
- * registers.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC registers are deinitialized
- * - ERROR: RTC registers are not deinitialized
- */
-ErrorStatus RTC_DeInit(void)
-{
- __IO uint32_t wutcounter = 0x00;
- uint32_t wutwfstatus = 0x00;
- ErrorStatus status = ERROR;
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- /* Reset TR, DR and CR registers */
- RTC->TR = (uint32_t)0x00000000;
- RTC->DR = (uint32_t)0x00002101;
- /* Reset All CR bits except CR[2:0] */
- RTC->CR &= (uint32_t)0x00000007;
-
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- do
- {
- wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
- wutcounter++;
- } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
-
- if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
- {
- status = ERROR;
- }
- else
- {
- /* Reset all RTC CR register bits */
- RTC->CR &= (uint32_t)0x00000000;
- RTC->WUTR = (uint32_t)0x0000FFFF;
- RTC->PRER = (uint32_t)0x007F00FF;
- RTC->CALIBR = (uint32_t)0x00000000;
- RTC->ALRMAR = (uint32_t)0x00000000;
- RTC->ALRMBR = (uint32_t)0x00000000;
- RTC->SHIFTR = (uint32_t)0x00000000;
- RTC->CALR = (uint32_t)0x00000000;
- RTC->ALRMASSR = (uint32_t)0x00000000;
- RTC->ALRMBSSR = (uint32_t)0x00000000;
-
- /* Reset ISR register and exit initialization mode */
- RTC->ISR = (uint32_t)0x00000000;
-
- /* Reset Tamper and alternate functions configuration register */
- RTC->TAFCR = 0x00000000;
-
- if(RTC_WaitForSynchro() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Initializes the RTC registers according to the specified parameters
- * in RTC_InitStruct.
- * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains
- * the configuration information for the RTC peripheral.
- * @note The RTC Prescaler register is write protected and can be written in
- * initialization mode only.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC registers are initialized
- * - ERROR: RTC registers are not initialized
- */
-ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));
- assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));
- assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- /* Clear RTC CR FMT Bit */
- RTC->CR &= ((uint32_t)~(RTC_CR_FMT));
- /* Set RTC_CR register */
- RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat));
-
- /* Configure the RTC PRER */
- RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);
- RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);
-
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- status = SUCCESS;
- }
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Fills each RTC_InitStruct member with its default value.
- * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be
- * initialized.
- * @retval None
- */
-void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)
-{
- /* Initialize the RTC_HourFormat member */
- RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;
-
- /* Initialize the RTC_AsynchPrediv member */
- RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;
-
- /* Initialize the RTC_SynchPrediv member */
- RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF;
-}
-
-/**
- * @brief Enables or disables the RTC registers write protection.
- * @note All the RTC registers are write protected except for RTC_ISR[13:8],
- * RTC_TAFCR and RTC_BKPxR.
- * @note Writing a wrong key reactivates the write protection.
- * @note The protection mechanism is not affected by system reset.
- * @param NewState: new state of the write protection.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_WriteProtectionCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
- }
- else
- {
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
- }
-}
-
-/**
- * @brief Enters the RTC Initialization mode.
- * @note The RTC Initialization mode is write protected, use the
- * RTC_WriteProtectionCmd(DISABLE) before calling this function.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC is in Init mode
- * - ERROR: RTC is not in Init mode
- */
-ErrorStatus RTC_EnterInitMode(void)
-{
- __IO uint32_t initcounter = 0x00;
- ErrorStatus status = ERROR;
- uint32_t initstatus = 0x00;
-
- /* Check if the Initialization mode is set */
- if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
- {
- /* Set the Initialization mode */
- RTC->ISR = (uint32_t)RTC_INIT_MASK;
-
- /* Wait till RTC is in INIT state and if Time out is reached exit */
- do
- {
- initstatus = RTC->ISR & RTC_ISR_INITF;
- initcounter++;
- } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
-
- if ((RTC->ISR & RTC_ISR_INITF) != RESET)
- {
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
- }
- else
- {
- status = SUCCESS;
- }
-
- return (status);
-}
-
-/**
- * @brief Exits the RTC Initialization mode.
- * @note When the initialization sequence is complete, the calendar restarts
- * counting after 4 RTCCLK cycles.
- * @note The RTC Initialization mode is write protected, use the
- * RTC_WriteProtectionCmd(DISABLE) before calling this function.
- * @param None
- * @retval None
- */
-void RTC_ExitInitMode(void)
-{
- /* Exit Initialization mode */
- RTC->ISR &= (uint32_t)~RTC_ISR_INIT;
-}
-
-/**
- * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are
- * synchronized with RTC APB clock.
- * @note The RTC Resynchronization mode is write protected, use the
- * RTC_WriteProtectionCmd(DISABLE) before calling this function.
- * @note To read the calendar through the shadow registers after Calendar
- * initialization, calendar update or after wakeup from low power modes
- * the software must first clear the RSF flag.
- * The software must then wait until it is set again before reading
- * the calendar, which means that the calendar registers have been
- * correctly copied into the RTC_TR and RTC_DR shadow registers.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC registers are synchronised
- * - ERROR: RTC registers are not synchronised
- */
-ErrorStatus RTC_WaitForSynchro(void)
-{
- __IO uint32_t synchrocounter = 0;
- ErrorStatus status = ERROR;
- uint32_t synchrostatus = 0x00;
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Clear RSF flag */
- RTC->ISR &= (uint32_t)RTC_RSF_MASK;
-
- /* Wait the registers to be synchronised */
- do
- {
- synchrostatus = RTC->ISR & RTC_ISR_RSF;
- synchrocounter++;
- } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
-
- if ((RTC->ISR & RTC_ISR_RSF) != RESET)
- {
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return (status);
-}
-
-/**
- * @brief Enables or disables the RTC reference clock detection.
- * @param NewState: new state of the RTC reference clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC reference clock detection is enabled
- * - ERROR: RTC reference clock detection is disabled
- */
-ErrorStatus RTC_RefClockCmd(FunctionalState NewState)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- if (NewState != DISABLE)
- {
- /* Enable the RTC reference clock detection */
- RTC->CR |= RTC_CR_REFCKON;
- }
- else
- {
- /* Disable the RTC reference clock detection */
- RTC->CR &= ~RTC_CR_REFCKON;
- }
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- status = SUCCESS;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Enables or Disables the Bypass Shadow feature.
- * @note When the Bypass Shadow is enabled the calendar value are taken
- * directly from the Calendar counter.
- * @param NewState: new state of the Bypass Shadow feature.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
-*/
-void RTC_BypassShadowCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- if (NewState != DISABLE)
- {
- /* Set the BYPSHAD bit */
- RTC->CR |= (uint8_t)RTC_CR_BYPSHAD;
- }
- else
- {
- /* Reset the BYPSHAD bit */
- RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group2 Time and Date configuration functions
- * @brief Time and Date configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Time and Date configuration functions #####
- ===============================================================================
-
- [..] This section provide functions allowing to program and read the RTC Calendar
- (Time and Date).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set the RTC current time.
- * @param RTC_Format: specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains
- * the time configuration information for the RTC.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Time register is configured
- * - ERROR: RTC Time register is not configured
- */
-ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
-{
- uint32_t tmpreg = 0;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- if (RTC_Format == RTC_Format_BIN)
- {
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours));
- assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
- }
- else
- {
- RTC_TimeStruct->RTC_H12 = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));
- }
- assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));
- assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));
- }
- else
- {
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
- assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
- }
- else
- {
- RTC_TimeStruct->RTC_H12 = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));
- }
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));
- }
-
- /* Check the input parameters format */
- if (RTC_Format != RTC_Format_BIN)
- {
- tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \
- ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \
- ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \
- ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16));
- }
- else
- {
- tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \
- (((uint32_t)RTC_TimeStruct->RTC_H12) << 16));
- }
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- /* Set the RTC_TR register */
- RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
-
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if(RTC_WaitForSynchro() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
- else
- {
- status = SUCCESS;
- }
- }
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Fills each RTC_TimeStruct member with its default value
- * (Time = 00h:00min:00sec).
- * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be
- * initialized.
- * @retval None
- */
-void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)
-{
- /* Time = 00h:00min:00sec */
- RTC_TimeStruct->RTC_H12 = RTC_H12_AM;
- RTC_TimeStruct->RTC_Hours = 0;
- RTC_TimeStruct->RTC_Minutes = 0;
- RTC_TimeStruct->RTC_Seconds = 0;
-}
-
-/**
- * @brief Get the RTC current Time.
- * @param RTC_Format: specifies the format of the returned parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will
- * contain the returned current time configuration.
- * @retval None
- */
-void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- /* Get the RTC_TR register */
- tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK);
-
- /* Fill the structure fields with the read parameters */
- RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
- RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
- RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
- RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
-
- /* Check the input parameters format */
- if (RTC_Format == RTC_Format_BIN)
- {
- /* Convert the structure parameters to Binary format */
- RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
- RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);
- RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds);
- }
-}
-
-/**
- * @brief Gets the RTC current Calendar Sub seconds value.
- * @note This function freeze the Time and Date registers after reading the
- * SSR register.
- * @param None
- * @retval RTC current Calendar Sub seconds value.
- */
-uint32_t RTC_GetSubSecond(void)
-{
- uint32_t tmpreg = 0;
-
- /* Get sub seconds values from the correspondent registers*/
- tmpreg = (uint32_t)(RTC->SSR);
-
- /* Read DR register to unfroze calendar registers */
- (void) (RTC->DR);
-
- return (tmpreg);
-}
-
-/**
- * @brief Set the RTC current date.
- * @param RTC_Format: specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains
- * the date configuration information for the RTC.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Date register is configured
- * - ERROR: RTC Date register is not configured
- */
-ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
-{
- uint32_t tmpreg = 0;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10))
- {
- RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A;
- }
- if (RTC_Format == RTC_Format_BIN)
- {
- assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year));
- assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month));
- assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date));
- }
- else
- {
- assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year)));
- tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
- assert_param(IS_RTC_MONTH(tmpreg));
- tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
- assert_param(IS_RTC_DATE(tmpreg));
- }
- assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay));
-
- /* Check the input parameters format */
- if (RTC_Format != RTC_Format_BIN)
- {
- tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \
- (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \
- ((uint32_t)RTC_DateStruct->RTC_Date) | \
- (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13));
- }
- else
- {
- tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \
- ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13));
- }
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- /* Set the RTC_DR register */
- RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK);
-
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if(RTC_WaitForSynchro() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
- else
- {
- status = SUCCESS;
- }
- }
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Fills each RTC_DateStruct member with its default value
- * (Monday, January 01 xx00).
- * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be
- * initialized.
- * @retval None
- */
-void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct)
-{
- /* Monday, January 01 xx00 */
- RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday;
- RTC_DateStruct->RTC_Date = 1;
- RTC_DateStruct->RTC_Month = RTC_Month_January;
- RTC_DateStruct->RTC_Year = 0;
-}
-
-/**
- * @brief Get the RTC current date.
- * @param RTC_Format: specifies the format of the returned parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will
- * contain the returned current date configuration.
- * @retval None
- */
-void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- /* Get the RTC_TR register */
- tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK);
-
- /* Fill the structure fields with the read parameters */
- RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
- RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
- RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU));
- RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13);
-
- /* Check the input parameters format */
- if (RTC_Format == RTC_Format_BIN)
- {
- /* Convert the structure parameters to Binary format */
- RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);
- RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
- RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group3 Alarms configuration functions
- * @brief Alarms (Alarm A and Alarm B) configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Alarms A and B configuration functions #####
- ===============================================================================
-
- [..] This section provide functions allowing to program and read the RTC Alarms.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set the specified RTC Alarm.
- * @note The Alarm register can only be written when the corresponding Alarm
- * is disabled (Use the RTC_AlarmCmd(DISABLE)).
- * @param RTC_Format: specifies the format of the returned parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_Alarm: specifies the alarm to be configured.
- * This parameter can be one of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @arg RTC_Alarm_B: to select Alarm B
- * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that
- * contains the alarm configuration parameters.
- * @retval None
- */
-void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
- assert_param(IS_RTC_ALARM(RTC_Alarm));
- assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));
-
- if (RTC_Format == RTC_Format_BIN)
- {
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
- assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
- }
- else
- {
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
- }
- assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));
- assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));
-
- if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
- }
- else
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
- }
- }
- else
- {
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
- assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
- }
- else
- {
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));
- }
-
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));
-
- if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
- {
- tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
- }
- else
- {
- tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
- }
- }
-
- /* Check the input parameters format */
- if (RTC_Format != RTC_Format_BIN)
- {
- tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask));
- }
- else
- {
- tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask));
- }
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Alarm register */
- if (RTC_Alarm == RTC_Alarm_A)
- {
- RTC->ALRMAR = (uint32_t)tmpreg;
- }
- else
- {
- RTC->ALRMBR = (uint32_t)tmpreg;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Fills each RTC_AlarmStruct member with its default value
- * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =
- * all fields are masked).
- * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)
-{
- /* Alarm Time Settings : Time = 00h:00mn:00sec */
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM;
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0;
-
- /* Alarm Date Settings : Date = 1st day of the month */
- RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;
- RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1;
-
- /* Alarm Masks Settings : Mask = all fields are not masked */
- RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None;
-}
-
-/**
- * @brief Get the RTC Alarm value and masks.
- * @param RTC_Format: specifies the format of the output parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_Alarm: specifies the alarm to be read.
- * This parameter can be one of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @arg RTC_Alarm_B: to select Alarm B
- * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will
- * contains the output alarm configuration values.
- * @retval None
- */
-void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
- assert_param(IS_RTC_ALARM(RTC_Alarm));
-
- /* Get the RTC_ALRMxR register */
- if (RTC_Alarm == RTC_Alarm_A)
- {
- tmpreg = (uint32_t)(RTC->ALRMAR);
- }
- else
- {
- tmpreg = (uint32_t)(RTC->ALRMBR);
- }
-
- /* Fill the structure with the read parameters */
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \
- RTC_ALRMAR_HU)) >> 16);
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \
- RTC_ALRMAR_MNU)) >> 8);
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \
- RTC_ALRMAR_SU));
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
- RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
- RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
- RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All);
-
- if (RTC_Format == RTC_Format_BIN)
- {
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
- RTC_AlarmTime.RTC_Hours);
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
- RTC_AlarmTime.RTC_Minutes);
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
- RTC_AlarmTime.RTC_Seconds);
- RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
- }
-}
-
-/**
- * @brief Enables or disables the specified RTC Alarm.
- * @param RTC_Alarm: specifies the alarm to be configured.
- * This parameter can be any combination of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @arg RTC_Alarm_B: to select Alarm B
- * @param NewState: new state of the specified alarm.
- * This parameter can be: ENABLE or DISABLE.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Alarm is enabled/disabled
- * - ERROR: RTC Alarm is not enabled/disabled
- */
-ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)
-{
- __IO uint32_t alarmcounter = 0x00;
- uint32_t alarmstatus = 0x00;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_CMD_ALARM(RTC_Alarm));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Alarm state */
- if (NewState != DISABLE)
- {
- RTC->CR |= (uint32_t)RTC_Alarm;
-
- status = SUCCESS;
- }
- else
- {
- /* Disable the Alarm in RTC_CR register */
- RTC->CR &= (uint32_t)~RTC_Alarm;
-
- /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
- do
- {
- alarmstatus = RTC->ISR & (RTC_Alarm >> 8);
- alarmcounter++;
- } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));
-
- if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Configure the RTC AlarmA/B Sub seconds value and mask.*
- * @note This function is performed only when the Alarm is disabled.
- * @param RTC_Alarm: specifies the alarm to be configured.
- * This parameter can be one of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @arg RTC_Alarm_B: to select Alarm B
- * @param RTC_AlarmSubSecondValue: specifies the Sub seconds value.
- * This parameter can be a value from 0 to 0x00007FFF.
- * @param RTC_AlarmSubSecondMask: specifies the Sub seconds Mask.
- * This parameter can be any combination of the following values:
- * @arg RTC_AlarmSubSecondMask_All : All Alarm SS fields are masked.
- * There is no comparison on sub seconds for Alarm.
- * @arg RTC_AlarmSubSecondMask_SS14_1 : SS[14:1] are don't care in Alarm comparison.
- * Only SS[0] is compared
- * @arg RTC_AlarmSubSecondMask_SS14_2 : SS[14:2] are don't care in Alarm comparison.
- * Only SS[1:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_3 : SS[14:3] are don't care in Alarm comparison.
- * Only SS[2:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_4 : SS[14:4] are don't care in Alarm comparison.
- * Only SS[3:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_5 : SS[14:5] are don't care in Alarm comparison.
- * Only SS[4:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_6 : SS[14:6] are don't care in Alarm comparison.
- * Only SS[5:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_7 : SS[14:7] are don't care in Alarm comparison.
- * Only SS[6:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_8 : SS[14:8] are don't care in Alarm comparison.
- * Only SS[7:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_9 : SS[14:9] are don't care in Alarm comparison.
- * Only SS[8:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison.
- * Only SS[9:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison.
- * Only SS[10:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison.
- * Only SS[11:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison.
- * Only SS[12:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14 : SS[14] is don't care in Alarm comparison.
- * Only SS[13:0] are compared
- * @arg RTC_AlarmSubSecondMask_None : SS[14:0] are compared and must match
- * to activate alarm
- * @retval None
- */
-void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_ALARM(RTC_Alarm));
- assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));
- assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Alarm A or Alarm B Sub Second registers */
- tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask);
-
- if (RTC_Alarm == RTC_Alarm_A)
- {
- /* Configure the Alarm A Sub Second register */
- RTC->ALRMASSR = tmpreg;
- }
- else
- {
- /* Configure the Alarm B Sub Second register */
- RTC->ALRMBSSR = tmpreg;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
-}
-
-/**
- * @brief Gets the RTC Alarm Sub seconds value.
- * @param RTC_Alarm: specifies the alarm to be read.
- * This parameter can be one of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @arg RTC_Alarm_B: to select Alarm B
- * @param None
- * @retval RTC Alarm Sub seconds value.
- */
-uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
-{
- uint32_t tmpreg = 0;
-
- /* Get the RTC_ALRMxR register */
- if (RTC_Alarm == RTC_Alarm_A)
- {
- tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS);
- }
- else
- {
- tmpreg = (uint32_t)((RTC->ALRMBSSR) & RTC_ALRMBSSR_SS);
- }
-
- return (tmpreg);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group4 WakeUp Timer configuration functions
- * @brief WakeUp Timer configuration functions
- *
-@verbatim
- ===============================================================================
- ##### WakeUp Timer configuration functions #####
- ===============================================================================
-
- [..] This section provide functions allowing to program and read the RTC WakeUp.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the RTC Wakeup clock source.
- * @note The WakeUp Clock source can only be changed when the RTC WakeUp
- * is disabled (Use the RTC_WakeUpCmd(DISABLE)).
- * @param RTC_WakeUpClock: Wakeup Clock source.
- * This parameter can be one of the following values:
- * @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16
- * @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8
- * @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4
- * @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2
- * @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE
- * @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE
- * @retval None
- */
-void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock)
-{
- /* Check the parameters */
- assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Clear the Wakeup Timer clock source bits in CR register */
- RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
- /* Configure the clock source */
- RTC->CR |= (uint32_t)RTC_WakeUpClock;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Configures the RTC Wakeup counter.
- * @note The RTC WakeUp counter can only be written when the RTC WakeUp
- * is disabled (Use the RTC_WakeUpCmd(DISABLE)).
- * @param RTC_WakeUpCounter: specifies the WakeUp counter.
- * This parameter can be a value from 0x0000 to 0xFFFF.
- * @retval None
- */
-void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)
-{
- /* Check the parameters */
- assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Wakeup Timer counter */
- RTC->WUTR = (uint32_t)RTC_WakeUpCounter;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Returns the RTC WakeUp timer counter value.
- * @param None
- * @retval The RTC WakeUp Counter value.
- */
-uint32_t RTC_GetWakeUpCounter(void)
-{
- /* Get the counter value */
- return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT));
-}
-
-/**
- * @brief Enables or Disables the RTC WakeUp timer.
- * @param NewState: new state of the WakeUp timer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-ErrorStatus RTC_WakeUpCmd(FunctionalState NewState)
-{
- __IO uint32_t wutcounter = 0x00;
- uint32_t wutwfstatus = 0x00;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- if (NewState != DISABLE)
- {
- /* Enable the Wakeup Timer */
- RTC->CR |= (uint32_t)RTC_CR_WUTE;
- status = SUCCESS;
- }
- else
- {
- /* Disable the Wakeup Timer */
- RTC->CR &= (uint32_t)~RTC_CR_WUTE;
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- do
- {
- wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
- wutcounter++;
- } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
-
- if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group5 Daylight Saving configuration functions
- * @brief Daylight Saving configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Daylight Saving configuration functions #####
- ===============================================================================
-
- [..] This section provide functions allowing to configure the RTC DayLight Saving.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Adds or substract one hour from the current time.
- * @param RTC_DayLightSaveOperation: the value of hour adjustment.
- * This parameter can be one of the following values:
- * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time)
- * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time)
- * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit
- * in CR register to store the operation.
- * This parameter can be one of the following values:
- * @arg RTC_StoreOperation_Reset: BCK Bit Reset
- * @arg RTC_StoreOperation_Set: BCK Bit Set
- * @retval None
- */
-void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
-{
- /* Check the parameters */
- assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));
- assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Clear the bits to be configured */
- RTC->CR &= (uint32_t)~(RTC_CR_BCK);
-
- /* Configure the RTC_CR register */
- RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Returns the RTC Day Light Saving stored operation.
- * @param None
- * @retval RTC Day Light Saving stored operation.
- * - RTC_StoreOperation_Reset
- * - RTC_StoreOperation_Set
- */
-uint32_t RTC_GetStoreOperation(void)
-{
- return (RTC->CR & RTC_CR_BCK);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group6 Output pin Configuration function
- * @brief Output pin Configuration function
- *
-@verbatim
- ===============================================================================
- ##### Output pin Configuration function #####
- ===============================================================================
-
- [..] This section provide functions allowing to configure the RTC Output source.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the RTC output source (AFO_ALARM).
- * @param RTC_Output: Specifies which signal will be routed to the RTC output.
- * This parameter can be one of the following values:
- * @arg RTC_Output_Disable: No output selected
- * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output
- * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output
- * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output
- * @param RTC_OutputPolarity: Specifies the polarity of the output signal.
- * This parameter can be one of the following:
- * @arg RTC_OutputPolarity_High: The output pin is high when the
- * ALRAF/ALRBF/WUTF is high (depending on OSEL)
- * @arg RTC_OutputPolarity_Low: The output pin is low when the
- * ALRAF/ALRBF/WUTF is high (depending on OSEL)
- * @retval None
- */
-void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
-{
- /* Check the parameters */
- assert_param(IS_RTC_OUTPUT(RTC_Output));
- assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Clear the bits to be configured */
- RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL);
-
- /* Configure the output selection and polarity */
- RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity);
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group7 Digital Calibration configuration functions
- * @brief Coarse Calibration configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Digital Calibration configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the Coarse calibration parameters.
- * @param RTC_CalibSign: specifies the sign of the coarse calibration value.
- * This parameter can be one of the following values:
- * @arg RTC_CalibSign_Positive: The value sign is positive
- * @arg RTC_CalibSign_Negative: The value sign is negative
- * @param Value: value of coarse calibration expressed in ppm (coded on 5 bits).
- *
- * @note This Calibration value should be between 0 and 63 when using negative
- * sign with a 2-ppm step.
- *
- * @note This Calibration value should be between 0 and 126 when using positive
- * sign with a 4-ppm step.
- *
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Coarse calibration are initialized
- * - ERROR: RTC Coarse calibration are not initialized
- */
-ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign));
- assert_param(IS_RTC_CALIB_VALUE(Value));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- /* Set the coarse calibration value */
- RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value);
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- status = SUCCESS;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Enables or disables the Coarse calibration process.
- * @param NewState: new state of the Coarse calibration.
- * This parameter can be: ENABLE or DISABLE.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Coarse calibration are enabled/disabled
- * - ERROR: RTC Coarse calibration are not enabled/disabled
- */
-ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- if (NewState != DISABLE)
- {
- /* Enable the Coarse Calibration */
- RTC->CR |= (uint32_t)RTC_CR_DCE;
- }
- else
- {
- /* Disable the Coarse Calibration */
- RTC->CR &= (uint32_t)~RTC_CR_DCE;
- }
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- status = SUCCESS;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Enables or disables the RTC clock to be output through the relative pin.
- * @param NewState: new state of the digital calibration Output.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_CalibOutputCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- if (NewState != DISABLE)
- {
- /* Enable the RTC clock output */
- RTC->CR |= (uint32_t)RTC_CR_COE;
- }
- else
- {
- /* Disable the RTC clock output */
- RTC->CR &= (uint32_t)~RTC_CR_COE;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param RTC_CalibOutput : Select the Calibration output Selection .
- * This parameter can be one of the following values:
- * @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz.
- * @arg RTC_CalibOutput_1Hz : A signal has a regular waveform at 1Hz.
- * @retval None
-*/
-void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput)
-{
- /* Check the parameters */
- assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /*clear flags before configuration */
- RTC->CR &= (uint32_t)~(RTC_CR_COSEL);
-
- /* Configure the RTC_CR register */
- RTC->CR |= (uint32_t)RTC_CalibOutput;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Configures the Smooth Calibration Settings.
- * @param RTC_SmoothCalibPeriod : Select the Smooth Calibration Period.
- * This parameter can be can be one of the following values:
- * @arg RTC_SmoothCalibPeriod_32sec : The smooth calibration period is 32s.
- * @arg RTC_SmoothCalibPeriod_16sec : The smooth calibration period is 16s.
- * @arg RTC_SmoothCalibPeriod_8sec : The smooth calibration period is 8s.
- * @param RTC_SmoothCalibPlusPulses : Select to Set or reset the CALP bit.
- * This parameter can be one of the following values:
- * @arg RTC_SmoothCalibPlusPulses_Set : Add one RTCCLK pulse every 2**11 pulses.
- * @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.
- * @param RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
- * This parameter can be one any value from 0 to 0x000001FF.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Calib registers are configured
- * - ERROR: RTC Calib registers are not configured
-*/
-ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
- uint32_t RTC_SmoothCalibPlusPulses,
- uint32_t RTC_SmouthCalibMinusPulsesValue)
-{
- ErrorStatus status = ERROR;
- uint32_t recalpfcount = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod));
- assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));
- assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* check if a calibration is pending*/
- if ((RTC->ISR & RTC_ISR_RECALPF) != RESET)
- {
- /* wait until the Calibration is completed*/
- while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))
- {
- recalpfcount++;
- }
- }
-
- /* check if the calibration pending is completed or if there is no calibration operation at all*/
- if ((RTC->ISR & RTC_ISR_RECALPF) == RESET)
- {
- /* Configure the Smooth calibration settings */
- RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue);
-
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return (ErrorStatus)(status);
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Group8 TimeStamp configuration functions
- * @brief TimeStamp configuration functions
- *
-@verbatim
- ===============================================================================
- ##### TimeStamp configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or Disables the RTC TimeStamp functionality with the
- * specified time stamp pin stimulating edge.
- * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is
- * activated.
- * This parameter can be one of the following:
- * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising
- * edge of the related pin.
- * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the
- * falling edge of the related pin.
- * @param NewState: new state of the TimeStamp.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Get the RTC_CR register and clear the bits to be configured */
- tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
- /* Get the new configuration */
- if (NewState != DISABLE)
- {
- tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE);
- }
- else
- {
- tmpreg |= (uint32_t)(RTC_TimeStampEdge);
- }
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Time Stamp TSEDGE and Enable bits */
- RTC->CR = (uint32_t)tmpreg;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Get the RTC TimeStamp value and masks.
- * @param RTC_Format: specifies the format of the output parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will
- * contains the TimeStamp time values.
- * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will
- * contains the TimeStamp date values.
- * @retval None
- */
-void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
- RTC_DateTypeDef* RTC_StampDateStruct)
-{
- uint32_t tmptime = 0, tmpdate = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- /* Get the TimeStamp time and date registers values */
- tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK);
- tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK);
-
- /* Fill the Time structure fields with the read parameters */
- RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
- RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
- RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
- RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
-
- /* Fill the Date structure fields with the read parameters */
- RTC_StampDateStruct->RTC_Year = 0;
- RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
- RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
- RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
-
- /* Check the input parameters format */
- if (RTC_Format == RTC_Format_BIN)
- {
- /* Convert the Time structure parameters to Binary format */
- RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours);
- RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes);
- RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds);
-
- /* Convert the Date structure parameters to Binary format */
- RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month);
- RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date);
- RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay);
- }
-}
-
-/**
- * @brief Get the RTC timestamp Sub seconds value.
- * @param None
- * @retval RTC current timestamp Sub seconds value.
- */
-uint32_t RTC_GetTimeStampSubSecond(void)
-{
- /* Get timestamp sub seconds values from the correspondent registers */
- return (uint32_t)(RTC->TSSSR);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group9 Tampers configuration functions
- * @brief Tampers configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Tampers configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the select Tamper pin edge.
- * @param RTC_Tamper: Selected tamper pin.
- * This parameter can be RTC_Tamper_1 or RTC_Tamper 2
- * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that
- * stimulates tamper event.
- * This parameter can be one of the following values:
- * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
- * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
- * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
- * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
- * @retval None
- */
-void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER(RTC_Tamper));
- assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));
-
- if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge)
- {
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1));
- }
- else
- {
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1);
- }
-}
-
-/**
- * @brief Enables or Disables the Tamper detection.
- * @param RTC_Tamper: Selected tamper pin.
- * This parameter can be RTC_Tamper_1 or RTC_Tamper_2
- * @param NewState: new state of the tamper pin.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER(RTC_Tamper));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected Tamper pin */
- RTC->TAFCR |= (uint32_t)RTC_Tamper;
- }
- else
- {
- /* Disable the selected Tamper pin */
- RTC->TAFCR &= (uint32_t)~RTC_Tamper;
- }
-}
-
-/**
- * @brief Configures the Tampers Filter.
- * @param RTC_TamperFilter: Specifies the tampers filter.
- * This parameter can be one of the following values:
- * @arg RTC_TamperFilter_Disable: Tamper filter is disabled.
- * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive
- * samples at the active level
- * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive
- * samples at the active level
- * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive
- * samples at the active level
- * @retval None
- */
-void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));
-
- /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT);
-
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR |= (uint32_t)RTC_TamperFilter;
-}
-
-/**
- * @brief Configures the Tampers Sampling Frequency.
- * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.
- * This parameter can be one of the following values:
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 32768
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 16384
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 8192
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 4096
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 2048
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 1024
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 512
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 256
- * @retval None
- */
-void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));
-
- /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ);
-
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq;
-}
-
-/**
- * @brief Configures the Tampers Pins input Precharge Duration.
- * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input
- * Precharge Duration.
- * This parameter can be one of the following values:
- * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are precharged before sampling during 1 RTCCLK cycle
- * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are precharged before sampling during 2 RTCCLK cycle
- * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are precharged before sampling during 4 RTCCLK cycle
- * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are precharged before sampling during 8 RTCCLK cycle
- * @retval None
- */
-void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration));
-
- /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH);
-
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration;
-}
-
-/**
- * @brief Enables or Disables the TimeStamp on Tamper Detection Event.
- * @note The timestamp is valid even the TSE bit in tamper control register
- * is reset.
- * @param NewState: new state of the timestamp on tamper event.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Save timestamp on tamper detection event */
- RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS;
- }
- else
- {
- /* Tamper detection does not cause a timestamp to be saved */
- RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS;
- }
-}
-
-/**
- * @brief Enables or Disables the Precharge of Tamper pin.
- * @param NewState: new state of tamper pull up.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_TamperPullUpCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable precharge of the selected Tamper pin */
- RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS;
- }
- else
- {
- /* Disable precharge of the selected Tamper pin */
- RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group10 Backup Data Registers configuration functions
- * @brief Backup Data Registers configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Backup Data Registers configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Writes a data in a specified RTC Backup data register.
- * @param RTC_BKP_DR: RTC Backup data Register number.
- * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
- * specify the register.
- * @param Data: Data to be written in the specified RTC Backup data register.
- * @retval None
- */
-void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_BKP(RTC_BKP_DR));
-
- tmp = RTC_BASE + 0x50;
- tmp += (RTC_BKP_DR * 4);
-
- /* Write the specified register */
- *(__IO uint32_t *)tmp = (uint32_t)Data;
-}
-
-/**
- * @brief Reads data from the specified RTC Backup data Register.
- * @param RTC_BKP_DR: RTC Backup data Register number.
- * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
- * specify the register.
- * @retval None
- */
-uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_BKP(RTC_BKP_DR));
-
- tmp = RTC_BASE + 0x50;
- tmp += (RTC_BKP_DR * 4);
-
- /* Read the specified register */
- return (*(__IO uint32_t *)tmp);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group11 RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions
- * @brief RTC Tamper and TimeStamp Pins Selection and Output Type Config
- * configuration functions
- *
-@verbatim
- ==================================================================================================
- ##### RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions #####
- ==================================================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Selects the RTC Tamper Pin.
- * @param RTC_TamperPin: specifies the RTC Tamper Pin.
- * This parameter can be one of the following values:
- * @arg RTC_TamperPin_Default: RTC_AF1 is used as RTC Tamper Pin.
- * @arg RTC_TamperPin_Pos1: RTC_AF2 is selected as RTC Tamper Pin.
- * @retval None
- */
-void RTC_TamperPinSelection(uint32_t RTC_TamperPin)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER_PIN(RTC_TamperPin));
-
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPINSEL);
- RTC->TAFCR |= (uint32_t)(RTC_TamperPin);
-}
-
-/**
- * @brief Selects the RTC TimeStamp Pin.
- * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
- * This parameter can be one of the following values:
- * @arg RTC_TimeStampPin_PC13: PC13 is selected as RTC TimeStamp Pin.
- * @arg RTC_TimeStampPin_PI8: PI8 is selected as RTC TimeStamp Pin.
- * @retval None
- */
-void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
-
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TSINSEL);
- RTC->TAFCR |= (uint32_t)(RTC_TimeStampPin);
-}
-
-/**
- * @brief Configures the RTC Output Pin mode.
- * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode.
- * This parameter can be one of the following values:
- * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in
- * Open Drain mode.
- * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in
- * Push Pull mode.
- * @retval None
- */
-void RTC_OutputTypeConfig(uint32_t RTC_OutputType)
-{
- /* Check the parameters */
- assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));
-
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE);
- RTC->TAFCR |= (uint32_t)(RTC_OutputType);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group12 Shift control synchronisation functions
- * @brief Shift control synchronisation functions
- *
-@verbatim
- ===============================================================================
- ##### Shift control synchronisation functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the Synchronization Shift Control Settings.
- * @note When REFCKON is set, firmware must not write to Shift control register
- * @param RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar.
- * This parameter can be one of the following values :
- * @arg RTC_ShiftAdd1S_Set : Add one second to the clock calendar.
- * @arg RTC_ShiftAdd1S_Reset: No effect.
- * @param RTC_ShiftSubFS: Select the number of Second Fractions to Substitute.
- * This parameter can be one any value from 0 to 0x7FFF.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Shift registers are configured
- * - ERROR: RTC Shift registers are not configured
-*/
-ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
-{
- ErrorStatus status = ERROR;
- uint32_t shpfcount = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));
- assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Check if a Shift is pending*/
- if ((RTC->ISR & RTC_ISR_SHPF) != RESET)
- {
- /* Wait until the shift is completed*/
- while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT))
- {
- shpfcount++;
- }
- }
-
- /* Check if the Shift pending is completed or if there is no Shift operation at all*/
- if ((RTC->ISR & RTC_ISR_SHPF) == RESET)
- {
- /* check if the reference clock detection is disabled */
- if((RTC->CR & RTC_CR_REFCKON) == RESET)
- {
- /* Configure the Shift settings */
- RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S);
-
- if(RTC_WaitForSynchro() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
- else
- {
- status = ERROR;
- }
- }
- else
- {
- status = ERROR;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return (ErrorStatus)(status);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group13 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] All RTC interrupts are connected to the EXTI controller.
-
- (+) To enable the RTC Alarm interrupt, the following sequence is required:
- (++) Configure and enable the EXTI Line 17 in interrupt mode and select
- the rising edge sensitivity using the EXTI_Init() function.
- (++) Configure and enable the RTC_Alarm IRQ channel in the NVIC using the
- NVIC_Init() function.
- (++) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using
- the RTC_SetAlarm() and RTC_AlarmCmd() functions.
-
- (+) To enable the RTC Wakeup interrupt, the following sequence is required:
- (++) Configure and enable the EXTI Line 22 in interrupt mode and select the
- rising edge sensitivity using the EXTI_Init() function.
- (++) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the
- NVIC_Init() function.
- (++) Configure the RTC to generate the RTC wakeup timer event using the
- RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd()
- functions.
-
- (+) To enable the RTC Tamper interrupt, the following sequence is required:
- (++) Configure and enable the EXTI Line 21 in interrupt mode and select
- the rising edge sensitivity using the EXTI_Init() function.
- (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the
- NVIC_Init() function.
- (++) Configure the RTC to detect the RTC tamper event using the
- RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
-
- (+) To enable the RTC TimeStamp interrupt, the following sequence is required:
- (++) Configure and enable the EXTI Line 21 in interrupt mode and select the
- rising edge sensitivity using the EXTI_Init() function.
- (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the
- NVIC_Init() function.
- (++) Configure the RTC to detect the RTC time stamp event using the
- RTC_TimeStampCmd() functions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified RTC interrupts.
- * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_TS: Time Stamp interrupt mask
- * @arg RTC_IT_WUT: WakeUp Timer interrupt mask
- * @arg RTC_IT_ALRB: Alarm B interrupt mask
- * @arg RTC_IT_ALRA: Alarm A interrupt mask
- * @arg RTC_IT_TAMP: Tamper event interrupt mask
- * @param NewState: new state of the specified RTC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RTC_CONFIG_IT(RTC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- if (NewState != DISABLE)
- {
- /* Configure the Interrupts in the RTC_CR register */
- RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE);
- /* Configure the Tamper Interrupt in the RTC_TAFCR */
- RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE);
- }
- else
- {
- /* Configure the Interrupts in the RTC_CR register */
- RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE);
- /* Configure the Tamper Interrupt in the RTC_TAFCR */
- RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE);
- }
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Checks whether the specified RTC flag is set or not.
- * @param RTC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg RTC_FLAG_RECALPF: RECALPF event flag.
- * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
- * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag
- * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag
- * @arg RTC_FLAG_TSF: Time Stamp event flag
- * @arg RTC_FLAG_WUTF: WakeUp Timer flag
- * @arg RTC_FLAG_ALRBF: Alarm B flag
- * @arg RTC_FLAG_ALRAF: Alarm A flag
- * @arg RTC_FLAG_INITF: Initialization mode flag
- * @arg RTC_FLAG_RSF: Registers Synchronized flag
- * @arg RTC_FLAG_INITS: Registers Configured flag
- * @arg RTC_FLAG_SHPF: Shift operation pending flag.
- * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag
- * @arg RTC_FLAG_ALRBWF: Alarm B Write flag
- * @arg RTC_FLAG_ALRAWF: Alarm A write flag
- * @retval The new state of RTC_FLAG (SET or RESET).
- */
-FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
-
- /* Get all the flags */
- tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK);
-
- /* Return the status of the flag */
- if ((tmpreg & RTC_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the RTC's pending flags.
- * @param RTC_FLAG: specifies the RTC flag to clear.
- * This parameter can be any combination of the following values:
- * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
- * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag
- * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag
- * @arg RTC_FLAG_TSF: Time Stamp event flag
- * @arg RTC_FLAG_WUTF: WakeUp Timer flag
- * @arg RTC_FLAG_ALRBF: Alarm B flag
- * @arg RTC_FLAG_ALRAF: Alarm A flag
- * @arg RTC_FLAG_RSF: Registers Synchronized flag
- * @retval None
- */
-void RTC_ClearFlag(uint32_t RTC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
-
- /* Clear the Flags in the RTC_ISR register */
- RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));
-}
-
-/**
- * @brief Checks whether the specified RTC interrupt has occurred or not.
- * @param RTC_IT: specifies the RTC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg RTC_IT_TS: Time Stamp interrupt
- * @arg RTC_IT_WUT: WakeUp Timer interrupt
- * @arg RTC_IT_ALRB: Alarm B interrupt
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_TAMP1: Tamper 1 event interrupt
- * @arg RTC_IT_TAMP2: Tamper 2 event interrupt
- * @retval The new state of RTC_IT (SET or RESET).
- */
-ITStatus RTC_GetITStatus(uint32_t RTC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t tmpreg = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_GET_IT(RTC_IT));
-
- /* Get the TAMPER Interrupt enable bit and pending bit */
- tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));
-
- /* Get the Interrupt enable Status */
- enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15)) | (tmpreg & (RTC_IT >> 16)));
-
- /* Get the Interrupt pending bit */
- tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));
-
- /* Get the status of the Interrupt */
- if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the RTC's interrupt pending bits.
- * @param RTC_IT: specifies the RTC interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_TS: Time Stamp interrupt
- * @arg RTC_IT_WUT: WakeUp Timer interrupt
- * @arg RTC_IT_ALRB: Alarm B interrupt
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_TAMP1: Tamper 1 event interrupt
- * @arg RTC_IT_TAMP2: Tamper 2 event interrupt
- * @retval None
- */
-void RTC_ClearITPendingBit(uint32_t RTC_IT)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_CLEAR_IT(RTC_IT));
-
- /* Get the RTC_ISR Interrupt pending bits mask */
- tmpreg = (uint32_t)(RTC_IT >> 4);
-
- /* Clear the interrupt pending bits in the RTC_ISR register */
- RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));
-}
-
-/**
- * @}
- */
-
-/**
- * @brief Converts a 2 digit decimal to BCD format.
- * @param Value: Byte to be converted.
- * @retval Converted byte
- */
-static uint8_t RTC_ByteToBcd2(uint8_t Value)
-{
- uint8_t bcdhigh = 0;
-
- while (Value >= 10)
- {
- bcdhigh++;
- Value -= 10;
- }
-
- return ((uint8_t)(bcdhigh << 4) | Value);
-}
-
-/**
- * @brief Convert from 2 digit BCD to Binary.
- * @param Value: BCD value to be converted.
- * @retval Converted word
- */
-static uint8_t RTC_Bcd2ToByte(uint8_t Value)
-{
- uint8_t tmp = 0;
- tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
- return (tmp + (Value & (uint8_t)0x0F));
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_rtc.h b/底盘/底盘-old/底盘/Library/stm32f4xx_rtc.h
deleted file mode 100644
index 3fc037e..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_rtc.h
+++ /dev/null
@@ -1,880 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_rtc.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the RTC firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_RTC_H
-#define __STM32F4xx_RTC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup RTC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief RTC Init structures definition
- */
-typedef struct
-{
- uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.
- This parameter can be a value of @ref RTC_Hour_Formats */
-
- uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
- This parameter must be set to a value lower than 0x7F */
-
- uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
- This parameter must be set to a value lower than 0x7FFF */
-}RTC_InitTypeDef;
-
-/**
- * @brief RTC Time structure definition
- */
-typedef struct
-{
- uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour.
- This parameter must be set to a value in the 0-12 range
- if the RTC_HourFormat_12 is selected or 0-23 range if
- the RTC_HourFormat_24 is selected. */
-
- uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes.
- This parameter must be set to a value in the 0-59 range. */
-
- uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds.
- This parameter must be set to a value in the 0-59 range. */
-
- uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time.
- This parameter can be a value of @ref RTC_AM_PM_Definitions */
-}RTC_TimeTypeDef;
-
-/**
- * @brief RTC Date structure definition
- */
-typedef struct
-{
- uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
- This parameter can be a value of @ref RTC_WeekDay_Definitions */
-
- uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format).
- This parameter can be a value of @ref RTC_Month_Date_Definitions */
-
- uint8_t RTC_Date; /*!< Specifies the RTC Date.
- This parameter must be set to a value in the 1-31 range. */
-
- uint8_t RTC_Year; /*!< Specifies the RTC Date Year.
- This parameter must be set to a value in the 0-99 range. */
-}RTC_DateTypeDef;
-
-/**
- * @brief RTC Alarm structure definition
- */
-typedef struct
-{
- RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */
-
- uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks.
- This parameter can be a value of @ref RTC_AlarmMask_Definitions */
-
- uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
- This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
-
- uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
- If the Alarm Date is selected, this parameter
- must be set to a value in the 1-31 range.
- If the Alarm WeekDay is selected, this
- parameter can be a value of @ref RTC_WeekDay_Definitions */
-}RTC_AlarmTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RTC_Exported_Constants
- * @{
- */
-
-
-/** @defgroup RTC_Hour_Formats
- * @{
- */
-#define RTC_HourFormat_24 ((uint32_t)0x00000000)
-#define RTC_HourFormat_12 ((uint32_t)0x00000040)
-#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \
- ((FORMAT) == RTC_HourFormat_24))
-/**
- * @}
- */
-
-/** @defgroup RTC_Asynchronous_Predivider
- * @{
- */
-#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Synchronous_Predivider
- * @{
- */
-#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Time_Definitions
- * @{
- */
-#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
-#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
-#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
-#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_AM_PM_Definitions
- * @{
- */
-#define RTC_H12_AM ((uint8_t)0x00)
-#define RTC_H12_PM ((uint8_t)0x40)
-#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Year_Date_Definitions
- * @{
- */
-#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Month_Date_Definitions
- * @{
- */
-
-/* Coded in BCD format */
-#define RTC_Month_January ((uint8_t)0x01)
-#define RTC_Month_February ((uint8_t)0x02)
-#define RTC_Month_March ((uint8_t)0x03)
-#define RTC_Month_April ((uint8_t)0x04)
-#define RTC_Month_May ((uint8_t)0x05)
-#define RTC_Month_June ((uint8_t)0x06)
-#define RTC_Month_July ((uint8_t)0x07)
-#define RTC_Month_August ((uint8_t)0x08)
-#define RTC_Month_September ((uint8_t)0x09)
-#define RTC_Month_October ((uint8_t)0x10)
-#define RTC_Month_November ((uint8_t)0x11)
-#define RTC_Month_December ((uint8_t)0x12)
-#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
-#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_WeekDay_Definitions
- * @{
- */
-
-#define RTC_Weekday_Monday ((uint8_t)0x01)
-#define RTC_Weekday_Tuesday ((uint8_t)0x02)
-#define RTC_Weekday_Wednesday ((uint8_t)0x03)
-#define RTC_Weekday_Thursday ((uint8_t)0x04)
-#define RTC_Weekday_Friday ((uint8_t)0x05)
-#define RTC_Weekday_Saturday ((uint8_t)0x06)
-#define RTC_Weekday_Sunday ((uint8_t)0x07)
-#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
- ((WEEKDAY) == RTC_Weekday_Tuesday) || \
- ((WEEKDAY) == RTC_Weekday_Wednesday) || \
- ((WEEKDAY) == RTC_Weekday_Thursday) || \
- ((WEEKDAY) == RTC_Weekday_Friday) || \
- ((WEEKDAY) == RTC_Weekday_Saturday) || \
- ((WEEKDAY) == RTC_Weekday_Sunday))
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Alarm_Definitions
- * @{
- */
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
- ((WEEKDAY) == RTC_Weekday_Tuesday) || \
- ((WEEKDAY) == RTC_Weekday_Wednesday) || \
- ((WEEKDAY) == RTC_Weekday_Thursday) || \
- ((WEEKDAY) == RTC_Weekday_Friday) || \
- ((WEEKDAY) == RTC_Weekday_Saturday) || \
- ((WEEKDAY) == RTC_Weekday_Sunday))
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_AlarmDateWeekDay_Definitions
- * @{
- */
-#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000)
-#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000)
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
- ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_AlarmMask_Definitions
- * @{
- */
-#define RTC_AlarmMask_None ((uint32_t)0x00000000)
-#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000)
-#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)
-#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)
-#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)
-#define RTC_AlarmMask_All ((uint32_t)0x80808080)
-#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarms_Definitions
- * @{
- */
-#define RTC_Alarm_A ((uint32_t)0x00000100)
-#define RTC_Alarm_B ((uint32_t)0x00000200)
-#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
-#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
-
-/**
- * @}
- */
-
- /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
- * @{
- */
-#define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
- There is no comparison on sub seconds
- for Alarm */
-#define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm
- comparison. Only SS[0] is compared. */
-#define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm
- comparison. Only SS[1:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm
- comparison. Only SS[2:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm
- comparison. Only SS[3:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm
- comparison. Only SS[4:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm
- comparison. Only SS[5:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm
- comparison. Only SS[6:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm
- comparison. Only SS[7:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm
- comparison. Only SS[8:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm
- comparison. Only SS[9:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm
- comparison. Only SS[10:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm
- comparison.Only SS[11:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm
- comparison. Only SS[12:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
- comparison.Only SS[13:0] are compared */
-#define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
- to activate alarm. */
-#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
- ((MASK) == RTC_AlarmSubSecondMask_None))
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarm_Sub_Seconds_Value
- * @{
- */
-
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Wakeup_Timer_Definitions
- * @{
- */
-#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)
-#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)
-#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)
-#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)
-#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)
-#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)
-#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
- ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
- ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
- ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
- ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
- ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
-#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
-/**
- * @}
- */
-
-/** @defgroup RTC_Time_Stamp_Edges_definitions
- * @{
- */
-#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)
-#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)
-#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
- ((EDGE) == RTC_TimeStampEdge_Falling))
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_selection_Definitions
- * @{
- */
-#define RTC_Output_Disable ((uint32_t)0x00000000)
-#define RTC_Output_AlarmA ((uint32_t)0x00200000)
-#define RTC_Output_AlarmB ((uint32_t)0x00400000)
-#define RTC_Output_WakeUp ((uint32_t)0x00600000)
-
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
- ((OUTPUT) == RTC_Output_AlarmA) || \
- ((OUTPUT) == RTC_Output_AlarmB) || \
- ((OUTPUT) == RTC_Output_WakeUp))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_Polarity_Definitions
- * @{
- */
-#define RTC_OutputPolarity_High ((uint32_t)0x00000000)
-#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)
-#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
- ((POL) == RTC_OutputPolarity_Low))
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Digital_Calibration_Definitions
- * @{
- */
-#define RTC_CalibSign_Positive ((uint32_t)0x00000000)
-#define RTC_CalibSign_Negative ((uint32_t)0x00000080)
-#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \
- ((SIGN) == RTC_CalibSign_Negative))
-#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
-
-/**
- * @}
- */
-
- /** @defgroup RTC_Calib_Output_selection_Definitions
- * @{
- */
-#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000)
-#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000)
-#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \
- ((OUTPUT) == RTC_CalibOutput_1Hz))
-/**
- * @}
- */
-
-/** @defgroup RTC_Smooth_calib_period_Definitions
- * @{
- */
-#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
- period is 32s, else 2exp20 RTCCLK seconds */
-#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibration
- period is 16s, else 2exp19 RTCCLK seconds */
-#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
- period is 8s, else 2exp18 RTCCLK seconds */
-#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
- ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
- ((PERIOD) == RTC_SmoothCalibPeriod_8sec))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions
- * @{
- */
-#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added
- during a X -second window = Y - CALM[8:0].
- with Y = 512, 256, 128 when X = 32, 16, 8 */
-#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
- during a 32-second window = CALM[8:0]. */
-#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
- ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions
- * @{
- */
-#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_DayLightSaving_Definitions
- * @{
- */
-#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)
-#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)
-#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
- ((SAVE) == RTC_DayLightSaving_ADD1H))
-
-#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)
-#define RTC_StoreOperation_Set ((uint32_t)0x00040000)
-#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
- ((OPERATION) == RTC_StoreOperation_Set))
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Trigger_Definitions
- * @{
- */
-#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)
-#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)
-#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)
-#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001)
-#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
- ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
- ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
- ((TRIGGER) == RTC_TamperTrigger_HighLevel))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Filter_Definitions
- * @{
- */
-#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
-
-#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2
- consecutive samples at the active level */
-#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4
- consecutive samples at the active level */
-#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8
- consecutive samples at the active level. */
-#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
- ((FILTER) == RTC_TamperFilter_2Sample) || \
- ((FILTER) == RTC_TamperFilter_4Sample) || \
- ((FILTER) == RTC_TamperFilter_8Sample))
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions
- * @{
- */
-#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 32768 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 16384 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 8192 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 4096 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 2048 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 1024 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 512 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 256 */
-#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
-
-/**
- * @}
- */
-
- /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions
- * @{
- */
-#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
- sampling during 1 RTCCLK cycle */
-#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
- sampling during 2 RTCCLK cycles */
-#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
- sampling during 4 RTCCLK cycles */
-#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
- sampling during 8 RTCCLK cycles */
-
-#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
- ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
- ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
- ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Pins_Definitions
- * @{
- */
-#define RTC_Tamper_1 RTC_TAFCR_TAMP1E
-#define RTC_Tamper_2 RTC_TAFCR_TAMP2E
-#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1) || ((TAMPER) == RTC_Tamper_2))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Pin_Selection
- * @{
- */
-#define RTC_TamperPin_Default ((uint32_t)0x00000000)
-#define RTC_TamperPin_Pos1 ((uint32_t)0x00010000)
-#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_Default) || \
- ((PIN) == RTC_TamperPin_Pos1))
-/* Legacy Defines */
-#define RTC_TamperPin_PC13 RTC_TamperPin_Default
-#define RTC_TamperPin_PI8 RTC_TamperPin_Pos1
-/**
- * @}
- */
-
-/** @defgroup RTC_TimeStamp_Pin_Selection
- * @{
- */
-#define RTC_TimeStampPin_PC13 ((uint32_t)0x00000000)
-#define RTC_TimeStampPin_PI8 ((uint32_t)0x00020000)
-#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \
- ((PIN) == RTC_TimeStampPin_PI8))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_Type_ALARM_OUT
- * @{
- */
-#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)
-#define RTC_OutputType_PushPull ((uint32_t)0x00040000)
-#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
- ((TYPE) == RTC_OutputType_PushPull))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Add_1_Second_Parameter_Definitions
- * @{
- */
-#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000)
-#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000)
-#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
- ((SEL) == RTC_ShiftAdd1S_Set))
-/**
- * @}
- */
-
-/** @defgroup RTC_Substract_Fraction_Of_Second_Value
- * @{
- */
-#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Backup_Registers_Definitions
- * @{
- */
-
-#define RTC_BKP_DR0 ((uint32_t)0x00000000)
-#define RTC_BKP_DR1 ((uint32_t)0x00000001)
-#define RTC_BKP_DR2 ((uint32_t)0x00000002)
-#define RTC_BKP_DR3 ((uint32_t)0x00000003)
-#define RTC_BKP_DR4 ((uint32_t)0x00000004)
-#define RTC_BKP_DR5 ((uint32_t)0x00000005)
-#define RTC_BKP_DR6 ((uint32_t)0x00000006)
-#define RTC_BKP_DR7 ((uint32_t)0x00000007)
-#define RTC_BKP_DR8 ((uint32_t)0x00000008)
-#define RTC_BKP_DR9 ((uint32_t)0x00000009)
-#define RTC_BKP_DR10 ((uint32_t)0x0000000A)
-#define RTC_BKP_DR11 ((uint32_t)0x0000000B)
-#define RTC_BKP_DR12 ((uint32_t)0x0000000C)
-#define RTC_BKP_DR13 ((uint32_t)0x0000000D)
-#define RTC_BKP_DR14 ((uint32_t)0x0000000E)
-#define RTC_BKP_DR15 ((uint32_t)0x0000000F)
-#define RTC_BKP_DR16 ((uint32_t)0x00000010)
-#define RTC_BKP_DR17 ((uint32_t)0x00000011)
-#define RTC_BKP_DR18 ((uint32_t)0x00000012)
-#define RTC_BKP_DR19 ((uint32_t)0x00000013)
-#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
- ((BKP) == RTC_BKP_DR1) || \
- ((BKP) == RTC_BKP_DR2) || \
- ((BKP) == RTC_BKP_DR3) || \
- ((BKP) == RTC_BKP_DR4) || \
- ((BKP) == RTC_BKP_DR5) || \
- ((BKP) == RTC_BKP_DR6) || \
- ((BKP) == RTC_BKP_DR7) || \
- ((BKP) == RTC_BKP_DR8) || \
- ((BKP) == RTC_BKP_DR9) || \
- ((BKP) == RTC_BKP_DR10) || \
- ((BKP) == RTC_BKP_DR11) || \
- ((BKP) == RTC_BKP_DR12) || \
- ((BKP) == RTC_BKP_DR13) || \
- ((BKP) == RTC_BKP_DR14) || \
- ((BKP) == RTC_BKP_DR15) || \
- ((BKP) == RTC_BKP_DR16) || \
- ((BKP) == RTC_BKP_DR17) || \
- ((BKP) == RTC_BKP_DR18) || \
- ((BKP) == RTC_BKP_DR19))
-/**
- * @}
- */
-
-/** @defgroup RTC_Input_parameter_format_definitions
- * @{
- */
-#define RTC_Format_BIN ((uint32_t)0x000000000)
-#define RTC_Format_BCD ((uint32_t)0x000000001)
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Flags_Definitions
- * @{
- */
-#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)
-#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
-#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)
-#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)
-#define RTC_FLAG_TSF ((uint32_t)0x00000800)
-#define RTC_FLAG_WUTF ((uint32_t)0x00000400)
-#define RTC_FLAG_ALRBF ((uint32_t)0x00000200)
-#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)
-#define RTC_FLAG_INITF ((uint32_t)0x00000040)
-#define RTC_FLAG_RSF ((uint32_t)0x00000020)
-#define RTC_FLAG_INITS ((uint32_t)0x00000010)
-#define RTC_FLAG_SHPF ((uint32_t)0x00000008)
-#define RTC_FLAG_WUTWF ((uint32_t)0x00000004)
-#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002)
-#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)
-#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
- ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \
- ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
- ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
- ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
- ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_RECALPF) || \
- ((FLAG) == RTC_FLAG_TAMP2F) ||((FLAG) == RTC_FLAG_SHPF))
-#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
-/**
- * @}
- */
-
-/** @defgroup RTC_Interrupts_Definitions
- * @{
- */
-#define RTC_IT_TS ((uint32_t)0x00008000)
-#define RTC_IT_WUT ((uint32_t)0x00004000)
-#define RTC_IT_ALRB ((uint32_t)0x00002000)
-#define RTC_IT_ALRA ((uint32_t)0x00001000)
-#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
-#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
-#define RTC_IT_TAMP2 ((uint32_t)0x00040000)
-
-#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
-#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \
- ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \
- ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2))
-#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF90FFF) == (uint32_t)RESET))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Legacy
- * @{
- */
-#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig
-#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the RTC configuration to the default reset state *****/
-ErrorStatus RTC_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
-void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
-void RTC_WriteProtectionCmd(FunctionalState NewState);
-ErrorStatus RTC_EnterInitMode(void);
-void RTC_ExitInitMode(void);
-ErrorStatus RTC_WaitForSynchro(void);
-ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
-void RTC_BypassShadowCmd(FunctionalState NewState);
-
-/* Time and Date configuration functions **************************************/
-ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
-void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
-void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
-uint32_t RTC_GetSubSecond(void);
-ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
-void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
-void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
-
-/* Alarms (Alarm A and Alarm B) configuration functions **********************/
-void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
-void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
-void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
-ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
-void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
-uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
-
-/* WakeUp Timer configuration functions ***************************************/
-void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);
-void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
-uint32_t RTC_GetWakeUpCounter(void);
-ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
-
-/* Daylight Saving configuration functions ************************************/
-void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
-uint32_t RTC_GetStoreOperation(void);
-
-/* Output pin Configuration function ******************************************/
-void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
-
-/* Digital Calibration configuration functions *********************************/
-ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value);
-ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState);
-void RTC_CalibOutputCmd(FunctionalState NewState);
-void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
-ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
- uint32_t RTC_SmoothCalibPlusPulses,
- uint32_t RTC_SmouthCalibMinusPulsesValue);
-
-/* TimeStamp configuration functions ******************************************/
-void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
-void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
- RTC_DateTypeDef* RTC_StampDateStruct);
-uint32_t RTC_GetTimeStampSubSecond(void);
-
-/* Tampers configuration functions ********************************************/
-void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
-void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
-void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
-void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
-void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
-void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
-void RTC_TamperPullUpCmd(FunctionalState NewState);
-
-/* Backup Data Registers configuration functions ******************************/
-void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
-uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
-
-/* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration
- functions ******************************************************************/
-void RTC_TamperPinSelection(uint32_t RTC_TamperPin);
-void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin);
-void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
-
-/* RTC_Shift_control_synchonisation_functions *********************************/
-ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
-
-/* Interrupts and flags management functions **********************************/
-void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
-FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
-void RTC_ClearFlag(uint32_t RTC_FLAG);
-ITStatus RTC_GetITStatus(uint32_t RTC_IT);
-void RTC_ClearITPendingBit(uint32_t RTC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_RTC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_sai.c b/底盘/底盘-old/底盘/Library/stm32f4xx_sai.c
deleted file mode 100644
index fe1e894..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_sai.c
+++ /dev/null
@@ -1,1159 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_sai.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Serial Audio Interface (SAI):
- * + Initialization and Configuration
- * + Data transfers functions
- * + DMA transfers management
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
-
- (#) Enable peripheral clock using the following functions
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_SAI1, ENABLE) for SAI1
-
- (#) For each SAI Block A/B enable SCK, SD, FS and MCLK GPIO clocks
- using RCC_AHB1PeriphClockCmd() function.
-
- (#) Peripherals alternate function:
- (++) Connect the pin to the desired peripherals' Alternate
- Function (AF) using GPIO_PinAFConfig() function.
- (++) Configure the desired pin in alternate function by:
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- (++) Select the type, pull-up/pull-down and output speed via
- GPIO_PuPd, GPIO_OType and GPIO_Speed members
- (++) Call GPIO_Init() function
- -@@- If an external clock source is used then the I2S CKIN pin should be
- also configured in Alternate function Push-pull pull-up mode.
-
- (#) The SAI clock can be generated from different clock source :
- PLL I2S, PLL SAI or external clock source.
- (++) The PLL I2S is configured using the following functions RCC_PLLI2SConfig(),
- RCC_PLLI2SCmd(ENABLE), RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY) and
- RCC_SAIPLLI2SClkDivConfig() or;
-
- (++) The PLL SAI is configured using the following functions RCC_PLLSAIConfig(),
- RCC_PLLSAICmd(ENABLE), RCC_GetFlagStatus(RCC_FLAG_PLLSAIRDY) and
- RCC_SAIPLLSAIClkDivConfig()or;
-
- (++) External clock source is configured using the function
- RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the
- define constant I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file.
-
- (#) Each SAI Block A or B has its own clock generator to make these two blocks
- completely independent. The Clock generator is configured using RCC_SAIBlockACLKConfig() and
- RCC_SAIBlockBCLKConfig() functions.
-
- (#) Each SAI Block A or B can be configured separately :
- (++) Program the Master clock divider, Audio mode, Protocol, Data Length, Clock Strobing Edge,
- Synchronous mode, Output drive and FIFO Thresold using SAI_Init() function.
- In case of master mode, program the Master clock divider (MCKDIV) using
- the following formula :
- (+++) MCLK_x = SAI_CK_x / (MCKDIV * 2) with MCLK_x = 256 * FS
- (+++) FS = SAI_CK_x / (MCKDIV * 2) * 256
- (+++) MCKDIV = SAI_CK_x / FS * 512
- (++) Program the Frame Length, Frame active Length, FS Definition, FS Polarity,
- FS Offset using SAI_FrameInit() function.
- (++) Program the Slot First Bit Offset, Slot Size, Slot Number, Slot Active
- using SAI_SlotInit() function.
-
- (#) Enable the NVIC and the corresponding interrupt using the function
- SAI_ITConfig() if you need to use interrupt mode.
-
- (#) When using the DMA mode
- (++) Configure the DMA using DMA_Init() function
- (++) Active the needed channel Request using SAI_DMACmd() function
-
- (#) Enable the SAI using the SAI_Cmd() function.
-
- (#) Enable the DMA using the DMA_Cmd() function when using DMA mode.
-
- (#) The SAI has some specific functions which can be useful depending
- on the audio protocol selected.
- (++) Enable Mute mode when the audio block is a transmitter using SAI_MuteModeCmd()
- function and configure the value transmitted during mute using SAI_MuteValueConfig().
- (++) Detect the Mute mode when audio block is a receiver using SAI_MuteFrameCounterConfig().
- (++) Enable the MONO mode without any data preprocessing in memory when the number
- of slot is equal to 2 using SAI_MonoModeConfig() function.
- (++) Enable data companding algorithm (U law and A law) using SAI_CompandingModeConfig().
- (++) Choose the behavior of the SD line in output when an inactive slot is sent
- on the data line using SAI_TRIStateConfig() function.
- [..]
- (@) In master TX mode: enabling the audio block immediately generates the bit clock
- for the external slaves even if there is no data in the FIFO, However FS signal
- generation is conditioned by the presence of data in the FIFO.
-
- (@) In master RX mode: enabling the audio block immediately generates the bit clock
- and FS signal for the external slaves.
-
- (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:
- (+@) First bit Offset <= (SLOT size - Data size)
- (+@) Data size <= SLOT size
- (+@) Number of SLOT x SLOT size = Frame length
- (+@) The number of slots should be even when bit FSDEF in the SAI_xFRCR is set.
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_sai.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SAI
- * @brief SAI driver modules
- * @{
- */
-#if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) || \
- defined (STM32F401xx) || defined (STM32F411xE) || defined (STM32F446xx) || defined (STM32F469_479xx) || \
- defined (STM32F413_423xx)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* *SAI registers Masks */
-#define CR1_CLEAR_MASK ((uint32_t)0xFF07C010)
-#define FRCR_CLEAR_MASK ((uint32_t)0xFFF88000)
-#define SLOTR_CLEAR_MASK ((uint32_t)0x0000F020)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SAI_Private_Functions
- * @{
- */
-
-/** @defgroup SAI_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This section provides a set of functions allowing to initialize the SAI Audio
- Block Mode, Audio Protocol, Data size, Synchronization between audio block,
- Master clock Divider, Fifo threshold, Frame configuration, slot configuration,
- Tristate mode, Companding mode and Mute mode.
- [..]
- The SAI_Init(), SAI_FrameInit() and SAI_SlotInit() functions follows the SAI Block
- configuration procedures for Master mode and Slave mode (details for these procedures
- are available in reference manual(RM0090).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitialize the SAIx peripheral registers to their default reset values.
- * @param SAIx: To select the SAIx peripheral, where x can be the different instances
- *
- * @retval None
- */
-void SAI_DeInit(SAI_TypeDef* SAIx)
-{
- /* Check the parameters */
- assert_param(IS_SAI_PERIPH(SAIx));
-
- if(SAIx == SAI1)
- {
- /* Enable SAI1 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SAI1, ENABLE);
- /* Release SAI1 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SAI1, DISABLE);
- }
- else
- {
-#if defined(STM32F446xx)
- if(SAIx == SAI2)
- {
- /* Enable SAI2 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SAI2, ENABLE);
- /* Release SAI2 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SAI2, DISABLE);
- }
-#endif /* STM32F446xx */
- }
-}
-
-/**
- * @brief Initializes the SAI Block x peripheral according to the specified
- * parameters in the SAI_InitStruct.
- *
- * @note SAI clock is generated from a specific output of the PLLSAI or a specific
- * output of the PLLI2S or from an alternate function bypassing the PLL I2S.
- *
- * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral.
- * @param SAI_InitStruct: pointer to a SAI_InitTypeDef structure that
- * contains the configuration information for the specified SAI Block peripheral.
- * @retval None
- */
-void SAI_Init(SAI_Block_TypeDef* SAI_Block_x, SAI_InitTypeDef* SAI_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x));
-
- /* Check the SAI Block parameters */
- assert_param(IS_SAI_BLOCK_MODE(SAI_InitStruct->SAI_AudioMode));
- assert_param(IS_SAI_BLOCK_PROTOCOL(SAI_InitStruct->SAI_Protocol));
- assert_param(IS_SAI_BLOCK_DATASIZE(SAI_InitStruct->SAI_DataSize));
- assert_param(IS_SAI_BLOCK_FIRST_BIT(SAI_InitStruct->SAI_FirstBit));
- assert_param(IS_SAI_BLOCK_CLOCK_STROBING(SAI_InitStruct->SAI_ClockStrobing));
- assert_param(IS_SAI_BLOCK_SYNCHRO(SAI_InitStruct->SAI_Synchro));
- assert_param(IS_SAI_BLOCK_SYNCEXT(SAI_InitStruct->SAI_SynchroExt));
- assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(SAI_InitStruct->SAI_OUTDRIV));
- assert_param(IS_SAI_BLOCK_NODIVIDER(SAI_InitStruct->SAI_NoDivider));
- assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(SAI_InitStruct->SAI_MasterDivider));
- assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(SAI_InitStruct->SAI_FIFOThreshold));
-
- /* SAI Block_x CR1 Configuration */
- /* Get the SAI Block_x CR1 value */
- tmpreg = SAI_Block_x->CR1;
- /* Clear MODE, PRTCFG, DS, LSBFIRST, CKSTR, SYNCEN, OUTDRIV, NODIV, and MCKDIV bits */
- tmpreg &= CR1_CLEAR_MASK;
- /* Configure SAI_Block_x: Audio mode, Protocol, Data Size, first transmitted bit, Clock strobing
- edge, Synchronization mode, Output drive, Master Divider and FIFO level */
- /* Set MODE bits according to SAI_AudioMode value */
- /* Set PRTCFG bits according to SAI_Protocol value */
- /* Set DS bits according to SAI_DataSize value */
- /* Set LSBFIRST bit according to SAI_FirstBit value */
- /* Set CKSTR bit according to SAI_ClockStrobing value */
- /* Set SYNCEN bit according to SAI_Synchro value */
- /* Set OUTDRIV bit according to SAI_OUTDRIV value */
- /* Set NODIV bit according to SAI_NoDivider value */
- /* Set MCKDIV bits according to SAI_MasterDivider value */
- tmpreg |= (uint32_t)(SAI_InitStruct->SAI_AudioMode | SAI_InitStruct->SAI_Protocol |
- SAI_InitStruct->SAI_DataSize | SAI_InitStruct->SAI_FirstBit |
- SAI_InitStruct->SAI_ClockStrobing | SAI_InitStruct->SAI_Synchro |
- SAI_InitStruct->SAI_OUTDRIV | SAI_InitStruct->SAI_NoDivider |
- SAI_InitStruct->SAI_SynchroExt | (uint32_t)((SAI_InitStruct->SAI_MasterDivider) << 20));
- /* Write to SAI_Block_x CR1 */
- SAI_Block_x->CR1 = tmpreg;
-
- /* SAI Block_x CR2 Configuration */
- /* Get the SAIBlock_x CR2 value */
- tmpreg = SAI_Block_x->CR2;
- /* Clear FTH bits */
- tmpreg &= ~(SAI_xCR2_FTH);
- /* Configure the FIFO Level */
- /* Set FTH bits according to SAI_FIFOThreshold value */
- tmpreg |= (uint32_t)(SAI_InitStruct->SAI_FIFOThreshold);
- /* Write to SAI_Block_x CR2 */
- SAI_Block_x->CR2 = tmpreg;
-}
-
-/**
- * @brief Initializes the SAI Block Audio frame according to the specified
- * parameters in the SAI_FrameInitStruct.
- *
- * @note this function has no meaning if the AC'97 or SPDIF audio protocol
- * are selected.
- *
- * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral.
- * @param SAI_FrameInitStruct: pointer to an SAI_FrameInitTypeDef structure that
- * contains the configuration of audio frame for a specified SAI Block
- * @retval None
- */
-void SAI_FrameInit(SAI_Block_TypeDef* SAI_Block_x, SAI_FrameInitTypeDef* SAI_FrameInitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x));
-
- /* Check the SAI Block frame parameters */
- assert_param(IS_SAI_BLOCK_FRAME_LENGTH(SAI_FrameInitStruct->SAI_FrameLength));
- assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(SAI_FrameInitStruct->SAI_ActiveFrameLength));
- assert_param(IS_SAI_BLOCK_FS_DEFINITION(SAI_FrameInitStruct->SAI_FSDefinition));
- assert_param(IS_SAI_BLOCK_FS_POLARITY(SAI_FrameInitStruct->SAI_FSPolarity));
- assert_param(IS_SAI_BLOCK_FS_OFFSET(SAI_FrameInitStruct->SAI_FSOffset));
-
- /* SAI Block_x FRCR Configuration */
- /* Get the SAI Block_x FRCR value */
- tmpreg = SAI_Block_x->FRCR;
- /* Clear FRL, FSALL, FSDEF, FSPOL, FSOFF bits */
- tmpreg &= FRCR_CLEAR_MASK;
- /* Configure SAI_Block_x Frame: Frame Length, Active Frame Length, Frame Synchronization
- Definition, Frame Synchronization Polarity and Frame Synchronization Polarity */
- /* Set FRL bits according to SAI_FrameLength value */
- /* Set FSALL bits according to SAI_ActiveFrameLength value */
- /* Set FSDEF bit according to SAI_FSDefinition value */
- /* Set FSPOL bit according to SAI_FSPolarity value */
- /* Set FSOFF bit according to SAI_FSOffset value */
- tmpreg |= (uint32_t)((uint32_t)(SAI_FrameInitStruct->SAI_FrameLength - 1) |
- SAI_FrameInitStruct->SAI_FSOffset |
- SAI_FrameInitStruct->SAI_FSDefinition |
- SAI_FrameInitStruct->SAI_FSPolarity |
- (uint32_t)((SAI_FrameInitStruct->SAI_ActiveFrameLength - 1) << 8));
-
- /* Write to SAI_Block_x FRCR */
- SAI_Block_x->FRCR = tmpreg;
-}
-
-/**
- * @brief Initializes the SAI Block audio Slot according to the specified
- * parameters in the SAI_SlotInitStruct.
- *
- * @note this function has no meaning if the AC'97 or SPDIF audio protocol
- * are selected.
- *
- * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral.
- * @param SAI_SlotInitStruct: pointer to an SAI_SlotInitTypeDef structure that
- * contains the configuration of audio slot for a specified SAI Block
- * @retval None
- */
-void SAI_SlotInit(SAI_Block_TypeDef* SAI_Block_x, SAI_SlotInitTypeDef* SAI_SlotInitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x));
-
- /* Check the SAI Block Slot parameters */
- assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(SAI_SlotInitStruct->SAI_FirstBitOffset));
- assert_param(IS_SAI_BLOCK_SLOT_SIZE(SAI_SlotInitStruct->SAI_SlotSize));
- assert_param(IS_SAI_BLOCK_SLOT_NUMBER(SAI_SlotInitStruct->SAI_SlotNumber));
- assert_param(IS_SAI_SLOT_ACTIVE(SAI_SlotInitStruct->SAI_SlotActive));
-
- /* SAI Block_x SLOTR Configuration */
- /* Get the SAI Block_x SLOTR value */
- tmpreg = SAI_Block_x->SLOTR;
- /* Clear FBOFF, SLOTSZ, NBSLOT, SLOTEN bits */
- tmpreg &= SLOTR_CLEAR_MASK;
- /* Configure SAI_Block_x Slot: First bit offset, Slot size, Number of Slot in
- audio frame and slots activated in audio frame */
- /* Set FBOFF bits according to SAI_FirstBitOffset value */
- /* Set SLOTSZ bits according to SAI_SlotSize value */
- /* Set NBSLOT bits according to SAI_SlotNumber value */
- /* Set SLOTEN bits according to SAI_SlotActive value */
- tmpreg |= (uint32_t)(SAI_SlotInitStruct->SAI_FirstBitOffset |
- SAI_SlotInitStruct->SAI_SlotSize |
- SAI_SlotInitStruct->SAI_SlotActive |
- (uint32_t)((SAI_SlotInitStruct->SAI_SlotNumber - 1) << 8));
-
- /* Write to SAI_Block_x SLOTR */
- SAI_Block_x->SLOTR = tmpreg;
-}
-
-/**
- * @brief Fills each SAI_InitStruct member with its default value.
- * @param SAI_InitStruct: pointer to a SAI_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void SAI_StructInit(SAI_InitTypeDef* SAI_InitStruct)
-{
- /* Reset SAI init structure parameters values */
- /* Initialize the SAI_AudioMode member */
- SAI_InitStruct->SAI_AudioMode = SAI_Mode_MasterTx;
- /* Initialize the SAI_Protocol member */
- SAI_InitStruct->SAI_Protocol = SAI_Free_Protocol;
- /* Initialize the SAI_DataSize member */
- SAI_InitStruct->SAI_DataSize = SAI_DataSize_8b;
- /* Initialize the SAI_FirstBit member */
- SAI_InitStruct->SAI_FirstBit = SAI_FirstBit_MSB;
- /* Initialize the SAI_ClockStrobing member */
- SAI_InitStruct->SAI_ClockStrobing = SAI_ClockStrobing_FallingEdge;
- /* Initialize the SAI_Synchro member */
- SAI_InitStruct->SAI_Synchro = SAI_Asynchronous;
- /* Initialize the SAI_SynchroExt member */
- SAI_InitStruct->SAI_SynchroExt = SAI_SyncExt_Disable;
- /* Initialize the SAI_OUTDRIV member */
- SAI_InitStruct->SAI_OUTDRIV = SAI_OutputDrive_Disabled;
- /* Initialize the SAI_NoDivider member */
- SAI_InitStruct->SAI_NoDivider = SAI_MasterDivider_Enabled;
- /* Initialize the SAI_MasterDivider member */
- SAI_InitStruct->SAI_MasterDivider = 0;
- /* Initialize the SAI_FIFOThreshold member */
- SAI_InitStruct->SAI_FIFOThreshold = SAI_Threshold_FIFOEmpty;
-}
-
-/**
- * @brief Fills each SAI_FrameInitStruct member with its default value.
- * @param SAI_FrameInitStruct: pointer to a SAI_FrameInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void SAI_FrameStructInit(SAI_FrameInitTypeDef* SAI_FrameInitStruct)
-{
- /* Reset SAI Frame init structure parameters values */
- /* Initialize the SAI_FrameLength member */
- SAI_FrameInitStruct->SAI_FrameLength = 8;
- /* Initialize the SAI_ActiveFrameLength member */
- SAI_FrameInitStruct->SAI_ActiveFrameLength = 1;
- /* Initialize the SAI_FSDefinition member */
- SAI_FrameInitStruct->SAI_FSDefinition = SAI_FS_StartFrame;
- /* Initialize the SAI_FSPolarity member */
- SAI_FrameInitStruct->SAI_FSPolarity = SAI_FS_ActiveLow;
- /* Initialize the SAI_FSOffset member */
- SAI_FrameInitStruct->SAI_FSOffset = SAI_FS_FirstBit;
-}
-
-/**
- * @brief Fills each SAI_SlotInitStruct member with its default value.
- * @param SAI_SlotInitStruct: pointer to a SAI_SlotInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void SAI_SlotStructInit(SAI_SlotInitTypeDef* SAI_SlotInitStruct)
-{
- /* Reset SAI Slot init structure parameters values */
- /* Initialize the SAI_FirstBitOffset member */
- SAI_SlotInitStruct->SAI_FirstBitOffset = 0;
- /* Initialize the SAI_SlotSize member */
- SAI_SlotInitStruct->SAI_SlotSize = SAI_SlotSize_DataSize;
- /* Initialize the SAI_SlotNumber member */
- SAI_SlotInitStruct->SAI_SlotNumber = 1;
- /* Initialize the SAI_SlotActive member */
- SAI_SlotInitStruct->SAI_SlotActive = SAI_Slot_NotActive;
-
-}
-
-/**
- * @brief Enables or disables the specified SAI Block peripheral.
- * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral.
- * @param NewState: new state of the SAI_Block_x peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SAI_Cmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SAI peripheral */
- SAI_Block_x->CR1 |= SAI_xCR1_SAIEN;
- }
- else
- {
- /* Disable the selected SAI peripheral */
- SAI_Block_x->CR1 &= ~(SAI_xCR1_SAIEN);
- }
-}
-
-/**
- * @brief Configures the mono mode for the selected SAI block.
- *
- * @note This function has a meaning only when the number of slot is equal to 2.
- *
- * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral.
- * @param SAI_MonoMode: specifies the SAI block mono mode.
- * This parameter can be one of the following values:
- * @arg SAI_MonoMode : Set mono audio mode
- * @arg SAI_StreoMode : Set streo audio mode
- * @retval None
- */
-void SAI_MonoModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_Mono_StreoMode)
-{
- /* Check the parameters */
- assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x));
- assert_param(IS_SAI_BLOCK_MONO_STREO_MODE(SAI_MonoMode));
- /* Clear MONO bit */
- SAI_Block_x->CR1 &= ~(SAI_xCR1_MONO);
- /* Set new Mono Mode value */
- SAI_Block_x->CR1 |= SAI_MonoMode;
-}
-
-/**
- * @brief Configures the TRIState management on data line for the selected SAI block.
- *
- * @note This function has a meaning only when the SAI block is configured in transmitter
- *
- * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral.
- * @param SAI_TRIState: specifies the SAI block TRIState management.
- * This parameter can be one of the following values:
- * @arg SAI_Output_NotReleased : SD output line is still driven by the SAI.
- * @arg SAI_Output_Released : SD output line is released (HI-Z)
- * @retval None
- */
-void SAI_TRIStateConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_TRIState)
-{
- /* Check the parameters */
- assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x));
- assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(SAI_TRIState));
- /* Clear MONO bit */
- SAI_Block_x->CR1 &= ~(SAI_xCR1_MONO);
- /* Set new Mono Mode value */
- SAI_Block_x->CR1 |= SAI_MonoMode;
-
-}
-
-/**
- * @brief Configures the companding mode for the selected SAI block.
- *
- * @note The data expansion or data compression are determined by the state of
- * SAI block selected (transmitter or receiver).
-
- * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral.
- * @param SAI_CompandingMode: specifies the SAI block companding mode.
- * This parameter can be one of the following values:
- * @arg SAI_NoCompanding : no companding algorithm set
- * @arg SAI_ULaw_1CPL_Companding : Set U law (algorithm 1's complement representation)
- * @arg SAI_ALaw_1CPL_Companding : Set A law (algorithm 1's complement representation)
- * @arg SAI_ULaw_2CPL_Companding : Set U law (algorithm 2's complement representation)
- * @arg SAI_ALaw_2CPL_Companding : Set A law (algorithm 2's complement representation)
- * @retval None
- */
-void SAI_CompandingModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_CompandingMode)
-{
- /* Check the parameters */
- assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x));
- assert_param(IS_SAI_BLOCK_COMPANDING_MODE(SAI_CompandingMode));
- /* Clear Companding Mode bits */
- SAI_Block_x->CR2 &= ~(SAI_xCR2_COMP);
- /* Set new Companding Mode value */
- SAI_Block_x->CR2 |= SAI_CompandingMode;
-}
-
-/**
- * @brief Enables or disables the Mute mode for the selected SAI block.
- *
- * @note This function has a meaning only when the audio block is transmitter
- * @note Mute mode is applied for an entire frame for all the valid slot
- * It becomes active at the end of an audio frame when set somewhere in a frame.
- * Mute mode exit occurs at the end of the frame in which the bit MUTE has been set.
- *
- * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral.
- * @param NewState: new state of the SAIx block.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SAI_MuteModeCmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SAI block mute mode */
- SAI_Block_x->CR2 |= SAI_xCR2_MUTE;
- }
- else
- {
- /* Disable the selected SAI SS output */
- SAI_Block_x->CR2 &= ~(SAI_xCR2_MUTE);
- }
-}
-
-/**
- * @brief Configure the mute value for the selected SAI block.
- *
- * @note This function has a meaning only when the audio block is transmitter
- * @note the configuration last value sent during mute mode has only a meaning
- * when the number of slot is lower or equal to 2 and if the MUTE bit is set.
- *
- * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral.
- * @param SAI_MuteValue: specifies the SAI block mute value.
- * This parameter can be one of the following values:
- * @arg SAI_ZeroValue : bit value 0 is sent during Mute Mode
- * @arg SAI_LastSentValue : Last value is sent during Mute Mode
- * @retval None
- */
-void SAI_MuteValueConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteValue)
-{
- /* Check the parameters */
- assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x));
- assert_param(IS_SAI_BLOCK_MUTE_VALUE(SAI_MuteValue));
-
- /* Clear Mute value bits */
- SAI_Block_x->CR2 &= ~(SAI_xCR2_MUTEVAL);
- /* Set new Mute value */
- SAI_Block_x->CR2 |= SAI_MuteValue;
-}
-
-/**
- * @brief Enables or disables the Mute mode for the selected SAI block.
- *
- * @note This function has a meaning only when the audio block is Receiver
- * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral.
- * @param SAI_MuteCounter: specifies the SAI block mute value.
- * This parameter can be a number between 0 and 63.
-
- * @retval None
- */
-void SAI_MuteFrameCounterConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteCounter)
-{
- /* Check the parameters */
- assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x));
- assert_param(IS_SAI_BLOCK_MUTE_COUNTER(SAI_MuteCounter));
-
- /* Clear Mute value bits */
- SAI_Block_x->CR2 &= ~(SAI_xCR2_MUTECNT);
- /* Set new Mute value */
- SAI_Block_x->CR2 |= (SAI_MuteCounter << 7);
-}
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F469_479xx) || defined(STM32F413_423xx) || defined(STM32F446xx)
-/**
- * @brief Configure SAI Block synchronization mode
- * @param SAI_InitStruct: pointer to a SAI_InitTypeDef structure that
- * contains the configuration information for the specified SAI Block peripheral.
- * @param SAIx: To select the SAIx peripheral, where x can be the different instances
- * @retval None
- */
-void SAI_BlockSynchroConfig(SAI_InitTypeDef* SAI_InitStruct, SAI_TypeDef* SAIx)
-{
- uint32_t tmpregisterGCR = 0U;
-
-#if defined(STM32F446xx)
- /* This setting must be done with both audio block (A & B) disabled */
- switch(SAI_InitStruct->SAI_SynchroExt)
- {
- case SAI_SyncExt_Disable :
- tmpregisterGCR = 0U;
- break;
- case SAI_SyncExt_OutBlockA_Enable :
- tmpregisterGCR = SAI_GCR_SYNCOUT_0;
- break;
- case SAI_SyncExt_OutBlockB_Enable :
- tmpregisterGCR = SAI_GCR_SYNCOUT_1;
- break;
- default:
- break;
- }
-
- if(((SAI_InitStruct->SAI_Synchro) == SAI_Synchronous_Ext) && (SAIx == SAI1))
- {
- tmpregisterGCR |= SAI_GCR_SYNCIN_0;
- }
-
- if(SAIx == SAI1)
- {
- SAI1->GCR = tmpregisterGCR;
- }
- else
- {
- SAI2->GCR = tmpregisterGCR;
- }
-
-#endif /* STM32F446xx */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F469_479xx) || defined(STM32F413_423xx)
- /* This setting must be done with both audio block (A & B) disabled */
- switch(SAI_InitStruct->SAI_SynchroExt)
- {
- case SAI_SyncExt_Disable :
- tmpregisterGCR = 0U;
- break;
- case SAI_SyncExt_OutBlockA_Enable :
- tmpregisterGCR = SAI_GCR_SYNCOUT_0;
- break;
- case SAI_SyncExt_OutBlockB_Enable :
- tmpregisterGCR = SAI_GCR_SYNCOUT_1;
- break;
- default:
- break;
- }
- SAI1->GCR = tmpregisterGCR;
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469_479xx || STM32F413_423xx */
-}
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469_479xx || STM32F413_423xx || STM32F446xx */
-
-/**
- * @brief Reinitialize the FIFO pointer
- *
- * @note The FIFO pointers can be reinitialized at anytime The data present
- * into the FIFO, if it is not empty, will be lost.
- *
- * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral.
- * @param NewState: new state of the selected SAI TI communication mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SAI_FlushFIFO(SAI_Block_TypeDef* SAI_Block_x)
-{
- /* Check the parameters */
- assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x));
-
- /* FIFO flush */
- SAI_Block_x->CR2 |= SAI_xCR2_FFLUSH;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SAI_Group2 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers functions #####
- ===============================================================================
- [..]
- This section provides a set of functions allowing to manage the SAI data transfers.
- [..]
- In reception, data are received and then stored into an internal FIFO while
- In transmission, data are first stored into an internal FIFO before being
- transmitted.
- [..]
- The read access of the SAI_xDR register can be done using the SAI_ReceiveData()
- function and returns the Rx buffered value. Whereas a write access to the SAI_DR
- can be done using SAI_SendData() function and stores the written data into
- Tx buffer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the most recent received data by the SAI block x peripheral.
- * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral.
- *
- * @retval The value of the received data.
- */
-uint32_t SAI_ReceiveData(SAI_Block_TypeDef* SAI_Block_x)
-{
- /* Check the parameters */
- assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x));
-
- /* Return the data in the DR register */
- return SAI_Block_x->DR;
-}
-
-/**
- * @brief Transmits a Data through the SAI block x peripheral.
- * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral.
- *
- * @param Data: Data to be transmitted.
- * @retval None
- */
-void SAI_SendData(SAI_Block_TypeDef* SAI_Block_x, uint32_t Data)
-{
- /* Check the parameters */
- assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x));
-
- /* Write in the DR register the data to be sent */
- SAI_Block_x->DR = Data;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SAI_Group3 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the SAI Block x DMA interface.
- * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral.
- * @param NewState: new state of the selected SAI block DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SAI_DMACmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SAI block mute mode */
- SAI_Block_x->CR1 |= SAI_xCR1_DMAEN;
- }
- else
- {
- /* Disable the selected SAI SS output */
- SAI_Block_x->CR1 &= ~(SAI_xCR1_DMAEN);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup SAI_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..]
- This section provides a set of functions allowing to configure the SAI Interrupts
- sources and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to manage
- the communication: Polling mode, Interrupt mode or DMA mode.
-
- *** Polling Mode ***
- ====================
- [..]
- In Polling Mode, the SAI communication can be managed by 7 flags:
- (#) SAI_FLAG_FREQ : to indicate if there is a FIFO Request to write or to read.
- (#) SAI_FLAG_MUTEDET : to indicate if a MUTE frame detected
- (#) SAI_FLAG_OVRUDR : to indicate if an Overrun or Underrun error occur
- (#) SAI_FLAG_AFSDET : to indicate if there is the detection of a audio frame
- synchronisation (FS) earlier than expected
- (#) SAI_FLAG_LFSDET : to indicate if there is the detection of a audio frame
- synchronisation (FS) later than expected
- (#) SAI_FLAG_CNRDY : to indicate if the codec is not ready to communicate during
- the reception of the TAG 0 (slot0) of the AC97 audio frame
- (#) SAI_FLAG_WCKCFG: to indicate if wrong clock configuration in master mode
- error occurs.
- [..]
- In this Mode it is advised to use the following functions:
- (+) FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG);
- (+) void SAI_ClearFlag(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG);
-
- *** Interrupt Mode ***
- ======================
- [..]
- In Interrupt Mode, the SAI communication can be managed by 7 interrupt sources
- and 7 pending bits:
- (+) Pending Bits:
- (##) SAI_IT_FREQ : to indicate if there is a FIFO Request to write or to read.
- (##) SAI_IT_MUTEDET : to indicate if a MUTE frame detected.
- (##) SAI_IT_OVRUDR : to indicate if an Overrun or Underrun error occur.
- (##) SAI_IT_AFSDET : to indicate if there is the detection of a audio frame
- synchronisation (FS) earlier than expected.
- (##) SAI_IT_LFSDET : to indicate if there is the detection of a audio frame
- synchronisation (FS) later than expected.
- (##) SAI_IT_CNRDY : to indicate if the codec is not ready to communicate during
- the reception of the TAG 0 (slot0) of the AC97 audio frame.
- (##) SAI_IT_WCKCFG: to indicate if wrong clock configuration in master mode
- error occurs.
-
- (+) Interrupt Source:
- (##) SAI_IT_FREQ : specifies the interrupt source for FIFO Request.
- (##) SAI_IT_MUTEDET : specifies the interrupt source for MUTE frame detected.
- (##) SAI_IT_OVRUDR : specifies the interrupt source for overrun or underrun error.
- (##) SAI_IT_AFSDET : specifies the interrupt source for anticipated frame synchronization
- detection interrupt.
- (##) SAI_IT_LFSDET : specifies the interrupt source for late frame synchronization
- detection interrupt.
- (##) SAI_IT_CNRDY : specifies the interrupt source for codec not ready interrupt
- (##) SAI_IT_WCKCFG: specifies the interrupt source for wrong clock configuration
- interrupt.
- [..]
- In this Mode it is advised to use the following functions:
- (+) void SAI_ITConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState);
- (+) ITStatus SAI_GetITStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT);
- (+) void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT);
-
- *** DMA Mode ***
- ================
- [..]
- In DMA Mode, each SAI audio block has an independent DMA interface in order to
- read or to write into the SAI_xDR register (to hit the internal FIFO).
- There is one DMA channel by audio block following basic DMA request/acknowledge
- protocol.
- [..]
- In this Mode it is advised to use the following function:
- (+) void SAI_DMACmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState);
- [..]
- This section provides also functions allowing to
- (+) Check the SAI Block enable status
- (+)Check the FIFO status
-
- *** SAI Block Enable status ***
- ===============================
- [..]
- After disabling a SAI Block, it is recommended to check (or wait until) the SAI Block
- is effectively disabled. If a Block is disabled while an audio frame transfer is ongoing
- the current frame will be transferred and the block will be effectively disabled only at
- the end of audio frame.
- To monitor this state it is possible to use the following function:
- (+) FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x);
-
- *** SAI Block FIFO status ***
- =============================
- [..]
- It is possible to monitor the FIFO status when a transfer is ongoing using the following
- function:
- (+) uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified SAI Block interrupts.
- * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral.
- * @param SAI_IT: specifies the SAI interrupt source to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg SAI_IT_FREQ: FIFO Request interrupt mask
- * @arg SAI_IT_MUTEDET: MUTE detection interrupt mask
- * @arg SAI_IT_OVRUDR: overrun/underrun interrupt mask
- * @arg SAI_IT_AFSDET: anticipated frame synchronization detection
- * interrupt mask
- * @arg SAI_IT_LFSDET: late frame synchronization detection interrupt
- * mask
- * @arg SAI_IT_CNRDY: codec not ready interrupt mask
- * @arg SAI_IT_WCKCFG: wrong clock configuration interrupt mask
- * @param NewState: new state of the specified SAI interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SAI_ITConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SAI_BLOCK_CONFIG_IT(SAI_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SAI Block interrupt */
- SAI_Block_x->IMR |= SAI_IT;
- }
- else
- {
- /* Disable the selected SAI Block interrupt */
- SAI_Block_x->IMR &= ~(SAI_IT);
- }
-}
-
-/**
- * @brief Checks whether the specified SAI block x flag is set or not.
- * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral.
- * @param SAI_FLAG: specifies the SAI block flag to check.
- * This parameter can be one of the following values:
- * @arg SAI_FLAG_FREQ: FIFO Request flag.
- * @arg SAI_FLAG_MUTEDET: MUTE detection flag.
- * @arg SAI_FLAG_OVRUDR: overrun/underrun flag.
- * @arg SAI_FLAG_WCKCFG: wrong clock configuration flag.
- * @arg SAI_FLAG_CNRDY: codec not ready flag.
- * @arg SAI_FLAG_AFSDET: anticipated frame synchronization detection flag.
- * @arg SAI_FLAG_LFSDET: late frame synchronization detection flag.
- * @retval The new state of SAI_FLAG (SET or RESET).
- */
-FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x));
- assert_param(IS_SAI_BLOCK_GET_FLAG(SAI_FLAG));
-
- /* Check the status of the specified SAI flag */
- if ((SAI_Block_x->SR & SAI_FLAG) != (uint32_t)RESET)
- {
- /* SAI_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* SAI_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the SAI_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the specified SAI Block x flag.
- * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral.
- * @param SAI_FLAG: specifies the SAI block flag to check.
- * This parameter can be one of the following values:
- * @arg SAI_FLAG_MUTEDET: MUTE detection flag.
- * @arg SAI_FLAG_OVRUDR: overrun/underrun flag.
- * @arg SAI_FLAG_WCKCFG: wrong clock configuration flag.
- * @arg SAI_FLAG_CNRDY: codec not ready flag.
- * @arg SAI_FLAG_AFSDET: anticipated frame synchronization detection flag.
- * @arg SAI_FLAG_LFSDET: late frame synchronization detection flag.
- *
- * @note FREQ (FIFO Request) flag is cleared :
- * - When the audio block is transmitter and the FIFO is full or the FIFO
- * has one data (one buffer mode) depending the bit FTH in the
- * SAI_xCR2 register.
- * - When the audio block is receiver and the FIFO is not empty
- *
- * @retval None
- */
-void SAI_ClearFlag(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x));
- assert_param(IS_SAI_BLOCK_CLEAR_FLAG(SAI_FLAG));
-
- /* Clear the selected SAI Block flag */
- SAI_Block_x->CLRFR |= SAI_FLAG;
-}
-
-/**
- * @brief Checks whether the specified SAI Block x interrupt has occurred or not.
- * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral.
- * @param SAI_IT: specifies the SAI interrupt source to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg SAI_IT_FREQ: FIFO Request interrupt
- * @arg SAI_IT_MUTEDET: MUTE detection interrupt
- * @arg SAI_IT_OVRUDR: overrun/underrun interrupt
- * @arg SAI_IT_AFSDET: anticipated frame synchronization detection interrupt
- * @arg SAI_IT_LFSDET: late frame synchronization detection interrupt
- * @arg SAI_IT_CNRDY: codec not ready interrupt
- * @arg SAI_IT_WCKCFG: wrong clock configuration interrupt
- *
- * @retval The new state of SAI_IT (SET or RESET).
- */
-ITStatus SAI_GetITStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x));
- assert_param(IS_SAI_BLOCK_CONFIG_IT(SAI_IT));
-
- /* Get the SAI_IT enable bit status */
- enablestatus = (SAI_Block_x->IMR & SAI_IT) ;
-
- /* Check the status of the specified SAI interrupt */
- if (((SAI_Block_x->SR & SAI_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
- {
- /* SAI_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* SAI_IT is reset */
- bitstatus = RESET;
- }
- /* Return the SAI_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the SAI Block x interrupt pending bit.
- * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral.
- * @param SAI_IT: specifies the SAI Block interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg SAI_IT_MUTEDET: MUTE detection interrupt.
- * @arg SAI_IT_OVRUDR: overrun/underrun interrupt.
- * @arg SAI_IT_WCKCFG: wrong clock configuration interrupt.
- * @arg SAI_IT_CNRDY: codec not ready interrupt.
- * @arg SAI_IT_AFSDET: anticipated frame synchronization detection interrupt.
- * @arg SAI_IT_LFSDET: late frame synchronization detection interrupt.
- *
- * @note FREQ (FIFO Request) flag is cleared :
- * - When the audio block is transmitter and the FIFO is full or the FIFO
- * has one data (one buffer mode) depending the bit FTH in the
- * SAI_xCR2 register.
- * - When the audio block is receiver and the FIFO is not empty
- *
- * @retval None
- */
-void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT)
-{
- /* Check the parameters */
- assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x));
- assert_param(IS_SAI_BLOCK_CONFIG_IT(SAI_IT));
-
- /* Clear the selected SAI Block x interrupt pending bit */
- SAI_Block_x->CLRFR |= SAI_IT;
-}
-
-/**
- * @brief Returns the status of EN bit for the specified SAI Block x.
- * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral.
- *
- * @note After disabling a SAI Block, it is recommended to check (or wait until)
- * the SAI Block is effectively disabled. If a Block is disabled while
- * an audio frame transfer is ongoing, the current frame will be
- * transferred and the block will be effectively disabled only at
- * the end of audio frame.
- *
- * @retval Current state of the DMAy Streamx (ENABLE or DISABLE).
- */
-FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x)
-{
- FunctionalState state = DISABLE;
-
- /* Check the parameters */
- assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x));
- if ((SAI_Block_x->CR1 & (uint32_t)SAI_xCR1_SAIEN) != 0)
- {
- /* The selected SAI Block x EN bit is set (audio frame transfer is ongoing) */
- state = ENABLE;
- }
- else
- {
- /* The selected SAI Block x EN bit is cleared (SAI Block is disabled and
- all transfers are complete) */
- state = DISABLE;
- }
- return state;
-}
-
-/**
- * @brief Returns the current SAI Block x FIFO filled level.
- * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral.
- *
- * @retval The FIFO filling state.
- * - SAI_FIFOStatus_Empty: when FIFO is empty
- * - SAI_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
- * and not empty.
- * - SAI_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
- * - SAI_FIFOStatus_HalfFull: if more than 1 half-full.
- * - SAI_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
- * - SAI_FIFOStatus_Full: when FIFO is full
- */
-uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x));
-
- /* Get the FIFO level bits */
- tmpreg = (uint32_t)((SAI_Block_x->SR & SAI_xSR_FLVL));
-
- return tmpreg;
-}
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx || STM32F469_479xx */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_sai.h b/底盘/底盘-old/底盘/Library/stm32f4xx_sai.h
deleted file mode 100644
index 0c1c7ad..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_sai.h
+++ /dev/null
@@ -1,641 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_sai.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the SAI
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_SAI_H
-#define __STM32F4xx_SAI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup SAI
- * @{
- */
-#if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) || \
- defined (STM32F401xx) || defined (STM32F411xE) || defined (STM32F446xx) || defined (STM32F469_479xx) || \
- defined (STM32F413_423xx)
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief SAI Block Init structure definition
- */
-
-typedef struct
-{
- uint32_t SAI_AudioMode; /*!< Specifies the SAI Block Audio Mode.
- This parameter can be a value of @ref SAI_Block_Mode */
-
- uint32_t SAI_Protocol; /*!< Specifies the SAI Block Protocol.
- This parameter can be a value of @ref SAI_Block_Protocol */
-
- uint32_t SAI_DataSize; /*!< Specifies the SAI Block data size.
- This parameter can be a value of @ref SAI_Block_Data_Size
- @note this value is ignored when AC'97 or SPDIF protocols are selected.*/
-
- uint32_t SAI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission
- @note this value has no meaning when AC'97 or SPDIF protocols are selected.*/
-
- uint32_t SAI_ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity.
- This parameter can be a value of @ref SAI_Block_Clock_Strobing */
-
- uint32_t SAI_Synchro; /*!< Specifies SAI Block synchronization
- This parameter can be a value of @ref SAI_Block_Synchronization */
-
- uint32_t SAI_SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common
- for BlockA and BlockB
- This parameter can be a value of @ref SAI_Block_SyncExt
- @note: If both audio blocks of same SAI are used, this parameter has
- to be set to the same value for each audio block */
-
- uint32_t SAI_OUTDRIV; /*!< Specifies when SAI Block outputs are driven.
- This parameter can be a value of @ref SAI_Block_Output_Drive
- @note this value has to be set before enabling the audio block
- but after the audio block configuration. */
-
- uint32_t SAI_NoDivider; /*!< Specifies whether Master Clock will be divided or not.
- This parameter can be a value of @ref SAI_Block_NoDivider */
-
- uint32_t SAI_MasterDivider; /*!< Specifies SAI Block Master Clock Divider.
- @note the Master Clock Frequency is calculated accordingly to the
- following formula : MCLK_x = SAI_CK_x/(MCKDIV[3:0]*2)*/
-
- uint32_t SAI_FIFOThreshold; /*!< Specifies SAI Block FIFO Threshold.
- This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
-}SAI_InitTypeDef;
-
-/**
- * @brief SAI Block Frame Init structure definition
- */
-
-typedef struct
-{
-
- uint32_t SAI_FrameLength; /*!< Specifies the Frame Length, the number of SCK clocks
- for each audio frame.
- This parameter must be a number between 8 and 256.
- @note If master Clock MCLK_x pin is declared as an output, the frame length
- should be Aligned to a number equal to power of 2 in order to keep
- in an audio frame, an integer number of MCLK pulses by bit Clock.
- @note this value is ignored when AC'97 or SPDIF protocols are selected.*/
-
- uint32_t SAI_ActiveFrameLength; /*!< Specifies the Frame synchronization active level length.
- This Parameter specifies the length in number of bit clock (SCK + 1)
- of the active level of FS signal in audio frame.
- This parameter must be a number between 1 and 128.
- @note this value is ignored when AC'97 or SPDIF protocols are selected.*/
-
- uint32_t SAI_FSDefinition; /*!< Specifies the Frame Synchronization definition.
- This parameter can be a value of @ref SAI_Block_FS_Definition
- @note this value is ignored when AC'97 or SPDIF protocols are selected.*/
-
- uint32_t SAI_FSPolarity; /*!< Specifies the Frame Synchronization Polarity.
- This parameter can be a value of @ref SAI_Block_FS_Polarity
- @note this value is ignored when AC'97 or SPDIF protocols are selected.*/
-
- uint32_t SAI_FSOffset; /*!< Specifies the Frame Synchronization Offset.
- This parameter can be a value of @ref SAI_Block_FS_Offset
- @note this value is ignored when AC'97 or SPDIF protocols are selected.*/
-
-}SAI_FrameInitTypeDef;
-
-/**
- * @brief SAI Block Slot Init Structure definition
- */
-
-typedef struct
-{
- uint32_t SAI_FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot.
- This parameter must be a number between 0 and 24.
- @note this value is ignored when AC'97 or SPDIF protocols are selected.*/
-
- uint32_t SAI_SlotSize; /*!< Specifies the Slot Size.
- This parameter can be a value of @ref SAI_Block_Slot_Size
- @note this value is ignored when AC'97 or SPDIF protocols are selected.*/
-
- uint32_t SAI_SlotNumber; /*!< Specifies the number of slot in the audio frame.
- This parameter must be a number between 1 and 16.
- @note this value is ignored when AC'97 or SPDIF protocols are selected.*/
-
- uint32_t SAI_SlotActive; /*!< Specifies the slots in audio frame that will be activated.
- This parameter can be a value of @ ref SAI_Block_Slot_Active
- @note this value is ignored when AC'97 or SPDIF protocols are selected.*/
-}SAI_SlotInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SAI_Exported_Constants
- * @{
- */
-
-#if defined(STM32F446xx)
-#define IS_SAI_PERIPH(PERIPH) (((PERIPH) == SAI1) || ((PERIPH) == SAI2))
-
-#define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \
- ((PERIPH) == SAI1_Block_B) || \
- ((PERIPH) == SAI2_Block_A) || \
- ((PERIPH) == SAI2_Block_B))
-#endif /* STM32F446xx */
-
-#if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F411xE) || defined(STM32F413_423xx) || defined (STM32F469_479xx)
-
-#define IS_SAI_PERIPH(PERIPH) ((PERIPH) == SAI1)
-
-#define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \
- ((PERIPH) == SAI1_Block_B))
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F413_423xx || STM32F469_479xx */
-
-/** @defgroup SAI_Block_Mode
- * @{
- */
-#define SAI_Mode_MasterTx ((uint32_t)0x00000000)
-#define SAI_Mode_MasterRx ((uint32_t)0x00000001)
-#define SAI_Mode_SlaveTx ((uint32_t)0x00000002)
-#define SAI_Mode_SlaveRx ((uint32_t)0x00000003)
-#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_Mode_MasterTx) || \
- ((MODE) == SAI_Mode_MasterRx) || \
- ((MODE) == SAI_Mode_SlaveTx) || \
- ((MODE) == SAI_Mode_SlaveRx))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Protocol
- * @{
- */
-
-#define SAI_Free_Protocol ((uint32_t)0x00000000)
-#define SAI_SPDIF_Protocol ((uint32_t)SAI_xCR1_PRTCFG_0)
-#define SAI_AC97_Protocol ((uint32_t)SAI_xCR1_PRTCFG_1)
-#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_Free_Protocol) || \
- ((PROTOCOL) == SAI_SPDIF_Protocol) || \
- ((PROTOCOL) == SAI_AC97_Protocol))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Data_Size
- * @{
- */
-
-#define SAI_DataSize_8b ((uint32_t)0x00000040)
-#define SAI_DataSize_10b ((uint32_t)0x00000060)
-#define SAI_DataSize_16b ((uint32_t)0x00000080)
-#define SAI_DataSize_20b ((uint32_t)0x000000A0)
-#define SAI_DataSize_24b ((uint32_t)0x000000C0)
-#define SAI_DataSize_32b ((uint32_t)0x000000E0)
-#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DataSize_8b) || \
- ((DATASIZE) == SAI_DataSize_10b) || \
- ((DATASIZE) == SAI_DataSize_16b) || \
- ((DATASIZE) == SAI_DataSize_20b) || \
- ((DATASIZE) == SAI_DataSize_24b) || \
- ((DATASIZE) == SAI_DataSize_32b))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_MSB_LSB_transmission
- * @{
- */
-
-#define SAI_FirstBit_MSB ((uint32_t)0x00000000)
-#define SAI_FirstBit_LSB ((uint32_t)SAI_xCR1_LSBFIRST)
-#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FirstBit_MSB) || \
- ((BIT) == SAI_FirstBit_LSB))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Clock_Strobing
- * @{
- */
-
-#define SAI_ClockStrobing_FallingEdge ((uint32_t)0x00000000)
-#define SAI_ClockStrobing_RisingEdge ((uint32_t)SAI_xCR1_CKSTR)
-#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_ClockStrobing_FallingEdge) || \
- ((CLOCK) == SAI_ClockStrobing_RisingEdge))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Synchronization
- * @{
- */
-
-#define SAI_Asynchronous ((uint32_t)0x00000000)
-#define SAI_Synchronous ((uint32_t)SAI_xCR1_SYNCEN_0)
-#define SAI_Synchronous_Ext ((uint32_t)SAI_xCR1_SYNCEN_1)
-#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_Synchronous) || \
- ((SYNCHRO) == SAI_Asynchronous) || \
- ((SYNCHRO) == SAI_Synchronous_Ext))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_SyncExt SAI External synchronisation
- * @{
- */
-#define SAI_SyncExt_Disable ((uint32_t)0x00000000)
-#define SAI_SyncExt_OutBlockA_Enable ((uint32_t)SAI_GCR_SYNCOUT_0)
-#define SAI_SyncExt_OutBlockB_Enable ((uint32_t)SAI_GCR_SYNCOUT_1)
-#define IS_SAI_BLOCK_SYNCEXT(SYNCHRO) (((SYNCHRO) == SAI_SyncExt_Disable) || \
- ((SYNCHRO) == SAI_SyncExt_OutBlockA_Enable)|| \
- ((SYNCHRO) == SAI_SyncExt_OutBlockB_Enable))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Output_Drive
- * @{
- */
-
-#define SAI_OutputDrive_Disabled ((uint32_t)0x00000000)
-#define SAI_OutputDrive_Enabled ((uint32_t)SAI_xCR1_OUTDRIV)
-#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OutputDrive_Disabled) || \
- ((DRIVE) == SAI_OutputDrive_Enabled))
-/**
- * @}
- */
-
-
-
-/** @defgroup SAI_Block_NoDivider
- * @{
- */
-
-#define SAI_MasterDivider_Enabled ((uint32_t)0x00000000)
-#define SAI_MasterDivider_Disabled ((uint32_t)SAI_xCR1_NODIV)
-#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MasterDivider_Enabled) || \
- ((NODIVIDER) == SAI_MasterDivider_Disabled))
-/**
- * @}
- */
-
-
-/** @defgroup SAI_Block_Master_Divider
- * @{
- */
-#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
-
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Frame_Length
- * @{
- */
-#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
-
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Active_FrameLength
- * @{
- */
-#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))
-
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_FS_Definition
- * @{
- */
-
-#define SAI_FS_StartFrame ((uint32_t)0x00000000)
-#define I2S_FS_ChannelIdentification ((uint32_t)SAI_xFRCR_FSDEF)
-#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_StartFrame) || \
- ((DEFINITION) == I2S_FS_ChannelIdentification))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_FS_Polarity
- * @{
- */
-
-#define SAI_FS_ActiveLow ((uint32_t)0x00000000)
-#define SAI_FS_ActiveHigh ((uint32_t)SAI_xFRCR_FSPO)
-#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ActiveLow) || \
- ((POLARITY) == SAI_FS_ActiveHigh))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_FS_Offset
- * @{
- */
-
-#define SAI_FS_FirstBit ((uint32_t)0x00000000)
-#define SAI_FS_BeforeFirstBit ((uint32_t)SAI_xFRCR_FSOFF)
-#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FirstBit) || \
- ((OFFSET) == SAI_FS_BeforeFirstBit))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Slot_FirstBit_Offset
- * @{
- */
-#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
-
-/**
- * @}
- */
-
- /** @defgroup SAI_Block_Slot_Size
- * @{
- */
-#define SAI_SlotSize_DataSize ((uint32_t)0x00000000)
-#define SAI_SlotSize_16b ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
-#define SAI_SlotSize_32b ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
-#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SlotSize_DataSize) || \
- ((SIZE) == SAI_SlotSize_16b) || \
- ((SIZE) == SAI_SlotSize_32b))
-
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Slot_Number
- * @{
- */
-#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
-
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Slot_Active
- * @{
- */
-#define SAI_Slot_NotActive ((uint32_t)0x00000000)
-#define SAI_SlotActive_0 ((uint32_t)0x00010000)
-#define SAI_SlotActive_1 ((uint32_t)0x00020000)
-#define SAI_SlotActive_2 ((uint32_t)0x00040000)
-#define SAI_SlotActive_3 ((uint32_t)0x00080000)
-#define SAI_SlotActive_4 ((uint32_t)0x00100000)
-#define SAI_SlotActive_5 ((uint32_t)0x00200000)
-#define SAI_SlotActive_6 ((uint32_t)0x00400000)
-#define SAI_SlotActive_7 ((uint32_t)0x00800000)
-#define SAI_SlotActive_8 ((uint32_t)0x01000000)
-#define SAI_SlotActive_9 ((uint32_t)0x02000000)
-#define SAI_SlotActive_10 ((uint32_t)0x04000000)
-#define SAI_SlotActive_11 ((uint32_t)0x08000000)
-#define SAI_SlotActive_12 ((uint32_t)0x10000000)
-#define SAI_SlotActive_13 ((uint32_t)0x20000000)
-#define SAI_SlotActive_14 ((uint32_t)0x40000000)
-#define SAI_SlotActive_15 ((uint32_t)0x80000000)
-#define SAI_SlotActive_ALL ((uint32_t)0xFFFF0000)
-
-#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) != 0)
-
-/**
- * @}
- */
-
-/** @defgroup SAI_Mono_Streo_Mode
- * @{
- */
-
-#define SAI_MonoMode ((uint32_t)SAI_xCR1_MONO)
-#define SAI_StreoMode ((uint32_t)0x00000000)
-#define IS_SAI_BLOCK_MONO_STREO_MODE(MODE) (((MODE) == SAI_MonoMode) ||\
- ((MODE) == SAI_StreoMode))
-/**
- * @}
- */
-
-/** @defgroup SAI_TRIState_Management
- * @{
- */
-
-#define SAI_Output_NotReleased ((uint32_t)0x00000000)
-#define SAI_Output_Released ((uint32_t)SAI_xCR2_TRIS)
-#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_Output_NotReleased) ||\
- ((STATE) == SAI_Output_Released))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Fifo_Threshold
- * @{
- */
-
-#define SAI_Threshold_FIFOEmpty ((uint32_t)0x00000000)
-#define SAI_FIFOThreshold_1QuarterFull ((uint32_t)0x00000001)
-#define SAI_FIFOThreshold_HalfFull ((uint32_t)0x00000002)
-#define SAI_FIFOThreshold_3QuartersFull ((uint32_t)0x00000003)
-#define SAI_FIFOThreshold_Full ((uint32_t)0x00000004)
-#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_Threshold_FIFOEmpty) || \
- ((THRESHOLD) == SAI_FIFOThreshold_1QuarterFull) || \
- ((THRESHOLD) == SAI_FIFOThreshold_HalfFull) || \
- ((THRESHOLD) == SAI_FIFOThreshold_3QuartersFull) || \
- ((THRESHOLD) == SAI_FIFOThreshold_Full))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Companding_Mode
- * @{
- */
-
-#define SAI_NoCompanding ((uint32_t)0x00000000)
-#define SAI_ULaw_1CPL_Companding ((uint32_t)0x00008000)
-#define SAI_ALaw_1CPL_Companding ((uint32_t)0x0000C000)
-#define SAI_ULaw_2CPL_Companding ((uint32_t)0x0000A000)
-#define SAI_ALaw_2CPL_Companding ((uint32_t)0x0000E000)
-#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NoCompanding) || \
- ((MODE) == SAI_ULaw_1CPL_Companding) || \
- ((MODE) == SAI_ALaw_1CPL_Companding) || \
- ((MODE) == SAI_ULaw_2CPL_Companding) || \
- ((MODE) == SAI_ALaw_2CPL_Companding))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Mute_Value
- * @{
- */
-
-#define SAI_ZeroValue ((uint32_t)0x00000000)
-#define SAI_LastSentValue ((uint32_t)SAI_xCR2_MUTEVAL)
-#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZeroValue) || \
- ((VALUE) == SAI_LastSentValue))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Mute_Frame_Counter
- * @{
- */
-
-#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
-
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Interrupts_Definition
- * @{
- */
-
-#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)
-#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE)
-#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE)
-#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE)
-#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE)
-#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)
-#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)
-
-#define IS_SAI_BLOCK_CONFIG_IT(IT) (((IT) == SAI_IT_OVRUDR) || \
- ((IT) == SAI_IT_MUTEDET) || \
- ((IT) == SAI_IT_WCKCFG) || \
- ((IT) == SAI_IT_FREQ) || \
- ((IT) == SAI_IT_CNRDY) || \
- ((IT) == SAI_IT_AFSDET) || \
- ((IT) == SAI_IT_LFSDET))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Flags_Definition
- * @{
- */
-
-#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)
-#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET)
-#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG)
-#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ)
-#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY)
-#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)
-#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)
-
-#define IS_SAI_BLOCK_GET_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \
- ((FLAG) == SAI_FLAG_MUTEDET) || \
- ((FLAG) == SAI_FLAG_WCKCFG) || \
- ((FLAG) == SAI_FLAG_FREQ) || \
- ((FLAG) == SAI_FLAG_CNRDY) || \
- ((FLAG) == SAI_FLAG_AFSDET) || \
- ((FLAG) == SAI_FLAG_LFSDET))
-
-#define IS_SAI_BLOCK_CLEAR_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \
- ((FLAG) == SAI_FLAG_MUTEDET) || \
- ((FLAG) == SAI_FLAG_WCKCFG) || \
- ((FLAG) == SAI_FLAG_FREQ) || \
- ((FLAG) == SAI_FLAG_CNRDY) || \
- ((FLAG) == SAI_FLAG_AFSDET) || \
- ((FLAG) == SAI_FLAG_LFSDET))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Fifo_Status_Level
- * @{
- */
-#define SAI_FIFOStatus_Empty ((uint32_t)0x00000000)
-#define SAI_FIFOStatus_Less1QuarterFull ((uint32_t)0x00010000)
-#define SAI_FIFOStatus_1QuarterFull ((uint32_t)0x00020000)
-#define SAI_FIFOStatus_HalfFull ((uint32_t)0x00030000)
-#define SAI_FIFOStatus_3QuartersFull ((uint32_t)0x00040000)
-#define SAI_FIFOStatus_Full ((uint32_t)0x00050000)
-
-#define IS_SAI_BLOCK_FIFO_STATUS(STATUS) (((STATUS) == SAI_FIFOStatus_Less1QuarterFull ) || \
- ((STATUS) == SAI_FIFOStatus_HalfFull) || \
- ((STATUS) == SAI_FIFOStatus_1QuarterFull) || \
- ((STATUS) == SAI_FIFOStatus_3QuartersFull) || \
- ((STATUS) == SAI_FIFOStatus_Full) || \
- ((STATUS) == SAI_FIFOStatus_Empty))
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the SAI configuration to the default reset state *****/
-void SAI_DeInit(SAI_TypeDef* SAIx);
-
-/* Initialization and Configuration functions *********************************/
-void SAI_Init(SAI_Block_TypeDef* SAI_Block_x, SAI_InitTypeDef* SAI_InitStruct);
-void SAI_FrameInit(SAI_Block_TypeDef* SAI_Block_x, SAI_FrameInitTypeDef* SAI_FrameInitStruct);
-void SAI_SlotInit(SAI_Block_TypeDef* SAI_Block_x, SAI_SlotInitTypeDef* SAI_SlotInitStruct);
-void SAI_StructInit(SAI_InitTypeDef* SAI_InitStruct);
-void SAI_FrameStructInit(SAI_FrameInitTypeDef* SAI_FrameInitStruct);
-void SAI_SlotStructInit(SAI_SlotInitTypeDef* SAI_SlotInitStruct);
-
-void SAI_Cmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState);
-void SAI_MonoModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_Mono_StreoMode);
-void SAI_TRIStateConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_TRIState);
-void SAI_CompandingModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_CompandingMode);
-void SAI_MuteModeCmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState);
-void SAI_MuteValueConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteValue);
-void SAI_MuteFrameCounterConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteCounter);
-void SAI_FlushFIFO(SAI_Block_TypeDef* SAI_Block_x);
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F469_479xx) || defined(STM32F413_423xx) || defined(STM32F446xx)
-void SAI_BlockSynchroConfig(SAI_InitTypeDef* SAI_InitStruct, SAI_TypeDef* SAIx);
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469_479xx || STM32F413_423xx || STM32F446xx */
-/* Data transfers functions ***************************************************/
-void SAI_SendData(SAI_Block_TypeDef* SAI_Block_x, uint32_t Data);
-uint32_t SAI_ReceiveData(SAI_Block_TypeDef* SAI_Block_x);
-
-/* DMA transfers management functions *****************************************/
-void SAI_DMACmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void SAI_ITConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState);
-FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG);
-void SAI_ClearFlag(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG);
-ITStatus SAI_GetITStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT);
-void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT);
-FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x);
-uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x);
-
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx || STM32F469_479xx */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_SAI_H */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_sdio.c b/底盘/底盘-old/底盘/Library/stm32f4xx_sdio.c
deleted file mode 100644
index 483cadb..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_sdio.c
+++ /dev/null
@@ -1,1003 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_sdio.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Secure digital input/output interface (SDIO)
- * peripheral:
- * + Initialization and Configuration
- * + Command path state machine (CPSM) management
- * + Data path state machine (DPSM) management
- * + SDIO IO Cards mode management
- * + CE-ATA mode management
- * + DMA transfers management
- * + Interrupts and flags management
- *
-@verbatim
-
- ===================================================================
- ##### How to use this driver #####
- ===================================================================
- [..]
- (#) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL
- (PLL48CLK). Before to start working with SDIO peripheral make sure that the
- PLL is well configured.
- The SDIO peripheral uses two clock signals:
- (++) SDIO adapter clock (SDIOCLK = 48 MHz)
- (++) APB2 bus clock (PCLK2)
-
- -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition:
- Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK))
-
- (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE).
-
- (#) According to the SDIO mode, enable the GPIO clocks using
- RCC_AHB1PeriphClockCmd() function.
- The I/O can be one of the following configurations:
- (++) 1-bit data length: SDIO_CMD, SDIO_CK and D0.
- (++) 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0].
- (++) 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0].
-
- (#) Peripheral alternate function:
- (++) Connect the pin to the desired peripherals' Alternate Function (AF)
- using GPIO_PinAFConfig() function
- (++) Configure the desired pin in alternate function by:
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd,
- GPIO_OType and GPIO_Speed members
- (++) Call GPIO_Init() function
-
- (#) Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide,
- hardware, flow control and the Clock Divider using the SDIO_Init()
- function.
-
- (#) Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON)
- function.
-
- (#) Enable the clock using the SDIO_ClockCmd() function.
-
- (#) Enable the NVIC and the corresponding interrupt using the function
- SDIO_ITConfig() if you need to use interrupt mode.
-
- (#) When using the DMA mode
- (++) Configure the DMA using DMA_Init() function
- (++) Active the needed channel Request using SDIO_DMACmd() function
-
- (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.
-
- (#) To control the CPSM (Command Path State Machine) and send
- commands to the card use the SDIO_SendCommand(),
- SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has
- to fill the command structure (pointer to SDIO_CmdInitTypeDef) according
- to the selected command to be sent.
- The parameters that should be filled are:
- (++) Command Argument
- (++) Command Index
- (++) Command Response type
- (++) Command Wait
- (++) CPSM Status (Enable or Disable).
-
- -@@- To check if the command is well received, read the SDIO_CMDRESP
- register using the SDIO_GetCommandResponse().
- The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the
- SDIO_GetResponse() function.
-
- (#) To control the DPSM (Data Path State Machine) and send/receive
- data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(),
- SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions.
-
- *** Read Operations ***
- =======================
- [..]
- (#) First, user has to fill the data structure (pointer to
- SDIO_DataInitTypeDef) according to the selected data type to be received.
- The parameters that should be filled are:
- (++) Data TimeOut
- (++) Data Length
- (++) Data Block size
- (++) Data Transfer direction: should be from card (To SDIO)
- (++) Data Transfer mode
- (++) DPSM Status (Enable or Disable)
-
- (#) Configure the SDIO resources to receive the data from the card
- according to selected transfer mode (Refer to Step 8, 9 and 10).
-
- (#) Send the selected Read command (refer to step 11).
-
- (#) Use the SDIO flags/interrupts to check the transfer status.
-
- *** Write Operations ***
- ========================
- [..]
- (#) First, user has to fill the data structure (pointer to
- SDIO_DataInitTypeDef) according to the selected data type to be received.
- The parameters that should be filled are:
- (++) Data TimeOut
- (++) Data Length
- (++) Data Block size
- (++) Data Transfer direction: should be to card (To CARD)
- (++) Data Transfer mode
- (++) DPSM Status (Enable or Disable)
-
- (#) Configure the SDIO resources to send the data to the card according to
- selected transfer mode (Refer to Step 8, 9 and 10).
-
- (#) Send the selected Write command (refer to step 11).
-
- (#) Use the SDIO flags/interrupts to check the transfer status.
-
-
-@endverbatim
- *
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_sdio.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SDIO
- * @brief SDIO driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ------------ SDIO registers bit address in the alias region ----------- */
-#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
-
-/* --- CLKCR Register ---*/
-/* Alias word address of CLKEN bit */
-#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
-#define CLKEN_BitNumber 0x08
-#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
-
-/* --- CMD Register ---*/
-/* Alias word address of SDIOSUSPEND bit */
-#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
-#define SDIOSUSPEND_BitNumber 0x0B
-#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
-
-/* Alias word address of ENCMDCOMPL bit */
-#define ENCMDCOMPL_BitNumber 0x0C
-#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
-
-/* Alias word address of NIEN bit */
-#define NIEN_BitNumber 0x0D
-#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
-
-/* Alias word address of ATACMD bit */
-#define ATACMD_BitNumber 0x0E
-#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
-
-/* --- DCTRL Register ---*/
-/* Alias word address of DMAEN bit */
-#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
-#define DMAEN_BitNumber 0x03
-#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
-
-/* Alias word address of RWSTART bit */
-#define RWSTART_BitNumber 0x08
-#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
-
-/* Alias word address of RWSTOP bit */
-#define RWSTOP_BitNumber 0x09
-#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
-
-/* Alias word address of RWMOD bit */
-#define RWMOD_BitNumber 0x0A
-#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
-
-/* Alias word address of SDIOEN bit */
-#define SDIOEN_BitNumber 0x0B
-#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
-
-/* ---------------------- SDIO registers bit mask ------------------------ */
-/* --- CLKCR Register ---*/
-/* CLKCR register clear mask */
-#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
-
-/* --- PWRCTRL Register ---*/
-/* SDIO PWRCTRL Mask */
-#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
-
-/* --- DCTRL Register ---*/
-/* SDIO DCTRL Clear Mask */
-#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
-
-/* --- CMD Register ---*/
-/* CMD Register clear mask */
-#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
-
-/* SDIO RESP Registers Address */
-#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SDIO_Private_Functions
- * @{
- */
-
-/** @defgroup SDIO_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the SDIO peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void SDIO_DeInit(void)
-{
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE);
-}
-
-/**
- * @brief Initializes the SDIO peripheral according to the specified
- * parameters in the SDIO_InitStruct.
- * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
- * that contains the configuration information for the SDIO peripheral.
- * @retval None
- */
-void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
- assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
- assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
- assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
- assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
-
-/*---------------------------- SDIO CLKCR Configuration ------------------------*/
- /* Get the SDIO CLKCR value */
- tmpreg = SDIO->CLKCR;
-
- /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
- tmpreg &= CLKCR_CLEAR_MASK;
-
- /* Set CLKDIV bits according to SDIO_ClockDiv value */
- /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
- /* Set BYPASS bit according to SDIO_ClockBypass value */
- /* Set WIDBUS bits according to SDIO_BusWide value */
- /* Set NEGEDGE bits according to SDIO_ClockEdge value */
- /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
- tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
- SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
- SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
-
- /* Write to SDIO CLKCR */
- SDIO->CLKCR = tmpreg;
-}
-
-/**
- * @brief Fills each SDIO_InitStruct member with its default value.
- * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
-{
- /* SDIO_InitStruct members default value */
- SDIO_InitStruct->SDIO_ClockDiv = 0x00;
- SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
- SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
- SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
- SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
- SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
-}
-
-/**
- * @brief Enables or disables the SDIO Clock.
- * @param NewState: new state of the SDIO Clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_ClockCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Sets the power status of the controller.
- * @param SDIO_PowerState: new state of the Power state.
- * This parameter can be one of the following values:
- * @arg SDIO_PowerState_OFF: SDIO Power OFF
- * @arg SDIO_PowerState_ON: SDIO Power ON
- * @retval None
- */
-void SDIO_SetPowerState(uint32_t SDIO_PowerState)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
-
- SDIO->POWER = SDIO_PowerState;
-}
-
-/**
- * @brief Gets the power status of the controller.
- * @param None
- * @retval Power status of the controller. The returned value can be one of the
- * following values:
- * - 0x00: Power OFF
- * - 0x02: Power UP
- * - 0x03: Power ON
- */
-uint32_t SDIO_GetPowerState(void)
-{
- return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group2 Command path state machine (CPSM) management functions
- * @brief Command path state machine (CPSM) management functions
- *
-@verbatim
- ===============================================================================
- ##### Command path state machine (CPSM) management functions #####
- ===============================================================================
-
- This section provide functions allowing to program and read the Command path
- state machine (CPSM).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the SDIO Command according to the specified
- * parameters in the SDIO_CmdInitStruct and send the command.
- * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef
- * structure that contains the configuration information for the SDIO
- * command.
- * @retval None
- */
-void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
- assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
- assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
- assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
-
-/*---------------------------- SDIO ARG Configuration ------------------------*/
- /* Set the SDIO Argument value */
- SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
-
-/*---------------------------- SDIO CMD Configuration ------------------------*/
- /* Get the SDIO CMD value */
- tmpreg = SDIO->CMD;
- /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
- tmpreg &= CMD_CLEAR_MASK;
- /* Set CMDINDEX bits according to SDIO_CmdIndex value */
- /* Set WAITRESP bits according to SDIO_Response value */
- /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
- /* Set CPSMEN bits according to SDIO_CPSM value */
- tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
- | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
-
- /* Write to SDIO CMD */
- SDIO->CMD = tmpreg;
-}
-
-/**
- * @brief Fills each SDIO_CmdInitStruct member with its default value.
- * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
- * structure which will be initialized.
- * @retval None
- */
-void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
-{
- /* SDIO_CmdInitStruct members default value */
- SDIO_CmdInitStruct->SDIO_Argument = 0x00;
- SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
- SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
- SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
- SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
-}
-
-/**
- * @brief Returns command index of last command for which response received.
- * @param None
- * @retval Returns the command index of the last command response received.
- */
-uint8_t SDIO_GetCommandResponse(void)
-{
- return (uint8_t)(SDIO->RESPCMD);
-}
-
-/**
- * @brief Returns response received from the card for the last command.
- * @param SDIO_RESP: Specifies the SDIO response register.
- * This parameter can be one of the following values:
- * @arg SDIO_RESP1: Response Register 1
- * @arg SDIO_RESP2: Response Register 2
- * @arg SDIO_RESP3: Response Register 3
- * @arg SDIO_RESP4: Response Register 4
- * @retval The Corresponding response register value.
- */
-uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_RESP(SDIO_RESP));
-
- tmp = SDIO_RESP_ADDR + SDIO_RESP;
-
- return (*(__IO uint32_t *) tmp);
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group3 Data path state machine (DPSM) management functions
- * @brief Data path state machine (DPSM) management functions
- *
-@verbatim
- ===============================================================================
- ##### Data path state machine (DPSM) management functions #####
- ===============================================================================
-
- This section provide functions allowing to program and read the Data path
- state machine (DPSM).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the SDIO data path according to the specified
- * parameters in the SDIO_DataInitStruct.
- * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure
- * that contains the configuration information for the SDIO command.
- * @retval None
- */
-void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
- assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
- assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
- assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
- assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
-
-/*---------------------------- SDIO DTIMER Configuration ---------------------*/
- /* Set the SDIO Data TimeOut value */
- SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
-
-/*---------------------------- SDIO DLEN Configuration -----------------------*/
- /* Set the SDIO DataLength value */
- SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
-
-/*---------------------------- SDIO DCTRL Configuration ----------------------*/
- /* Get the SDIO DCTRL value */
- tmpreg = SDIO->DCTRL;
- /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
- tmpreg &= DCTRL_CLEAR_MASK;
- /* Set DEN bit according to SDIO_DPSM value */
- /* Set DTMODE bit according to SDIO_TransferMode value */
- /* Set DTDIR bit according to SDIO_TransferDir value */
- /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
- tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
- | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
-
- /* Write to SDIO DCTRL */
- SDIO->DCTRL = tmpreg;
-}
-
-/**
- * @brief Fills each SDIO_DataInitStruct member with its default value.
- * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
-{
- /* SDIO_DataInitStruct members default value */
- SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
- SDIO_DataInitStruct->SDIO_DataLength = 0x00;
- SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
- SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
- SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
- SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
-}
-
-/**
- * @brief Returns number of remaining data bytes to be transferred.
- * @param None
- * @retval Number of remaining data bytes to be transferred
- */
-uint32_t SDIO_GetDataCounter(void)
-{
- return SDIO->DCOUNT;
-}
-
-/**
- * @brief Read one data word from Rx FIFO.
- * @param None
- * @retval Data received
- */
-uint32_t SDIO_ReadData(void)
-{
- return SDIO->FIFO;
-}
-
-/**
- * @brief Write one data word to Tx FIFO.
- * @param Data: 32-bit data word to write.
- * @retval None
- */
-void SDIO_WriteData(uint32_t Data)
-{
- SDIO->FIFO = Data;
-}
-
-/**
- * @brief Returns the number of words left to be written to or read from FIFO.
- * @param None
- * @retval Remaining number of words.
- */
-uint32_t SDIO_GetFIFOCount(void)
-{
- return SDIO->FIFOCNT;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group4 SDIO IO Cards mode management functions
- * @brief SDIO IO Cards mode management functions
- *
-@verbatim
- ===============================================================================
- ##### SDIO IO Cards mode management functions #####
- ===============================================================================
-
- This section provide functions allowing to program and read the SDIO IO Cards.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the SD I/O Read Wait operation.
- * @param NewState: new state of the Start SDIO Read Wait operation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_StartSDIOReadWait(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
-}
-
-/**
- * @brief Stops the SD I/O Read Wait operation.
- * @param NewState: new state of the Stop SDIO Read Wait operation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_StopSDIOReadWait(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
-}
-
-/**
- * @brief Sets one of the two options of inserting read wait interval.
- * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
- * This parameter can be:
- * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
- * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
- * @retval None
- */
-void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
-
- *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
-}
-
-/**
- * @brief Enables or disables the SD I/O Mode Operation.
- * @param NewState: new state of SDIO specific operation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_SetSDIOOperation(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the SD I/O Mode suspend command sending.
- * @param NewState: new state of the SD I/O Mode suspend command.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group5 CE-ATA mode management functions
- * @brief CE-ATA mode management functions
- *
-@verbatim
- ===============================================================================
- ##### CE-ATA mode management functions #####
- ===============================================================================
-
- This section provide functions allowing to program and read the CE-ATA card.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the command completion signal.
- * @param NewState: new state of command completion signal.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_CommandCompletionCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the CE-ATA interrupt.
- * @param NewState: new state of CE-ATA interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_CEATAITCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
-}
-
-/**
- * @brief Sends CE-ATA command (CMD61).
- * @param NewState: new state of CE-ATA command.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_SendCEATACmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group6 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
-
- This section provide functions allowing to program SDIO DMA transfer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the SDIO DMA request.
- * @param NewState: new state of the selected SDIO DMA request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_DMACmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group7 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the SDIO interrupts.
- * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
- * @param NewState: new state of the specified SDIO interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_IT(SDIO_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the SDIO interrupts */
- SDIO->MASK |= SDIO_IT;
- }
- else
- {
- /* Disable the SDIO interrupts */
- SDIO->MASK &= ~SDIO_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified SDIO flag is set or not.
- * @param SDIO_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
- * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_CMDACT: Command transfer in progress
- * @arg SDIO_FLAG_TXACT: Data transmit in progress
- * @arg SDIO_FLAG_RXACT: Data receive in progress
- * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
- * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
- * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
- * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
- * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
- * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
- * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
- * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
- * @retval The new state of SDIO_FLAG (SET or RESET).
- */
-FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_SDIO_FLAG(SDIO_FLAG));
-
- if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the SDIO's pending flags.
- * @param SDIO_FLAG: specifies the flag to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
- * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
- * @retval None
- */
-void SDIO_ClearFlag(uint32_t SDIO_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
-
- SDIO->ICR = SDIO_FLAG;
-}
-
-/**
- * @brief Checks whether the specified SDIO interrupt has occurred or not.
- * @param SDIO_IT: specifies the SDIO interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
- * @retval The new state of SDIO_IT (SET or RESET).
- */
-ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_SDIO_GET_IT(SDIO_IT));
- if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the SDIO's interrupt pending bits.
- * @param SDIO_IT: specifies the interrupt pending bit to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
- * @retval None
- */
-void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
-
- SDIO->ICR = SDIO_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_sdio.h b/底盘/底盘-old/底盘/Library/stm32f4xx_sdio.h
deleted file mode 100644
index d63e6ac..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_sdio.h
+++ /dev/null
@@ -1,528 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_sdio.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the SDIO firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_SDIO_H
-#define __STM32F4xx_SDIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup SDIO
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-typedef struct
-{
- uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref SDIO_Clock_Edge */
-
- uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
- enabled or disabled.
- This parameter can be a value of @ref SDIO_Clock_Bypass */
-
- uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
- disabled when the bus is idle.
- This parameter can be a value of @ref SDIO_Clock_Power_Save */
-
- uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.
- This parameter can be a value of @ref SDIO_Bus_Wide */
-
- uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
- This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
-
- uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
- This parameter can be a value between 0x00 and 0xFF. */
-
-} SDIO_InitTypeDef;
-
-typedef struct
-{
- uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent
- to a card as part of a command message. If a command
- contains an argument, it must be loaded into this register
- before writing the command to the command register */
-
- uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */
-
- uint32_t SDIO_Response; /*!< Specifies the SDIO response type.
- This parameter can be a value of @ref SDIO_Response_Type */
-
- uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait for interrupt request is enabled or disabled.
- This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
-
- uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
- is enabled or disabled.
- This parameter can be a value of @ref SDIO_CPSM_State */
-} SDIO_CmdInitTypeDef;
-
-typedef struct
-{
- uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
-
- uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */
-
- uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.
- This parameter can be a value of @ref SDIO_Data_Block_Size */
-
- uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer
- is a read or write.
- This parameter can be a value of @ref SDIO_Transfer_Direction */
-
- uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
- This parameter can be a value of @ref SDIO_Transfer_Type */
-
- uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
- is enabled or disabled.
- This parameter can be a value of @ref SDIO_DPSM_State */
-} SDIO_DataInitTypeDef;
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SDIO_Exported_Constants
- * @{
- */
-
-/** @defgroup SDIO_Clock_Edge
- * @{
- */
-
-#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
-#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
-#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
- ((EDGE) == SDIO_ClockEdge_Falling))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Clock_Bypass
- * @{
- */
-
-#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
-#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
-#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
- ((BYPASS) == SDIO_ClockBypass_Enable))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Clock_Power_Save
- * @{
- */
-
-#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
-#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
-#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
- ((SAVE) == SDIO_ClockPowerSave_Enable))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Bus_Wide
- * @{
- */
-
-#define SDIO_BusWide_1b ((uint32_t)0x00000000)
-#define SDIO_BusWide_4b ((uint32_t)0x00000800)
-#define SDIO_BusWide_8b ((uint32_t)0x00001000)
-#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
- ((WIDE) == SDIO_BusWide_8b))
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Hardware_Flow_Control
- * @{
- */
-
-#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
-#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
-#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
- ((CONTROL) == SDIO_HardwareFlowControl_Enable))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Power_State
- * @{
- */
-
-#define SDIO_PowerState_OFF ((uint32_t)0x00000000)
-#define SDIO_PowerState_ON ((uint32_t)0x00000003)
-#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
-/**
- * @}
- */
-
-
-/** @defgroup SDIO_Interrupt_sources
- * @{
- */
-
-#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
-#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
-#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
-#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
-#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
-#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
-#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
-#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
-#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
-#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
-#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
-#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
-#define SDIO_IT_TXACT ((uint32_t)0x00001000)
-#define SDIO_IT_RXACT ((uint32_t)0x00002000)
-#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
-#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
-#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
-#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
-#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
-#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
-#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
-#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
-#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
-#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
-#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Command_Index
- * @{
- */
-
-#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
-/**
- * @}
- */
-
-/** @defgroup SDIO_Response_Type
- * @{
- */
-
-#define SDIO_Response_No ((uint32_t)0x00000000)
-#define SDIO_Response_Short ((uint32_t)0x00000040)
-#define SDIO_Response_Long ((uint32_t)0x000000C0)
-#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
- ((RESPONSE) == SDIO_Response_Short) || \
- ((RESPONSE) == SDIO_Response_Long))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Wait_Interrupt_State
- * @{
- */
-
-#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
-#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
-#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
-#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
- ((WAIT) == SDIO_Wait_Pend))
-/**
- * @}
- */
-
-/** @defgroup SDIO_CPSM_State
- * @{
- */
-
-#define SDIO_CPSM_Disable ((uint32_t)0x00000000)
-#define SDIO_CPSM_Enable ((uint32_t)0x00000400)
-#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Response_Registers
- * @{
- */
-
-#define SDIO_RESP1 ((uint32_t)0x00000000)
-#define SDIO_RESP2 ((uint32_t)0x00000004)
-#define SDIO_RESP3 ((uint32_t)0x00000008)
-#define SDIO_RESP4 ((uint32_t)0x0000000C)
-#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
- ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Data_Length
- * @{
- */
-
-#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
-/**
- * @}
- */
-
-/** @defgroup SDIO_Data_Block_Size
- * @{
- */
-
-#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
-#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
-#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
-#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
-#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
-#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
-#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
-#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
-#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
-#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
-#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
-#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
-#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
-#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
-#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
-#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
- ((SIZE) == SDIO_DataBlockSize_2b) || \
- ((SIZE) == SDIO_DataBlockSize_4b) || \
- ((SIZE) == SDIO_DataBlockSize_8b) || \
- ((SIZE) == SDIO_DataBlockSize_16b) || \
- ((SIZE) == SDIO_DataBlockSize_32b) || \
- ((SIZE) == SDIO_DataBlockSize_64b) || \
- ((SIZE) == SDIO_DataBlockSize_128b) || \
- ((SIZE) == SDIO_DataBlockSize_256b) || \
- ((SIZE) == SDIO_DataBlockSize_512b) || \
- ((SIZE) == SDIO_DataBlockSize_1024b) || \
- ((SIZE) == SDIO_DataBlockSize_2048b) || \
- ((SIZE) == SDIO_DataBlockSize_4096b) || \
- ((SIZE) == SDIO_DataBlockSize_8192b) || \
- ((SIZE) == SDIO_DataBlockSize_16384b))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Transfer_Direction
- * @{
- */
-
-#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
-#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
-#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
- ((DIR) == SDIO_TransferDir_ToSDIO))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Transfer_Type
- * @{
- */
-
-#define SDIO_TransferMode_Block ((uint32_t)0x00000000)
-#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
-#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
- ((MODE) == SDIO_TransferMode_Block))
-/**
- * @}
- */
-
-/** @defgroup SDIO_DPSM_State
- * @{
- */
-
-#define SDIO_DPSM_Disable ((uint32_t)0x00000000)
-#define SDIO_DPSM_Enable ((uint32_t)0x00000001)
-#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
-/**
- * @}
- */
-
-/** @defgroup SDIO_Flags
- * @{
- */
-
-#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
-#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
-#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
-#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
-#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
-#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
-#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
-#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
-#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
-#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
-#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
-#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
-#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
-#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
-#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
-#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
-#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
-#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
-#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
-#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
-#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
-#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
-#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
-#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
-#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
- ((FLAG) == SDIO_FLAG_DCRCFAIL) || \
- ((FLAG) == SDIO_FLAG_CTIMEOUT) || \
- ((FLAG) == SDIO_FLAG_DTIMEOUT) || \
- ((FLAG) == SDIO_FLAG_TXUNDERR) || \
- ((FLAG) == SDIO_FLAG_RXOVERR) || \
- ((FLAG) == SDIO_FLAG_CMDREND) || \
- ((FLAG) == SDIO_FLAG_CMDSENT) || \
- ((FLAG) == SDIO_FLAG_DATAEND) || \
- ((FLAG) == SDIO_FLAG_STBITERR) || \
- ((FLAG) == SDIO_FLAG_DBCKEND) || \
- ((FLAG) == SDIO_FLAG_CMDACT) || \
- ((FLAG) == SDIO_FLAG_TXACT) || \
- ((FLAG) == SDIO_FLAG_RXACT) || \
- ((FLAG) == SDIO_FLAG_TXFIFOHE) || \
- ((FLAG) == SDIO_FLAG_RXFIFOHF) || \
- ((FLAG) == SDIO_FLAG_TXFIFOF) || \
- ((FLAG) == SDIO_FLAG_RXFIFOF) || \
- ((FLAG) == SDIO_FLAG_TXFIFOE) || \
- ((FLAG) == SDIO_FLAG_RXFIFOE) || \
- ((FLAG) == SDIO_FLAG_TXDAVL) || \
- ((FLAG) == SDIO_FLAG_RXDAVL) || \
- ((FLAG) == SDIO_FLAG_SDIOIT) || \
- ((FLAG) == SDIO_FLAG_CEATAEND))
-
-#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
-
-#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
- ((IT) == SDIO_IT_DCRCFAIL) || \
- ((IT) == SDIO_IT_CTIMEOUT) || \
- ((IT) == SDIO_IT_DTIMEOUT) || \
- ((IT) == SDIO_IT_TXUNDERR) || \
- ((IT) == SDIO_IT_RXOVERR) || \
- ((IT) == SDIO_IT_CMDREND) || \
- ((IT) == SDIO_IT_CMDSENT) || \
- ((IT) == SDIO_IT_DATAEND) || \
- ((IT) == SDIO_IT_STBITERR) || \
- ((IT) == SDIO_IT_DBCKEND) || \
- ((IT) == SDIO_IT_CMDACT) || \
- ((IT) == SDIO_IT_TXACT) || \
- ((IT) == SDIO_IT_RXACT) || \
- ((IT) == SDIO_IT_TXFIFOHE) || \
- ((IT) == SDIO_IT_RXFIFOHF) || \
- ((IT) == SDIO_IT_TXFIFOF) || \
- ((IT) == SDIO_IT_RXFIFOF) || \
- ((IT) == SDIO_IT_TXFIFOE) || \
- ((IT) == SDIO_IT_RXFIFOE) || \
- ((IT) == SDIO_IT_TXDAVL) || \
- ((IT) == SDIO_IT_RXDAVL) || \
- ((IT) == SDIO_IT_SDIOIT) || \
- ((IT) == SDIO_IT_CEATAEND))
-
-#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Read_Wait_Mode
- * @{
- */
-
-#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)
-#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
-#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
- ((MODE) == SDIO_ReadWaitMode_DATA2))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/* Function used to set the SDIO configuration to the default reset state ****/
-void SDIO_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
-void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
-void SDIO_ClockCmd(FunctionalState NewState);
-void SDIO_SetPowerState(uint32_t SDIO_PowerState);
-uint32_t SDIO_GetPowerState(void);
-
-/* Command path state machine (CPSM) management functions *********************/
-void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
-void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
-uint8_t SDIO_GetCommandResponse(void);
-uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
-
-/* Data path state machine (DPSM) management functions ************************/
-void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
-void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
-uint32_t SDIO_GetDataCounter(void);
-uint32_t SDIO_ReadData(void);
-void SDIO_WriteData(uint32_t Data);
-uint32_t SDIO_GetFIFOCount(void);
-
-/* SDIO IO Cards mode management functions ************************************/
-void SDIO_StartSDIOReadWait(FunctionalState NewState);
-void SDIO_StopSDIOReadWait(FunctionalState NewState);
-void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
-void SDIO_SetSDIOOperation(FunctionalState NewState);
-void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
-
-/* CE-ATA mode management functions *******************************************/
-void SDIO_CommandCompletionCmd(FunctionalState NewState);
-void SDIO_CEATAITCmd(FunctionalState NewState);
-void SDIO_SendCEATACmd(FunctionalState NewState);
-
-/* DMA transfers management functions *****************************************/
-void SDIO_DMACmd(FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
-FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
-void SDIO_ClearFlag(uint32_t SDIO_FLAG);
-ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
-void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_SDIO_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_spdifrx.c b/底盘/底盘-old/底盘/Library/stm32f4xx_spdifrx.c
deleted file mode 100644
index 658701d..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_spdifrx.c
+++ /dev/null
@@ -1,486 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_spdifrx.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Serial Audio Interface (SPDIFRX):
- * + Initialization and Configuration
- * + Data transfers functions
- * + DMA transfers management
- * + Interrupts and flags management
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_spdifrx.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SPDIFRX
- * @brief SPDIFRX driver modules
- * @{
- */
-#if defined(STM32F446xx)
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define CR_CLEAR_MASK 0x000000FE7
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SPDIFRX_Private_Functions
- * @{
- */
-
-/** @defgroup SPDIFRX_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This section provides a set of functions allowing to initialize the SPDIFRX Audio
-
- Block Mode, Audio Protocol, Data size, Synchronization between audio block,
- Master clock Divider, FIFO threshold, Frame configuration, slot configuration,
- Tristate mode, Companding mode and Mute mode.
- [..]
- The SPDIFRX_Init(), SPDIFRX_FrameInit() and SPDIFRX_SlotInit() functions follows the SPDIFRX Block
- configuration procedures for Master mode and Slave mode (details for these procedures
- are available in reference manual(RMxxxx).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitialize the SPDIFRXx peripheral registers to their default reset values.
- * @param void
- * @retval None
- */
-void SPDIFRX_DeInit(void)
-{
- /* Enable SPDIFRX reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPDIFRX, ENABLE);
- /* Release SPDIFRX from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPDIFRX, DISABLE);
-}
-
-/**
- * @brief Initializes the SPDIFRX peripheral according to the specified
- * parameters in the SPDIFRX_InitStruct.
- *
- * @note SPDIFRX clock is generated from a specific output of the PLLSPDIFRX or a specific
- * output of the PLLI2S or from an alternate function bypassing the PLL I2S.
- *
- * @param SPDIFRX_InitStruct: pointer to a SPDIFRX_InitTypeDef structure that
- * contains the configuration information for the specified SPDIFRX Block peripheral.
- * @retval None
- */
-void SPDIFRX_Init(SPDIFRX_InitTypeDef* SPDIFRX_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the SPDIFRX parameters */
- assert_param(IS_STEREO_MODE(SPDIFRX_InitStruct->SPDIFRX_StereoMode));
- assert_param(IS_SPDIFRX_INPUT_SELECT(SPDIFRX_InitStruct->SPDIFRX_InputSelection));
- assert_param(IS_SPDIFRX_MAX_RETRIES(SPDIFRX_InitStruct->SPDIFRX_Retries));
- assert_param(IS_SPDIFRX_WAIT_FOR_ACTIVITY(SPDIFRX_InitStruct->SPDIFRX_WaitForActivity));
- assert_param(IS_SPDIFRX_CHANNEL(SPDIFRX_InitStruct->SPDIFRX_ChannelSelection));
- assert_param(IS_SPDIFRX_DATA_FORMAT(SPDIFRX_InitStruct->SPDIFRX_DataFormat));
-
- /* SPDIFRX CR Configuration */
- /* Get the SPDIFRX CR value */
- tmpreg = SPDIFRX->CR;
- /* Clear INSEL, WFA, NBTR, CHSEL, DRFMT and RXSTEO bits */
- tmpreg &= CR_CLEAR_MASK;
- /* Configure SPDIFRX: Input selection, Maximum allowed re-tries during synchronization phase,
- wait for activity, Channel Selection, Data samples format and stereo/mono mode */
- /* Set INSEL bits according to SPDIFRX_InputSelection value */
- /* Set WFA bit according to SPDIFRX_WaitForActivity value */
- /* Set NBTR bit according to SPDIFRX_Retries value */
- /* Set CHSEL bit according to SPDIFRX_ChannelSelection value */
- /* Set DRFMT bits according to SPDIFRX_DataFormat value */
- /* Set RXSTEO bit according to SPDIFRX_StereoMode value */
-
- tmpreg |= (uint32_t)(SPDIFRX_InitStruct->SPDIFRX_InputSelection | SPDIFRX_InitStruct->SPDIFRX_WaitForActivity |
- SPDIFRX_InitStruct->SPDIFRX_Retries | SPDIFRX_InitStruct->SPDIFRX_ChannelSelection |
- SPDIFRX_InitStruct->SPDIFRX_DataFormat | SPDIFRX_InitStruct->SPDIFRX_StereoMode
- );
-
- /* Write to SPDIFRX CR */
- SPDIFRX->CR = tmpreg;
-}
-
-/**
- * @brief Fills each SPDIFRX_InitStruct member with its default value.
- * @param SPDIFRX_InitStruct: pointer to a SPDIFRX_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void SPDIFRX_StructInit(SPDIFRX_InitTypeDef* SPDIFRX_InitStruct)
-{
- /* Reset SPDIFRX init structure parameters values */
- /* Initialize the PDIF_InputSelection member */
- SPDIFRX_InitStruct->SPDIFRX_InputSelection = SPDIFRX_Input_IN0;
- /* Initialize the SPDIFRX_WaitForActivity member */
- SPDIFRX_InitStruct->SPDIFRX_WaitForActivity = SPDIFRX_WaitForActivity_On;
- /* Initialize the SPDIFRX_Retries member */
- SPDIFRX_InitStruct->SPDIFRX_Retries = SPDIFRX_16MAX_RETRIES;
- /* Initialize the SPDIFRX_ChannelSelection member */
- SPDIFRX_InitStruct->SPDIFRX_ChannelSelection = SPDIFRX_Select_Channel_A;
- /* Initialize the SPDIFRX_DataFormat member */
- SPDIFRX_InitStruct->SPDIFRX_DataFormat = SPDIFRX_MSB_DataFormat;
- /* Initialize the SPDIFRX_StereoMode member */
- SPDIFRX_InitStruct->SPDIFRX_StereoMode = SPDIFRX_StereoMode_Enabled;
-}
-
-/**
- * @brief Enables or disables the SPDIFRX frame x bit.
- * @param NewState: new state of the selected SPDIFRX frame bit.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPDIFRX_SetPreambleTypeBit(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPDIFRX frame bit */
- SPDIFRX->CR |= SPDIFRX_CR_PTMSK;
- }
- else
- {
- /* Disable the selected SPDIFRX frame bit */
- SPDIFRX->CR &= ~(SPDIFRX_CR_PTMSK);
- }
-}
-
-/**
- * @brief Enables or disables the SPDIFRX frame x bit.
- * @param NewState: new state of the selected SPDIFRX frame bit.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPDIFRX_SetUserDataChannelStatusBits(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPDIFRX frame bit */
- SPDIFRX->CR |= SPDIFRX_CR_CUMSK;
- }
- else
- {
- /* Disable the selected SPDIFRX frame bit */
- SPDIFRX->CR &= ~(SPDIFRX_CR_CUMSK);
- }
-}
-
-/**
- * @brief Enables or disables the SPDIFRX frame x bit.
- * @param NewState: new state of the selected SPDIFRX frame bit.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPDIFRX_SetValidityBit(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPDIFRX frame bit */
- SPDIFRX->CR |= SPDIFRX_CR_VMSK;
- }
- else
- {
- /* Disable the selected SPDIFRX frame bit */
- SPDIFRX->CR &= ~(SPDIFRX_CR_VMSK);
- }
-}
-
-/**
- * @brief Enables or disables the SPDIFRX frame x bit.
- * @param NewState: new state of the selected SPDIFRX frame bit.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPDIFRX_SetParityBit(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPDIFRX frame bit */
- SPDIFRX->CR |= SPDIFRX_CR_PMSK;
- }
- else
- {
- /* Disable the selected SPDIFRX frame bit */
- SPDIFRX->CR &= ~(SPDIFRX_CR_PMSK);
- }
-}
-
-/**
- * @brief Enables or disables the SPDIFRX DMA interface (RX).
- * @param NewState: new state of the selected SPDIFRX DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPDIFRX_RxDMACmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPDIFRX DMA requests */
- SPDIFRX->CR |= SPDIFRX_CR_RXDMAEN;
- }
- else
- {
- /* Disable the selected SPDIFRX DMA requests */
- SPDIFRX->CR &= ~(SPDIFRX_CR_RXDMAEN);
- }
-}
-
-/**
- * @brief Enables or disables the SPDIFRX DMA interface (Control Buffer).
- * @param NewState: new state of the selected SPDIFRX DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPDIFRX_CbDMACmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPDIFRX DMA requests */
- SPDIFRX->CR |= SPDIFRX_CR_CBDMAEN;
- }
- else
- {
- /* Disable the selected SPDIFRX DMA requests */
- SPDIFRX->CR &= ~(SPDIFRX_CR_CBDMAEN);
- }
-}
-
-/**
- * @brief Enables or disables the SPDIFRX peripheral.
- * @param SPDIFRX_State: specifies the SPDIFRX peripheral state.
- * This parameter can be one of the following values:
- * @arg SPDIFRX_STATE_IDLE : Disable SPDIFRX-RX (STATE_IDLE)
- * @arg SPDIFRX_STATE_SYNC : Enable SPDIFRX-RX Synchronization only
- * @arg SPDIFRX_STATE_RCV : Enable SPDIFRX Receiver
- * @retval None
- */
-void SPDIFRX_Cmd(uint32_t SPDIFRX_State)
-{
- /* Check the parameters */
- assert_param(IS_SPDIFRX_STATE(SPDIFRX_State));
-
- /* Clear SPDIFRXEN bits */
- SPDIFRX->CR &= ~(SPDIFRX_CR_SPDIFEN);
- /* Set new SPDIFRXEN value */
- SPDIFRX->CR |= SPDIFRX_State;
-}
-
-/**
- * @brief Enables or disables the specified SPDIFRX Block interrupts.
- * @param SPDIFRX_IT: specifies the SPDIFRX interrupt source to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg SPDIFRX_IT_RXNE: RXNE interrupt enable
- * @arg SPDIFRX_IT_CSRNE: Control Buffer Ready Interrupt Enable
- * @arg SPDIFRX_IT_PERRIE: Parity error interrupt enable
- * @arg SPDIFRX_IT_OVRIE: Overrun error Interrupt Enable
- * @arg SPDIFRX_IT_SBLKIE: Synchronization Block Detected Interrupt Enable
- * @arg SPDIFRX_IT_SYNCDIE: Synchronization Done
- * @arg SPDIFRX_IT_IFEIE: Serial Interface Error Interrupt Enable
- * @param NewState: new state of the specified SPDIFRX interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPDIFRX_ITConfig(uint32_t SPDIFRX_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPDIFRX_CONFIG_IT(SPDIFRX_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPDIFRX interrupt */
- SPDIFRX->IMR |= SPDIFRX_IT;
- }
- else
- {
- /* Disable the selected SPDIFRX interrupt */
- SPDIFRX->IMR &= ~(SPDIFRX_IT);
- }
-}
-
-/**
- * @brief Checks whether the specified SPDIFRX flag is set or not.
- * @param SPDIFRX_FLAG: specifies the SPDIFRX flag to check.
- * This parameter can be one of the following values:
- * @arg SPDIFRX_FLAG_RXNE: Read data register not empty flag.
- * @arg SPDIFRX_FLAG_CSRNE: The Control Buffer register is not empty flag.
- * @arg SPDIFRX_FLAG_PERR: Parity error flag.
- * @arg SPDIFRX_FLAG_OVR: Overrun error flag.
- * @arg SPDIFRX_FLAG_SBD: Synchronization Block Detected flag.
- * @arg SPDIFRX_FLAG_SYNCD: Synchronization Done flag.
- * @arg SPDIFRX_FLAG_FERR: Framing error flag.
- * @arg SPDIFRX_FLAG_SERR: Synchronization error flag.
- * @arg SPDIFRX_FLAG_TERR: Time-out error flag.
- * @retval The new state of SPDIFRX_FLAG (SET or RESET).
- */
-FlagStatus SPDIFRX_GetFlagStatus(uint32_t SPDIFRX_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_SPDIFRX_FLAG(SPDIFRX_FLAG));
-
- /* Check the status of the specified SPDIFRX flag */
- if ((SPDIFRX->SR & SPDIFRX_FLAG) != (uint32_t)RESET)
- {
- /* SPDIFRX_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* SPDIFRX_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the SPDIFRX_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the specified SPDIFRX flag.
- * @param SPDIFRX_FLAG: specifies the SPDIFRX flag to check.
- * This parameter can be one of the following values:
- * @arg SPDIFRX_FLAG_PERR: Parity error flag.
- * @arg SPDIFRX_FLAG_OVR: Overrun error flag.
- * @arg SPDIFRX_FLAG_SBD: Synchronization Block Detected flag.
- * @arg SPDIFRX_FLAG_SYNCD: Synchronization Done flag.
- *
- * @retval None
- */
-void SPDIFRX_ClearFlag(uint32_t SPDIFRX_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_SPDIFRX_CLEAR_FLAG(SPDIFRX_FLAG));
-
- /* Clear the selected SPDIFRX Block flag */
- SPDIFRX->IFCR |= SPDIFRX_FLAG;
-}
-
-/**
- * @brief Checks whether the specified SPDIFRX interrupt has occurred or not.
- * @param SPDIFRX_IT: specifies the SPDIFRX interrupt source to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg SPDIFRX_IT_RXNE: RXNE interrupt enable
- * @arg SPDIFRX_IT_CSRNE: Control Buffer Ready Interrupt Enable
- * @arg SPDIFRX_IT_PERRIE: Parity error interrupt enable
- * @arg SPDIFRX_IT_OVRIE: Overrun error Interrupt Enable
- * @arg SPDIFRX_IT_SBLKIE: Synchronization Block Detected Interrupt Enable
- * @arg SPDIFRX_IT_SYNCDIE: Synchronization Done
- * @arg SPDIFRX_IT_IFEIE: Serial Interface Error Interrupt Enable
- * @retval The new state of SPDIFRX_IT (SET or RESET).
- */
-ITStatus SPDIFRX_GetITStatus(uint32_t SPDIFRX_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_SPDIFRX_CONFIG_IT(SPDIFRX_IT));
-
- /* Get the SPDIFRX_IT enable bit status */
- enablestatus = (SPDIFRX->IMR & SPDIFRX_IT) ;
-
- /* Check the status of the specified SPDIFRX interrupt */
- if (((SPDIFRX->SR & SPDIFRX_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
- {
- /* SPDIFRX_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* SPDIFRX_IT is reset */
- bitstatus = RESET;
- }
- /* Return the SPDIFRX_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the SPDIFRX interrupt pending bit.
- * @param SAI_IT: specifies the SPDIFRX interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg SPDIFRX_IT_MUTEDET: MUTE detection interrupt.
- * @arg SPDIFRX_IT_OVRUDR: overrun/underrun interrupt.
- * @arg SPDIFRX_IT_WCKCFG: wrong clock configuration interrupt.
- * @arg SPDIFRX_IT_CNRDY: codec not ready interrupt.
- * @arg SPDIFRX_IT_AFSDET: anticipated frame synchronization detection interrupt.
- * @arg SPDIFRX_IT_LFSDET: late frame synchronization detection interrupt.
- *
- * @note FREQ (FIFO Request) flag is cleared :
- * - When the audio block is transmitter and the FIFO is full or the FIFO
- * has one data (one buffer mode) depending the bit FTH in the
- * SPDIFRX_xCR2 register.
- * - When the audio block is receiver and the FIFO is not empty
- *
- * @retval None
- */
-void SPDIFRX_ClearITPendingBit(uint32_t SPDIFRX_IT)
-{
- /* Check the parameters */
- assert_param(IS_SPDIFRX_CLEAR_FLAG(SPDIFRX_IT));
-
- /* Clear the selected SPDIFRX interrupt pending bit */
- SPDIFRX->IFCR |= SPDIFRX_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* STM32F446xx */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_spdifrx.h b/底盘/底盘-old/底盘/Library/stm32f4xx_spdifrx.h
deleted file mode 100644
index b02d2eb..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_spdifrx.h
+++ /dev/null
@@ -1,254 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_spdifrx.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the SPDIFRX firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_SPDIFRX_H
-#define __STM32F4xx_SPDIFRX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup SPDIFRX
- * @{
- */
-#if defined(STM32F446xx)
-/* Exported types ------------------------------------------------------------*/
-/**
- * @brief SPDIFRX Init structure definition
- */
-typedef struct
-{
- uint32_t SPDIFRX_InputSelection; /*!< Specifies the SPDIFRX input selection.
- This parameter can be a value of @ref SPDIFRX_Input_Selection */
-
- uint32_t SPDIFRX_Retries; /*!< Specifies the Maximum allowed re-tries during synchronization phase.
- This parameter can be a value of @ref SPDIFRX_Max_Retries */
-
- uint32_t SPDIFRX_WaitForActivity; /*!< Specifies the wait for activity on SPDIFRX selected input.
- This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */
-
- uint32_t SPDIFRX_ChannelSelection; /*!< Specifies whether the control flow will take the channel status from channel A or B.
- This parameter can be a value of @ref SPDIFRX_Channel_Selection */
-
- uint32_t SPDIFRX_DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).
- This parameter can be a value of @ref SPDIFRX_Data_Format */
-
- uint32_t SPDIFRX_StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
- This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
-}SPDIFRX_InitTypeDef;
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SPDIFRX_Exported_Constants
- * @{
- */
-#define IS_SPDIFRX_PERIPH(PERIPH) (((PERIPH) == SPDIFRX))
-
-/** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection
- * @{
- */
-#define SPDIFRX_Input_IN0 ((uint32_t)0x00000000)
-#define SPDIFRX_Input_IN1 ((uint32_t)0x00010000)
-#define SPDIFRX_Input_IN2 ((uint32_t)0x00020000)
-#define SPDIFRX_Input_IN3 ((uint32_t)0x00030000)
-#define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_Input_IN1) || \
- ((INPUT) == SPDIFRX_Input_IN2) || \
- ((INPUT) == SPDIFRX_Input_IN3) || \
- ((INPUT) == SPDIFRX_Input_IN0))
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_Max_Retries SPDIFRX Max Retries
- * @{
- */
-#define SPDIFRX_1MAX_RETRIES ((uint32_t)0x00000000)
-#define SPDIFRX_4MAX_RETRIES ((uint32_t)0x00001000)
-#define SPDIFRX_16MAX_RETRIES ((uint32_t)0x00002000)
-#define SPDIFRX_64MAX_RETRIES ((uint32_t)0x00003000)
-#define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_1MAX_RETRIES) || \
- ((RET) == SPDIFRX_4MAX_RETRIES) || \
- ((RET) == SPDIFRX_16MAX_RETRIES) || \
- ((RET) == SPDIFRX_64MAX_RETRIES))
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity
- * @{
- */
-#define SPDIFRX_WaitForActivity_Off ((uint32_t)0x00000000)
-#define SPDIFRX_WaitForActivity_On ((uint32_t)SPDIFRX_CR_WFA)
-#define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WaitForActivity_On) || \
- ((VAL) == SPDIFRX_WaitForActivity_Off))
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_ChannelSelection SPDIFRX Channel Selection
- * @{
- */
-#define SPDIFRX_Select_Channel_A ((uint32_t)0x00000000)
-#define SPDIFRX_Select_Channel_B ((uint32_t)SPDIFRX_CR_CHSEL)
-#define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_Select_Channel_A) || \
- ((CHANNEL) == SPDIFRX_Select_Channel_B))
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_Block_Synchronization SPDIFRX Block Synchronization
- * @{
- */
-#define SPDIFRX_LSB_DataFormat ((uint32_t)0x00000000)
-#define SPDIFRX_MSB_DataFormat ((uint32_t)0x00000010)
-#define SPDIFRX_32BITS_DataFormat ((uint32_t)0x00000020)
-#define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_LSB_DataFormat) || \
- ((FORMAT) == SPDIFRX_MSB_DataFormat) || \
- ((FORMAT) == SPDIFRX_32BITS_DataFormat))
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_StereoMode SPDIFRX StereoMode
- * @{
- */
-#define SPDIFRX_StereoMode_Disabled ((uint32_t)0x00000000)
-#define SPDIFRX_StereoMode_Enabled ((uint32_t)SPDIFRX_CR_RXSTEO)
-#define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_StereoMode_Disabled) || \
- ((MODE) == SPDIFRX_StereoMode_Enabled))
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_State SPDIFRX State
- * @{
- */
-#define SPDIFRX_STATE_IDLE ((uint32_t)0x00000000)
-#define SPDIFRX_STATE_SYNC ((uint32_t)0x00000001)
-#define SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN)
-#define IS_SPDIFRX_STATE(STATE) (((STATE) == SPDIFRX_STATE_IDLE) || \
- ((STATE) == SPDIFRX_STATE_SYNC) || \
- ((STATE) == SPDIFRX_STATE_RCV))
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition
- * @{
- */
-#define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)
-#define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)
-#define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)
-#define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)
-#define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)
-#define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)
-#define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )
-#define IS_SPDIFRX_CONFIG_IT(IT) (((IT) == SPDIFRX_IT_RXNE) || \
- ((IT) == SPDIFRX_IT_CSRNE) || \
- ((IT) == SPDIFRX_IT_PERRIE) || \
- ((IT) == SPDIFRX_IT_OVRIE) || \
- ((IT) == SPDIFRX_IT_SBLKIE) || \
- ((IT) == SPDIFRX_IT_SYNCDIE) || \
- ((IT) == SPDIFRX_IT_IFEIE))
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition
- * @{
- */
-#define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)
-#define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)
-#define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)
-#define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)
-#define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)
-#define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)
-#define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)
-#define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)
-#define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)
-#define IS_SPDIFRX_FLAG(FLAG) (((FLAG) == SPDIFRX_FLAG_RXNE) || ((FLAG) == SPDIFRX_FLAG_CSRNE) || \
- ((FLAG) == SPDIFRX_FLAG_PERR) || ((FLAG) == SPDIFRX_FLAG_OVR) || \
- ((FLAG) == SPDIFRX_SR_SBD) || ((FLAG) == SPDIFRX_SR_SYNCD) || \
- ((FLAG) == SPDIFRX_SR_FERR) || ((FLAG) == SPDIFRX_SR_SERR) || \
- ((FLAG) == SPDIFRX_SR_TERR))
-#define IS_SPDIFRX_CLEAR_FLAG(FLAG) (((FLAG) == SPDIFRX_FLAG_PERR) || ((FLAG) == SPDIFRX_FLAG_OVR) || \
- ((FLAG) == SPDIFRX_SR_SBD) || ((FLAG) == SPDIFRX_SR_SYNCD))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the SPDIFRX configuration to the default reset state *****/
-void SPDIFRX_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void SPDIFRX_Init(SPDIFRX_InitTypeDef* SPDIFRX_InitStruct);
-void SPDIFRX_StructInit(SPDIFRX_InitTypeDef* SPDIFRX_InitStruct);
-void SPDIFRX_Cmd(uint32_t SPDIFRX_State);
-void SPDIFRX_SetPreambleTypeBit(FunctionalState NewState);
-void SPDIFRX_SetUserDataChannelStatusBits(FunctionalState NewState);
-void SPDIFRX_SetValidityBit(FunctionalState NewState);
-void SPDIFRX_SetParityBit(FunctionalState NewState);
-
-/* Data transfers functions ***************************************************/
-uint32_t SPDIFRX_ReceiveData(void);
-
-/* DMA transfers management functions *****************************************/
-void SPDIFRX_RxDMACmd(FunctionalState NewState);
-void SPDIFRX_CbDMACmd(FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void SPDIFRX_ITConfig(uint32_t SPDIFRX_IT, FunctionalState NewState);
-FlagStatus SPDIFRX_GetFlagStatus(uint32_t SPDIFRX_FLAG);
-void SPDIFRX_ClearFlag(uint32_t SPDIFRX_FLAG);
-ITStatus SPDIFRX_GetITStatus(uint32_t SPDIFRX_IT);
-void SPDIFRX_ClearITPendingBit(uint32_t SPDIFRX_IT);
-
-#endif /* STM32F446xx */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_SPDIFRX_H */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_spi.c b/底盘/底盘-old/底盘/Library/stm32f4xx_spi.c
deleted file mode 100644
index e45e1d0..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_spi.c
+++ /dev/null
@@ -1,1325 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_spi.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Serial peripheral interface (SPI):
- * + Initialization and Configuration
- * + Data transfers functions
- * + Hardware CRC Calculation
- * + DMA transfers management
- * + Interrupts and flags management
- *
-@verbatim
-
- ===================================================================
- ##### How to use this driver #####
- ===================================================================
- [..]
- (#) Enable peripheral clock using the following functions
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI4
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI5
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI6.
-
- (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd()
- function. In I2S mode, if an external clock source is used then the I2S
- CKIN pin GPIO clock should also be enabled.
-
- (#) Peripherals alternate function:
- (++) Connect the pin to the desired peripherals' Alternate Function (AF)
- using GPIO_PinAFConfig() function
- (++) Configure the desired pin in alternate function by:
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd,
- GPIO_OType and GPIO_Speed members
- (++) Call GPIO_Init() function In I2S mode, if an external clock source is
- used then the I2S CKIN pin should be also configured in Alternate
- function Push-pull pull-up mode.
-
- (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave
- Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
- function.
- In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio
- frequency and Polarity using I2S_Init() function. For I2S mode, make sure
- that either:
- (++) I2S PLL is configured using the functions
- RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), RCC_PLLI2SCmd(ENABLE) and
- RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY); or
- (++) External clock source is configured using the function
- RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly
- the define constant I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file.
-
- (#) Enable the NVIC and the corresponding interrupt using the function
- SPI_ITConfig() if you need to use interrupt mode.
-
- (#) When using the DMA mode
- (++) Configure the DMA using DMA_Init() function
- (++) Active the needed channel Request using SPI_I2S_DMACmd() function
-
- (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using
- I2S_Cmd().
-
- (#) Enable the DMA using the DMA_Cmd() function when using DMA mode.
-
- (#) Optionally, you can enable/configure the following parameters without
- re-initialization (i.e there is no need to call again SPI_Init() function):
- (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
- is programmed as Data direction parameter using the SPI_Init() function
- it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx
- using the SPI_BiDirectionalLineConfig() function.
- (++) When SPI_NSS_Soft is selected as Slave Select Management parameter
- using the SPI_Init() function it can be possible to manage the
- NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
- (++) Reconfigure the data size using the SPI_DataSizeConfig() function
- (++) Enable or disable the SS output using the SPI_SSOutputCmd() function
-
- (#) To use the CRC Hardware calculation feature refer to the Peripheral
- CRC hardware Calculation subsection.
-
-
- [..] It is possible to use SPI in I2S full duplex mode, in this case, each SPI
- peripheral is able to manage sending and receiving data simultaneously
- using two data lines. Each SPI peripheral has an extended block called I2Sxext
- (ie. I2S2ext for SPI2 and I2S3ext for SPI3).
- The extension block is not a full SPI IP, it is used only as I2S slave to
- implement full duplex mode. The extension block uses the same clock sources
- as its master.
- To configure I2S full duplex you have to:
-
- (#) Configure SPIx in I2S mode (I2S_Init() function) as described above.
-
- (#) Call the I2S_FullDuplexConfig() function using the same structure passed to
- I2S_Init() function.
-
- (#) Call I2S_Cmd() for SPIx then for its extended block.
-
- (#) To configure interrupts or DMA requests and to get/clear flag status,
- use I2Sxext instance for the extension block.
-
- [..] Functions that can be called with I2Sxext instances are: I2S_Cmd(),
- I2S_FullDuplexConfig(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(),
- SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(),
- SPI_I2S_ClearFlag(), SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit().
-
- Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx):
-
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
- I2S_StructInit(&I2SInitStruct);
- I2SInitStruct.Mode = I2S_Mode_MasterTx;
- I2S_Init(SPI3, &I2SInitStruct);
- I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct)
- I2S_Cmd(SPI3, ENABLE);
- I2S_Cmd(SPI3ext, ENABLE);
- ...
- while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
- {}
- SPI_I2S_SendData(SPI3, txdata[i]);
- ...
- while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET)
- {}
- rxdata[i] = SPI_I2S_ReceiveData(I2S3ext);
- ...
-
- [..]
- (@) In I2S mode: if an external clock is used as source clock for the I2S,
- then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should
- be enabled and set to the value of the source clock frequency (in Hz).
-
- (@) In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd()
- just after calling the function SPI_Init().
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_spi.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SPI
- * @brief SPI driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* SPI registers Masks */
-#define CR1_CLEAR_MASK ((uint16_t)0x3040)
-#define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040)
-
-/* RCC PLLs masks */
-#define PLLCFGR_PPLR_MASK ((uint32_t)0x70000000)
-#define PLLCFGR_PPLN_MASK ((uint32_t)0x00007FC0)
-
-#define SPI_CR2_FRF ((uint16_t)0x0010)
-#define SPI_SR_TIFRFE ((uint16_t)0x0100)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SPI_Private_Functions
- * @{
- */
-
-/** @defgroup SPI_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides a set of functions allowing to initialize the SPI
- Direction, SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS
- Management, SPI Baud Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
-
- [..] The SPI_Init() function follows the SPI configuration procedures for Master
- mode and Slave mode (details for these procedures are available in reference
- manual (RM0090)).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initialize the SPIx peripheral registers to their default reset values.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode.
- *
- * @note The extended I2S blocks (ie. I2S2ext and I2S3ext blocks) are de-initialized
- * when the relative I2S peripheral is de-initialized (the extended block's clock
- * is managed by the I2S peripheral clock).
- *
- * @retval None
- */
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- if (SPIx == SPI1)
- {
- /* Enable SPI1 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
- /* Release SPI1 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
- }
- else if (SPIx == SPI2)
- {
- /* Enable SPI2 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
- /* Release SPI2 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
- }
- else if (SPIx == SPI3)
- {
- /* Enable SPI3 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
- /* Release SPI3 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
- }
- else if (SPIx == SPI4)
- {
- /* Enable SPI4 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, ENABLE);
- /* Release SPI4 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, DISABLE);
- }
- else if (SPIx == SPI5)
- {
- /* Enable SPI5 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, ENABLE);
- /* Release SPI5 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, DISABLE);
- }
- else
- {
- if (SPIx == SPI6)
- {
- /* Enable SPI6 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, ENABLE);
- /* Release SPI6 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the SPIx peripheral according to the specified
- * parameters in the SPI_InitStruct.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
- * contains the configuration information for the specified SPI peripheral.
- * @retval None
- */
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
-{
- uint16_t tmpreg = 0;
-
- /* check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Check the SPI parameters */
- assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
- assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
- assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
- assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
- assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
- assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
- assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
- assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
- assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
-
-/*---------------------------- SPIx CR1 Configuration ------------------------*/
- /* Get the SPIx CR1 value */
- tmpreg = SPIx->CR1;
- /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
- tmpreg &= CR1_CLEAR_MASK;
- /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
- master/salve mode, CPOL and CPHA */
- /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
- /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
- /* Set LSBFirst bit according to SPI_FirstBit value */
- /* Set BR bits according to SPI_BaudRatePrescaler value */
- /* Set CPOL bit according to SPI_CPOL value */
- /* Set CPHA bit according to SPI_CPHA value */
- tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
- SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
- SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
- SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
- /* Write to SPIx CR1 */
- SPIx->CR1 = tmpreg;
-
- /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
- SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
-/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
- /* Write to SPIx CRCPOLY */
- SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
-}
-
-/**
- * @brief Initializes the SPIx peripheral according to the specified
- * parameters in the I2S_InitStruct.
- * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode).
- * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
- * contains the configuration information for the specified SPI peripheral
- * configured in I2S mode.
- *
- * @note The function calculates the optimal prescaler needed to obtain the most
- * accurate audio frequency (depending on the I2S clock source, the PLL values
- * and the product configuration). But in case the prescaler value is greater
- * than 511, the default value (0x02) will be configured instead.
- *
- * @note if an external clock is used as source clock for the I2S, then the define
- * I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should be enabled and set
- * to the value of the source clock frequency (in Hz).
- *
- * @retval None
- */
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
-{
- uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
- uint32_t tmp = 0, i2sclk = 0;
-#ifndef I2S_EXTERNAL_CLOCK_VAL
- uint32_t pllm = 0, plln = 0, pllr = 0;
-#endif /* I2S_EXTERNAL_CLOCK_VAL */
-
- /* Check the I2S parameters */
- assert_param(IS_SPI_23_PERIPH(SPIx));
- assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
- assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
- assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
- assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
- assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
- assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
-
-/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK;
- SPIx->I2SPR = 0x0002;
-
- /* Get the I2SCFGR register value */
- tmpreg = SPIx->I2SCFGR;
-
- /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
- if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
- {
- i2sodd = (uint16_t)0;
- i2sdiv = (uint16_t)2;
- }
- /* If the requested audio frequency is not the default, compute the prescaler */
- else
- {
- /* Check the frame length (For the Prescaler computing) *******************/
- if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
- {
- /* Packet length is 16 bits */
- packetlength = 16;
- }
- else
- {
- /* Packet length is 32 bits */
- packetlength = 32;
- }
-
- if(I2S_InitStruct->I2S_Standard <= I2S_Standard_LSB)
- {
- /* In I2S standard packet length is multiplied by 2 */
- packetlength = packetlength * 2;
- }
-
- /* Get I2S source Clock frequency ****************************************/
-
- /* If an external I2S clock has to be used, this define should be set
- in the project configuration or in the stm32f4xx_conf.h file */
- #ifdef I2S_EXTERNAL_CLOCK_VAL
- /* Set external clock as I2S clock source */
- if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0)
- {
- RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC;
- }
-
- /* Set the I2S clock to the external clock value */
- i2sclk = I2S_EXTERNAL_CLOCK_VAL;
-
- #else /* There is no define for External I2S clock source */
- /* Set PLLI2S as I2S clock source */
- if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0)
- {
- RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC;
- }
-
- /* Get the PLLI2SN value */
- plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \
- (RCC_PLLI2SCFGR_PLLI2SN >> 6));
-
- /* Get the PLLI2SR value */
- pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \
- (RCC_PLLI2SCFGR_PLLI2SR >> 28));
-
- /* Get the PLLM value */
- pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
-
- if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)
- {
- /* Get the I2S source clock value */
- i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr);
- }
- else
- { /* Get the I2S source clock value */
- i2sclk = (uint32_t)(((HSI_VALUE / pllm) * plln) / pllr);
- }
- #endif /* I2S_EXTERNAL_CLOCK_VAL */
-
- /* Compute the Real divider depending on the MCLK output state, with a floating point */
- if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
- {
- /* MCLK output is enabled */
- tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
- }
- else
- {
- /* MCLK output is disabled */
- tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
- }
-
- /* Remove the flatting point */
- tmp = tmp / 10;
-
- /* Check the parity of the divider */
- i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
-
- /* Compute the i2sdiv prescaler */
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
-
- /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint16_t) (i2sodd << 8);
- }
-
- /* Test if the divider is 1 or 0 or greater than 0xFF */
- if ((i2sdiv < 2) || (i2sdiv > 0xFF))
- {
- /* Set the default values */
- i2sdiv = 2;
- i2sodd = 0;
- }
-
- /* Write to SPIx I2SPR register the computed value */
- SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
-
- /* Configure the I2S with the SPI_InitStruct values */
- tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \
- (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
- (uint16_t)I2S_InitStruct->I2S_CPOL))));
-
-#if defined(SPI_I2SCFGR_ASTRTEN)
- if((I2S_InitStruct->I2S_Standard == I2S_Standard_PCMShort) || (I2S_InitStruct->I2S_Standard == I2S_Standard_PCMLong))
- {
- /* Write to SPIx I2SCFGR */
- SPIx->I2SCFGR = tmpreg | SPI_I2SCFGR_ASTRTEN;
- }
-#else
- /* Write to SPIx I2SCFGR */
- SPIx->I2SCFGR = tmpreg ;
-#endif
-}
-
-/**
- * @brief Fills each SPI_InitStruct member with its default value.
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
-{
-/*--------------- Reset SPI init structure parameters values -----------------*/
- /* Initialize the SPI_Direction member */
- SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
- /* initialize the SPI_Mode member */
- SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
- /* initialize the SPI_DataSize member */
- SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
- /* Initialize the SPI_CPOL member */
- SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
- /* Initialize the SPI_CPHA member */
- SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
- /* Initialize the SPI_NSS member */
- SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
- /* Initialize the SPI_BaudRatePrescaler member */
- SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
- /* Initialize the SPI_FirstBit member */
- SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
- /* Initialize the SPI_CRCPolynomial member */
- SPI_InitStruct->SPI_CRCPolynomial = 7;
-}
-
-/**
- * @brief Fills each I2S_InitStruct member with its default value.
- * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
-{
-/*--------------- Reset I2S init structure parameters values -----------------*/
- /* Initialize the I2S_Mode member */
- I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
-
- /* Initialize the I2S_Standard member */
- I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
-
- /* Initialize the I2S_DataFormat member */
- I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
-
- /* Initialize the I2S_MCLKOutput member */
- I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
-
- /* Initialize the I2S_AudioFreq member */
- I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
-
- /* Initialize the I2S_CPOL member */
- I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
-}
-
-/**
- * @brief Enables or disables the specified SPI peripheral.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param NewState: new state of the SPIx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI peripheral */
- SPIx->CR1 |= SPI_CR1_SPE;
- }
- else
- {
- /* Disable the selected SPI peripheral */
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
- }
-}
-
-/**
- * @brief Enables or disables the specified SPI peripheral (in I2S mode).
- * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (or I2Sxext
- * for full duplex mode).
- * @param NewState: new state of the SPIx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_23_PERIPH_EXT(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI peripheral (in I2S mode) */
- SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
- }
- else
- {
- /* Disable the selected SPI peripheral in I2S mode */
- SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
- }
-}
-
-/**
- * @brief Configures the data size for the selected SPI.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param SPI_DataSize: specifies the SPI data size.
- * This parameter can be one of the following values:
- * @arg SPI_DataSize_16b: Set data frame format to 16bit
- * @arg SPI_DataSize_8b: Set data frame format to 8bit
- * @retval None
- */
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_DATASIZE(SPI_DataSize));
- /* Clear DFF bit */
- SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
- /* Set new DFF bit value */
- SPIx->CR1 |= SPI_DataSize;
-}
-
-/**
- * @brief Selects the data transfer direction in bidirectional mode for the specified SPI.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param SPI_Direction: specifies the data transfer direction in bidirectional mode.
- * This parameter can be one of the following values:
- * @arg SPI_Direction_Tx: Selects Tx transmission direction
- * @arg SPI_Direction_Rx: Selects Rx receive direction
- * @retval None
- */
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_DIRECTION(SPI_Direction));
- if (SPI_Direction == SPI_Direction_Tx)
- {
- /* Set the Tx only mode */
- SPIx->CR1 |= SPI_Direction_Tx;
- }
- else
- {
- /* Set the Rx only mode */
- SPIx->CR1 &= SPI_Direction_Rx;
- }
-}
-
-/**
- * @brief Configures internally by software the NSS pin for the selected SPI.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
- * This parameter can be one of the following values:
- * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
- * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
- * @retval None
- */
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
- if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
- {
- /* Set NSS pin internally by software */
- SPIx->CR1 |= SPI_NSSInternalSoft_Set;
- }
- else
- {
- /* Reset NSS pin internally by software */
- SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the SS output for the selected SPI.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param NewState: new state of the SPIx SS output.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI SS output */
- SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;
- }
- else
- {
- /* Disable the selected SPI SS output */
- SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
- }
-}
-
-/**
- * @brief Enables or disables the SPIx/I2Sx DMA interface.
- *
- * @note This function can be called only after the SPI_Init() function has
- * been called.
- * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA
- * are not taken into consideration and are configured by hardware
- * respectively to the TI mode requirements.
- *
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6
- * @param NewState: new state of the selected SPI TI communication mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TI mode for the selected SPI peripheral */
- SPIx->CR2 |= SPI_CR2_FRF;
- }
- else
- {
- /* Disable the TI mode for the selected SPI peripheral */
- SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF;
- }
-}
-
-/**
- * @brief Configures the full duplex mode for the I2Sx peripheral using its
- * extension I2Sxext according to the specified parameters in the
- * I2S_InitStruct.
- * @param I2Sxext: where x can be 2 or 3 to select the I2S peripheral extension block.
- * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
- * contains the configuration information for the specified I2S peripheral
- * extension.
- *
- * @note The structure pointed by I2S_InitStruct parameter should be the same
- * used for the master I2S peripheral. In this case, if the master is
- * configured as transmitter, the slave will be receiver and vice versa.
- * Or you can force a different mode by modifying the field I2S_Mode to the
- * value I2S_SlaveRx or I2S_SlaveTx independently of the master configuration.
- *
- * @note The I2S full duplex extension can be configured in slave mode only.
- *
- * @retval None
- */
-void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct)
-{
- uint16_t tmpreg = 0, tmp = 0;
-
- /* Check the I2S parameters */
- assert_param(IS_I2S_EXT_PERIPH(I2Sxext));
- assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
- assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
- assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
- assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
-
-/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK;
- I2Sxext->I2SPR = 0x0002;
-
- /* Get the I2SCFGR register value */
- tmpreg = I2Sxext->I2SCFGR;
-
- /* Get the mode to be configured for the extended I2S */
- if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx))
- {
- tmp = I2S_Mode_SlaveRx;
- }
- else
- {
- if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx))
- {
- tmp = I2S_Mode_SlaveTx;
- }
- }
-
-
- /* Configure the I2S with the SPI_InitStruct values */
- tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
- (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
- (uint16_t)I2S_InitStruct->I2S_CPOL))));
-
- /* Write to SPIx I2SCFGR */
- I2Sxext->I2SCFGR = tmpreg;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group2 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers functions #####
- ===============================================================================
-
- [..] This section provides a set of functions allowing to manage the SPI data
- transfers. In reception, data are received and then stored into an internal
- Rx buffer while. In transmission, data are first stored into an internal Tx
- buffer before being transmitted.
-
- [..] The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData()
- function and returns the Rx buffered value. Whereas a write access to the SPI_DR
- can be done using SPI_I2S_SendData() function and stores the written data into
- Tx buffer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @retval The value of the received data.
- */
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
-
- /* Return the data in the DR register */
- return SPIx->DR;
-}
-
-/**
- * @brief Transmits a Data through the SPIx/I2Sx peripheral.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param Data: Data to be transmitted.
- * @retval None
- */
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
-
- /* Write in the DR register the data to be sent */
- SPIx->DR = Data;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group3 Hardware CRC Calculation functions
- * @brief Hardware CRC Calculation functions
- *
-@verbatim
- ===============================================================================
- ##### Hardware CRC Calculation functions #####
- ===============================================================================
-
- [..] This section provides a set of functions allowing to manage the SPI CRC hardware
- calculation
-
- [..] SPI communication using CRC is possible through the following procedure:
- (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler,
- Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
- function.
- (#) Enable the CRC calculation using the SPI_CalculateCRC() function.
- (#) Enable the SPI using the SPI_Cmd() function
- (#) Before writing the last data to the TX buffer, set the CRCNext bit using the
- SPI_TransmitCRC() function to indicate that after transmission of the last
- data, the CRC should be transmitted.
- (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT
- bit is reset. The CRC is also received and compared against the SPI_RXCRCR
- value.
- If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
- can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
-
- [..]
- (@) It is advised not to read the calculated CRC values during the communication.
-
- (@) When the SPI is in slave mode, be careful to enable CRC calculation only
- when the clock is stable, that is, when the clock is in the steady state.
- If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive
- to the SCK slave input clock as soon as CRCEN is set, and this, whatever
- the value of the SPE bit.
-
- (@) With high bitrate frequencies, be careful when transmitting the CRC.
- As the number of used CPU cycles has to be as low as possible in the CRC
- transfer phase, it is forbidden to call software functions in the CRC
- transmission sequence to avoid errors in the last data and CRC reception.
- In fact, CRCNEXT bit has to be written before the end of the transmission/reception
- of the last data.
-
- (@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the
- degradation of the SPI speed performance due to CPU accesses impacting the
- SPI bandwidth.
-
- (@) When the STM32F4xx is configured as slave and the NSS hardware mode is
- used, the NSS pin needs to be kept low between the data phase and the CRC
- phase.
-
- (@) When the SPI is configured in slave mode with the CRC feature enabled, CRC
- calculation takes place even if a high level is applied on the NSS pin.
- This may happen for example in case of a multi-slave environment where the
- communication master addresses slaves alternately.
-
- (@) Between a slave de-selection (high level on NSS) and a new slave selection
- (low level on NSS), the CRC value should be cleared on both master and slave
- sides in order to resynchronize the master and slave for their respective
- CRC calculation.
-
- (@) To clear the CRC, follow the procedure below:
- (#@) Disable SPI using the SPI_Cmd() function
- (#@) Disable the CRC calculation using the SPI_CalculateCRC() function.
- (#@) Enable the CRC calculation using the SPI_CalculateCRC() function.
- (#@) Enable SPI using the SPI_Cmd() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the CRC value calculation of the transferred bytes.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param NewState: new state of the SPIx CRC value calculation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI CRC calculation */
- SPIx->CR1 |= SPI_CR1_CRCEN;
- }
- else
- {
- /* Disable the selected SPI CRC calculation */
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
- }
-}
-
-/**
- * @brief Transmit the SPIx CRC value.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @retval None
- */
-void SPI_TransmitCRC(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Enable the selected SPI CRC transmission */
- SPIx->CR1 |= SPI_CR1_CRCNEXT;
-}
-
-/**
- * @brief Returns the transmit or the receive CRC register value for the specified SPI.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param SPI_CRC: specifies the CRC register to be read.
- * This parameter can be one of the following values:
- * @arg SPI_CRC_Tx: Selects Tx CRC register
- * @arg SPI_CRC_Rx: Selects Rx CRC register
- * @retval The selected CRC register value..
- */
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
-{
- uint16_t crcreg = 0;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_CRC(SPI_CRC));
- if (SPI_CRC != SPI_CRC_Rx)
- {
- /* Get the Tx CRC register */
- crcreg = SPIx->TXCRCR;
- }
- else
- {
- /* Get the Rx CRC register */
- crcreg = SPIx->RXCRCR;
- }
- /* Return the selected CRC register */
- return crcreg;
-}
-
-/**
- * @brief Returns the CRC Polynomial register value for the specified SPI.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @retval The CRC Polynomial register value.
- */
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Return the CRC polynomial register */
- return SPIx->CRCPR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group4 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the SPIx/I2Sx DMA interface.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
- * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
- * @param NewState: new state of the selected SPI DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI DMA requests */
- SPIx->CR2 |= SPI_I2S_DMAReq;
- }
- else
- {
- /* Disable the selected SPI DMA requests */
- SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group5 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
- [..] This section provides a set of functions allowing to configure the SPI Interrupts
- sources and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to manage
- the communication: Polling mode, Interrupt mode or DMA mode.
-
- *** Polling Mode ***
- ====================
-[..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
- (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register
- (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register
- (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.
- (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur
- (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur
- (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur
- (#) I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs.
- (#) I2S_FLAG_UDR: to indicate an Underrun error occurs.
- (#) I2S_FLAG_CHSIDE: to indicate Channel Side.
-
- (@) Do not use the BSY flag to handle each data transmission or reception. It is
- better to use the TXE and RXNE flags instead.
-
- [..] In this Mode it is advised to use the following functions:
- (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
- (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-
- *** Interrupt Mode ***
- ======================
- [..] In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources
- and 7 pending bits:
- (+) Pending Bits:
- (##) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register
- (##) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register
- (##) SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only)
- (##) SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only)
- (##) SPI_I2S_IT_OVR : to indicate if an Overrun error occur
- (##) I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only).
- (##) I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only).
-
- (+) Interrupt Source:
- (##) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty
- interrupt.
- (##) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not
- empty interrupt.
- (##) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
-
- [..] In this Mode it is advised to use the following functions:
- (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
- (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
- (+) void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-
- *** DMA Mode ***
- ================
- [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests:
- (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request
- (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request
-
- [..] In this Mode it is advised to use the following function:
- (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState
- NewState);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified SPI/I2S interrupts.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
- * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
- * @arg SPI_I2S_IT_ERR: Error interrupt mask
- * @param NewState: new state of the specified SPI interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
-{
- uint16_t itpos = 0, itmask = 0 ;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
-
- /* Get the SPI IT index */
- itpos = SPI_I2S_IT >> 4;
-
- /* Set the IT mask */
- itmask = (uint16_t)1 << (uint16_t)itpos;
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI interrupt */
- SPIx->CR2 |= itmask;
- }
- else
- {
- /* Disable the selected SPI interrupt */
- SPIx->CR2 &= (uint16_t)~itmask;
- }
-}
-
-/**
- * @brief Checks whether the specified SPIx/I2Sx flag is set or not.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_FLAG: specifies the SPI flag to check.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
- * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
- * @arg SPI_I2S_FLAG_BSY: Busy flag.
- * @arg SPI_I2S_FLAG_OVR: Overrun flag.
- * @arg SPI_FLAG_MODF: Mode Fault flag.
- * @arg SPI_FLAG_CRCERR: CRC Error flag.
- * @arg SPI_I2S_FLAG_TIFRFE: Format Error.
- * @arg I2S_FLAG_UDR: Underrun Error flag.
- * @arg I2S_FLAG_CHSIDE: Channel Side flag.
- * @retval The new state of SPI_I2S_FLAG (SET or RESET).
- */
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
-
- /* Check the status of the specified SPI flag */
- if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
- {
- /* SPI_I2S_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* SPI_I2S_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the SPI_I2S_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the SPIx CRC Error (CRCERR) flag.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_FLAG: specifies the SPI flag to clear.
- * This function clears only CRCERR flag.
- * @arg SPI_FLAG_CRCERR: CRC Error flag.
- *
- * @note OVR (OverRun error) flag is cleared by software sequence: a read
- * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
- * @note UDR (UnderRun error) flag is cleared by a read operation to
- * SPI_SR register (SPI_I2S_GetFlagStatus()).
- * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a
- * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
- *
- * @retval None
- */
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
-
- /* Clear the selected SPI CRC Error (CRCERR) flag */
- SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
-}
-
-/**
- * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_IT: specifies the SPI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
- * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
- * @arg SPI_I2S_IT_OVR: Overrun interrupt.
- * @arg SPI_IT_MODF: Mode Fault interrupt.
- * @arg SPI_IT_CRCERR: CRC Error interrupt.
- * @arg I2S_IT_UDR: Underrun interrupt.
- * @arg SPI_I2S_IT_TIFRFE: Format Error interrupt.
- * @retval The new state of SPI_I2S_IT (SET or RESET).
- */
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itpos = 0, itmask = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
-
- /* Get the SPI_I2S_IT index */
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);
-
- /* Get the SPI_I2S_IT IT mask */
- itmask = SPI_I2S_IT >> 4;
-
- /* Set the IT mask */
- itmask = 0x01 << itmask;
-
- /* Get the SPI_I2S_IT enable bit status */
- enablestatus = (SPIx->CR2 & itmask) ;
-
- /* Check the status of the specified SPI interrupt */
- if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
- {
- /* SPI_I2S_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* SPI_I2S_IT is reset */
- bitstatus = RESET;
- }
- /* Return the SPI_I2S_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
- * This function clears only CRCERR interrupt pending bit.
- * @arg SPI_IT_CRCERR: CRC Error interrupt.
- *
- * @note OVR (OverRun Error) interrupt pending bit is cleared by software
- * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData())
- * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
- * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read
- * operation to SPI_SR register (SPI_I2S_GetITStatus()).
- * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
- * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus())
- * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable
- * the SPI).
- * @retval None
- */
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
-{
- uint16_t itpos = 0;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
-
- /* Get the SPI_I2S IT index */
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);
-
- /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
- SPIx->SR = (uint16_t)~itpos;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_spi.h b/底盘/底盘-old/底盘/Library/stm32f4xx_spi.h
deleted file mode 100644
index e161899..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_spi.h
+++ /dev/null
@@ -1,541 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_spi.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the SPI
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_SPI_H
-#define __STM32F4xx_SPI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup SPI
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief SPI Init structure definition
- */
-
-typedef struct
-{
- uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
- This parameter can be a value of @ref SPI_data_direction */
-
- uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.
- This parameter can be a value of @ref SPI_mode */
-
- uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
- This parameter can be a value of @ref SPI_data_size */
-
- uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
- This parameter can be a value of @ref SPI_Clock_Polarity */
-
- uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
- This parameter can be a value of @ref SPI_Clock_Phase */
-
- uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
- hardware (NSS pin) or by software using the SSI bit.
- This parameter can be a value of @ref SPI_Slave_Select_management */
-
- uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
- used to configure the transmit and receive SCK clock.
- This parameter can be a value of @ref SPI_BaudRate_Prescaler
- @note The communication clock is derived from the master
- clock. The slave clock does not need to be set. */
-
- uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SPI_MSB_LSB_transmission */
-
- uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
-}SPI_InitTypeDef;
-
-/**
- * @brief I2S Init structure definition
- */
-
-typedef struct
-{
-
- uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
- This parameter can be a value of @ref I2S_Mode */
-
- uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
- This parameter can be a value of @ref I2S_Standard */
-
- uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
- This parameter can be a value of @ref I2S_Data_Format */
-
- uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
- This parameter can be a value of @ref I2S_MCLK_Output */
-
- uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
- This parameter can be a value of @ref I2S_Audio_Frequency */
-
- uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
- This parameter can be a value of @ref I2S_Clock_Polarity */
-}I2S_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SPI_Exported_Constants
- * @{
- */
-
-#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
- ((PERIPH) == SPI2) || \
- ((PERIPH) == SPI3) || \
- ((PERIPH) == SPI4) || \
- ((PERIPH) == SPI5) || \
- ((PERIPH) == SPI6))
-
-#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \
- ((PERIPH) == SPI2) || \
- ((PERIPH) == SPI3) || \
- ((PERIPH) == SPI4) || \
- ((PERIPH) == SPI5) || \
- ((PERIPH) == SPI6) || \
- ((PERIPH) == I2S2ext) || \
- ((PERIPH) == I2S3ext))
-
-#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
- ((PERIPH) == SPI3))
-
-#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \
- ((PERIPH) == SPI3) || \
- ((PERIPH) == I2S2ext) || \
- ((PERIPH) == I2S3ext))
-
-#define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \
- ((PERIPH) == I2S3ext))
-
-
-/** @defgroup SPI_data_direction
- * @{
- */
-
-#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
-#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
-#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
-#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
-#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
- ((MODE) == SPI_Direction_2Lines_RxOnly) || \
- ((MODE) == SPI_Direction_1Line_Rx) || \
- ((MODE) == SPI_Direction_1Line_Tx))
-/**
- * @}
- */
-
-/** @defgroup SPI_mode
- * @{
- */
-
-#define SPI_Mode_Master ((uint16_t)0x0104)
-#define SPI_Mode_Slave ((uint16_t)0x0000)
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
- ((MODE) == SPI_Mode_Slave))
-/**
- * @}
- */
-
-/** @defgroup SPI_data_size
- * @{
- */
-
-#define SPI_DataSize_16b ((uint16_t)0x0800)
-#define SPI_DataSize_8b ((uint16_t)0x0000)
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
- ((DATASIZE) == SPI_DataSize_8b))
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Polarity
- * @{
- */
-
-#define SPI_CPOL_Low ((uint16_t)0x0000)
-#define SPI_CPOL_High ((uint16_t)0x0002)
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
- ((CPOL) == SPI_CPOL_High))
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Phase
- * @{
- */
-
-#define SPI_CPHA_1Edge ((uint16_t)0x0000)
-#define SPI_CPHA_2Edge ((uint16_t)0x0001)
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
- ((CPHA) == SPI_CPHA_2Edge))
-/**
- * @}
- */
-
-/** @defgroup SPI_Slave_Select_management
- * @{
- */
-
-#define SPI_NSS_Soft ((uint16_t)0x0200)
-#define SPI_NSS_Hard ((uint16_t)0x0000)
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
- ((NSS) == SPI_NSS_Hard))
-/**
- * @}
- */
-
-/** @defgroup SPI_BaudRate_Prescaler
- * @{
- */
-
-#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
-#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
-#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
-#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
-#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
-#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
-#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
-#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_256))
-/**
- * @}
- */
-
-/** @defgroup SPI_MSB_LSB_transmission
- * @{
- */
-
-#define SPI_FirstBit_MSB ((uint16_t)0x0000)
-#define SPI_FirstBit_LSB ((uint16_t)0x0080)
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
- ((BIT) == SPI_FirstBit_LSB))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Mode
- * @{
- */
-
-#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
-#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
-#define I2S_Mode_MasterTx ((uint16_t)0x0200)
-#define I2S_Mode_MasterRx ((uint16_t)0x0300)
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
- ((MODE) == I2S_Mode_SlaveRx) || \
- ((MODE) == I2S_Mode_MasterTx)|| \
- ((MODE) == I2S_Mode_MasterRx))
-/**
- * @}
- */
-
-
-/** @defgroup SPI_I2S_Standard
- * @{
- */
-
-#define I2S_Standard_Phillips ((uint16_t)0x0000)
-#define I2S_Standard_MSB ((uint16_t)0x0010)
-#define I2S_Standard_LSB ((uint16_t)0x0020)
-#define I2S_Standard_PCMShort ((uint16_t)0x0030)
-#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
- ((STANDARD) == I2S_Standard_MSB) || \
- ((STANDARD) == I2S_Standard_LSB) || \
- ((STANDARD) == I2S_Standard_PCMShort) || \
- ((STANDARD) == I2S_Standard_PCMLong))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Data_Format
- * @{
- */
-
-#define I2S_DataFormat_16b ((uint16_t)0x0000)
-#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
-#define I2S_DataFormat_24b ((uint16_t)0x0003)
-#define I2S_DataFormat_32b ((uint16_t)0x0005)
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
- ((FORMAT) == I2S_DataFormat_16bextended) || \
- ((FORMAT) == I2S_DataFormat_24b) || \
- ((FORMAT) == I2S_DataFormat_32b))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_MCLK_Output
- * @{
- */
-
-#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
-#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
- ((OUTPUT) == I2S_MCLKOutput_Disable))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Audio_Frequency
- * @{
- */
-
-#define I2S_AudioFreq_192k ((uint32_t)192000)
-#define I2S_AudioFreq_96k ((uint32_t)96000)
-#define I2S_AudioFreq_48k ((uint32_t)48000)
-#define I2S_AudioFreq_44k ((uint32_t)44100)
-#define I2S_AudioFreq_32k ((uint32_t)32000)
-#define I2S_AudioFreq_22k ((uint32_t)22050)
-#define I2S_AudioFreq_16k ((uint32_t)16000)
-#define I2S_AudioFreq_11k ((uint32_t)11025)
-#define I2S_AudioFreq_8k ((uint32_t)8000)
-#define I2S_AudioFreq_Default ((uint32_t)2)
-
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
- ((FREQ) <= I2S_AudioFreq_192k)) || \
- ((FREQ) == I2S_AudioFreq_Default))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Clock_Polarity
- * @{
- */
-
-#define I2S_CPOL_Low ((uint16_t)0x0000)
-#define I2S_CPOL_High ((uint16_t)0x0008)
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
- ((CPOL) == I2S_CPOL_High))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_DMA_transfer_requests
- * @{
- */
-
-#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
-#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
-#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup SPI_NSS_internal_software_management
- * @{
- */
-
-#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
-#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
-#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
- ((INTERNAL) == SPI_NSSInternalSoft_Reset))
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_Transmit_Receive
- * @{
- */
-
-#define SPI_CRC_Tx ((uint8_t)0x00)
-#define SPI_CRC_Rx ((uint8_t)0x01)
-#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
-/**
- * @}
- */
-
-/** @defgroup SPI_direction_transmit_receive
- * @{
- */
-
-#define SPI_Direction_Rx ((uint16_t)0xBFFF)
-#define SPI_Direction_Tx ((uint16_t)0x4000)
-#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
- ((DIRECTION) == SPI_Direction_Tx))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_interrupts_definition
- * @{
- */
-
-#define SPI_I2S_IT_TXE ((uint8_t)0x71)
-#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
-#define SPI_I2S_IT_ERR ((uint8_t)0x50)
-#define I2S_IT_UDR ((uint8_t)0x53)
-#define SPI_I2S_IT_TIFRFE ((uint8_t)0x58)
-
-#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
- ((IT) == SPI_I2S_IT_RXNE) || \
- ((IT) == SPI_I2S_IT_ERR))
-
-#define SPI_I2S_IT_OVR ((uint8_t)0x56)
-#define SPI_IT_MODF ((uint8_t)0x55)
-#define SPI_IT_CRCERR ((uint8_t)0x54)
-
-#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
-
-#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \
- ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \
- ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\
- ((IT) == SPI_I2S_IT_TIFRFE))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_flags_definition
- * @{
- */
-
-#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
-#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
-#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
-#define I2S_FLAG_UDR ((uint16_t)0x0008)
-#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
-#define SPI_FLAG_MODF ((uint16_t)0x0020)
-#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
-#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
-#define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100)
-
-#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
-#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
- ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
- ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
- ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
- ((FLAG) == SPI_I2S_FLAG_TIFRFE))
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_polynomial
- * @{
- */
-
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Legacy
- * @{
- */
-
-#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx
-#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx
-#define SPI_IT_TXE SPI_I2S_IT_TXE
-#define SPI_IT_RXNE SPI_I2S_IT_RXNE
-#define SPI_IT_ERR SPI_I2S_IT_ERR
-#define SPI_IT_OVR SPI_I2S_IT_OVR
-#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE
-#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE
-#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR
-#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY
-#define SPI_DeInit SPI_I2S_DeInit
-#define SPI_ITConfig SPI_I2S_ITConfig
-#define SPI_DMACmd SPI_I2S_DMACmd
-#define SPI_SendData SPI_I2S_SendData
-#define SPI_ReceiveData SPI_I2S_ReceiveData
-#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus
-#define SPI_ClearFlag SPI_I2S_ClearFlag
-#define SPI_GetITStatus SPI_I2S_GetITStatus
-#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the SPI configuration to the default reset state *****/
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
-
-/* Initialization and Configuration functions *********************************/
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-
-void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct);
-
-/* Data transfers functions ***************************************************/
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
-
-/* Hardware CRC Calculation functions *****************************************/
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_TransmitCRC(SPI_TypeDef* SPIx);
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
-
-/* DMA transfers management functions *****************************************/
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_SPI_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_syscfg.c b/底盘/底盘-old/底盘/Library/stm32f4xx_syscfg.c
deleted file mode 100644
index 8f4c438..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_syscfg.c
+++ /dev/null
@@ -1,513 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_syscfg.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the SYSCFG peripheral.
- *
- @verbatim
-
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..] This driver provides functions for:
-
- (#) Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig()
-
- (#) Swapping the internal flash Bank1 and Bank2 this features is only visible for
- STM32F42xxx/43xxx devices Devices.
-
- (#) Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig()
-
- (#) Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig()
-
- -@- SYSCFG APB clock must be enabled to get write access to SYSCFG registers,
- using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_syscfg.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SYSCFG
- * @brief SYSCFG driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ------------ RCC registers bit address in the alias region ----------- */
-#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
-/* --- MEMRMP Register ---*/
-/* Alias word address of UFB_MODE bit */
-#define MEMRMP_OFFSET SYSCFG_OFFSET
-#define UFB_MODE_BitNumber ((uint8_t)0x8)
-#define UFB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BitNumber * 4))
-
-/* --- PMC Register ---*/
-/* Alias word address of MII_RMII_SEL bit */
-#define PMC_OFFSET (SYSCFG_OFFSET + 0x04)
-#define MII_RMII_SEL_BitNumber ((uint8_t)0x17)
-#define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
-
-/* --- CMPCR Register ---*/
-/* Alias word address of CMP_PD bit */
-#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20)
-#define CMP_PD_BitNumber ((uint8_t)0x00)
-#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4))
-
-/* --- MCHDLYCR Register ---*/
-/* Alias word address of BSCKSEL bit */
-#define MCHDLYCR_OFFSET (SYSCFG_OFFSET + 0x30)
-#define BSCKSEL_BIT_NUMBER POSITION_VAL(SYSCFG_MCHDLYCR_BSCKSEL)
-#define MCHDLYCR_BSCKSEL_BB (uint32_t)(PERIPH_BB_BASE + (MCHDLYCR_OFFSET * 32) + (BSCKSEL_BIT_NUMBER * 4))
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SYSCFG_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the Alternate Functions (remap and EXTI configuration)
- * registers to their default reset values.
- * @param None
- * @retval None
- */
-void SYSCFG_DeInit(void)
-{
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);
-}
-
-/**
- * @brief Changes the mapping of the specified pin.
- * @param SYSCFG_Memory: selects the memory remapping.
- * This parameter can be one of the following values:
- * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
- * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
- * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F405xx/407xx, STM32F415xx/417xx and STM32F413_423xx devices.
- * @arg SYSCFG_MemoryRemap_FMC: FMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F42xxx/43xxx devices.
- * @arg SYSCFG_MemoryRemap_ExtMEM: External Memory mapped at 0x00000000 for STM32F446xx/STM32F469_479xx devices.
- * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000
- * @arg SYSCFG_MemoryRemap_SDRAM: FMC (External SDRAM) mapped at 0x00000000 for STM32F42xxx/43xxx devices.
- * @retval None
- */
-void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
-{
- /* Check the parameters */
- assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));
-
- SYSCFG->MEMRMP = SYSCFG_MemoryRemap;
-}
-
-/**
- * @brief Enables or disables the Internal FLASH Bank Swapping.
- *
- * @note This function can be used only for STM32F42xxx/43xxx devices.
- *
- * @param NewState: new state of Internal FLASH Bank swapping.
- * This parameter can be one of the following values:
- * @arg ENABLE: Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
- * and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)
- * @arg DISABLE:(the default state) Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000)
- and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000)
- * @retval None
- */
-void SYSCFG_MemorySwappingBank(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) UFB_MODE_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Selects the GPIO pin used as EXTI Line.
- * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for
- * EXTI lines where x can be (A..K) for STM32F42xxx/43xxx devices, (A..I)
- * for STM32F405xx/407xx and STM32F415xx/417xx devices or (A, B, C, D and H)
- * for STM32401xx devices.
- *
- * @param EXTI_PinSourcex: specifies the EXTI line to be configured.
- * This parameter can be EXTI_PinSourcex where x can be (0..15, except
- * for EXTI_PortSourceGPIOI x can be (0..11) for STM32F405xx/407xx
- * and STM32F405xx/407xx devices and for EXTI_PortSourceGPIOK x can
- * be (0..7) for STM32F42xxx/43xxx devices.
- *
- * @retval None
- */
-void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
-{
- uint32_t tmp = 0x00;
-
- /* Check the parameters */
- assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
- assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
-
- tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
- SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
- SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
-}
-
-/**
- * @brief Selects the ETHERNET media interface
- * @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode.
- * This parameter can be one of the following values:
- * @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected
- * @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected
- * @retval None
- */
-void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface)
-{
- assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface));
- /* Configure MII_RMII selection bit */
- *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface;
-}
-
-/**
- * @brief Enables or disables the I/O Compensation Cell.
- * @note The I/O compensation cell can be used only when the device supply
- * voltage ranges from 2.4 to 3.6 V.
- * @param NewState: new state of the I/O Compensation Cell.
- * This parameter can be one of the following values:
- * @arg ENABLE: I/O compensation cell enabled
- * @arg DISABLE: I/O compensation cell power-down mode
- * @retval None
- */
-void SYSCFG_CompensationCellCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Checks whether the I/O Compensation Cell ready flag is set or not.
- * @param None
- * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET)
- */
-FlagStatus SYSCFG_GetCompensationCellStatus(void)
-{
- FlagStatus bitstatus = RESET;
-
- if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
-/**
- * @brief Connects the selected parameter to the break input of TIM1.
- * @note The selected configuration is locked and can be unlocked by system reset
- * @param SYSCFG_Break: selects the configuration to be connected to break
- * input of TIM1
- * This parameter can be any combination of the following values:
- * @arg SYSCFG_Break_PVD: PVD interrupt is connected to the break input of TIM1/8.
- * @arg SYSCFG_Break_HardFault: Lockup output of CortexM4 is connected to the break input of TIM1/8.
- * @retval None
- */
-void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
-{
- /* Check the parameter */
- assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));
-
- SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
-}
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */
-
-#if defined(STM32F413_423xx)
-/**
- * @brief Select the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
- * @param source: BITSTREAM_CLOCK_DFSDM2.
- * BITSTREAM_CLOCK_TIM2OC1.
- * @retval None
- */
-void DFSDM_BitstreamClock_SourceSelection(uint32_t source)
-{
- uint32_t tmp = 0;
-
- tmp = SYSCFG->MCHDLYCR;
- tmp = (tmp &(~SYSCFG_MCHDLYCR_BSCKSEL));
-
- SYSCFG->MCHDLYCR = (tmp|source);
-}
-
-/**
- * @brief Disable Delay Clock for DFSDM1/2.
- * @param MCHDLY: MCHDLY_CLOCK_DFSDM2.
- * MCHDLY_CLOCK_DFSDM1.
- * @retval None
- */
-void DFSDM_DisableDelayClock(uint32_t MCHDLY)
-{
- uint32_t tmp = 0;
-
- tmp = SYSCFG->MCHDLYCR;
- if(MCHDLY == MCHDLY_CLOCK_DFSDM2)
- {
- tmp =tmp &(~SYSCFG_MCHDLYCR_MCHDLY2EN);
- }
- else
- {
- tmp =tmp &(~SYSCFG_MCHDLYCR_MCHDLY1EN);
- }
-
- SYSCFG->MCHDLYCR = tmp;
-}
-
-/**
- * @brief Enable Delay Clock for DFSDM1/2.
- * @param MCHDLY: MCHDLY_CLOCK_DFSDM2.
- * MCHDLY_CLOCK_DFSDM1.
- * @retval None
- */
-void DFSDM_EnableDelayClock(uint32_t MCHDLY)
-{
- uint32_t tmp = 0;
-
- tmp = SYSCFG->MCHDLYCR;
- tmp = tmp & ~MCHDLY;
-
- SYSCFG->MCHDLYCR = (tmp|MCHDLY);
-}
-
-/**
- * @brief Select the source for CKin signals for DFSDM1/2.
- * @param source: DFSDM2_CKIN_PAD.
- * DFSDM2_CKIN_DM.
- * DFSDM1_CKIN_PAD.
- * DFSDM1_CKIN_DM.
- * @retval None
- */
-void DFSDM_ClockIn_SourceSelection(uint32_t source)
-{
- uint32_t tmp = 0;
-
- tmp = SYSCFG->MCHDLYCR;
- if((source == DFSDM2_CKIN_PAD) || (source == DFSDM2_CKIN_DM))
- {
- tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CFG);
- }
- else
- {
- tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CFG);
- }
-
- SYSCFG->MCHDLYCR |= (source|tmp);
-}
-
-/**
- * @brief Select the source for CKOut signals for DFSDM1/2.
- * @param source: DFSDM2_CKOUT_DFSDM2.
- * DFSDM2_CKOUT_M27.
- * DFSDM1_CKOUT_DFSDM1.
- * DFSDM1_CKOUT_M27.
- * @retval None
- */
-void DFSDM_ClockOut_SourceSelection(uint32_t source)
-{
- uint32_t tmp = 0;
-
- tmp = SYSCFG->MCHDLYCR;
-
- if((source == DFSDM2_CKOUT_DFSDM2) || (source == DFSDM2_CKOUT_M27))
- {
- tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CKOSEL);
- }
- else
- {
- tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CKOSEL);
- }
-
- SYSCFG->MCHDLYCR |= (source|tmp);
-}
-
-/**
- * @brief Select the source for DataIn0 signals for DFSDM1/2.
- * @param source: DATAIN0_DFSDM2_PAD.
- * DATAIN0_DFSDM2_DATAIN1.
- * DATAIN0_DFSDM1_PAD.
- * DATAIN0_DFSDM1_DATAIN1.
- * @retval None
- */
-void DFSDM_DataIn0_SourceSelection(uint32_t source)
-{
- uint32_t tmp = 0;
-
- tmp = SYSCFG->MCHDLYCR;
-
- if((source == DATAIN0_DFSDM2_PAD)|| (source == DATAIN0_DFSDM2_DATAIN1))
- {
- tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D0SEL);
- }
- else
- {
- tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1D0SEL);
- }
- SYSCFG->MCHDLYCR |= (source|tmp);
-}
-
-/**
- * @brief Select the source for DataIn2 signals for DFSDM1/2.
- * @param source: DATAIN2_DFSDM2_PAD.
- * DATAIN2_DFSDM2_DATAIN3.
- * DATAIN2_DFSDM1_PAD.
- * DATAIN2_DFSDM1_DATAIN3.
- * @retval None
- */
-void DFSDM_DataIn2_SourceSelection(uint32_t source)
-{
- uint32_t tmp = 0;
-
- tmp = SYSCFG->MCHDLYCR;
-
- if((source == DATAIN2_DFSDM2_PAD)|| (source == DATAIN2_DFSDM2_DATAIN3))
- {
- tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D2SEL);
- }
- else
- {
- tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1D2SEL);
- }
- SYSCFG->MCHDLYCR |= (source|tmp);
-}
-
-/**
- * @brief Select the source for DataIn4 signals for DFSDM2.
- * @param source: DATAIN4_DFSDM2_PAD.
- * DATAIN4_DFSDM2_DATAIN5
- * @retval None
- */
-void DFSDM_DataIn4_SourceSelection(uint32_t source)
-{
- uint32_t tmp = 0;
-
- tmp = SYSCFG->MCHDLYCR;
- tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D4SEL);
-
- SYSCFG->MCHDLYCR |= (source|tmp);
-}
-
-/**
- * @brief Select the source for DataIn6 signals for DFSDM2.
- * @param source: DATAIN6_DFSDM2_PAD.
- * DATAIN6_DFSDM2_DATAIN7.
- * @retval None
- */
-void DFSDM_DataIn6_SourceSelection(uint32_t source)
-{
- uint32_t tmp = 0;
-
- tmp = SYSCFG->MCHDLYCR;
-
- tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D6SEL);
-
- SYSCFG->MCHDLYCR |= (source|tmp);
-}
-
-/**
- * @brief Configure the distribution of the bitstream clock gated from TIM4.
- * @param source: DFSDM1_CLKIN0_TIM4OC2
- * DFSDM1_CLKIN2_TIM4OC2
- * DFSDM1_CLKIN1_TIM4OC1
- * DFSDM1_CLKIN3_TIM4OC1
- * @retval None
- */
-void DFSDM1_BitStreamClk_Config(uint32_t source)
-{
- uint32_t tmp = 0;
-
- tmp = SYSCFG->MCHDLYCR;
-
- if ((source == DFSDM1_CLKIN0_TIM4OC2) || (source == DFSDM1_CLKIN2_TIM4OC2))
- {
- tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CK02SEL);
- }
- else
- {
- tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CK13SEL);
- }
-
- SYSCFG->MCHDLYCR |= (source|tmp);
-}
-
-/**
- * @brief Configure the distribution of the bitstream clock gated from TIM3.
- * @param source: DFSDM2_CLKIN0_TIM3OC4
- * DFSDM2_CLKIN4_TIM3OC4
- * DFSDM2_CLKIN1_TIM3OC3
- * DFSDM2_CLKIN5_TIM3OC3
- * DFSDM2_CLKIN2_TIM3OC2
- * DFSDM2_CLKIN6_TIM3OC2
- * DFSDM2_CLKIN3_TIM3OC1
- * DFSDM2_CLKIN7_TIM3OC1
- * @retval None
- */
-void DFSDM2_BitStreamClk_Config(uint32_t source)
-{
- uint32_t tmp = 0;
-
- tmp = SYSCFG->MCHDLYCR;
-
- if ((source == DFSDM2_CLKIN0_TIM3OC4) || (source == DFSDM2_CLKIN4_TIM3OC4))
- {
- tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK04SEL);
- }
- else if ((source == DFSDM2_CLKIN1_TIM3OC3) || (source == DFSDM2_CLKIN5_TIM3OC3))
- {
- tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK15SEL);
-
- }else if ((source == DFSDM2_CLKIN2_TIM3OC2) || (source == DFSDM2_CLKIN6_TIM3OC2))
- {
- tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK26SEL);
- }
- else
- {
- tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK37SEL);
- }
-
- SYSCFG->MCHDLYCR |= (source|tmp);
-}
-
-#endif /* STM32F413_423xx */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_syscfg.h b/底盘/底盘-old/底盘/Library/stm32f4xx_syscfg.h
deleted file mode 100644
index 8f7484d..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_syscfg.h
+++ /dev/null
@@ -1,342 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_syscfg.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the SYSCFG firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_SYSCFG_H
-#define __STM32F4xx_SYSCFG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup SYSCFG
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SYSCFG_Exported_Constants
- * @{
- */
-#if defined(STM32F413_423xx)
-/** @defgroup BITSTREAM_CLOCK Bit Stream clock source selection
- * @{
- */
-#define BITSTREAM_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_BSCKSEL
-#define BITSTREAM_CLOCK_TIM2OC1 (uint32_t)0x00000000
-/**
- * @}
- */
-
-/** @defgroup MCHDLY_CLOCK MCHDLY Clock enable
- * @{
- */
-#define MCHDLY_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_MCHDLY2EN
-#define MCHDLY_CLOCK_DFSDM1 SYSCFG_MCHDLYCR_MCHDLY1EN
-/**
- * @}
- */
-
-/** @defgroup DFSDM_CLOCKIN_SOURCE DFSDM Clock In Source Selection
- * @{
- */
-#define DFSDM2_CKIN_PAD (uint32_t)0x00000000
-#define DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG
-#define DFSDM1_CKIN_PAD (uint32_t)0x00000000
-#define DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG
-/**
- * @}
- */
-
-/** @defgroup DFSDM_CLOCKOUT_SOURCE DFSDM Clock Source Selection
- * @{
- */
-#define DFSDM2_CKOUT_DFSDM2 (uint32_t)0x00000000
-#define DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL
-#define DFSDM1_CKOUT_DFSDM1 (uint32_t)0x00000000U
-#define DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL
-/**
- * @}
- */
-
-/** @defgroup DFSDM_DATAIN0_SOURCE DFSDM Source Selection For DATAIN0
- * @{
- */
-#define DATAIN0_DFSDM2_PAD (uint32_t)0x00000000
-#define DATAIN0_DFSDM2_DATAIN1 SYSCFG_MCHDLYCR_DFSDM2D0SEL
-#define DATAIN0_DFSDM1_PAD (uint32_t)0x00000000
-#define DATAIN0_DFSDM1_DATAIN1 SYSCFG_MCHDLYCR_DFSDM1D0SEL
-/**
- * @}
- */
-
-/** @defgroup DFSDM_DATAIN2_SOURCE DFSDM Source Selection For DATAIN2
- * @{
- */
-#define DATAIN2_DFSDM2_PAD (uint32_t)0x00000000
-#define DATAIN2_DFSDM2_DATAIN3 SYSCFG_MCHDLYCR_DFSDM2D2SEL
-#define DATAIN2_DFSDM1_PAD (uint32_t)0x00000000
-#define DATAIN2_DFSDM1_DATAIN3 SYSCFG_MCHDLYCR_DFSDM1D2SEL
-/**
- * @}
- */
-
-/** @defgroup DFSDM_DATAIN4_SOURCE DFSDM Source Selection For DATAIN4
- * @{
- */
-#define DATAIN4_DFSDM2_PAD (uint32_t)0x00000000
-#define DATAIN4_DFSDM2_DATAIN5 SYSCFG_MCHDLYCR_DFSDM2D4SEL
-/**
- * @}
- */
-
-/** @defgroup DFSDM_DATAIN6_SOURCE DFSDM Source Selection For DATAIN6
- * @{
- */
-#define DATAIN6_DFSDM2_PAD (uint32_t)0x00000000
-#define DATAIN6_DFSDM2_DATAIN7 SYSCFG_MCHDLYCR_DFSDM2D6SEL
-/**
- * @}
- */
-
-/** @defgroup DFSDM_CLKIN_SOURCE DFSDM1 Source Selection For CLKIN
- * @{
- */
-#define DFSDM1_CLKIN0_TIM4OC2 (uint32_t)0x00000000
-#define DFSDM1_CLKIN2_TIM4OC2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL
-#define DFSDM1_CLKIN1_TIM4OC1 (uint32_t)0x00000000
-#define DFSDM1_CLKIN3_TIM4OC1 SYSCFG_MCHDLYCR_DFSDM1CK13SEL
-/**
- * @}
- */
-
-/** @defgroup DFSDM_CLKIN_SOURCE DFSDM2 Source Selection For CLKIN
- * @{
- */
-#define DFSDM2_CLKIN0_TIM3OC4 (uint32_t)0x00000000
-#define DFSDM2_CLKIN4_TIM3OC4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL
-#define DFSDM2_CLKIN1_TIM3OC3 (uint32_t)0x00000000
-#define DFSDM2_CLKIN5_TIM3OC3 SYSCFG_MCHDLYCR_DFSDM2CK15SEL
-#define DFSDM2_CLKIN2_TIM3OC2 (uint32_t)0x00000000
-#define DFSDM2_CLKIN6_TIM3OC2 SYSCFG_MCHDLYCR_DFSDM2CK26SEL
-#define DFSDM2_CLKIN3_TIM3OC1 (uint32_t)0x00000000
-#define DFSDM2_CLKIN7_TIM3OC1 SYSCFG_MCHDLYCR_DFSDM2CK37SEL
-/**
- * @}
- */
-#endif /* STM32F413_423xx */
-
-/** @defgroup SYSCFG_EXTI_Port_Sources
- * @{
- */
-#define EXTI_PortSourceGPIOA ((uint8_t)0x00)
-#define EXTI_PortSourceGPIOB ((uint8_t)0x01)
-#define EXTI_PortSourceGPIOC ((uint8_t)0x02)
-#define EXTI_PortSourceGPIOD ((uint8_t)0x03)
-#define EXTI_PortSourceGPIOE ((uint8_t)0x04)
-#define EXTI_PortSourceGPIOF ((uint8_t)0x05)
-#define EXTI_PortSourceGPIOG ((uint8_t)0x06)
-#define EXTI_PortSourceGPIOH ((uint8_t)0x07)
-#define EXTI_PortSourceGPIOI ((uint8_t)0x08)
-#define EXTI_PortSourceGPIOJ ((uint8_t)0x09)
-#define EXTI_PortSourceGPIOK ((uint8_t)0x0A)
-
-#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOI) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOJ) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOK))
-
-/**
- * @}
- */
-
-
-/** @defgroup SYSCFG_EXTI_Pin_Sources
- * @{
- */
-#define EXTI_PinSource0 ((uint8_t)0x00)
-#define EXTI_PinSource1 ((uint8_t)0x01)
-#define EXTI_PinSource2 ((uint8_t)0x02)
-#define EXTI_PinSource3 ((uint8_t)0x03)
-#define EXTI_PinSource4 ((uint8_t)0x04)
-#define EXTI_PinSource5 ((uint8_t)0x05)
-#define EXTI_PinSource6 ((uint8_t)0x06)
-#define EXTI_PinSource7 ((uint8_t)0x07)
-#define EXTI_PinSource8 ((uint8_t)0x08)
-#define EXTI_PinSource9 ((uint8_t)0x09)
-#define EXTI_PinSource10 ((uint8_t)0x0A)
-#define EXTI_PinSource11 ((uint8_t)0x0B)
-#define EXTI_PinSource12 ((uint8_t)0x0C)
-#define EXTI_PinSource13 ((uint8_t)0x0D)
-#define EXTI_PinSource14 ((uint8_t)0x0E)
-#define EXTI_PinSource15 ((uint8_t)0x0F)
-#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
- ((PINSOURCE) == EXTI_PinSource1) || \
- ((PINSOURCE) == EXTI_PinSource2) || \
- ((PINSOURCE) == EXTI_PinSource3) || \
- ((PINSOURCE) == EXTI_PinSource4) || \
- ((PINSOURCE) == EXTI_PinSource5) || \
- ((PINSOURCE) == EXTI_PinSource6) || \
- ((PINSOURCE) == EXTI_PinSource7) || \
- ((PINSOURCE) == EXTI_PinSource8) || \
- ((PINSOURCE) == EXTI_PinSource9) || \
- ((PINSOURCE) == EXTI_PinSource10) || \
- ((PINSOURCE) == EXTI_PinSource11) || \
- ((PINSOURCE) == EXTI_PinSource12) || \
- ((PINSOURCE) == EXTI_PinSource13) || \
- ((PINSOURCE) == EXTI_PinSource14) || \
- ((PINSOURCE) == EXTI_PinSource15))
-/**
- * @}
- */
-
-
-/** @defgroup SYSCFG_Memory_Remap_Config
- * @{
- */
-#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
-#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)
-#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
-#define SYSCFG_MemoryRemap_SDRAM ((uint8_t)0x04)
-
-#if defined (STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
-#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)
-#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
-
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
-#define SYSCFG_MemoryRemap_FMC ((uint8_t)0x02)
-#endif /* STM32F427_437xx || STM32F429_439xx */
-
-#if defined (STM32F446xx) || defined (STM32F469_479xx)
-#define SYSCFG_MemoryRemap_ExtMEM ((uint8_t)0x02)
-#endif /* STM32F446xx || STM32F469_479xx */
-
-#if defined (STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
-#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
- ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
- ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
- ((REMAP) == SYSCFG_MemoryRemap_FSMC))
-#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
-
-#if defined (STM32F401xx) || defined (STM32F410xx) || defined (STM32F411xE)
-#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
- ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
- ((REMAP) == SYSCFG_MemoryRemap_SRAM))
-#endif /* STM32F401xx || STM32F410xx || STM32F411xE */
-
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
-#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
- ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
- ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
- ((REMAP) == SYSCFG_MemoryRemap_SDRAM) || \
- ((REMAP) == SYSCFG_MemoryRemap_FMC))
-#endif /* STM32F427_437xx || STM32F429_439xx */
-
-#if defined (STM32F446xx) || defined (STM32F469_479xx)
-#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
- ((REMAP) == SYSCFG_MemoryRemap_ExtMEM) || \
- ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
- ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
- ((REMAP) == SYSCFG_MemoryRemap_SDRAM))
-#endif /* STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
-#define SYSCFG_Break_PVD SYSCFG_CFGR2_PVDL
-#define SYSCFG_Break_HardFault SYSCFG_CFGR2_CLL
-
-#define IS_SYSCFG_LOCK_CONFIG(BREAK) (((BREAK) == SYSCFG_Break_PVD) || \
- ((BREAK) == SYSCFG_Break_HardFault))
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */
-/**
- * @}
- */
-
-
-/** @defgroup SYSCFG_ETHERNET_Media_Interface
- * @{
- */
-#define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000)
-#define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001)
-
-#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \
- ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-void SYSCFG_DeInit(void);
-void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);
-void SYSCFG_MemorySwappingBank(FunctionalState NewState);
-void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
-void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface);
-void SYSCFG_CompensationCellCmd(FunctionalState NewState);
-FlagStatus SYSCFG_GetCompensationCellStatus(void);
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
-void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */
-#if defined(STM32F413_423xx)
-void DFSDM_BitstreamClock_SourceSelection(uint32_t source);
-void DFSDM_DisableDelayClock(uint32_t MCHDLY);
-void DFSDM_EnableDelayClock(uint32_t MCHDLY);
-void DFSDM_ClockIn_SourceSelection(uint32_t source);
-void DFSDM_ClockOut_SourceSelection(uint32_t source);
-void DFSDM_DataIn0_SourceSelection(uint32_t source);
-void DFSDM_DataIn2_SourceSelection(uint32_t source);
-void DFSDM_DataIn4_SourceSelection(uint32_t source);
-void DFSDM_DataIn6_SourceSelection(uint32_t source);
-void DFSDM1_BitStreamClk_Config(uint32_t source);
-void DFSDM2_BitStreamClk_Config(uint32_t source);
-#endif /* STM32F413_423xx */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_SYSCFG_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_tim.c b/底盘/底盘-old/底盘/Library/stm32f4xx_tim.c
deleted file mode 100644
index c6b9023..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_tim.c
+++ /dev/null
@@ -1,3357 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_tim.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the TIM peripheral:
- * + TimeBase management
- * + Output Compare management
- * + Input Capture management
- * + Advanced-control timers (TIM1 and TIM8) specific features
- * + Interrupts, DMA and flags management
- * + Clocks management
- * + Synchronization management
- * + Specific interface management
- * + Specific remapping management
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- This driver provides functions to configure and program the TIM
- of all STM32F4xx devices.
- These functions are split in 9 groups:
-
- (#) TIM TimeBase management: this group includes all needed functions
- to configure the TM Timebase unit:
- (++) Set/Get Prescaler
- (++) Set/Get Autoreload
- (++) Counter modes configuration
- (++) Set Clock division
- (++) Select the One Pulse mode
- (++) Update Request Configuration
- (++) Update Disable Configuration
- (++) Auto-Preload Configuration
- (++) Enable/Disable the counter
-
- (#) TIM Output Compare management: this group includes all needed
- functions to configure the Capture/Compare unit used in Output
- compare mode:
- (++) Configure each channel, independently, in Output Compare mode
- (++) Select the output compare modes
- (++) Select the Polarities of each channel
- (++) Set/Get the Capture/Compare register values
- (++) Select the Output Compare Fast mode
- (++) Select the Output Compare Forced mode
- (++) Output Compare-Preload Configuration
- (++) Clear Output Compare Reference
- (++) Select the OCREF Clear signal
- (++) Enable/Disable the Capture/Compare Channels
-
- (#) TIM Input Capture management: this group includes all needed
- functions to configure the Capture/Compare unit used in
- Input Capture mode:
- (++) Configure each channel in input capture mode
- (++) Configure Channel1/2 in PWM Input mode
- (++) Set the Input Capture Prescaler
- (++) Get the Capture/Compare values
-
- (#) Advanced-control timers (TIM1 and TIM8) specific features
- (++) Configures the Break input, dead time, Lock level, the OSSI,
- the OSSR State and the AOE(automatic output enable)
- (++) Enable/Disable the TIM peripheral Main Outputs
- (++) Select the Commutation event
- (++) Set/Reset the Capture Compare Preload Control bit
-
- (#) TIM interrupts, DMA and flags management
- (++) Enable/Disable interrupt sources
- (++) Get flags status
- (++) Clear flags/ Pending bits
- (++) Enable/Disable DMA requests
- (++) Configure DMA burst mode
- (++) Select CaptureCompare DMA request
-
- (#) TIM clocks management: this group includes all needed functions
- to configure the clock controller unit:
- (++) Select internal/External clock
- (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx
-
- (#) TIM synchronization management: this group includes all needed
- functions to configure the Synchronization unit:
- (++) Select Input Trigger
- (++) Select Output Trigger
- (++) Select Master Slave Mode
- (++) ETR Configuration when used as external trigger
-
- (#) TIM specific interface management, this group includes all
- needed functions to use the specific TIM interface:
- (++) Encoder Interface Configuration
- (++) Select Hall Sensor
-
- (#) TIM specific remapping management includes the Remapping
- configuration of specific timers
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_tim.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup TIM
- * @brief TIM driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ---------------------- TIM registers bit mask ------------------------ */
-#define SMCR_ETR_MASK ((uint16_t)0x00FF)
-#define CCMR_OFFSET ((uint16_t)0x0018)
-#define CCER_CCE_SET ((uint16_t)0x0001)
-#define CCER_CCNE_SET ((uint16_t)0x0004)
-#define CCMR_OC13M_MASK ((uint16_t)0xFF8F)
-#define CCMR_OC24M_MASK ((uint16_t)0x8FFF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup TIM_Private_Functions
- * @{
- */
-
-/** @defgroup TIM_Group1 TimeBase management functions
- * @brief TimeBase management functions
- *
-@verbatim
- ===============================================================================
- ##### TimeBase management functions #####
- ===============================================================================
-
-
- ##### TIM Driver: how to use it in Timing(Time base) Mode #####
- ===============================================================================
- [..]
- To use the Timer in Timing(Time base) mode, the following steps are mandatory:
-
- (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
-
- (#) Fill the TIM_TimeBaseInitStruct with the desired parameters.
-
- (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit
- with the corresponding configuration
-
- (#) Enable the NVIC if you need to generate the update interrupt.
-
- (#) Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update)
-
- (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
-
- -@- All other functions can be used separately to modify, if needed,
- a specific feature of the Timer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the TIMx peripheral registers to their default reset values.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @retval None
-
- */
-void TIM_DeInit(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- if (TIMx == TIM1)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
- }
- else if (TIMx == TIM2)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
- }
- else if (TIMx == TIM3)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
- }
- else if (TIMx == TIM4)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
- }
- else if (TIMx == TIM5)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
- }
- else if (TIMx == TIM6)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
- }
- else if (TIMx == TIM7)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
- }
- else if (TIMx == TIM8)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
- }
- else if (TIMx == TIM9)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
- }
- else if (TIMx == TIM10)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
- }
- else if (TIMx == TIM11)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
- }
- else if (TIMx == TIM12)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);
- }
- else if (TIMx == TIM13)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);
- }
- else
- {
- if (TIMx == TIM14)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the TIMx Time Base Unit peripheral according to
- * the specified parameters in the TIM_TimeBaseInitStruct.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
- uint16_t tmpcr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
- assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
-
- tmpcr1 = TIMx->CR1;
-
- if((TIMx == TIM1) || (TIMx == TIM8)||
- (TIMx == TIM2) || (TIMx == TIM3)||
- (TIMx == TIM4) || (TIMx == TIM5))
- {
- /* Select the Counter Mode */
- tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS));
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
- }
-
- if((TIMx != TIM6) && (TIMx != TIM7))
- {
- /* Set the clock division */
- tmpcr1 &= (uint16_t)(~TIM_CR1_CKD);
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
- }
-
- TIMx->CR1 = tmpcr1;
-
- /* Set the Autoreload value */
- TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
-
- /* Set the Prescaler value */
- TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
-
- if ((TIMx == TIM1) || (TIMx == TIM8))
- {
- /* Set the Repetition Counter value */
- TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
- }
-
- /* Generate an update event to reload the Prescaler
- and the repetition counter(only for TIM1 and TIM8) value immediately */
- TIMx->EGR = TIM_PSCReloadMode_Immediate;
-}
-
-/**
- * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
- * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
- * structure which will be initialized.
- * @retval None
- */
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
- /* Set the default configuration */
- TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
- TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
- TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
- TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
- TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
-}
-
-/**
- * @brief Configures the TIMx Prescaler.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param Prescaler: specifies the Prescaler Register value
- * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
- * This parameter can be one of the following values:
- * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
- * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
- * @retval None
- */
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
- /* Set the Prescaler value */
- TIMx->PSC = Prescaler;
- /* Set or reset the UG Bit */
- TIMx->EGR = TIM_PSCReloadMode;
-}
-
-/**
- * @brief Specifies the TIMx Counter Mode to be used.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_CounterMode: specifies the Counter Mode to be used
- * This parameter can be one of the following values:
- * @arg TIM_CounterMode_Up: TIM Up Counting Mode
- * @arg TIM_CounterMode_Down: TIM Down Counting Mode
- * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
- * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
- * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
- * @retval None
- */
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
-{
- uint16_t tmpcr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
-
- tmpcr1 = TIMx->CR1;
-
- /* Reset the CMS and DIR Bits */
- tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS);
-
- /* Set the Counter Mode */
- tmpcr1 |= TIM_CounterMode;
-
- /* Write to TIMx CR1 register */
- TIMx->CR1 = tmpcr1;
-}
-
-/**
- * @brief Sets the TIMx Counter Register value
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param Counter: specifies the Counter register new value.
- * @retval None
- */
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Set the Counter Register value */
- TIMx->CNT = Counter;
-}
-
-/**
- * @brief Sets the TIMx Autoreload Register value
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param Autoreload: specifies the Autoreload register new value.
- * @retval None
- */
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Set the Autoreload Register value */
- TIMx->ARR = Autoreload;
-}
-
-/**
- * @brief Gets the TIMx Counter value.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @retval Counter Register value
- */
-uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Get the Counter Register value */
- return TIMx->CNT;
-}
-
-/**
- * @brief Gets the TIMx Prescaler value.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @retval Prescaler Register value.
- */
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Get the Prescaler Register value */
- return TIMx->PSC;
-}
-
-/**
- * @brief Enables or Disables the TIMx Update event.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param NewState: new state of the TIMx UDIS bit
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the Update Disable Bit */
- TIMx->CR1 |= TIM_CR1_UDIS;
- }
- else
- {
- /* Reset the Update Disable Bit */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS;
- }
-}
-
-/**
- * @brief Configures the TIMx Update Request Interrupt source.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_UpdateSource: specifies the Update source.
- * This parameter can be one of the following values:
- * @arg TIM_UpdateSource_Global: Source of update is the counter
- * overflow/underflow or the setting of UG bit, or an update
- * generation through the slave mode controller.
- * @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow.
- * @retval None
- */
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
-
- if (TIM_UpdateSource != TIM_UpdateSource_Global)
- {
- /* Set the URS Bit */
- TIMx->CR1 |= TIM_CR1_URS;
- }
- else
- {
- /* Reset the URS Bit */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_URS;
- }
-}
-
-/**
- * @brief Enables or disables TIMx peripheral Preload register on ARR.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param NewState: new state of the TIMx peripheral Preload register
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the ARR Preload Bit */
- TIMx->CR1 |= TIM_CR1_ARPE;
- }
- else
- {
- /* Reset the ARR Preload Bit */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE;
- }
-}
-
-/**
- * @brief Selects the TIMx's One Pulse Mode.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_OPMode: specifies the OPM Mode to be used.
- * This parameter can be one of the following values:
- * @arg TIM_OPMode_Single
- * @arg TIM_OPMode_Repetitive
- * @retval None
- */
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
-
- /* Reset the OPM Bit */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM;
-
- /* Configure the OPM Mode */
- TIMx->CR1 |= TIM_OPMode;
-}
-
-/**
- * @brief Sets the TIMx Clock Division value.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_CKD: specifies the clock division value.
- * This parameter can be one of the following value:
- * @arg TIM_CKD_DIV1: TDTS = Tck_tim
- * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
- * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
- * @retval None
- */
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_CKD_DIV(TIM_CKD));
-
- /* Reset the CKD Bits */
- TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD);
-
- /* Set the CKD value */
- TIMx->CR1 |= TIM_CKD;
-}
-
-/**
- * @brief Enables or disables the specified TIM peripheral.
- * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral.
- * @param NewState: new state of the TIMx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TIM Counter */
- TIMx->CR1 |= TIM_CR1_CEN;
- }
- else
- {
- /* Disable the TIM Counter */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group2 Output Compare management functions
- * @brief Output Compare management functions
- *
-@verbatim
- ===============================================================================
- ##### Output Compare management functions #####
- ===============================================================================
-
-
- ##### TIM Driver: how to use it in Output Compare Mode #####
- ===============================================================================
- [..]
- To use the Timer in Output Compare mode, the following steps are mandatory:
-
- (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE)
- function
-
- (#) Configure the TIM pins by configuring the corresponding GPIO pins
-
- (#) Configure the Time base unit as described in the first part of this driver,
- (++) if needed, else the Timer will run with the default configuration:
- Autoreload value = 0xFFFF
- (++) Prescaler value = 0x0000
- (++) Counter mode = Up counting
- (++) Clock Division = TIM_CKD_DIV1
-
- (#) Fill the TIM_OCInitStruct with the desired parameters including:
- (++) The TIM Output Compare mode: TIM_OCMode
- (++) TIM Output State: TIM_OutputState
- (++) TIM Pulse value: TIM_Pulse
- (++) TIM Output Compare Polarity : TIM_OCPolarity
-
- (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired
- channel with the corresponding configuration
-
- (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
-
- -@- All other functions can be used separately to modify, if needed,
- a specific feature of the Timer.
-
- -@- In case of PWM mode, this function is mandatory:
- TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE);
-
- -@- If the corresponding interrupt or DMA request are needed, the user should:
- (+@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).
- (+@) Enable the corresponding interrupt (or DMA request) using the function
- TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the TIMx Channel1 according to the specified parameters in
- * the TIM_OCInitStruct.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M;
- tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S;
- /* Select the Output Compare Mode */
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC1P;
- /* Set the Output Compare Polarity */
- tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
-
- /* Set the Output State */
- tmpccer |= TIM_OCInitStruct->TIM_OutputState;
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC1NP;
- /* Set the Output N Polarity */
- tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
- /* Reset the Output N State */
- tmpccer &= (uint16_t)~TIM_CCER_CC1NE;
-
- /* Set the Output N State */
- tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS1;
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N;
- /* Set the Output Idle state */
- tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
- /* Set the Output N Idle state */
- tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel2 according to the specified parameters
- * in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M;
- tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC2P;
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC2NP;
- /* Set the Output N Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
- /* Reset the Output N State */
- tmpccer &= (uint16_t)~TIM_CCER_CC2NE;
-
- /* Set the Output N State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS2;
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N;
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
- /* Set the Output N Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel3 according to the specified parameters
- * in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 3: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M;
- tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S;
- /* Select the Output Compare Mode */
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC3P;
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC3NP;
- /* Set the Output N Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
- /* Reset the Output N State */
- tmpccer &= (uint16_t)~TIM_CCER_CC3NE;
-
- /* Set the Output N State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS3;
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N;
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
- /* Set the Output N Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel4 according to the specified parameters
- * in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M;
- tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC4P;
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
- /* Reset the Output Compare IDLE State */
- tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4;
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Fills each TIM_OCInitStruct member with its default value.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- /* Set the default configuration */
- TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
- TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
- TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
- TIM_OCInitStruct->TIM_Pulse = 0x00000000;
- TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
- TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
- TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
- TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
-}
-
-/**
- * @brief Selects the TIM Output Compare Mode.
- * @note This function disables the selected channel before changing the Output
- * Compare Mode. If needed, user has to enable this channel using
- * TIM_CCxCmd() and TIM_CCxNCmd() functions.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param TIM_OCMode: specifies the TIM Output Compare Mode.
- * This parameter can be one of the following values:
- * @arg TIM_OCMode_Timing
- * @arg TIM_OCMode_Active
- * @arg TIM_OCMode_Toggle
- * @arg TIM_OCMode_PWM1
- * @arg TIM_OCMode_PWM2
- * @arg TIM_ForcedAction_Active
- * @arg TIM_ForcedAction_InActive
- * @retval None
- */
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
-{
- uint32_t tmp = 0;
- uint16_t tmp1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_OCM(TIM_OCMode));
-
- tmp = (uint32_t) TIMx;
- tmp += CCMR_OFFSET;
-
- tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
-
- /* Disable the Channel: Reset the CCxE Bit */
- TIMx->CCER &= (uint16_t) ~tmp1;
-
- if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
- {
- tmp += (TIM_Channel>>1);
-
- /* Reset the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK;
-
- /* Configure the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp |= TIM_OCMode;
- }
- else
- {
- tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
-
- /* Reset the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK;
-
- /* Configure the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
- }
-}
-
-/**
- * @brief Sets the TIMx Capture Compare1 Register value
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param Compare1: specifies the Capture Compare1 register new value.
- * @retval None
- */
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
-
- /* Set the Capture Compare1 Register value */
- TIMx->CCR1 = Compare1;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare2 Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param Compare2: specifies the Capture Compare2 register new value.
- * @retval None
- */
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-
- /* Set the Capture Compare2 Register value */
- TIMx->CCR2 = Compare2;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare3 Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param Compare3: specifies the Capture Compare3 register new value.
- * @retval None
- */
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Set the Capture Compare3 Register value */
- TIMx->CCR3 = Compare3;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare4 Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param Compare4: specifies the Capture Compare4 register new value.
- * @retval None
- */
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Set the Capture Compare4 Register value */
- TIMx->CCR4 = Compare4;
-}
-
-/**
- * @brief Forces the TIMx output 1 waveform to active or inactive level.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC1REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
- * @retval None
- */
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1M Bits */
- tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M;
-
- /* Configure The Forced output Mode */
- tmpccmr1 |= TIM_ForcedAction;
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Forces the TIMx output 2 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC2REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
- * @retval None
- */
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2M Bits */
- tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M;
-
- /* Configure The Forced output Mode */
- tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Forces the TIMx output 3 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC3REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
- * @retval None
- */
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC1M Bits */
- tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M;
-
- /* Configure The Forced output Mode */
- tmpccmr2 |= TIM_ForcedAction;
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Forces the TIMx output 4 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC4REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
- * @retval None
- */
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC2M Bits */
- tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M;
-
- /* Configure The Forced output Mode */
- tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1PE Bit */
- tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE);
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr1 |= TIM_OCPreload;
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2PE Bit */
- tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE);
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC3PE Bit */
- tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE);
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr2 |= TIM_OCPreload;
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC4PE Bit */
- tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE);
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 1 Fast feature.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1FE Bit */
- tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE;
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr1 |= TIM_OCFast;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 2 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2FE Bit */
- tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE);
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 3 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC3FE Bit */
- tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE;
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr2 |= TIM_OCFast;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 4 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC4FE Bit */
- tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE);
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Clears or safeguards the OCREF1 signal on an external event
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1CE Bit */
- tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr1 |= TIM_OCClear;
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Clears or safeguards the OCREF2 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2CE Bit */
- tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Clears or safeguards the OCREF3 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC3CE Bit */
- tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr2 |= TIM_OCClear;
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Clears or safeguards the OCREF4 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC4CE Bit */
- tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx channel 1 polarity.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC1 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC1P Bit */
- tmpccer &= (uint16_t)(~TIM_CCER_CC1P);
- tmpccer |= TIM_OCPolarity;
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 1N polarity.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC1N Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC1NP Bit */
- tmpccer &= (uint16_t)~TIM_CCER_CC1NP;
- tmpccer |= TIM_OCNPolarity;
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 2 polarity.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_OCPolarity: specifies the OC2 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC2P Bit */
- tmpccer &= (uint16_t)(~TIM_CCER_CC2P);
- tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 2N polarity.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC2N Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC2NP Bit */
- tmpccer &= (uint16_t)~TIM_CCER_CC2NP;
- tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 3 polarity.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC3 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC3P Bit */
- tmpccer &= (uint16_t)~TIM_CCER_CC3P;
- tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 3N polarity.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC3N Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC3NP Bit */
- tmpccer &= (uint16_t)~TIM_CCER_CC3NP;
- tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 4 polarity.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC4 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC4P Bit */
- tmpccer &= (uint16_t)~TIM_CCER_CC4P;
- tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel x.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
- * @retval None
- */
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
-{
- uint16_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_CCX(TIM_CCx));
-
- tmp = CCER_CCE_SET << TIM_Channel;
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= (uint16_t)~ tmp;
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel xN.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
- * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
- * @retval None
- */
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
-{
- uint16_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_CCXN(TIM_CCxN));
-
- tmp = CCER_CCNE_SET << TIM_Channel;
-
- /* Reset the CCxNE Bit */
- TIMx->CCER &= (uint16_t) ~tmp;
-
- /* Set or reset the CCxNE Bit */
- TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group3 Input Capture management functions
- * @brief Input Capture management functions
- *
-@verbatim
- ===============================================================================
- ##### Input Capture management functions #####
- ===============================================================================
-
- ##### TIM Driver: how to use it in Input Capture Mode #####
- ===============================================================================
- [..]
- To use the Timer in Input Capture mode, the following steps are mandatory:
-
- (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE)
- function
-
- (#) Configure the TIM pins by configuring the corresponding GPIO pins
-
- (#) Configure the Time base unit as described in the first part of this driver,
- if needed, else the Timer will run with the default configuration:
- (++) Autoreload value = 0xFFFF
- (++) Prescaler value = 0x0000
- (++) Counter mode = Up counting
- (++) Clock Division = TIM_CKD_DIV1
-
- (#) Fill the TIM_ICInitStruct with the desired parameters including:
- (++) TIM Channel: TIM_Channel
- (++) TIM Input Capture polarity: TIM_ICPolarity
- (++) TIM Input Capture selection: TIM_ICSelection
- (++) TIM Input Capture Prescaler: TIM_ICPrescaler
- (++) TIM Input Capture filter value: TIM_ICFilter
-
- (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel
- with the corresponding configuration and to measure only frequency
- or duty cycle of the input signal, or, Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct)
- to configure the desired channels with the corresponding configuration
- and to measure the frequency and the duty cycle of the input signal
-
- (#) Enable the NVIC or the DMA to read the measured frequency.
-
- (#) Enable the corresponding interrupt (or DMA request) to read the Captured
- value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx)
- (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
-
- (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
-
- (#) Use TIM_GetCapturex(TIMx); to read the captured value.
-
- -@- All other functions can be used separately to modify, if needed,
- a specific feature of the Timer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the TIM peripheral according to the specified parameters
- * in the TIM_ICInitStruct.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
- assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
- assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
-
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
- {
- /* TI1 Configuration */
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
- {
- /* TI2 Configuration */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
- {
- /* TI3 Configuration */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else
- {
- /* TI4 Configuration */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
-}
-
-/**
- * @brief Fills each TIM_ICInitStruct member with its default value.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- /* Set the default configuration */
- TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
- TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
- TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
- TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
- TIM_ICInitStruct->TIM_ICFilter = 0x00;
-}
-
-/**
- * @brief Configures the TIM peripheral according to the specified parameters
- * in the TIM_ICInitStruct to measure an external PWM signal.
- * @param TIMx: where x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
- uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-
- /* Select the Opposite Input Polarity */
- if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
- {
- icoppositepolarity = TIM_ICPolarity_Falling;
- }
- else
- {
- icoppositepolarity = TIM_ICPolarity_Rising;
- }
- /* Select the Opposite Input */
- if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
- {
- icoppositeselection = TIM_ICSelection_IndirectTI;
- }
- else
- {
- icoppositeselection = TIM_ICSelection_DirectTI;
- }
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
- {
- /* TI1 Configuration */
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- /* TI2 Configuration */
- TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else
- {
- /* TI2 Configuration */
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- /* TI1 Configuration */
- TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
-}
-
-/**
- * @brief Gets the TIMx Input Capture 1 value.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @retval Capture Compare 1 Register value.
- */
-uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
-
- /* Get the Capture 1 Register value */
- return TIMx->CCR1;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 2 value.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @retval Capture Compare 2 Register value.
- */
-uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-
- /* Get the Capture 2 Register value */
- return TIMx->CCR2;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 3 value.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @retval Capture Compare 3 Register value.
- */
-uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Get the Capture 3 Register value */
- return TIMx->CCR3;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 4 value.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @retval Capture Compare 4 Register value.
- */
-uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Get the Capture 4 Register value */
- return TIMx->CCR4;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 1 prescaler.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC1PSC Bits */
- TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC;
-
- /* Set the IC1PSC value */
- TIMx->CCMR1 |= TIM_ICPSC;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 2 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC2PSC Bits */
- TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC;
-
- /* Set the IC2PSC value */
- TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
-}
-
-/**
- * @brief Sets the TIMx Input Capture 3 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC3PSC Bits */
- TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC;
-
- /* Set the IC3PSC value */
- TIMx->CCMR2 |= TIM_ICPSC;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 4 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC4PSC Bits */
- TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC;
-
- /* Set the IC4PSC value */
- TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features
- * @brief Advanced-control timers (TIM1 and TIM8) specific features
- *
-@verbatim
- ===============================================================================
- ##### Advanced-control timers (TIM1 and TIM8) specific features #####
- ===============================================================================
-
- ##### TIM Driver: how to use the Break feature #####
- ===============================================================================
- [..]
- After configuring the Timer channel(s) in the appropriate Output Compare mode:
-
- (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
- Break Polarity, dead time, Lock level, the OSSI/OSSR State and the
- AOE(automatic output enable).
-
- (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer
-
- (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE)
-
- (#) Once the break even occurs, the Timer's output signals are put in reset
- state or in a known state (according to the configuration made in
- TIM_BDTRConfig() function).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
- * and the AOE(automatic output enable).
- * @param TIMx: where x can be 1 or 8 to select the TIM
- * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
- * contains the BDTR Register configuration information for the TIM peripheral.
- * @retval None
- */
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
- assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
- assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
- assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
- assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
- assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
-
- /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
- TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
- TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
- TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
- TIM_BDTRInitStruct->TIM_AutomaticOutput;
-}
-
-/**
- * @brief Fills each TIM_BDTRInitStruct member with its default value.
- * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
-{
- /* Set the default configuration */
- TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
- TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
- TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
- TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
- TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
- TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
- TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
-}
-
-/**
- * @brief Enables or disables the TIM peripheral Main Outputs.
- * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral.
- * @param NewState: new state of the TIM peripheral Main Outputs.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TIM Main Output */
- TIMx->BDTR |= TIM_BDTR_MOE;
- }
- else
- {
- /* Disable the TIM Main Output */
- TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE;
- }
-}
-
-/**
- * @brief Selects the TIM peripheral Commutation event.
- * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
- * @param NewState: new state of the Commutation event.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the COM Bit */
- TIMx->CR2 |= TIM_CR2_CCUS;
- }
- else
- {
- /* Reset the COM Bit */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS;
- }
-}
-
-/**
- * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
- * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
- * @param NewState: new state of the Capture Compare Preload Control bit
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the CCPC Bit */
- TIMx->CR2 |= TIM_CR2_CCPC;
- }
- else
- {
- /* Reset the CCPC Bit */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group5 Interrupts DMA and flags management functions
- * @brief Interrupts, DMA and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts, DMA and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified TIM interrupts.
- * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral.
- * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg TIM_IT_Update: TIM update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- *
- * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used
- * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update,
- * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
- * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can
- * be used: TIM_IT_Update or TIM_IT_CC1
- * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8
- *
- * @param NewState: new state of the TIM interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_IT(TIM_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Interrupt sources */
- TIMx->DIER |= TIM_IT;
- }
- else
- {
- /* Disable the Interrupt sources */
- TIMx->DIER &= (uint16_t)~TIM_IT;
- }
-}
-
-/**
- * @brief Configures the TIMx event to be generate by software.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_EventSource: specifies the event source.
- * This parameter can be one or more of the following values:
- * @arg TIM_EventSource_Update: Timer update Event source
- * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
- * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
- * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
- * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
- * @arg TIM_EventSource_COM: Timer COM event source
- * @arg TIM_EventSource_Trigger: Timer Trigger Event source
- * @arg TIM_EventSource_Break: Timer Break event source
- *
- * @note TIM6 and TIM7 can only generate an update event.
- * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
- *
- * @retval None
- */
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
-
- /* Set the event sources */
- TIMx->EGR = TIM_EventSource;
-}
-
-/**
- * @brief Checks whether the specified TIM flag is set or not.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_Update: TIM update Flag
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
- * @arg TIM_FLAG_COM: TIM Commutation Flag
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag
- * @arg TIM_FLAG_Break: TIM Break Flag
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
- *
- * @note TIM6 and TIM7 can have only one update flag.
- * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
- *
- * @retval The new state of TIM_FLAG (SET or RESET).
- */
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
-
-
- if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the TIMx's pending flags.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_FLAG: specifies the flag bit to clear.
- * This parameter can be any combination of the following values:
- * @arg TIM_FLAG_Update: TIM update Flag
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
- * @arg TIM_FLAG_COM: TIM Commutation Flag
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag
- * @arg TIM_FLAG_Break: TIM Break Flag
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
- *
- * @note TIM6 and TIM7 can have only one update flag.
- * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
- *
- * @retval None
- */
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Clear the flags */
- TIMx->SR = (uint16_t)~TIM_FLAG;
-}
-
-/**
- * @brief Checks whether the TIM interrupt has occurred or not.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_IT: specifies the TIM interrupt source to check.
- * This parameter can be one of the following values:
- * @arg TIM_IT_Update: TIM update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- *
- * @note TIM6 and TIM7 can generate only an update interrupt.
- * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
- *
- * @retval The new state of the TIM_IT(SET or RESET).
- */
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itstatus = 0x0, itenable = 0x0;
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_GET_IT(TIM_IT));
-
- itstatus = TIMx->SR & TIM_IT;
-
- itenable = TIMx->DIER & TIM_IT;
- if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the TIMx's interrupt pending bits.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_IT: specifies the pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg TIM_IT_Update: TIM1 update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- *
- * @note TIM6 and TIM7 can generate only an update interrupt.
- * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
- *
- * @retval None
- */
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Clear the IT pending Bit */
- TIMx->SR = (uint16_t)~TIM_IT;
-}
-
-/**
- * @brief Configures the TIMx's DMA interface.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_DMABase: DMA Base address.
- * This parameter can be one of the following values:
- * @arg TIM_DMABase_CR1
- * @arg TIM_DMABase_CR2
- * @arg TIM_DMABase_SMCR
- * @arg TIM_DMABase_DIER
- * @arg TIM1_DMABase_SR
- * @arg TIM_DMABase_EGR
- * @arg TIM_DMABase_CCMR1
- * @arg TIM_DMABase_CCMR2
- * @arg TIM_DMABase_CCER
- * @arg TIM_DMABase_CNT
- * @arg TIM_DMABase_PSC
- * @arg TIM_DMABase_ARR
- * @arg TIM_DMABase_RCR
- * @arg TIM_DMABase_CCR1
- * @arg TIM_DMABase_CCR2
- * @arg TIM_DMABase_CCR3
- * @arg TIM_DMABase_CCR4
- * @arg TIM_DMABase_BDTR
- * @arg TIM_DMABase_DCR
- * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value
- * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
- * @retval None
- */
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
- assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
-
- /* Set the DMA Base and the DMA Burst Length */
- TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
-}
-
-/**
- * @brief Enables or disables the TIMx's DMA Requests.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
- * @param TIM_DMASource: specifies the DMA Request sources.
- * This parameter can be any combination of the following values:
- * @arg TIM_DMA_Update: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_Trigger: TIM Trigger DMA source
- * @param NewState: new state of the DMA Request sources.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST5_PERIPH(TIMx));
- assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DMA sources */
- TIMx->DIER |= TIM_DMASource;
- }
- else
- {
- /* Disable the DMA sources */
- TIMx->DIER &= (uint16_t)~TIM_DMASource;
- }
-}
-
-/**
- * @brief Selects the TIMx peripheral Capture Compare DMA source.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param NewState: new state of the Capture Compare DMA source
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the CCDS Bit */
- TIMx->CR2 |= TIM_CR2_CCDS;
- }
- else
- {
- /* Reset the CCDS Bit */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group6 Clocks management functions
- * @brief Clocks management functions
- *
-@verbatim
- ===============================================================================
- ##### Clocks management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the TIMx internal Clock
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @retval None
- */
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-
- /* Disable slave mode to clock the prescaler directly with the internal clock */
- TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;
-}
-
-/**
- * @brief Configures the TIMx Internal Trigger as External Clock
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_InputTriggerSource: Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal Trigger 0
- * @arg TIM_TS_ITR1: Internal Trigger 1
- * @arg TIM_TS_ITR2: Internal Trigger 2
- * @arg TIM_TS_ITR3: Internal Trigger 3
- * @retval None
- */
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
-
- /* Select the Internal Trigger */
- TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
-
- /* Select the External clock mode1 */
- TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
- * @brief Configures the TIMx Trigger as External Clock
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
- * to select the TIM peripheral.
- * @param TIM_TIxExternalCLKSource: Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
- * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
- * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
- * @param TIM_ICPolarity: specifies the TIx Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param ICFilter: specifies the filter value.
- * This parameter must be a value between 0x0 and 0xF.
- * @retval None
- */
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
- uint16_t TIM_ICPolarity, uint16_t ICFilter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
- assert_param(IS_TIM_IC_FILTER(ICFilter));
-
- /* Configure the Timer Input Clock Source */
- if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
- {
- TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
- }
- else
- {
- TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
- }
- /* Select the Trigger source */
- TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
- /* Select the External clock mode1 */
- TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
- * @brief Configures the External clock Mode1
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
- /* Configure the ETR Clock source */
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the SMS Bits */
- tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
-
- /* Select the External clock mode1 */
- tmpsmcr |= TIM_SlaveMode_External1;
-
- /* Select the Trigger selection : ETRF */
- tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
- tmpsmcr |= TIM_TS_ETRF;
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Configures the External clock Mode2
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-
- /* Enable the External clock mode2 */
- TIMx->SMCR |= TIM_SMCR_ECE;
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group7 Synchronization management functions
- * @brief Synchronization management functions
- *
-@verbatim
- ===============================================================================
- ##### Synchronization management functions #####
- ===============================================================================
-
- ##### TIM Driver: how to use it in synchronization Mode #####
- ===============================================================================
- [..]
-
- *** Case of two/several Timers ***
- ==================================
- [..]
- (#) Configure the Master Timers using the following functions:
- (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
- (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
- (#) Configure the Slave Timers using the following functions:
- (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
- (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
-
- *** Case of Timers and external trigger(ETR pin) ***
- ====================================================
- [..]
- (#) Configure the External trigger using this function:
- (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter);
- (#) Configure the Slave Timers using the following functions:
- (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
- (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Selects the Input Trigger source
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
- * to select the TIM peripheral.
- * @param TIM_InputTriggerSource: The Input Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal Trigger 0
- * @arg TIM_TS_ITR1: Internal Trigger 1
- * @arg TIM_TS_ITR2: Internal Trigger 2
- * @arg TIM_TS_ITR3: Internal Trigger 3
- * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
- * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
- * @arg TIM_TS_ETRF: External Trigger input
- * @retval None
- */
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the TS Bits */
- tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
-
- /* Set the Input Trigger source */
- tmpsmcr |= TIM_InputTriggerSource;
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Selects the TIMx Trigger Output Mode.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
- *
- * @param TIM_TRGOSource: specifies the Trigger Output source.
- * This parameter can be one of the following values:
- *
- * - For all TIMx
- * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO)
- *
- * - For all TIMx except TIM6 and TIM7
- * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
- * is to be set, as soon as a capture or compare match occurs(TRGO)
- * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO)
- *
- * @retval None
- */
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST5_PERIPH(TIMx));
- assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
-
- /* Reset the MMS Bits */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS;
- /* Select the TRGO source */
- TIMx->CR2 |= TIM_TRGOSource;
-}
-
-/**
- * @brief Selects the TIMx Slave Mode.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
- * @param TIM_SlaveMode: specifies the Timer Slave Mode.
- * This parameter can be one of the following values:
- * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize
- * the counter and triggers an update of the registers
- * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high
- * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI
- * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter
- * @retval None
- */
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
-
- /* Reset the SMS Bits */
- TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;
-
- /* Select the Slave Mode */
- TIMx->SMCR |= TIM_SlaveMode;
-}
-
-/**
- * @brief Sets or Resets the TIMx Master/Slave Mode.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
- * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
- * This parameter can be one of the following values:
- * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
- * and its slaves (through TRGO)
- * @arg TIM_MasterSlaveMode_Disable: No action
- * @retval None
- */
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
-
- /* Reset the MSM Bit */
- TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM;
-
- /* Set or Reset the MSM Bit */
- TIMx->SMCR |= TIM_MasterSlaveMode;
-}
-
-/**
- * @brief Configures the TIMx External Trigger (ETR).
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the ETR Bits */
- tmpsmcr &= SMCR_ETR_MASK;
-
- /* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group8 Specific interface management functions
- * @brief Specific interface management functions
- *
-@verbatim
- ===============================================================================
- ##### Specific interface management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the TIMx Encoder Interface.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
- * This parameter can be one of the following values:
- * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
- * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
- * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
- * on the level of the other input.
- * @param TIM_IC1Polarity: specifies the IC1 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Falling: IC Falling edge.
- * @arg TIM_ICPolarity_Rising: IC Rising edge.
- * @param TIM_IC2Polarity: specifies the IC2 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Falling: IC Falling edge.
- * @arg TIM_ICPolarity_Rising: IC Rising edge.
- * @retval None
- */
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
-{
- uint16_t tmpsmcr = 0;
- uint16_t tmpccmr1 = 0;
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
- assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
- assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
-
- /* Set the encoder Mode */
- tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
- tmpsmcr |= TIM_EncoderMode;
-
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */
- tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S);
- tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
-
- /* Set the TI1 and the TI2 Polarities */
- tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P);
- tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Enables or disables the TIMx's Hall sensor interface.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param NewState: new state of the TIMx Hall sensor interface.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the TI1S Bit */
- TIMx->CR2 |= TIM_CR2_TI1S;
- }
- else
- {
- /* Reset the TI1S Bit */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group9 Specific remapping management function
- * @brief Specific remapping management function
- *
-@verbatim
- ===============================================================================
- ##### Specific remapping management function #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
- * @param TIMx: where x can be 2, 5 or 11 to select the TIM peripheral.
- * @param TIM_Remap: specifies the TIM input remapping source.
- * This parameter can be one of the following values:
- * @arg TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
- * @arg TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.
- * @arg TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
- * @arg TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
- * @arg TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
- * @arg TIM5_LSI: TIM5 CH4 input is connected to LSI clock.
- * @arg TIM5_LSE: TIM5 CH4 input is connected to LSE clock.
- * @arg TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.
- * @arg TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default)
- * @arg TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock
- * (HSE divided by a programmable prescaler)
- * @retval None
- */
-void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_REMAP(TIM_Remap));
-
- /* Set the Timer remapping configuration */
- TIMx->OR = TIM_Remap;
-}
-/**
- * @}
- */
-
-/**
- * @brief Configure the TI1 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
- * to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
- * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr1 = 0, tmpccer = 0;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Select the Input and set the filter */
- tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F);
- tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI2 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
- * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 4);
-
- /* Select the Input and set the filter */
- tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
- tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
- tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI3 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
- * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 3: Reset the CC3E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 8);
-
- /* Select the Input and set the filter */
- tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F);
- tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
-
- /* Select the Polarity and set the CC3E Bit */
- tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI4 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
- * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 12);
-
- /* Select the Input and set the filter */
- tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
- tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
- tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
-
- /* Select the Polarity and set the CC4E Bit */
- tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer ;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_tim.h b/底盘/底盘-old/底盘/Library/stm32f4xx_tim.h
deleted file mode 100644
index bbdbef2..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_tim.h
+++ /dev/null
@@ -1,1142 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_tim.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the TIM firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_TIM_H
-#define __STM32F4xx_TIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup TIM
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief TIM Time Base Init structure definition
- * @note This structure is used with all TIMx except for TIM6 and TIM7.
- */
-
-typedef struct
-{
- uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
- This parameter can be a number between 0x0000 and 0xFFFF */
-
- uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
- This parameter can be a value of @ref TIM_Counter_Mode */
-
- uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
- Auto-Reload Register at the next update event.
- This parameter must be a number between 0x0000 and 0xFFFF. */
-
- uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
- This parameter can be a value of @ref TIM_Clock_Division_CKD */
-
- uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
- reaches zero, an update event is generated and counting restarts
- from the RCR value (N).
- This means in PWM mode that (N+1) corresponds to:
- - the number of PWM periods in edge-aligned mode
- - the number of half PWM period in center-aligned mode
- This parameter must be a number between 0x00 and 0xFF.
- @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_TimeBaseInitTypeDef;
-
-/**
- * @brief TIM Output Compare Init structure definition
- */
-
-typedef struct
-{
- uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
- uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
- This parameter can be a value of @ref TIM_Output_Compare_State */
-
- uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
- This parameter can be a value of @ref TIM_Output_Compare_N_State
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between 0x0000 and 0xFFFF */
-
- uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
- uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_OCInitTypeDef;
-
-/**
- * @brief TIM Input Capture Init structure definition
- */
-
-typedef struct
-{
-
- uint16_t TIM_Channel; /*!< Specifies the TIM channel.
- This parameter can be a value of @ref TIM_Channel */
-
- uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint16_t TIM_ICSelection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between 0x0 and 0xF */
-} TIM_ICInitTypeDef;
-
-/**
- * @brief BDTR structure definition
- * @note This structure is used only with TIM1 and TIM8.
- */
-
-typedef struct
-{
-
- uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
- This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
-
- uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
- This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
-
- uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
- This parameter can be a value of @ref TIM_Lock_level */
-
- uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
- switching-on of the outputs.
- This parameter can be a number between 0x00 and 0xFF */
-
- uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
- This parameter can be a value of @ref TIM_Break_Input_enable_disable */
-
- uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
- This parameter can be a value of @ref TIM_Break_Polarity */
-
- uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
- This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
-} TIM_BDTRInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup TIM_Exported_constants
- * @{
- */
-
-#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM5) || \
- ((PERIPH) == TIM6) || \
- ((PERIPH) == TIM7) || \
- ((PERIPH) == TIM8) || \
- ((PERIPH) == TIM9) || \
- ((PERIPH) == TIM10) || \
- ((PERIPH) == TIM11) || \
- ((PERIPH) == TIM12) || \
- (((PERIPH) == TIM13) || \
- ((PERIPH) == TIM14)))
-/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */
-#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM5) || \
- ((PERIPH) == TIM8) || \
- ((PERIPH) == TIM9) || \
- ((PERIPH) == TIM10) || \
- ((PERIPH) == TIM11) || \
- ((PERIPH) == TIM12) || \
- ((PERIPH) == TIM13) || \
- ((PERIPH) == TIM14))
-
-/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */
-#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM5) || \
- ((PERIPH) == TIM8) || \
- ((PERIPH) == TIM9) || \
- ((PERIPH) == TIM12))
-/* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */
-#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM5) || \
- ((PERIPH) == TIM8))
-/* LIST4: TIM1 and TIM8 */
-#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM8))
-/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
-#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM5) || \
- ((PERIPH) == TIM6) || \
- ((PERIPH) == TIM7) || \
- ((PERIPH) == TIM8))
-/* LIST6: TIM2, TIM5 and TIM11 */
-#define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \
- ((TIMx) == TIM5) || \
- ((TIMx) == TIM11))
-
-/** @defgroup TIM_Output_Compare_and_PWM_modes
- * @{
- */
-
-#define TIM_OCMode_Timing ((uint16_t)0x0000)
-#define TIM_OCMode_Active ((uint16_t)0x0010)
-#define TIM_OCMode_Inactive ((uint16_t)0x0020)
-#define TIM_OCMode_Toggle ((uint16_t)0x0030)
-#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
-#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
- ((MODE) == TIM_OCMode_Active) || \
- ((MODE) == TIM_OCMode_Inactive) || \
- ((MODE) == TIM_OCMode_Toggle)|| \
- ((MODE) == TIM_OCMode_PWM1) || \
- ((MODE) == TIM_OCMode_PWM2))
-#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
- ((MODE) == TIM_OCMode_Active) || \
- ((MODE) == TIM_OCMode_Inactive) || \
- ((MODE) == TIM_OCMode_Toggle)|| \
- ((MODE) == TIM_OCMode_PWM1) || \
- ((MODE) == TIM_OCMode_PWM2) || \
- ((MODE) == TIM_ForcedAction_Active) || \
- ((MODE) == TIM_ForcedAction_InActive))
-/**
- * @}
- */
-
-/** @defgroup TIM_One_Pulse_Mode
- * @{
- */
-
-#define TIM_OPMode_Single ((uint16_t)0x0008)
-#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
- ((MODE) == TIM_OPMode_Repetitive))
-/**
- * @}
- */
-
-/** @defgroup TIM_Channel
- * @{
- */
-
-#define TIM_Channel_1 ((uint16_t)0x0000)
-#define TIM_Channel_2 ((uint16_t)0x0004)
-#define TIM_Channel_3 ((uint16_t)0x0008)
-#define TIM_Channel_4 ((uint16_t)0x000C)
-
-#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
- ((CHANNEL) == TIM_Channel_2) || \
- ((CHANNEL) == TIM_Channel_3) || \
- ((CHANNEL) == TIM_Channel_4))
-
-#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
- ((CHANNEL) == TIM_Channel_2))
-#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
- ((CHANNEL) == TIM_Channel_2) || \
- ((CHANNEL) == TIM_Channel_3))
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Division_CKD
- * @{
- */
-
-#define TIM_CKD_DIV1 ((uint16_t)0x0000)
-#define TIM_CKD_DIV2 ((uint16_t)0x0100)
-#define TIM_CKD_DIV4 ((uint16_t)0x0200)
-#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
- ((DIV) == TIM_CKD_DIV2) || \
- ((DIV) == TIM_CKD_DIV4))
-/**
- * @}
- */
-
-/** @defgroup TIM_Counter_Mode
- * @{
- */
-
-#define TIM_CounterMode_Up ((uint16_t)0x0000)
-#define TIM_CounterMode_Down ((uint16_t)0x0010)
-#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
-#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
-#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
- ((MODE) == TIM_CounterMode_Down) || \
- ((MODE) == TIM_CounterMode_CenterAligned1) || \
- ((MODE) == TIM_CounterMode_CenterAligned2) || \
- ((MODE) == TIM_CounterMode_CenterAligned3))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Polarity
- * @{
- */
-
-#define TIM_OCPolarity_High ((uint16_t)0x0000)
-#define TIM_OCPolarity_Low ((uint16_t)0x0002)
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
- ((POLARITY) == TIM_OCPolarity_Low))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Polarity
- * @{
- */
-
-#define TIM_OCNPolarity_High ((uint16_t)0x0000)
-#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
-#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
- ((POLARITY) == TIM_OCNPolarity_Low))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_State
- * @{
- */
-
-#define TIM_OutputState_Disable ((uint16_t)0x0000)
-#define TIM_OutputState_Enable ((uint16_t)0x0001)
-#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
- ((STATE) == TIM_OutputState_Enable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_State
- * @{
- */
-
-#define TIM_OutputNState_Disable ((uint16_t)0x0000)
-#define TIM_OutputNState_Enable ((uint16_t)0x0004)
-#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
- ((STATE) == TIM_OutputNState_Enable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Capture_Compare_State
- * @{
- */
-
-#define TIM_CCx_Enable ((uint16_t)0x0001)
-#define TIM_CCx_Disable ((uint16_t)0x0000)
-#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
- ((CCX) == TIM_CCx_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Capture_Compare_N_State
- * @{
- */
-
-#define TIM_CCxN_Enable ((uint16_t)0x0004)
-#define TIM_CCxN_Disable ((uint16_t)0x0000)
-#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
- ((CCXN) == TIM_CCxN_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Input_enable_disable
- * @{
- */
-
-#define TIM_Break_Enable ((uint16_t)0x1000)
-#define TIM_Break_Disable ((uint16_t)0x0000)
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
- ((STATE) == TIM_Break_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Polarity
- * @{
- */
-
-#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
-#define TIM_BreakPolarity_High ((uint16_t)0x2000)
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
- ((POLARITY) == TIM_BreakPolarity_High))
-/**
- * @}
- */
-
-/** @defgroup TIM_AOE_Bit_Set_Reset
- * @{
- */
-
-#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
-#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
- ((STATE) == TIM_AutomaticOutput_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Lock_level
- * @{
- */
-
-#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
-#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
-#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
-#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
- ((LEVEL) == TIM_LOCKLevel_1) || \
- ((LEVEL) == TIM_LOCKLevel_2) || \
- ((LEVEL) == TIM_LOCKLevel_3))
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
- * @{
- */
-
-#define TIM_OSSIState_Enable ((uint16_t)0x0400)
-#define TIM_OSSIState_Disable ((uint16_t)0x0000)
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
- ((STATE) == TIM_OSSIState_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
- * @{
- */
-
-#define TIM_OSSRState_Enable ((uint16_t)0x0800)
-#define TIM_OSSRState_Disable ((uint16_t)0x0000)
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
- ((STATE) == TIM_OSSRState_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Idle_State
- * @{
- */
-
-#define TIM_OCIdleState_Set ((uint16_t)0x0100)
-#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
- ((STATE) == TIM_OCIdleState_Reset))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Idle_State
- * @{
- */
-
-#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
-#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
-#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
- ((STATE) == TIM_OCNIdleState_Reset))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Polarity
- * @{
- */
-
-#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
-#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
-#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
- ((POLARITY) == TIM_ICPolarity_Falling)|| \
- ((POLARITY) == TIM_ICPolarity_BothEdge))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Selection
- * @{
- */
-
-#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC2, IC1, IC4 or IC3, respectively. */
-#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
- ((SELECTION) == TIM_ICSelection_IndirectTI) || \
- ((SELECTION) == TIM_ICSelection_TRC))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Prescaler
- * @{
- */
-
-#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
-#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
-#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
-#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
- ((PRESCALER) == TIM_ICPSC_DIV2) || \
- ((PRESCALER) == TIM_ICPSC_DIV4) || \
- ((PRESCALER) == TIM_ICPSC_DIV8))
-/**
- * @}
- */
-
-/** @defgroup TIM_interrupt_sources
- * @{
- */
-
-#define TIM_IT_Update ((uint16_t)0x0001)
-#define TIM_IT_CC1 ((uint16_t)0x0002)
-#define TIM_IT_CC2 ((uint16_t)0x0004)
-#define TIM_IT_CC3 ((uint16_t)0x0008)
-#define TIM_IT_CC4 ((uint16_t)0x0010)
-#define TIM_IT_COM ((uint16_t)0x0020)
-#define TIM_IT_Trigger ((uint16_t)0x0040)
-#define TIM_IT_Break ((uint16_t)0x0080)
-#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
-
-#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
- ((IT) == TIM_IT_CC1) || \
- ((IT) == TIM_IT_CC2) || \
- ((IT) == TIM_IT_CC3) || \
- ((IT) == TIM_IT_CC4) || \
- ((IT) == TIM_IT_COM) || \
- ((IT) == TIM_IT_Trigger) || \
- ((IT) == TIM_IT_Break))
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Base_address
- * @{
- */
-
-#define TIM_DMABase_CR1 ((uint16_t)0x0000)
-#define TIM_DMABase_CR2 ((uint16_t)0x0001)
-#define TIM_DMABase_SMCR ((uint16_t)0x0002)
-#define TIM_DMABase_DIER ((uint16_t)0x0003)
-#define TIM_DMABase_SR ((uint16_t)0x0004)
-#define TIM_DMABase_EGR ((uint16_t)0x0005)
-#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
-#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
-#define TIM_DMABase_CCER ((uint16_t)0x0008)
-#define TIM_DMABase_CNT ((uint16_t)0x0009)
-#define TIM_DMABase_PSC ((uint16_t)0x000A)
-#define TIM_DMABase_ARR ((uint16_t)0x000B)
-#define TIM_DMABase_RCR ((uint16_t)0x000C)
-#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
-#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
-#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
-#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
-#define TIM_DMABase_BDTR ((uint16_t)0x0011)
-#define TIM_DMABase_DCR ((uint16_t)0x0012)
-#define TIM_DMABase_OR ((uint16_t)0x0013)
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
- ((BASE) == TIM_DMABase_CR2) || \
- ((BASE) == TIM_DMABase_SMCR) || \
- ((BASE) == TIM_DMABase_DIER) || \
- ((BASE) == TIM_DMABase_SR) || \
- ((BASE) == TIM_DMABase_EGR) || \
- ((BASE) == TIM_DMABase_CCMR1) || \
- ((BASE) == TIM_DMABase_CCMR2) || \
- ((BASE) == TIM_DMABase_CCER) || \
- ((BASE) == TIM_DMABase_CNT) || \
- ((BASE) == TIM_DMABase_PSC) || \
- ((BASE) == TIM_DMABase_ARR) || \
- ((BASE) == TIM_DMABase_RCR) || \
- ((BASE) == TIM_DMABase_CCR1) || \
- ((BASE) == TIM_DMABase_CCR2) || \
- ((BASE) == TIM_DMABase_CCR3) || \
- ((BASE) == TIM_DMABase_CCR4) || \
- ((BASE) == TIM_DMABase_BDTR) || \
- ((BASE) == TIM_DMABase_DCR) || \
- ((BASE) == TIM_DMABase_OR))
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Burst_Length
- * @{
- */
-
-#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
-#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
-#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
-#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
-#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
-#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
-#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
-#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
-#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
-#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
-#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
-#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
-#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
-#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
-#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
-#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
-#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
-#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
- ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_18Transfers))
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_sources
- * @{
- */
-
-#define TIM_DMA_Update ((uint16_t)0x0100)
-#define TIM_DMA_CC1 ((uint16_t)0x0200)
-#define TIM_DMA_CC2 ((uint16_t)0x0400)
-#define TIM_DMA_CC3 ((uint16_t)0x0800)
-#define TIM_DMA_CC4 ((uint16_t)0x1000)
-#define TIM_DMA_COM ((uint16_t)0x2000)
-#define TIM_DMA_Trigger ((uint16_t)0x4000)
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_External_Trigger_Prescaler
- * @{
- */
-
-#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
-#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
-#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
-#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
-#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
- ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
- ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
- ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
-/**
- * @}
- */
-
-/** @defgroup TIM_Internal_Trigger_Selection
- * @{
- */
-
-#define TIM_TS_ITR0 ((uint16_t)0x0000)
-#define TIM_TS_ITR1 ((uint16_t)0x0010)
-#define TIM_TS_ITR2 ((uint16_t)0x0020)
-#define TIM_TS_ITR3 ((uint16_t)0x0030)
-#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
-#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
-#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
-#define TIM_TS_ETRF ((uint16_t)0x0070)
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3) || \
- ((SELECTION) == TIM_TS_TI1F_ED) || \
- ((SELECTION) == TIM_TS_TI1FP1) || \
- ((SELECTION) == TIM_TS_TI2FP2) || \
- ((SELECTION) == TIM_TS_ETRF))
-#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3))
-/**
- * @}
- */
-
-/** @defgroup TIM_TIx_External_Clock_Source
- * @{
- */
-
-#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
-#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
-#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_External_Trigger_Polarity
- * @{
- */
-#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
-#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
-#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
- ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
-/**
- * @}
- */
-
-/** @defgroup TIM_Prescaler_Reload_Mode
- * @{
- */
-
-#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
-#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
-#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
- ((RELOAD) == TIM_PSCReloadMode_Immediate))
-/**
- * @}
- */
-
-/** @defgroup TIM_Forced_Action
- * @{
- */
-
-#define TIM_ForcedAction_Active ((uint16_t)0x0050)
-#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
-#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
- ((ACTION) == TIM_ForcedAction_InActive))
-/**
- * @}
- */
-
-/** @defgroup TIM_Encoder_Mode
- * @{
- */
-
-#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
-#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
-#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
- ((MODE) == TIM_EncoderMode_TI2) || \
- ((MODE) == TIM_EncoderMode_TI12))
-/**
- * @}
- */
-
-
-/** @defgroup TIM_Event_Source
- * @{
- */
-
-#define TIM_EventSource_Update ((uint16_t)0x0001)
-#define TIM_EventSource_CC1 ((uint16_t)0x0002)
-#define TIM_EventSource_CC2 ((uint16_t)0x0004)
-#define TIM_EventSource_CC3 ((uint16_t)0x0008)
-#define TIM_EventSource_CC4 ((uint16_t)0x0010)
-#define TIM_EventSource_COM ((uint16_t)0x0020)
-#define TIM_EventSource_Trigger ((uint16_t)0x0040)
-#define TIM_EventSource_Break ((uint16_t)0x0080)
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Update_Source
- * @{
- */
-
-#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
- or the setting of UG bit, or an update generation
- through the slave mode controller. */
-#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
-#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
- ((SOURCE) == TIM_UpdateSource_Regular))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Preload_State
- * @{
- */
-
-#define TIM_OCPreload_Enable ((uint16_t)0x0008)
-#define TIM_OCPreload_Disable ((uint16_t)0x0000)
-#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
- ((STATE) == TIM_OCPreload_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Fast_State
- * @{
- */
-
-#define TIM_OCFast_Enable ((uint16_t)0x0004)
-#define TIM_OCFast_Disable ((uint16_t)0x0000)
-#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
- ((STATE) == TIM_OCFast_Disable))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Clear_State
- * @{
- */
-
-#define TIM_OCClear_Enable ((uint16_t)0x0080)
-#define TIM_OCClear_Disable ((uint16_t)0x0000)
-#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
- ((STATE) == TIM_OCClear_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Output_Source
- * @{
- */
-
-#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
-#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
-#define TIM_TRGOSource_Update ((uint16_t)0x0020)
-#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
-#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
-#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
-#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
-#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
- ((SOURCE) == TIM_TRGOSource_Enable) || \
- ((SOURCE) == TIM_TRGOSource_Update) || \
- ((SOURCE) == TIM_TRGOSource_OC1) || \
- ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
- ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
- ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
- ((SOURCE) == TIM_TRGOSource_OC4Ref))
-/**
- * @}
- */
-
-/** @defgroup TIM_Slave_Mode
- * @{
- */
-
-#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
-#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
-#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
-#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
- ((MODE) == TIM_SlaveMode_Gated) || \
- ((MODE) == TIM_SlaveMode_Trigger) || \
- ((MODE) == TIM_SlaveMode_External1))
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Slave_Mode
- * @{
- */
-
-#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
-#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
- ((STATE) == TIM_MasterSlaveMode_Disable))
-/**
- * @}
- */
-/** @defgroup TIM_Remap
- * @{
- */
-
-#define TIM2_TIM8_TRGO ((uint16_t)0x0000)
-#define TIM2_ETH_PTP ((uint16_t)0x0400)
-#define TIM2_USBFS_SOF ((uint16_t)0x0800)
-#define TIM2_USBHS_SOF ((uint16_t)0x0C00)
-
-#define TIM5_GPIO ((uint16_t)0x0000)
-#define TIM5_LSI ((uint16_t)0x0040)
-#define TIM5_LSE ((uint16_t)0x0080)
-#define TIM5_RTC ((uint16_t)0x00C0)
-
-#define TIM11_GPIO ((uint16_t)0x0000)
-#define TIM11_HSE ((uint16_t)0x0002)
-
-#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)||\
- ((TIM_REMAP) == TIM2_ETH_PTP)||\
- ((TIM_REMAP) == TIM2_USBFS_SOF)||\
- ((TIM_REMAP) == TIM2_USBHS_SOF)||\
- ((TIM_REMAP) == TIM5_GPIO)||\
- ((TIM_REMAP) == TIM5_LSI)||\
- ((TIM_REMAP) == TIM5_LSE)||\
- ((TIM_REMAP) == TIM5_RTC)||\
- ((TIM_REMAP) == TIM11_GPIO)||\
- ((TIM_REMAP) == TIM11_HSE))
-
-/**
- * @}
- */
-/** @defgroup TIM_Flags
- * @{
- */
-
-#define TIM_FLAG_Update ((uint16_t)0x0001)
-#define TIM_FLAG_CC1 ((uint16_t)0x0002)
-#define TIM_FLAG_CC2 ((uint16_t)0x0004)
-#define TIM_FLAG_CC3 ((uint16_t)0x0008)
-#define TIM_FLAG_CC4 ((uint16_t)0x0010)
-#define TIM_FLAG_COM ((uint16_t)0x0020)
-#define TIM_FLAG_Trigger ((uint16_t)0x0040)
-#define TIM_FLAG_Break ((uint16_t)0x0080)
-#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
-#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
-#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
-#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
-#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
- ((FLAG) == TIM_FLAG_CC1) || \
- ((FLAG) == TIM_FLAG_CC2) || \
- ((FLAG) == TIM_FLAG_CC3) || \
- ((FLAG) == TIM_FLAG_CC4) || \
- ((FLAG) == TIM_FLAG_COM) || \
- ((FLAG) == TIM_FLAG_Trigger) || \
- ((FLAG) == TIM_FLAG_Break) || \
- ((FLAG) == TIM_FLAG_CC1OF) || \
- ((FLAG) == TIM_FLAG_CC2OF) || \
- ((FLAG) == TIM_FLAG_CC3OF) || \
- ((FLAG) == TIM_FLAG_CC4OF))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Filer_Value
- * @{
- */
-
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup TIM_External_Trigger_Filter
- * @{
- */
-
-#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup TIM_Legacy
- * @{
- */
-
-#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
-#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
-#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
-#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
-#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
-#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
-#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
-#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
-#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
-#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
-#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
-#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
-#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
-#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
-#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
-#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
-#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
-#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* TimeBase management ********************************************************/
-void TIM_DeInit(TIM_TypeDef* TIMx);
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
-uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Output Compare management **************************************************/
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
-
-/* Input Capture management ***************************************************/
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
-uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
-uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
-uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
-uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-
-/* Advanced-control timers (TIM1 and TIM8) specific features ******************/
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Interrupts, DMA and flags management ***************************************/
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Clocks management **********************************************************/
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
- uint16_t TIM_ICPolarity, uint16_t ICFilter);
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter);
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
-
-/* Synchronization management *************************************************/
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter);
-
-/* Specific interface management **********************************************/
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Specific remapping management **********************************************/
-void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_TIM_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_usart.c b/底盘/底盘-old/底盘/Library/stm32f4xx_usart.c
deleted file mode 100644
index 833a51e..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_usart.c
+++ /dev/null
@@ -1,1478 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_usart.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Universal synchronous asynchronous receiver
- * transmitter (USART):
- * + Initialization and Configuration
- * + Data transfers
- * + Multi-Processor Communication
- * + LIN mode
- * + Half-duplex mode
- * + Smartcard mode
- * + IrDA mode
- * + DMA transfers management
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable peripheral clock using the following functions
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3,
- UART4 or UART5.
-
- (#) According to the USART mode, enable the GPIO clocks using
- RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS,
- or/and SCLK).
-
- (#) Peripheral's alternate function:
- (++) Connect the pin to the desired peripherals' Alternate
- Function (AF) using GPIO_PinAFConfig() function
- (++) Configure the desired pin in alternate function by:
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- (++) Select the type, pull-up/pull-down and output speed via
- GPIO_PuPd, GPIO_OType and GPIO_Speed members
- (++) Call GPIO_Init() function
-
- (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
- flow control and Mode(Receiver/Transmitter) using the USART_Init()
- function.
-
- (#) For synchronous mode, enable the clock and program the polarity,
- phase and last bit using the USART_ClockInit() function.
-
- (#) Enable the NVIC and the corresponding interrupt using the function
- USART_ITConfig() if you need to use interrupt mode.
-
- (#) When using the DMA mode
- (++) Configure the DMA using DMA_Init() function
- (++) Active the needed channel Request using USART_DMACmd() function
-
- (#) Enable the USART using the USART_Cmd() function.
-
- (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.
-
- -@- Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections
- for more details
-
- [..]
- In order to reach higher communication baudrates, it is possible to
- enable the oversampling by 8 mode using the function USART_OverSampling8Cmd().
- This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd())
- and before calling the function USART_Init().
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_usart.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup USART
- * @brief USART driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */
-#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \
- USART_CR1_PS | USART_CR1_TE | \
- USART_CR1_RE))
-
-/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */
-#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
- USART_CR2_CPHA | USART_CR2_LBCL))
-
-/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */
-#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE))
-
-/*!< USART Interrupts mask */
-#define IT_MASK ((uint16_t)0x001F)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup USART_Private_Functions
- * @{
- */
-
-/** @defgroup USART_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USART
- in asynchronous and in synchronous modes.
- (+) For the asynchronous mode only these parameters can be configured:
- (++) Baud Rate
- (++) Word Length
- (++) Stop Bit
- (++) Parity: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible USART frame formats are as listed in the following table:
- +-------------------------------------------------------------+
- | M bit | PCE bit | USART frame |
- |---------------------|---------------------------------------|
- | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +-------------------------------------------------------------+
- (++) Hardware flow control
- (++) Receiver/transmitter modes
-
- [..]
- The USART_Init() function follows the USART asynchronous configuration
- procedure (details for the procedure are available in reference manual (RM0090)).
-
- (+) For the synchronous mode in addition to the asynchronous mode parameters these
- parameters should be also configured:
- (++) USART Clock Enabled
- (++) USART polarity
- (++) USART phase
- (++) USART LastBit
-
- [..]
- These parameters can be configured using the USART_ClockInit() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the USARTx peripheral registers to their default reset values.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @retval None
- */
-void USART_DeInit(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- if (USARTx == USART1)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
- }
- else if (USARTx == USART2)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
- }
- else if (USARTx == USART3)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
- }
- else if (USARTx == UART4)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
- }
- else if (USARTx == UART5)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
- }
- else if (USARTx == USART6)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE);
- }
- else if (USARTx == UART7)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, DISABLE);
- }
- else
- {
- if (USARTx == UART8)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the USARTx peripheral according to the specified
- * parameters in the USART_InitStruct .
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains
- * the configuration information for the specified USART peripheral.
- * @retval None
- */
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
-{
- uint32_t tmpreg = 0x00, apbclock = 0x00;
- uint32_t integerdivider = 0x00;
- uint32_t fractionaldivider = 0x00;
- RCC_ClocksTypeDef RCC_ClocksStatus;
-
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
- assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
- assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
- assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
- assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
- assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
-
- /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */
- if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
-/*---------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = USARTx->CR2;
-
- /* Clear STOP[13:12] bits */
- tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
-
- /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit :
- Set STOP[13:12] bits according to USART_StopBits value */
- tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
-
- /* Write to USART CR2 */
- USARTx->CR2 = (uint16_t)tmpreg;
-
-/*---------------------------- USART CR1 Configuration -----------------------*/
- tmpreg = USARTx->CR1;
-
- /* Clear M, PCE, PS, TE and RE bits */
- tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);
-
- /* Configure the USART Word Length, Parity and mode:
- Set the M bits according to USART_WordLength value
- Set PCE and PS bits according to USART_Parity value
- Set TE and RE bits according to USART_Mode value */
- tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
- USART_InitStruct->USART_Mode;
-
- /* Write to USART CR1 */
- USARTx->CR1 = (uint16_t)tmpreg;
-
-/*---------------------------- USART CR3 Configuration -----------------------*/
- tmpreg = USARTx->CR3;
-
- /* Clear CTSE and RTSE bits */
- tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);
-
- /* Configure the USART HFC :
- Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
- tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
-
- /* Write to USART CR3 */
- USARTx->CR3 = (uint16_t)tmpreg;
-
-/*---------------------------- USART BRR Configuration -----------------------*/
- /* Configure the USART Baud Rate */
- RCC_GetClocksFreq(&RCC_ClocksStatus);
-
- if ((USARTx == USART1) || (USARTx == USART6))
- {
- apbclock = RCC_ClocksStatus.PCLK2_Frequency;
- }
- else
- {
- apbclock = RCC_ClocksStatus.PCLK1_Frequency;
- }
-
- /* Determine the integer part */
- if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
- {
- /* Integer part computing in case Oversampling mode is 8 Samples */
- integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));
- }
- else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */
- {
- /* Integer part computing in case Oversampling mode is 16 Samples */
- integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
- }
- tmpreg = (integerdivider / 100) << 4;
-
- /* Determine the fractional part */
- fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
-
- /* Implement the fractional part in the register */
- if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
- {
- tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
- }
- else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */
- {
- tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
- }
-
- /* Write to USART BRR register */
- USARTx->BRR = (uint16_t)tmpreg;
-}
-
-/**
- * @brief Fills each USART_InitStruct member with its default value.
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
-{
- /* USART_InitStruct members default value */
- USART_InitStruct->USART_BaudRate = 9600;
- USART_InitStruct->USART_WordLength = USART_WordLength_8b;
- USART_InitStruct->USART_StopBits = USART_StopBits_1;
- USART_InitStruct->USART_Parity = USART_Parity_No ;
- USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
- USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-}
-
-/**
- * @brief Initializes the USARTx peripheral Clock according to the
- * specified parameters in the USART_ClockInitStruct .
- * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART peripheral.
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure that
- * contains the configuration information for the specified USART peripheral.
- * @note The Smart Card and Synchronous modes are not available for UART4 and UART5.
- * @retval None
- */
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
- uint32_t tmpreg = 0x00;
- /* Check the parameters */
- assert_param(IS_USART_1236_PERIPH(USARTx));
- assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
- assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
- assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
- assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
-
-/*---------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = USARTx->CR2;
- /* Clear CLKEN, CPOL, CPHA and LBCL bits */
- tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);
- /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
- /* Set CLKEN bit according to USART_Clock value */
- /* Set CPOL bit according to USART_CPOL value */
- /* Set CPHA bit according to USART_CPHA value */
- /* Set LBCL bit according to USART_LastBit value */
- tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
- USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
- /* Write to USART CR2 */
- USARTx->CR2 = (uint16_t)tmpreg;
-}
-
-/**
- * @brief Fills each USART_ClockInitStruct member with its default value.
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
- /* USART_ClockInitStruct members default value */
- USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
- USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
- USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
- USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
-}
-
-/**
- * @brief Enables or disables the specified USART peripheral.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USARTx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected USART by setting the UE bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_UE;
- }
- else
- {
- /* Disable the selected USART by clearing the UE bit in the CR1 register */
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE);
- }
-}
-
-/**
- * @brief Sets the system clock prescaler.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_Prescaler: specifies the prescaler clock.
- * @note The function is used for IrDA mode with UART4 and UART5.
- * @retval None
- */
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Clear the USART prescaler */
- USARTx->GTPR &= USART_GTPR_GT;
- /* Set the USART prescaler */
- USARTx->GTPR |= USART_Prescaler;
-}
-
-/**
- * @brief Enables or disables the USART's 8x oversampling mode.
- * @note This function has to be called before calling USART_Init() function
- * in order to have correct baudrate Divider value.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USART 8x oversampling mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_OVER8;
- }
- else
- {
- /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8);
- }
-}
-
-/**
- * @brief Enables or disables the USART's one bit sampling method.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USART one bit sampling method.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_ONEBIT;
- }
- else
- {
- /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group2 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the USART data
- transfers.
- [..]
- During an USART reception, data shifts in least significant bit first through
- the RX pin. In this mode, the USART_DR register consists of a buffer (RDR)
- between the internal bus and the received shift register.
- [..]
- When a transmission is taking place, a write instruction to the USART_DR register
- stores the data in the TDR register and which is copied in the shift register
- at the end of the current transmission.
- [..]
- The read access of the USART_DR register can be done using the USART_ReceiveData()
- function and returns the RDR buffered value. Whereas a write access to the USART_DR
- can be done using USART_SendData() function and stores the written data into
- TDR buffer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmits single data through the USARTx peripheral.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param Data: the data to transmit.
- * @retval None
- */
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DATA(Data));
-
- /* Transmit Data */
- USARTx->DR = (Data & (uint16_t)0x01FF);
-}
-
-/**
- * @brief Returns the most recent received data by the USARTx peripheral.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @retval The received data.
- */
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Receive Data */
- return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group3 MultiProcessor Communication functions
- * @brief Multi-Processor Communication functions
- *
-@verbatim
- ===============================================================================
- ##### Multi-Processor Communication functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the USART
- multiprocessor communication.
- [..]
- For instance one of the USARTs can be the master, its TX output is connected
- to the RX input of the other USART. The others are slaves, their respective
- TX outputs are logically ANDed together and connected to the RX input of the
- master.
- [..]
- USART multiprocessor communication is possible through the following procedure:
- (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode
- transmitter or Mode receiver and hardware flow control values using
- the USART_Init() function.
- (#) Configures the USART address using the USART_SetAddress() function.
- (#) Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark)
- using USART_WakeUpConfig() function only for the slaves.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function.
- [..]
- The USART Slave exit from mute mode when receive the wake up condition.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the address of the USART node.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_Address: Indicates the address of the USART node.
- * @retval None
- */
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_ADDRESS(USART_Address));
-
- /* Clear the USART address */
- USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD);
- /* Set the USART address node */
- USARTx->CR2 |= USART_Address;
-}
-
-/**
- * @brief Determines if the USART is in mute mode or not.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USART mute mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the USART mute mode by setting the RWU bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_RWU;
- }
- else
- {
- /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU);
- }
-}
-/**
- * @brief Selects the USART WakeUp method.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_WakeUp: specifies the USART wakeup method.
- * This parameter can be one of the following values:
- * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
- * @arg USART_WakeUp_AddressMark: WakeUp by an address mark
- * @retval None
- */
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_WAKEUP(USART_WakeUp));
-
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE);
- USARTx->CR1 |= USART_WakeUp;
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group4 LIN mode functions
- * @brief LIN mode functions
- *
-@verbatim
- ===============================================================================
- ##### LIN mode functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the USART LIN
- Mode communication.
- [..]
- In LIN mode, 8-bit data format with 1 stop bit is required in accordance with
- the LIN standard.
- [..]
- Only this LIN Feature is supported by the USART IP:
- (+) LIN Master Synchronous Break send capability and LIN slave break detection
- capability : 13-bit break generation and 10/11 bit break detection
-
- [..]
- USART LIN Master transmitter communication is possible through the following
- procedure:
- (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
- Mode transmitter or Mode receiver and hardware flow control values using
- the USART_Init() function.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Enable the LIN mode using the USART_LINCmd() function.
- (#) Send the break character using USART_SendBreak() function.
- [..]
- USART LIN Master receiver communication is possible through the following procedure:
- (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
- Mode transmitter or Mode receiver and hardware flow control values using
- the USART_Init() function.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Configures the break detection length using the USART_LINBreakDetectLengthConfig()
- function.
- (#) Enable the LIN mode using the USART_LINCmd() function.
-
- -@- In LIN mode, the following bits must be kept cleared:
- (+@) CLKEN in the USART_CR2 register,
- (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the USART LIN Break detection length.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_LINBreakDetectLength: specifies the LIN break detection length.
- * This parameter can be one of the following values:
- * @arg USART_LINBreakDetectLength_10b: 10-bit break detection
- * @arg USART_LINBreakDetectLength_11b: 11-bit break detection
- * @retval None
- */
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
-
- USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL);
- USARTx->CR2 |= USART_LINBreakDetectLength;
-}
-
-/**
- * @brief Enables or disables the USART's LIN mode.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USART LIN mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
- USARTx->CR2 |= USART_CR2_LINEN;
- }
- else
- {
- /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
- USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN);
- }
-}
-
-/**
- * @brief Transmits break characters.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @retval None
- */
-void USART_SendBreak(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Send break characters */
- USARTx->CR1 |= USART_CR1_SBK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group5 Halfduplex mode function
- * @brief Half-duplex mode function
- *
-@verbatim
- ===============================================================================
- ##### Half-duplex mode function #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the USART
- Half-duplex communication.
- [..]
- The USART can be configured to follow a single-wire half-duplex protocol where
- the TX and RX lines are internally connected.
- [..]
- USART Half duplex communication is possible through the following procedure:
- (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter
- or Mode receiver and hardware flow control values using the USART_Init()
- function.
- (#) Configures the USART address using the USART_SetAddress() function.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Enable the half duplex mode using USART_HalfDuplexCmd() function.
-
-
- -@- The RX pin is no longer used
- -@- In Half-duplex mode the following bits must be kept cleared:
- (+@) LINEN and CLKEN bits in the USART_CR2 register.
- (+@) SCEN and IREN bits in the USART_CR3 register.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the USART's Half Duplex communication.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USART Communication.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_HDSEL;
- }
- else
- {
- /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL);
- }
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup USART_Group6 Smartcard mode functions
- * @brief Smartcard mode functions
- *
-@verbatim
- ===============================================================================
- ##### Smartcard mode functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the USART
- Smartcard communication.
- [..]
- The Smartcard interface is designed to support asynchronous protocol Smartcards as
- defined in the ISO 7816-3 standard.
- [..]
- The USART can provide a clock to the smartcard through the SCLK output.
- In smartcard mode, SCLK is not associated to the communication but is simply derived
- from the internal peripheral input clock through a 5-bit prescaler.
- [..]
- Smartcard communication is possible through the following procedure:
- (#) Configures the Smartcard Prescaler using the USART_SetPrescaler() function.
- (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() function.
- (#) Program the USART clock using the USART_ClockInit() function as following:
- (++) USART Clock enabled
- (++) USART CPOL Low
- (++) USART CPHA on first edge
- (++) USART Last Bit Clock Enabled
- (#) Program the Smartcard interface using the USART_Init() function as following:
- (++) Word Length = 9 Bits
- (++) 1.5 Stop Bit
- (++) Even parity
- (++) BaudRate = 12096 baud
- (++) Hardware flow control disabled (RTS and CTS signals)
- (++) Tx and Rx enabled
- (#) POptionally you can enable the parity error interrupt using the USART_ITConfig()
- function
- (#) PEnable the USART using the USART_Cmd() function.
- (#) PEnable the Smartcard NACK using the USART_SmartCardNACKCmd() function.
- (#) PEnable the Smartcard interface using the USART_SmartCardCmd() function.
-
- Please refer to the ISO 7816-3 specification for more details.
-
- -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended
- to use 1.5 stop bits for both transmitting and receiving to avoid switching
- between the two configurations.
- -@- In smartcard mode, the following bits must be kept cleared:
- (+@) LINEN bit in the USART_CR2 register.
- (+@) HDSEL and IREN bits in the USART_CR3 register.
- -@- Smartcard mode is available on USART peripherals only (not available on UART4
- and UART5 peripherals).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the specified USART guard time.
- * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or
- * UART peripheral.
- * @param USART_GuardTime: specifies the guard time.
- * @retval None
- */
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
-{
- /* Check the parameters */
- assert_param(IS_USART_1236_PERIPH(USARTx));
-
- /* Clear the USART Guard time */
- USARTx->GTPR &= USART_GTPR_PSC;
- /* Set the USART guard time */
- USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
-}
-
-/**
- * @brief Enables or disables the USART's Smart Card mode.
- * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the Smart Card mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_1236_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the SC mode by setting the SCEN bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_SCEN;
- }
- else
- {
- /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN);
- }
-}
-
-/**
- * @brief Enables or disables NACK transmission.
- * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the NACK transmission.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_1236_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_NACK;
- }
- else
- {
- /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group7 IrDA mode functions
- * @brief IrDA mode functions
- *
-@verbatim
- ===============================================================================
- ##### IrDA mode functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the USART
- IrDA communication.
- [..]
- IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
- on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
- is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
- While receiving data, transmission should be avoided as the data to be transmitted
- could be corrupted.
- [..]
- IrDA communication is possible through the following procedure:
- (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver
- modes and hardware flow control values using the USART_Init() function.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Configures the IrDA pulse width by configuring the prescaler using
- the USART_SetPrescaler() function.
- (#) Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode
- using the USART_IrDAConfig() function.
- (#) Enable the IrDA using the USART_IrDACmd() function.
-
- -@- A pulse of width less than two and greater than one PSC period(s) may or may
- not be rejected.
- -@- The receiver set up time should be managed by software. The IrDA physical layer
- specification specifies a minimum of 10 ms delay between transmission and
- reception (IrDA is a half duplex protocol).
- -@- In IrDA mode, the following bits must be kept cleared:
- (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register.
- (+@) SCEN and HDSEL bits in the USART_CR3 register.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the USART's IrDA interface.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_IrDAMode: specifies the IrDA mode.
- * This parameter can be one of the following values:
- * @arg USART_IrDAMode_LowPower
- * @arg USART_IrDAMode_Normal
- * @retval None
- */
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
-
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP);
- USARTx->CR3 |= USART_IrDAMode;
-}
-
-/**
- * @brief Enables or disables the USART's IrDA interface.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the IrDA mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_IREN;
- }
- else
- {
- /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group8 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the USART's DMA interface.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_DMAReq: specifies the DMA request.
- * This parameter can be any combination of the following values:
- * @arg USART_DMAReq_Tx: USART DMA transmit request
- * @arg USART_DMAReq_Rx: USART DMA receive request
- * @param NewState: new state of the DMA Request sources.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DMAREQ(USART_DMAReq));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DMA transfer for selected requests by setting the DMAT and/or
- DMAR bits in the USART CR3 register */
- USARTx->CR3 |= USART_DMAReq;
- }
- else
- {
- /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
- DMAR bits in the USART CR3 register */
- USARTx->CR3 &= (uint16_t)~USART_DMAReq;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group9 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to configure the USART
- Interrupts sources, DMA channels requests and check or clear the flags or
- pending bits status.
- The user should identify which mode will be used in his application to manage
- the communication: Polling mode, Interrupt mode or DMA mode.
-
- *** Polling Mode ***
- ====================
- [..]
- In Polling Mode, the SPI communication can be managed by 10 flags:
- (#) USART_FLAG_TXE : to indicate the status of the transmit buffer register
- (#) USART_FLAG_RXNE : to indicate the status of the receive buffer register
- (#) USART_FLAG_TC : to indicate the status of the transmit operation
- (#) USART_FLAG_IDLE : to indicate the status of the Idle Line
- (#) USART_FLAG_CTS : to indicate the status of the nCTS input
- (#) USART_FLAG_LBD : to indicate the status of the LIN break detection
- (#) USART_FLAG_NE : to indicate if a noise error occur
- (#) USART_FLAG_FE : to indicate if a frame error occur
- (#) USART_FLAG_PE : to indicate if a parity error occur
- (#) USART_FLAG_ORE : to indicate if an Overrun error occur
- [..]
- In this Mode it is advised to use the following functions:
- (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
- (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
-
- *** Interrupt Mode ***
- ======================
- [..]
- In Interrupt Mode, the USART communication can be managed by 8 interrupt sources
- and 10 pending bits:
-
- (#) Pending Bits:
-
- (##) USART_IT_TXE : to indicate the status of the transmit buffer register
- (##) USART_IT_RXNE : to indicate the status of the receive buffer register
- (##) USART_IT_TC : to indicate the status of the transmit operation
- (##) USART_IT_IDLE : to indicate the status of the Idle Line
- (##) USART_IT_CTS : to indicate the status of the nCTS input
- (##) USART_IT_LBD : to indicate the status of the LIN break detection
- (##) USART_IT_NE : to indicate if a noise error occur
- (##) USART_IT_FE : to indicate if a frame error occur
- (##) USART_IT_PE : to indicate if a parity error occur
- (##) USART_IT_ORE : to indicate if an Overrun error occur
-
- (#) Interrupt Source:
-
- (##) USART_IT_TXE : specifies the interrupt source for the Tx buffer empty
- interrupt.
- (##) USART_IT_RXNE : specifies the interrupt source for the Rx buffer not
- empty interrupt.
- (##) USART_IT_TC : specifies the interrupt source for the Transmit complete
- interrupt.
- (##) USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt.
- (##) USART_IT_CTS : specifies the interrupt source for the CTS interrupt.
- (##) USART_IT_LBD : specifies the interrupt source for the LIN break detection
- interrupt.
- (##) USART_IT_PE : specifies the interrupt source for the parity error interrupt.
- (##) USART_IT_ERR : specifies the interrupt source for the errors interrupt.
-
- -@@- Some parameters are coded in order to use them as interrupt source
- or as pending bits.
- [..]
- In this Mode it is advised to use the following functions:
- (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
- (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
- (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
-
- *** DMA Mode ***
- ================
- [..]
- In DMA Mode, the USART communication can be managed by 2 DMA Channel requests:
- (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request
- (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request
- [..]
- In this Mode it is advised to use the following function:
- (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified USART interrupts.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg USART_IT_CTS: CTS change interrupt
- * @arg USART_IT_LBD: LIN Break detection interrupt
- * @arg USART_IT_TXE: Transmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @param NewState: new state of the specified USARTx interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
-{
- uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
- uint32_t usartxbase = 0x00;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CONFIG_IT(USART_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* The CTS interrupt is not available for UART4 and UART5 */
- if (USART_IT == USART_IT_CTS)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
- usartxbase = (uint32_t)USARTx;
-
- /* Get the USART register index */
- usartreg = (((uint8_t)USART_IT) >> 0x05);
-
- /* Get the interrupt position */
- itpos = USART_IT & IT_MASK;
- itmask = (((uint32_t)0x01) << itpos);
-
- if (usartreg == 0x01) /* The IT is in CR1 register */
- {
- usartxbase += 0x0C;
- }
- else if (usartreg == 0x02) /* The IT is in CR2 register */
- {
- usartxbase += 0x10;
- }
- else /* The IT is in CR3 register */
- {
- usartxbase += 0x14;
- }
- if (NewState != DISABLE)
- {
- *(__IO uint32_t*)usartxbase |= itmask;
- }
- else
- {
- *(__IO uint32_t*)usartxbase &= ~itmask;
- }
-}
-
-/**
- * @brief Checks whether the specified USART flag is set or not.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
- * @arg USART_FLAG_LBD: LIN Break detection flag
- * @arg USART_FLAG_TXE: Transmit data register empty flag
- * @arg USART_FLAG_TC: Transmission Complete flag
- * @arg USART_FLAG_RXNE: Receive data register not empty flag
- * @arg USART_FLAG_IDLE: Idle Line detection flag
- * @arg USART_FLAG_ORE: OverRun Error flag
- * @arg USART_FLAG_NE: Noise Error flag
- * @arg USART_FLAG_FE: Framing Error flag
- * @arg USART_FLAG_PE: Parity Error flag
- * @retval The new state of USART_FLAG (SET or RESET).
- */
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_FLAG(USART_FLAG));
-
- /* The CTS flag is not available for UART4 and UART5 */
- if (USART_FLAG == USART_FLAG_CTS)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
- if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the USARTx's pending flags.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
- * @arg USART_FLAG_LBD: LIN Break detection flag.
- * @arg USART_FLAG_TC: Transmission Complete flag.
- * @arg USART_FLAG_RXNE: Receive data register not empty flag.
- *
- * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
- * error) and IDLE (Idle line detected) flags are cleared by software
- * sequence: a read operation to USART_SR register (USART_GetFlagStatus())
- * followed by a read operation to USART_DR register (USART_ReceiveData()).
- * @note RXNE flag can be also cleared by a read to the USART_DR register
- * (USART_ReceiveData()).
- * @note TC flag can be also cleared by software sequence: a read operation to
- * USART_SR register (USART_GetFlagStatus()) followed by a write operation
- * to USART_DR register (USART_SendData()).
- * @note TXE flag is cleared only by a write to the USART_DR register
- * (USART_SendData()).
- *
- * @retval None
- */
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
-
- /* The CTS flag is not available for UART4 and UART5 */
- if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
- USARTx->SR = (uint16_t)~USART_FLAG;
-}
-
-/**
- * @brief Checks whether the specified USART interrupt has occurred or not.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_IT: specifies the USART interrupt source to check.
- * This parameter can be one of the following values:
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
- * @arg USART_IT_LBD: LIN Break detection interrupt
- * @arg USART_IT_TXE: Transmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set
- * @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set
- * @arg USART_IT_NE: Noise Error interrupt
- * @arg USART_IT_FE: Framing Error interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @retval The new state of USART_IT (SET or RESET).
- */
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
-{
- uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_GET_IT(USART_IT));
-
- /* The CTS interrupt is not available for UART4 and UART5 */
- if (USART_IT == USART_IT_CTS)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
- /* Get the USART register index */
- usartreg = (((uint8_t)USART_IT) >> 0x05);
- /* Get the interrupt position */
- itmask = USART_IT & IT_MASK;
- itmask = (uint32_t)0x01 << itmask;
-
- if (usartreg == 0x01) /* The IT is in CR1 register */
- {
- itmask &= USARTx->CR1;
- }
- else if (usartreg == 0x02) /* The IT is in CR2 register */
- {
- itmask &= USARTx->CR2;
- }
- else /* The IT is in CR3 register */
- {
- itmask &= USARTx->CR3;
- }
-
- bitpos = USART_IT >> 0x08;
- bitpos = (uint32_t)0x01 << bitpos;
- bitpos &= USARTx->SR;
- if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- return bitstatus;
-}
-
-/**
- * @brief Clears the USARTx's interrupt pending bits.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_IT: specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
- * @arg USART_IT_LBD: LIN Break detection interrupt
- * @arg USART_IT_TC: Transmission complete interrupt.
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt.
- *
- * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
- * error) and IDLE (Idle line detected) pending bits are cleared by
- * software sequence: a read operation to USART_SR register
- * (USART_GetITStatus()) followed by a read operation to USART_DR register
- * (USART_ReceiveData()).
- * @note RXNE pending bit can be also cleared by a read to the USART_DR register
- * (USART_ReceiveData()).
- * @note TC pending bit can be also cleared by software sequence: a read
- * operation to USART_SR register (USART_GetITStatus()) followed by a write
- * operation to USART_DR register (USART_SendData()).
- * @note TXE pending bit is cleared only by a write to the USART_DR register
- * (USART_SendData()).
- *
- * @retval None
- */
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
-{
- uint16_t bitpos = 0x00, itmask = 0x00;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLEAR_IT(USART_IT));
-
- /* The CTS interrupt is not available for UART4 and UART5 */
- if (USART_IT == USART_IT_CTS)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
- bitpos = USART_IT >> 0x08;
- itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
- USARTx->SR = (uint16_t)~itmask;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_usart.h b/底盘/底盘-old/底盘/Library/stm32f4xx_usart.h
deleted file mode 100644
index a68e182..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_usart.h
+++ /dev/null
@@ -1,425 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_usart.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the USART
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_USART_H
-#define __STM32F4xx_USART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup USART
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief USART Init Structure definition
- */
-
-typedef struct
-{
- uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
- The baud rate is computed using the following formula:
- - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate)))
- - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5
- Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
-
- uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref USART_Word_Length */
-
- uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref USART_Stop_Bits */
-
- uint16_t USART_Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref USART_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits). */
-
- uint16_t USART_Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref USART_Mode */
-
- uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
- or disabled.
- This parameter can be a value of @ref USART_Hardware_Flow_Control */
-} USART_InitTypeDef;
-
-/**
- * @brief USART Clock Init Structure definition
- */
-
-typedef struct
-{
-
- uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
- This parameter can be a value of @ref USART_Clock */
-
- uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock.
- This parameter can be a value of @ref USART_Clock_Polarity */
-
- uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref USART_Clock_Phase */
-
- uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
- data bit (MSB) has to be output on the SCLK pin in synchronous mode.
- This parameter can be a value of @ref USART_Last_Bit */
-} USART_ClockInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup USART_Exported_Constants
- * @{
- */
-
-#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
- ((PERIPH) == USART2) || \
- ((PERIPH) == USART3) || \
- ((PERIPH) == UART4) || \
- ((PERIPH) == UART5) || \
- ((PERIPH) == USART6) || \
- ((PERIPH) == UART7) || \
- ((PERIPH) == UART8) || \
- ((PERIPH) == UART9) || \
- ((PERIPH) == UART10))
-
-#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \
- ((PERIPH) == USART2) || \
- ((PERIPH) == USART3) || \
- ((PERIPH) == USART6))
-
-/** @defgroup USART_Word_Length
- * @{
- */
-
-#define USART_WordLength_8b ((uint16_t)0x0000)
-#define USART_WordLength_9b ((uint16_t)0x1000)
-
-#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
- ((LENGTH) == USART_WordLength_9b))
-/**
- * @}
- */
-
-/** @defgroup USART_Stop_Bits
- * @{
- */
-
-#define USART_StopBits_1 ((uint16_t)0x0000)
-#define USART_StopBits_0_5 ((uint16_t)0x1000)
-#define USART_StopBits_2 ((uint16_t)0x2000)
-#define USART_StopBits_1_5 ((uint16_t)0x3000)
-#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
- ((STOPBITS) == USART_StopBits_0_5) || \
- ((STOPBITS) == USART_StopBits_2) || \
- ((STOPBITS) == USART_StopBits_1_5))
-/**
- * @}
- */
-
-/** @defgroup USART_Parity
- * @{
- */
-
-#define USART_Parity_No ((uint16_t)0x0000)
-#define USART_Parity_Even ((uint16_t)0x0400)
-#define USART_Parity_Odd ((uint16_t)0x0600)
-#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
- ((PARITY) == USART_Parity_Even) || \
- ((PARITY) == USART_Parity_Odd))
-/**
- * @}
- */
-
-/** @defgroup USART_Mode
- * @{
- */
-
-#define USART_Mode_Rx ((uint16_t)0x0004)
-#define USART_Mode_Tx ((uint16_t)0x0008)
-#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
-/**
- * @}
- */
-
-/** @defgroup USART_Hardware_Flow_Control
- * @{
- */
-#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
-#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
-#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
-#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
-#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
- (((CONTROL) == USART_HardwareFlowControl_None) || \
- ((CONTROL) == USART_HardwareFlowControl_RTS) || \
- ((CONTROL) == USART_HardwareFlowControl_CTS) || \
- ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
-/**
- * @}
- */
-
-/** @defgroup USART_Clock
- * @{
- */
-#define USART_Clock_Disable ((uint16_t)0x0000)
-#define USART_Clock_Enable ((uint16_t)0x0800)
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
- ((CLOCK) == USART_Clock_Enable))
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Polarity
- * @{
- */
-
-#define USART_CPOL_Low ((uint16_t)0x0000)
-#define USART_CPOL_High ((uint16_t)0x0400)
-#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
-
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Phase
- * @{
- */
-
-#define USART_CPHA_1Edge ((uint16_t)0x0000)
-#define USART_CPHA_2Edge ((uint16_t)0x0200)
-#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
-
-/**
- * @}
- */
-
-/** @defgroup USART_Last_Bit
- * @{
- */
-
-#define USART_LastBit_Disable ((uint16_t)0x0000)
-#define USART_LastBit_Enable ((uint16_t)0x0100)
-#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
- ((LASTBIT) == USART_LastBit_Enable))
-/**
- * @}
- */
-
-/** @defgroup USART_Interrupt_definition
- * @{
- */
-
-#define USART_IT_PE ((uint16_t)0x0028)
-#define USART_IT_TXE ((uint16_t)0x0727)
-#define USART_IT_TC ((uint16_t)0x0626)
-#define USART_IT_RXNE ((uint16_t)0x0525)
-#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */
-#define USART_IT_IDLE ((uint16_t)0x0424)
-#define USART_IT_LBD ((uint16_t)0x0846)
-#define USART_IT_CTS ((uint16_t)0x096A)
-#define USART_IT_ERR ((uint16_t)0x0060)
-#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */
-#define USART_IT_NE ((uint16_t)0x0260)
-#define USART_IT_FE ((uint16_t)0x0160)
-
-/** @defgroup USART_Legacy
- * @{
- */
-#define USART_IT_ORE USART_IT_ORE_ER
-/**
- * @}
- */
-
-#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
- ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
- ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
- ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
-#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
- ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
- ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
- ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
- ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \
- ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
-#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
- ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
-/**
- * @}
- */
-
-/** @defgroup USART_DMA_Requests
- * @{
- */
-
-#define USART_DMAReq_Tx ((uint16_t)0x0080)
-#define USART_DMAReq_Rx ((uint16_t)0x0040)
-#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
-
-/**
- * @}
- */
-
-/** @defgroup USART_WakeUp_methods
- * @{
- */
-
-#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
-#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
-#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
- ((WAKEUP) == USART_WakeUp_AddressMark))
-/**
- * @}
- */
-
-/** @defgroup USART_LIN_Break_Detection_Length
- * @{
- */
-
-#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
-#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
-#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
- (((LENGTH) == USART_LINBreakDetectLength_10b) || \
- ((LENGTH) == USART_LINBreakDetectLength_11b))
-/**
- * @}
- */
-
-/** @defgroup USART_IrDA_Low_Power
- * @{
- */
-
-#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
-#define USART_IrDAMode_Normal ((uint16_t)0x0000)
-#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
- ((MODE) == USART_IrDAMode_Normal))
-/**
- * @}
- */
-
-/** @defgroup USART_Flags
- * @{
- */
-
-#define USART_FLAG_CTS ((uint16_t)0x0200)
-#define USART_FLAG_LBD ((uint16_t)0x0100)
-#define USART_FLAG_TXE ((uint16_t)0x0080)
-#define USART_FLAG_TC ((uint16_t)0x0040)
-#define USART_FLAG_RXNE ((uint16_t)0x0020)
-#define USART_FLAG_IDLE ((uint16_t)0x0010)
-#define USART_FLAG_ORE ((uint16_t)0x0008)
-#define USART_FLAG_NE ((uint16_t)0x0004)
-#define USART_FLAG_FE ((uint16_t)0x0002)
-#define USART_FLAG_PE ((uint16_t)0x0001)
-#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
- ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
- ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
- ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
- ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
-
-#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
-
-#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 10500001))
-#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
-#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the USART configuration to the default reset state ***/
-void USART_DeInit(USART_TypeDef* USARTx);
-
-/* Initialization and Configuration functions *********************************/
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-
-/* Data transfers functions ***************************************************/
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
-
-/* Multi-Processor Communication functions ************************************/
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-
-/* LIN mode functions *********************************************************/
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SendBreak(USART_TypeDef* USARTx);
-
-/* Half-duplex mode function **************************************************/
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-
-/* Smartcard mode functions ***************************************************/
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
-
-/* IrDA mode functions ********************************************************/
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
-
-/* DMA transfers management functions *****************************************/
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_USART_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_wwdg.c b/底盘/底盘-old/底盘/Library/stm32f4xx_wwdg.c
deleted file mode 100644
index 8a48913..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_wwdg.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_wwdg.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Window watchdog (WWDG) peripheral:
- * + Prescaler, Refresh window and Counter configuration
- * + WWDG activation
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### WWDG features #####
- ===============================================================================
- [..]
- Once enabled the WWDG generates a system reset on expiry of a programmed
- time period, unless the program refreshes the counter (downcounter)
- before to reach 0x3F value (i.e. a reset is generated when the counter
- value rolls over from 0x40 to 0x3F).
- An MCU reset is also generated if the counter value is refreshed
- before the counter has reached the refresh window value. This
- implies that the counter must be refreshed in a limited window.
-
- Once enabled the WWDG cannot be disabled except by a system reset.
-
- WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
- reset occurs.
-
- The WWDG counter input clock is derived from the APB clock divided
- by a programmable prescaler.
-
- WWDG counter clock = PCLK1 / Prescaler
- WWDG timeout = (WWDG counter clock) * (counter value)
-
- Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms
-
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function
-
- (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function
-
- (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function
-
- (#) Set the WWDG counter value and start it using WWDG_Enable() function.
- When the WWDG is enabled the counter value should be configured to
- a value greater than 0x40 to prevent generating an immediate reset.
-
- (#) Optionally you can enable the Early wakeup interrupt which is
- generated when the counter reach 0x40.
- Once enabled this interrupt cannot be disabled except by a system reset.
-
- (#) Then the application program must refresh the WWDG counter at regular
- intervals during normal operation to prevent an MCU reset, using
- WWDG_SetCounter() function. This operation must occur only when
- the counter value is lower than the refresh window value,
- programmed using WWDG_SetWindowValue().
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_wwdg.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup WWDG
- * @brief WWDG driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ----------- WWDG registers bit address in the alias region ----------- */
-#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
-/* Alias word address of EWI bit */
-#define CFR_OFFSET (WWDG_OFFSET + 0x04)
-#define EWI_BitNumber 0x09
-#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
-
-/* --------------------- WWDG registers bit mask ------------------------ */
-/* CFR register bit mask */
-#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)
-#define CFR_W_MASK ((uint32_t)0xFFFFFF80)
-#define BIT_MASK ((uint8_t)0x7F)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup WWDG_Private_Functions
- * @{
- */
-
-/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
- * @brief Prescaler, Refresh window and Counter configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Prescaler, Refresh window and Counter configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the WWDG peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void WWDG_DeInit(void)
-{
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
-}
-
-/**
- * @brief Sets the WWDG Prescaler.
- * @param WWDG_Prescaler: specifies the WWDG Prescaler.
- * This parameter can be one of the following values:
- * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
- * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
- * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
- * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
- * @retval None
- */
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
- /* Clear WDGTB[1:0] bits */
- tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
- /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
- tmpreg |= WWDG_Prescaler;
- /* Store the new value */
- WWDG->CFR = tmpreg;
-}
-
-/**
- * @brief Sets the WWDG window value.
- * @param WindowValue: specifies the window value to be compared to the downcounter.
- * This parameter value must be lower than 0x80.
- * @retval None
- */
-void WWDG_SetWindowValue(uint8_t WindowValue)
-{
- __IO uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
- /* Clear W[6:0] bits */
-
- tmpreg = WWDG->CFR & CFR_W_MASK;
-
- /* Set W[6:0] bits according to WindowValue value */
- tmpreg |= WindowValue & (uint32_t) BIT_MASK;
-
- /* Store the new value */
- WWDG->CFR = tmpreg;
-}
-
-/**
- * @brief Enables the WWDG Early Wakeup interrupt(EWI).
- * @note Once enabled this interrupt cannot be disabled except by a system reset.
- * @param None
- * @retval None
- */
-void WWDG_EnableIT(void)
-{
- *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
-}
-
-/**
- * @brief Sets the WWDG counter value.
- * @param Counter: specifies the watchdog counter value.
- * This parameter must be a number between 0x40 and 0x7F (to prevent generating
- * an immediate reset)
- * @retval None
- */
-void WWDG_SetCounter(uint8_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_WWDG_COUNTER(Counter));
- /* Write to T[6:0] bits to configure the counter value, no need to do
- a read-modify-write; writing a 0 to WDGA bit does nothing */
- WWDG->CR = Counter & BIT_MASK;
-}
-/**
- * @}
- */
-
-/** @defgroup WWDG_Group2 WWDG activation functions
- * @brief WWDG activation functions
- *
-@verbatim
- ===============================================================================
- ##### WWDG activation function #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables WWDG and load the counter value.
- * @param Counter: specifies the watchdog counter value.
- * This parameter must be a number between 0x40 and 0x7F (to prevent generating
- * an immediate reset)
- * @retval None
- */
-void WWDG_Enable(uint8_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_WWDG_COUNTER(Counter));
- WWDG->CR = WWDG_CR_WDGA | Counter;
-}
-/**
- * @}
- */
-
-/** @defgroup WWDG_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the Early Wakeup interrupt flag is set or not.
- * @param None
- * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
- */
-FlagStatus WWDG_GetFlagStatus(void)
-{
- FlagStatus bitstatus = RESET;
-
- if ((WWDG->SR) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears Early Wakeup interrupt flag.
- * @param None
- * @retval None
- */
-void WWDG_ClearFlag(void)
-{
- WWDG->SR = (uint32_t)RESET;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Library/stm32f4xx_wwdg.h b/底盘/底盘-old/底盘/Library/stm32f4xx_wwdg.h
deleted file mode 100644
index a5e3131..0000000
--- a/底盘/底盘-old/底盘/Library/stm32f4xx_wwdg.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_wwdg.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains all the functions prototypes for the WWDG firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_WWDG_H
-#define __STM32F4xx_WWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup WWDG
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Constants
- * @{
- */
-
-/** @defgroup WWDG_Prescaler
- * @{
- */
-
-#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
-#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
-#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
-#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
-#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
- ((PRESCALER) == WWDG_Prescaler_2) || \
- ((PRESCALER) == WWDG_Prescaler_4) || \
- ((PRESCALER) == WWDG_Prescaler_8))
-#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
-#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the WWDG configuration to the default reset state ****/
-void WWDG_DeInit(void);
-
-/* Prescaler, Refresh window and Counter configuration functions **************/
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
-void WWDG_SetWindowValue(uint8_t WindowValue);
-void WWDG_EnableIT(void);
-void WWDG_SetCounter(uint8_t Counter);
-
-/* WWDG activation function ***************************************************/
-void WWDG_Enable(uint8_t Counter);
-
-/* Interrupts and flags management functions **********************************/
-FlagStatus WWDG_GetFlagStatus(void);
-void WWDG_ClearFlag(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_WWDG_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/底盘/底盘-old/底盘/Listings/startup_stm32f40_41xxx.lst b/底盘/底盘-old/底盘/Listings/startup_stm32f40_41xxx.lst
deleted file mode 100644
index 9f2447e..0000000
--- a/底盘/底盘-old/底盘/Listings/startup_stm32f40_41xxx.lst
+++ /dev/null
@@ -1,1948 +0,0 @@
-
-
-
-ARM Macro Assembler Page 1
-
-
- 1 00000000 ;******************** (C) COPYRIGHT 2016 STMicroelectron
- ics ********************
- 2 00000000 ;* File Name : startup_stm32f40_41xxx.s
- 3 00000000 ;* Author : MCD Application Team
- 4 00000000 ;* @version : V1.8.1
- 5 00000000 ;* @date : 27-January-2022
- 6 00000000 ;* Description : STM32F40xxx/41xxx devices vector
- table for MDK-ARM toolchain.
- 7 00000000 ;* This module performs:
- 8 00000000 ;* - Set the initial SP
- 9 00000000 ;* - Set the initial PC == Reset_Ha
- ndler
- 10 00000000 ;* - Set the vector table entries w
- ith the exceptions ISR address
- 11 00000000 ;* - Configure the system clock and
- the external SRAM mounted on
- 12 00000000 ;* STM324xG-EVAL board to be used
- as data memory (optional,
- 13 00000000 ;* to be enabled by user)
- 14 00000000 ;* - Branches to __main in the C li
- brary (which eventually
- 15 00000000 ;* calls main()).
- 16 00000000 ;* After Reset the CortexM4 process
- or is in Thread mode,
- 17 00000000 ;* priority is Privileged, and the
- Stack is set to Main.
- 18 00000000 ;* <<< Use Configuration Wizard in Context Menu >>>
- 19 00000000 ;*******************************************************
- ***********************
- 20 00000000 ;* @attention
- 21 00000000 ;*
- 22 00000000 ;* Copyright (c) 2016 STMicroelectronics.
- 23 00000000 ;* All rights reserved.
- 24 00000000 ;*
- 25 00000000 ;* This software is licensed under terms that can be fou
- nd in the LICENSE file
- 26 00000000 ;* in the root directory of this software component.
- 27 00000000 ;* If no LICENSE file comes with this software, it is pr
- ovided AS-IS.
- 28 00000000 ;*
- 29 00000000 ;*******************************************************
- ***********************
- 30 00000000
- 31 00000000 ; Amount of memory (in bytes) allocated for Stack
- 32 00000000 ; Tailor this value to your application needs
- 33 00000000 ; Stack Configuration
- 34 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
- 35 00000000 ;
- 36 00000000
- 37 00000000 00000400
- Stack_Size
- EQU 0x00000400
- 38 00000000
- 39 00000000 AREA STACK, NOINIT, READWRITE, ALIGN
-=3
- 40 00000000 Stack_Mem
- SPACE Stack_Size
- 41 00000400 __initial_sp
- 42 00000400
-
-
-
-ARM Macro Assembler Page 2
-
-
- 43 00000400
- 44 00000400 ; Heap Configuration
- 45 00000400 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
- 46 00000400 ;
- 47 00000400
- 48 00000400 00000200
- Heap_Size
- EQU 0x00000200
- 49 00000400
- 50 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN=
-3
- 51 00000000 __heap_base
- 52 00000000 Heap_Mem
- SPACE Heap_Size
- 53 00000200 __heap_limit
- 54 00000200
- 55 00000200 PRESERVE8
- 56 00000200 THUMB
- 57 00000200
- 58 00000200
- 59 00000200 ; Vector Table Mapped to Address 0 at Reset
- 60 00000200 AREA RESET, DATA, READONLY
- 61 00000000 EXPORT __Vectors
- 62 00000000 EXPORT __Vectors_End
- 63 00000000 EXPORT __Vectors_Size
- 64 00000000
- 65 00000000 00000000
- __Vectors
- DCD __initial_sp ; Top of Stack
- 66 00000004 00000000 DCD Reset_Handler ; Reset Handler
- 67 00000008 00000000 DCD NMI_Handler ; NMI Handler
- 68 0000000C 00000000 DCD HardFault_Handler ; Hard Fault
- Handler
- 69 00000010 00000000 DCD MemManage_Handler
- ; MPU Fault Handler
-
- 70 00000014 00000000 DCD BusFault_Handler
- ; Bus Fault Handler
-
- 71 00000018 00000000 DCD UsageFault_Handler ; Usage Faul
- t Handler
- 72 0000001C 00000000 DCD 0 ; Reserved
- 73 00000020 00000000 DCD 0 ; Reserved
- 74 00000024 00000000 DCD 0 ; Reserved
- 75 00000028 00000000 DCD 0 ; Reserved
- 76 0000002C 00000000 DCD SVC_Handler ; SVCall Handler
- 77 00000030 00000000 DCD DebugMon_Handler ; Debug Monito
- r Handler
- 78 00000034 00000000 DCD 0 ; Reserved
- 79 00000038 00000000 DCD PendSV_Handler ; PendSV Handler
-
- 80 0000003C 00000000 DCD SysTick_Handler
- ; SysTick Handler
- 81 00000040
- 82 00000040 ; External Interrupts
- 83 00000040 00000000 DCD WWDG_IRQHandler ; Window WatchD
- og
-
-
-
-
-
-ARM Macro Assembler Page 3
-
-
- 84 00000044 00000000 DCD PVD_IRQHandler ; PVD through EX
- TI Line detection
-
-
- 85 00000048 00000000 DCD TAMP_STAMP_IRQHandler ; Tamper
- and TimeStamps thro
- ugh the EXTI line
-
- 86 0000004C 00000000 DCD RTC_WKUP_IRQHandler ; RTC Wakeu
- p through the EXTI
- line
-
- 87 00000050 00000000 DCD FLASH_IRQHandler ; FLASH
-
-
- 88 00000054 00000000 DCD RCC_IRQHandler ; RCC
-
-
- 89 00000058 00000000 DCD EXTI0_IRQHandler ; EXTI Line0
-
-
-
- 90 0000005C 00000000 DCD EXTI1_IRQHandler ; EXTI Line1
-
-
-
- 91 00000060 00000000 DCD EXTI2_IRQHandler ; EXTI Line2
-
-
-
- 92 00000064 00000000 DCD EXTI3_IRQHandler ; EXTI Line3
-
-
-
- 93 00000068 00000000 DCD EXTI4_IRQHandler ; EXTI Line4
-
-
-
- 94 0000006C 00000000 DCD DMA1_Stream0_IRQHandler ; DMA1
- Stream 0
-
-
- 95 00000070 00000000 DCD DMA1_Stream1_IRQHandler ; DMA1
- Stream 1
-
-
- 96 00000074 00000000 DCD DMA1_Stream2_IRQHandler ; DMA1
- Stream 2
-
-
- 97 00000078 00000000 DCD DMA1_Stream3_IRQHandler ; DMA1
- Stream 3
-
-
- 98 0000007C 00000000 DCD DMA1_Stream4_IRQHandler ; DMA1
- Stream 4
-
-
- 99 00000080 00000000 DCD DMA1_Stream5_IRQHandler ; DMA1
-
-
-
-ARM Macro Assembler Page 4
-
-
- Stream 5
-
-
- 100 00000084 00000000 DCD DMA1_Stream6_IRQHandler ; DMA1
- Stream 6
-
-
- 101 00000088 00000000 DCD ADC_IRQHandler ; ADC1, ADC2 and
- ADC3s
-
- 102 0000008C 00000000 DCD CAN1_TX_IRQHandler ; CAN1 TX
-
-
-
- 103 00000090 00000000 DCD CAN1_RX0_IRQHandler ; CAN1 RX0
-
-
-
- 104 00000094 00000000 DCD CAN1_RX1_IRQHandler ; CAN1 RX1
-
-
-
- 105 00000098 00000000 DCD CAN1_SCE_IRQHandler ; CAN1 SCE
-
-
-
- 106 0000009C 00000000 DCD EXTI9_5_IRQHandler ; External L
- ine[9:5]s
-
-
- 107 000000A0 00000000 DCD TIM1_BRK_TIM9_IRQHandler ; TIM1
- Break and TIM9
-
- 108 000000A4 00000000 DCD TIM1_UP_TIM10_IRQHandler ; TIM1
- Update and TIM10
-
- 109 000000A8 00000000 DCD TIM1_TRG_COM_TIM11_IRQHandler ;
- TIM1 Trigger and C
- ommutation and TIM1
- 1
- 110 000000AC 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu
- re Compare
-
-
- 111 000000B0 00000000 DCD TIM2_IRQHandler ; TIM2
-
-
- 112 000000B4 00000000 DCD TIM3_IRQHandler ; TIM3
-
-
- 113 000000B8 00000000 DCD TIM4_IRQHandler ; TIM4
-
-
- 114 000000BC 00000000 DCD I2C1_EV_IRQHandler ; I2C1 Event
-
-
-
- 115 000000C0 00000000 DCD I2C1_ER_IRQHandler ; I2C1 Error
-
-
-
-
-ARM Macro Assembler Page 5
-
-
-
-
- 116 000000C4 00000000 DCD I2C2_EV_IRQHandler ; I2C2 Event
-
-
-
- 117 000000C8 00000000 DCD I2C2_ER_IRQHandler ; I2C2 Error
-
-
-
- 118 000000CC 00000000 DCD SPI1_IRQHandler ; SPI1
-
-
- 119 000000D0 00000000 DCD SPI2_IRQHandler ; SPI2
-
-
- 120 000000D4 00000000 DCD USART1_IRQHandler ; USART1
-
-
- 121 000000D8 00000000 DCD USART2_IRQHandler ; USART2
-
-
- 122 000000DC 00000000 DCD USART3_IRQHandler ; USART3
-
-
- 123 000000E0 00000000 DCD EXTI15_10_IRQHandler ; External
- Line[15:10]s
-
-
- 124 000000E4 00000000 DCD RTC_Alarm_IRQHandler ; RTC Alar
- m (A and B) through
- EXTI Line
-
- 125 000000E8 00000000 DCD OTG_FS_WKUP_IRQHandler ; USB OT
- G FS Wakeup through
- EXTI line
-
- 126 000000EC 00000000 DCD TIM8_BRK_TIM12_IRQHandler ; TIM
- 8 Break and TIM12
-
- 127 000000F0 00000000 DCD TIM8_UP_TIM13_IRQHandler ; TIM8
- Update and TIM13
-
- 128 000000F4 00000000 DCD TIM8_TRG_COM_TIM14_IRQHandler ;
- TIM8 Trigger and C
- ommutation and TIM1
- 4
- 129 000000F8 00000000 DCD TIM8_CC_IRQHandler ; TIM8 Captu
- re Compare
-
-
- 130 000000FC 00000000 DCD DMA1_Stream7_IRQHandler ; DMA1
- Stream7
-
-
- 131 00000100 00000000 DCD FSMC_IRQHandler ; FSMC
-
-
- 132 00000104 00000000 DCD SDIO_IRQHandler ; SDIO
-
-
-
-ARM Macro Assembler Page 6
-
-
-
-
- 133 00000108 00000000 DCD TIM5_IRQHandler ; TIM5
-
-
- 134 0000010C 00000000 DCD SPI3_IRQHandler ; SPI3
-
-
- 135 00000110 00000000 DCD UART4_IRQHandler ; UART4
-
-
- 136 00000114 00000000 DCD UART5_IRQHandler ; UART5
-
-
- 137 00000118 00000000 DCD TIM6_DAC_IRQHandler ; TIM6 and
- DAC1&2 underrun err
- ors
-
- 138 0000011C 00000000 DCD TIM7_IRQHandler ; TIM7
-
- 139 00000120 00000000 DCD DMA2_Stream0_IRQHandler ; DMA2
- Stream 0
-
-
- 140 00000124 00000000 DCD DMA2_Stream1_IRQHandler ; DMA2
- Stream 1
-
-
- 141 00000128 00000000 DCD DMA2_Stream2_IRQHandler ; DMA2
- Stream 2
-
-
- 142 0000012C 00000000 DCD DMA2_Stream3_IRQHandler ; DMA2
- Stream 3
-
-
- 143 00000130 00000000 DCD DMA2_Stream4_IRQHandler ; DMA2
- Stream 4
-
-
- 144 00000134 00000000 DCD ETH_IRQHandler ; Ethernet
-
-
- 145 00000138 00000000 DCD ETH_WKUP_IRQHandler ; Ethernet
- Wakeup through EXTI
- line
-
- 146 0000013C 00000000 DCD CAN2_TX_IRQHandler ; CAN2 TX
-
-
-
- 147 00000140 00000000 DCD CAN2_RX0_IRQHandler ; CAN2 RX0
-
-
-
- 148 00000144 00000000 DCD CAN2_RX1_IRQHandler ; CAN2 RX1
-
-
-
-
-
-
-ARM Macro Assembler Page 7
-
-
- 149 00000148 00000000 DCD CAN2_SCE_IRQHandler ; CAN2 SCE
-
-
-
- 150 0000014C 00000000 DCD OTG_FS_IRQHandler ; USB OTG FS
-
-
- 151 00000150 00000000 DCD DMA2_Stream5_IRQHandler ; DMA2
- Stream 5
-
-
- 152 00000154 00000000 DCD DMA2_Stream6_IRQHandler ; DMA2
- Stream 6
-
-
- 153 00000158 00000000 DCD DMA2_Stream7_IRQHandler ; DMA2
- Stream 7
-
-
- 154 0000015C 00000000 DCD USART6_IRQHandler ; USART6
-
-
-
- 155 00000160 00000000 DCD I2C3_EV_IRQHandler ; I2C3 event
-
-
-
- 156 00000164 00000000 DCD I2C3_ER_IRQHandler ; I2C3 error
-
-
-
- 157 00000168 00000000 DCD OTG_HS_EP1_OUT_IRQHandler ; USB
- OTG HS End Point 1
- Out
-
- 158 0000016C 00000000 DCD OTG_HS_EP1_IN_IRQHandler ; USB
- OTG HS End Point 1
- In
-
- 159 00000170 00000000 DCD OTG_HS_WKUP_IRQHandler ; USB OT
- G HS Wakeup through
- EXTI
-
- 160 00000174 00000000 DCD OTG_HS_IRQHandler ; USB OTG HS
-
-
- 161 00000178 00000000 DCD DCMI_IRQHandler ; DCMI
-
-
- 162 0000017C 00000000 DCD CRYP_IRQHandler ; CRYP crypto
-
-
- 163 00000180 00000000 DCD HASH_RNG_IRQHandler
- ; Hash and Rng
- 164 00000184 00000000 DCD FPU_IRQHandler ; FPU
- 165 00000188
- 166 00000188 __Vectors_End
- 167 00000188
- 168 00000188 00000188
-
-
-
-ARM Macro Assembler Page 8
-
-
- __Vectors_Size
- EQU __Vectors_End - __Vectors
- 169 00000188
- 170 00000188 AREA |.text|, CODE, READONLY
- 171 00000000
- 172 00000000 ; Reset handler
- 173 00000000 Reset_Handler
- PROC
- 174 00000000 EXPORT Reset_Handler [WEAK
-]
- 175 00000000 IMPORT SystemInit
- 176 00000000 IMPORT __main
- 177 00000000
- 178 00000000 4806 LDR R0, =SystemInit
- 179 00000002 4780 BLX R0
- 180 00000004 4806 LDR R0, =__main
- 181 00000006 4700 BX R0
- 182 00000008 ENDP
- 183 00000008
- 184 00000008 ; Dummy Exception Handlers (infinite loops which can be
- modified)
- 185 00000008
- 186 00000008 NMI_Handler
- PROC
- 187 00000008 EXPORT NMI_Handler [WEA
-K]
- 188 00000008 E7FE B .
- 189 0000000A ENDP
- 191 0000000A HardFault_Handler
- PROC
- 192 0000000A EXPORT HardFault_Handler [WEA
-K]
- 193 0000000A E7FE B .
- 194 0000000C ENDP
- 196 0000000C MemManage_Handler
- PROC
- 197 0000000C EXPORT MemManage_Handler [WEA
-K]
- 198 0000000C E7FE B .
- 199 0000000E ENDP
- 201 0000000E BusFault_Handler
- PROC
- 202 0000000E EXPORT BusFault_Handler [WEA
-K]
- 203 0000000E E7FE B .
- 204 00000010 ENDP
- 206 00000010 UsageFault_Handler
- PROC
- 207 00000010 EXPORT UsageFault_Handler [WEA
-K]
- 208 00000010 E7FE B .
- 209 00000012 ENDP
- 210 00000012 SVC_Handler
- PROC
- 211 00000012 EXPORT SVC_Handler [WEA
-K]
- 212 00000012 E7FE B .
- 213 00000014 ENDP
- 215 00000014 DebugMon_Handler
-
-
-
-ARM Macro Assembler Page 9
-
-
- PROC
- 216 00000014 EXPORT DebugMon_Handler [WEA
-K]
- 217 00000014 E7FE B .
- 218 00000016 ENDP
- 219 00000016 PendSV_Handler
- PROC
- 220 00000016 EXPORT PendSV_Handler [WEA
-K]
- 221 00000016 E7FE B .
- 222 00000018 ENDP
- 223 00000018 SysTick_Handler
- PROC
- 224 00000018 EXPORT SysTick_Handler [WEA
-K]
- 225 00000018 E7FE B .
- 226 0000001A ENDP
- 227 0000001A
- 228 0000001A Default_Handler
- PROC
- 229 0000001A
- 230 0000001A EXPORT WWDG_IRQHandler
- [WEAK]
- 231 0000001A EXPORT PVD_IRQHandler
- [WEAK]
- 232 0000001A EXPORT TAMP_STAMP_IRQHandler
- [WEAK]
- 233 0000001A EXPORT RTC_WKUP_IRQHandler
- [WEAK]
- 234 0000001A EXPORT FLASH_IRQHandler
- [WEAK]
- 235 0000001A EXPORT RCC_IRQHandler
- [WEAK]
- 236 0000001A EXPORT EXTI0_IRQHandler
- [WEAK]
- 237 0000001A EXPORT EXTI1_IRQHandler
- [WEAK]
- 238 0000001A EXPORT EXTI2_IRQHandler
- [WEAK]
- 239 0000001A EXPORT EXTI3_IRQHandler
- [WEAK]
- 240 0000001A EXPORT EXTI4_IRQHandler
- [WEAK]
- 241 0000001A EXPORT DMA1_Stream0_IRQHandler
- [WEAK]
- 242 0000001A EXPORT DMA1_Stream1_IRQHandler
- [WEAK]
- 243 0000001A EXPORT DMA1_Stream2_IRQHandler
- [WEAK]
- 244 0000001A EXPORT DMA1_Stream3_IRQHandler
- [WEAK]
- 245 0000001A EXPORT DMA1_Stream4_IRQHandler
- [WEAK]
- 246 0000001A EXPORT DMA1_Stream5_IRQHandler
- [WEAK]
- 247 0000001A EXPORT DMA1_Stream6_IRQHandler
- [WEAK]
- 248 0000001A EXPORT ADC_IRQHandler
- [WEAK]
-
-
-
-ARM Macro Assembler Page 10
-
-
- 249 0000001A EXPORT CAN1_TX_IRQHandler
- [WEAK]
- 250 0000001A EXPORT CAN1_RX0_IRQHandler
- [WEAK]
- 251 0000001A EXPORT CAN1_RX1_IRQHandler
- [WEAK]
- 252 0000001A EXPORT CAN1_SCE_IRQHandler
- [WEAK]
- 253 0000001A EXPORT EXTI9_5_IRQHandler
- [WEAK]
- 254 0000001A EXPORT TIM1_BRK_TIM9_IRQHandler
- [WEAK]
- 255 0000001A EXPORT TIM1_UP_TIM10_IRQHandler
- [WEAK]
- 256 0000001A EXPORT TIM1_TRG_COM_TIM11_IRQHandler
- [WEAK]
- 257 0000001A EXPORT TIM1_CC_IRQHandler
- [WEAK]
- 258 0000001A EXPORT TIM2_IRQHandler
- [WEAK]
- 259 0000001A EXPORT TIM3_IRQHandler
- [WEAK]
- 260 0000001A EXPORT TIM4_IRQHandler
- [WEAK]
- 261 0000001A EXPORT I2C1_EV_IRQHandler
- [WEAK]
- 262 0000001A EXPORT I2C1_ER_IRQHandler
- [WEAK]
- 263 0000001A EXPORT I2C2_EV_IRQHandler
- [WEAK]
- 264 0000001A EXPORT I2C2_ER_IRQHandler
- [WEAK]
- 265 0000001A EXPORT SPI1_IRQHandler
- [WEAK]
- 266 0000001A EXPORT SPI2_IRQHandler
- [WEAK]
- 267 0000001A EXPORT USART1_IRQHandler
- [WEAK]
- 268 0000001A EXPORT USART2_IRQHandler
- [WEAK]
- 269 0000001A EXPORT USART3_IRQHandler
- [WEAK]
- 270 0000001A EXPORT EXTI15_10_IRQHandler
- [WEAK]
- 271 0000001A EXPORT RTC_Alarm_IRQHandler
- [WEAK]
- 272 0000001A EXPORT OTG_FS_WKUP_IRQHandler
- [WEAK]
- 273 0000001A EXPORT TIM8_BRK_TIM12_IRQHandler
- [WEAK]
- 274 0000001A EXPORT TIM8_UP_TIM13_IRQHandler
- [WEAK]
- 275 0000001A EXPORT TIM8_TRG_COM_TIM14_IRQHandler
- [WEAK]
- 276 0000001A EXPORT TIM8_CC_IRQHandler
- [WEAK]
- 277 0000001A EXPORT DMA1_Stream7_IRQHandler
- [WEAK]
- 278 0000001A EXPORT FSMC_IRQHandler
-
-
-
-ARM Macro Assembler Page 11
-
-
- [WEAK]
- 279 0000001A EXPORT SDIO_IRQHandler
- [WEAK]
- 280 0000001A EXPORT TIM5_IRQHandler
- [WEAK]
- 281 0000001A EXPORT SPI3_IRQHandler
- [WEAK]
- 282 0000001A EXPORT UART4_IRQHandler
- [WEAK]
- 283 0000001A EXPORT UART5_IRQHandler
- [WEAK]
- 284 0000001A EXPORT TIM6_DAC_IRQHandler
- [WEAK]
- 285 0000001A EXPORT TIM7_IRQHandler
- [WEAK]
- 286 0000001A EXPORT DMA2_Stream0_IRQHandler
- [WEAK]
- 287 0000001A EXPORT DMA2_Stream1_IRQHandler
- [WEAK]
- 288 0000001A EXPORT DMA2_Stream2_IRQHandler
- [WEAK]
- 289 0000001A EXPORT DMA2_Stream3_IRQHandler
- [WEAK]
- 290 0000001A EXPORT DMA2_Stream4_IRQHandler
- [WEAK]
- 291 0000001A EXPORT ETH_IRQHandler
- [WEAK]
- 292 0000001A EXPORT ETH_WKUP_IRQHandler
- [WEAK]
- 293 0000001A EXPORT CAN2_TX_IRQHandler
- [WEAK]
- 294 0000001A EXPORT CAN2_RX0_IRQHandler
- [WEAK]
- 295 0000001A EXPORT CAN2_RX1_IRQHandler
- [WEAK]
- 296 0000001A EXPORT CAN2_SCE_IRQHandler
- [WEAK]
- 297 0000001A EXPORT OTG_FS_IRQHandler
- [WEAK]
- 298 0000001A EXPORT DMA2_Stream5_IRQHandler
- [WEAK]
- 299 0000001A EXPORT DMA2_Stream6_IRQHandler
- [WEAK]
- 300 0000001A EXPORT DMA2_Stream7_IRQHandler
- [WEAK]
- 301 0000001A EXPORT USART6_IRQHandler
- [WEAK]
- 302 0000001A EXPORT I2C3_EV_IRQHandler
- [WEAK]
- 303 0000001A EXPORT I2C3_ER_IRQHandler
- [WEAK]
- 304 0000001A EXPORT OTG_HS_EP1_OUT_IRQHandler
- [WEAK]
- 305 0000001A EXPORT OTG_HS_EP1_IN_IRQHandler
- [WEAK]
- 306 0000001A EXPORT OTG_HS_WKUP_IRQHandler
- [WEAK]
- 307 0000001A EXPORT OTG_HS_IRQHandler
- [WEAK]
-
-
-
-ARM Macro Assembler Page 12
-
-
- 308 0000001A EXPORT DCMI_IRQHandler
- [WEAK]
- 309 0000001A EXPORT CRYP_IRQHandler
- [WEAK]
- 310 0000001A EXPORT HASH_RNG_IRQHandler
- [WEAK]
- 311 0000001A EXPORT FPU_IRQHandler
- [WEAK]
- 312 0000001A
- 313 0000001A WWDG_IRQHandler
- 314 0000001A PVD_IRQHandler
- 315 0000001A TAMP_STAMP_IRQHandler
- 316 0000001A RTC_WKUP_IRQHandler
- 317 0000001A FLASH_IRQHandler
- 318 0000001A RCC_IRQHandler
- 319 0000001A EXTI0_IRQHandler
- 320 0000001A EXTI1_IRQHandler
- 321 0000001A EXTI2_IRQHandler
- 322 0000001A EXTI3_IRQHandler
- 323 0000001A EXTI4_IRQHandler
- 324 0000001A DMA1_Stream0_IRQHandler
- 325 0000001A DMA1_Stream1_IRQHandler
- 326 0000001A DMA1_Stream2_IRQHandler
- 327 0000001A DMA1_Stream3_IRQHandler
- 328 0000001A DMA1_Stream4_IRQHandler
- 329 0000001A DMA1_Stream5_IRQHandler
- 330 0000001A DMA1_Stream6_IRQHandler
- 331 0000001A ADC_IRQHandler
- 332 0000001A CAN1_TX_IRQHandler
- 333 0000001A CAN1_RX0_IRQHandler
- 334 0000001A CAN1_RX1_IRQHandler
- 335 0000001A CAN1_SCE_IRQHandler
- 336 0000001A EXTI9_5_IRQHandler
- 337 0000001A TIM1_BRK_TIM9_IRQHandler
- 338 0000001A TIM1_UP_TIM10_IRQHandler
- 339 0000001A TIM1_TRG_COM_TIM11_IRQHandler
- 340 0000001A TIM1_CC_IRQHandler
- 341 0000001A TIM2_IRQHandler
- 342 0000001A TIM3_IRQHandler
- 343 0000001A TIM4_IRQHandler
- 344 0000001A I2C1_EV_IRQHandler
- 345 0000001A I2C1_ER_IRQHandler
- 346 0000001A I2C2_EV_IRQHandler
- 347 0000001A I2C2_ER_IRQHandler
- 348 0000001A SPI1_IRQHandler
- 349 0000001A SPI2_IRQHandler
- 350 0000001A USART1_IRQHandler
- 351 0000001A USART2_IRQHandler
- 352 0000001A USART3_IRQHandler
- 353 0000001A EXTI15_10_IRQHandler
- 354 0000001A RTC_Alarm_IRQHandler
- 355 0000001A OTG_FS_WKUP_IRQHandler
- 356 0000001A TIM8_BRK_TIM12_IRQHandler
- 357 0000001A TIM8_UP_TIM13_IRQHandler
- 358 0000001A TIM8_TRG_COM_TIM14_IRQHandler
- 359 0000001A TIM8_CC_IRQHandler
- 360 0000001A DMA1_Stream7_IRQHandler
- 361 0000001A FSMC_IRQHandler
- 362 0000001A SDIO_IRQHandler
-
-
-
-ARM Macro Assembler Page 13
-
-
- 363 0000001A TIM5_IRQHandler
- 364 0000001A SPI3_IRQHandler
- 365 0000001A UART4_IRQHandler
- 366 0000001A UART5_IRQHandler
- 367 0000001A TIM6_DAC_IRQHandler
- 368 0000001A TIM7_IRQHandler
- 369 0000001A DMA2_Stream0_IRQHandler
- 370 0000001A DMA2_Stream1_IRQHandler
- 371 0000001A DMA2_Stream2_IRQHandler
- 372 0000001A DMA2_Stream3_IRQHandler
- 373 0000001A DMA2_Stream4_IRQHandler
- 374 0000001A ETH_IRQHandler
- 375 0000001A ETH_WKUP_IRQHandler
- 376 0000001A CAN2_TX_IRQHandler
- 377 0000001A CAN2_RX0_IRQHandler
- 378 0000001A CAN2_RX1_IRQHandler
- 379 0000001A CAN2_SCE_IRQHandler
- 380 0000001A OTG_FS_IRQHandler
- 381 0000001A DMA2_Stream5_IRQHandler
- 382 0000001A DMA2_Stream6_IRQHandler
- 383 0000001A DMA2_Stream7_IRQHandler
- 384 0000001A USART6_IRQHandler
- 385 0000001A I2C3_EV_IRQHandler
- 386 0000001A I2C3_ER_IRQHandler
- 387 0000001A OTG_HS_EP1_OUT_IRQHandler
- 388 0000001A OTG_HS_EP1_IN_IRQHandler
- 389 0000001A OTG_HS_WKUP_IRQHandler
- 390 0000001A OTG_HS_IRQHandler
- 391 0000001A DCMI_IRQHandler
- 392 0000001A CRYP_IRQHandler
- 393 0000001A HASH_RNG_IRQHandler
- 394 0000001A FPU_IRQHandler
- 395 0000001A
- 396 0000001A E7FE B .
- 397 0000001C
- 398 0000001C ENDP
- 399 0000001C
- 400 0000001C ALIGN
- 401 0000001C
- 402 0000001C ;*******************************************************
- ************************
- 403 0000001C ; User Stack and Heap initialization
- 404 0000001C ;*******************************************************
- ************************
- 405 0000001C IF :DEF:__MICROLIB
- 406 0000001C
- 407 0000001C EXPORT __initial_sp
- 408 0000001C EXPORT __heap_base
- 409 0000001C EXPORT __heap_limit
- 410 0000001C
- 411 0000001C ELSE
- 426 ENDIF
- 427 0000001C
- 428 0000001C END
- 00000000
- 00000000
-Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M4.fp.sp --apcs=
-interwork --depend=.\objects\startup_stm32f40_41xxx.d -o.\objects\startup_stm32
-f40_41xxx.o -IC:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.17.1\Drivers\CMSIS\Devic
-
-
-
-ARM Macro Assembler Page 14
-
-
-e\ST\STM32F4xx\Include --predefine="__MICROLIB SETA 1" --predefine="__UVISION_V
-ERSION SETA 538" --predefine="STM32F407xx SETA 1" --list=.\listings\startup_stm
-32f40_41xxx.lst Start\startup_stm32f40_41xxx.s
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-STACK 00000000
-
-Symbol: STACK
- Definitions
- At line 39 in file Start\startup_stm32f40_41xxx.s
- Uses
- None
-Comment: STACK unused
-Stack_Mem 00000000
-
-Symbol: Stack_Mem
- Definitions
- At line 40 in file Start\startup_stm32f40_41xxx.s
- Uses
- None
-Comment: Stack_Mem unused
-__initial_sp 00000400
-
-Symbol: __initial_sp
- Definitions
- At line 41 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 65 in file Start\startup_stm32f40_41xxx.s
- At line 407 in file Start\startup_stm32f40_41xxx.s
-
-3 symbols
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-HEAP 00000000
-
-Symbol: HEAP
- Definitions
- At line 50 in file Start\startup_stm32f40_41xxx.s
- Uses
- None
-Comment: HEAP unused
-Heap_Mem 00000000
-
-Symbol: Heap_Mem
- Definitions
- At line 52 in file Start\startup_stm32f40_41xxx.s
- Uses
- None
-Comment: Heap_Mem unused
-__heap_base 00000000
-
-Symbol: __heap_base
- Definitions
- At line 51 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 408 in file Start\startup_stm32f40_41xxx.s
-Comment: __heap_base used once
-__heap_limit 00000200
-
-Symbol: __heap_limit
- Definitions
- At line 53 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 409 in file Start\startup_stm32f40_41xxx.s
-Comment: __heap_limit used once
-4 symbols
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-RESET 00000000
-
-Symbol: RESET
- Definitions
- At line 60 in file Start\startup_stm32f40_41xxx.s
- Uses
- None
-Comment: RESET unused
-__Vectors 00000000
-
-Symbol: __Vectors
- Definitions
- At line 65 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 61 in file Start\startup_stm32f40_41xxx.s
- At line 168 in file Start\startup_stm32f40_41xxx.s
-
-__Vectors_End 00000188
-
-Symbol: __Vectors_End
- Definitions
- At line 166 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 62 in file Start\startup_stm32f40_41xxx.s
- At line 168 in file Start\startup_stm32f40_41xxx.s
-
-3 symbols
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-.text 00000000
-
-Symbol: .text
- Definitions
- At line 170 in file Start\startup_stm32f40_41xxx.s
- Uses
- None
-Comment: .text unused
-ADC_IRQHandler 0000001A
-
-Symbol: ADC_IRQHandler
- Definitions
- At line 331 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 101 in file Start\startup_stm32f40_41xxx.s
- At line 248 in file Start\startup_stm32f40_41xxx.s
-
-BusFault_Handler 0000000E
-
-Symbol: BusFault_Handler
- Definitions
- At line 201 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 70 in file Start\startup_stm32f40_41xxx.s
- At line 202 in file Start\startup_stm32f40_41xxx.s
-
-CAN1_RX0_IRQHandler 0000001A
-
-Symbol: CAN1_RX0_IRQHandler
- Definitions
- At line 333 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 103 in file Start\startup_stm32f40_41xxx.s
- At line 250 in file Start\startup_stm32f40_41xxx.s
-
-CAN1_RX1_IRQHandler 0000001A
-
-Symbol: CAN1_RX1_IRQHandler
- Definitions
- At line 334 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 104 in file Start\startup_stm32f40_41xxx.s
- At line 251 in file Start\startup_stm32f40_41xxx.s
-
-CAN1_SCE_IRQHandler 0000001A
-
-Symbol: CAN1_SCE_IRQHandler
- Definitions
- At line 335 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 105 in file Start\startup_stm32f40_41xxx.s
- At line 252 in file Start\startup_stm32f40_41xxx.s
-
-CAN1_TX_IRQHandler 0000001A
-
-Symbol: CAN1_TX_IRQHandler
- Definitions
- At line 332 in file Start\startup_stm32f40_41xxx.s
- Uses
-
-
-
-ARM Macro Assembler Page 2 Alphabetic symbol ordering
-Relocatable symbols
-
- At line 102 in file Start\startup_stm32f40_41xxx.s
- At line 249 in file Start\startup_stm32f40_41xxx.s
-
-CAN2_RX0_IRQHandler 0000001A
-
-Symbol: CAN2_RX0_IRQHandler
- Definitions
- At line 377 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 147 in file Start\startup_stm32f40_41xxx.s
- At line 294 in file Start\startup_stm32f40_41xxx.s
-
-CAN2_RX1_IRQHandler 0000001A
-
-Symbol: CAN2_RX1_IRQHandler
- Definitions
- At line 378 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 148 in file Start\startup_stm32f40_41xxx.s
- At line 295 in file Start\startup_stm32f40_41xxx.s
-
-CAN2_SCE_IRQHandler 0000001A
-
-Symbol: CAN2_SCE_IRQHandler
- Definitions
- At line 379 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 149 in file Start\startup_stm32f40_41xxx.s
- At line 296 in file Start\startup_stm32f40_41xxx.s
-
-CAN2_TX_IRQHandler 0000001A
-
-Symbol: CAN2_TX_IRQHandler
- Definitions
- At line 376 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 146 in file Start\startup_stm32f40_41xxx.s
- At line 293 in file Start\startup_stm32f40_41xxx.s
-
-CRYP_IRQHandler 0000001A
-
-Symbol: CRYP_IRQHandler
- Definitions
- At line 392 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 162 in file Start\startup_stm32f40_41xxx.s
- At line 309 in file Start\startup_stm32f40_41xxx.s
-
-DCMI_IRQHandler 0000001A
-
-Symbol: DCMI_IRQHandler
- Definitions
- At line 391 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 161 in file Start\startup_stm32f40_41xxx.s
- At line 308 in file Start\startup_stm32f40_41xxx.s
-
-DMA1_Stream0_IRQHandler 0000001A
-
-
-
-
-ARM Macro Assembler Page 3 Alphabetic symbol ordering
-Relocatable symbols
-
-Symbol: DMA1_Stream0_IRQHandler
- Definitions
- At line 324 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 94 in file Start\startup_stm32f40_41xxx.s
- At line 241 in file Start\startup_stm32f40_41xxx.s
-
-DMA1_Stream1_IRQHandler 0000001A
-
-Symbol: DMA1_Stream1_IRQHandler
- Definitions
- At line 325 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 95 in file Start\startup_stm32f40_41xxx.s
- At line 242 in file Start\startup_stm32f40_41xxx.s
-
-DMA1_Stream2_IRQHandler 0000001A
-
-Symbol: DMA1_Stream2_IRQHandler
- Definitions
- At line 326 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 96 in file Start\startup_stm32f40_41xxx.s
- At line 243 in file Start\startup_stm32f40_41xxx.s
-
-DMA1_Stream3_IRQHandler 0000001A
-
-Symbol: DMA1_Stream3_IRQHandler
- Definitions
- At line 327 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 97 in file Start\startup_stm32f40_41xxx.s
- At line 244 in file Start\startup_stm32f40_41xxx.s
-
-DMA1_Stream4_IRQHandler 0000001A
-
-Symbol: DMA1_Stream4_IRQHandler
- Definitions
- At line 328 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 98 in file Start\startup_stm32f40_41xxx.s
- At line 245 in file Start\startup_stm32f40_41xxx.s
-
-DMA1_Stream5_IRQHandler 0000001A
-
-Symbol: DMA1_Stream5_IRQHandler
- Definitions
- At line 329 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 99 in file Start\startup_stm32f40_41xxx.s
- At line 246 in file Start\startup_stm32f40_41xxx.s
-
-DMA1_Stream6_IRQHandler 0000001A
-
-Symbol: DMA1_Stream6_IRQHandler
- Definitions
- At line 330 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 100 in file Start\startup_stm32f40_41xxx.s
-
-
-
-ARM Macro Assembler Page 4 Alphabetic symbol ordering
-Relocatable symbols
-
- At line 247 in file Start\startup_stm32f40_41xxx.s
-
-DMA1_Stream7_IRQHandler 0000001A
-
-Symbol: DMA1_Stream7_IRQHandler
- Definitions
- At line 360 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 130 in file Start\startup_stm32f40_41xxx.s
- At line 277 in file Start\startup_stm32f40_41xxx.s
-
-DMA2_Stream0_IRQHandler 0000001A
-
-Symbol: DMA2_Stream0_IRQHandler
- Definitions
- At line 369 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 139 in file Start\startup_stm32f40_41xxx.s
- At line 286 in file Start\startup_stm32f40_41xxx.s
-
-DMA2_Stream1_IRQHandler 0000001A
-
-Symbol: DMA2_Stream1_IRQHandler
- Definitions
- At line 370 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 140 in file Start\startup_stm32f40_41xxx.s
- At line 287 in file Start\startup_stm32f40_41xxx.s
-
-DMA2_Stream2_IRQHandler 0000001A
-
-Symbol: DMA2_Stream2_IRQHandler
- Definitions
- At line 371 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 141 in file Start\startup_stm32f40_41xxx.s
- At line 288 in file Start\startup_stm32f40_41xxx.s
-
-DMA2_Stream3_IRQHandler 0000001A
-
-Symbol: DMA2_Stream3_IRQHandler
- Definitions
- At line 372 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 142 in file Start\startup_stm32f40_41xxx.s
- At line 289 in file Start\startup_stm32f40_41xxx.s
-
-DMA2_Stream4_IRQHandler 0000001A
-
-Symbol: DMA2_Stream4_IRQHandler
- Definitions
- At line 373 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 143 in file Start\startup_stm32f40_41xxx.s
- At line 290 in file Start\startup_stm32f40_41xxx.s
-
-DMA2_Stream5_IRQHandler 0000001A
-
-Symbol: DMA2_Stream5_IRQHandler
-
-
-
-ARM Macro Assembler Page 5 Alphabetic symbol ordering
-Relocatable symbols
-
- Definitions
- At line 381 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 151 in file Start\startup_stm32f40_41xxx.s
- At line 298 in file Start\startup_stm32f40_41xxx.s
-
-DMA2_Stream6_IRQHandler 0000001A
-
-Symbol: DMA2_Stream6_IRQHandler
- Definitions
- At line 382 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 152 in file Start\startup_stm32f40_41xxx.s
- At line 299 in file Start\startup_stm32f40_41xxx.s
-
-DMA2_Stream7_IRQHandler 0000001A
-
-Symbol: DMA2_Stream7_IRQHandler
- Definitions
- At line 383 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 153 in file Start\startup_stm32f40_41xxx.s
- At line 300 in file Start\startup_stm32f40_41xxx.s
-
-DebugMon_Handler 00000014
-
-Symbol: DebugMon_Handler
- Definitions
- At line 215 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 77 in file Start\startup_stm32f40_41xxx.s
- At line 216 in file Start\startup_stm32f40_41xxx.s
-
-Default_Handler 0000001A
-
-Symbol: Default_Handler
- Definitions
- At line 228 in file Start\startup_stm32f40_41xxx.s
- Uses
- None
-Comment: Default_Handler unused
-ETH_IRQHandler 0000001A
-
-Symbol: ETH_IRQHandler
- Definitions
- At line 374 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 144 in file Start\startup_stm32f40_41xxx.s
- At line 291 in file Start\startup_stm32f40_41xxx.s
-
-ETH_WKUP_IRQHandler 0000001A
-
-Symbol: ETH_WKUP_IRQHandler
- Definitions
- At line 375 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 145 in file Start\startup_stm32f40_41xxx.s
- At line 292 in file Start\startup_stm32f40_41xxx.s
-
-
-
-
-ARM Macro Assembler Page 6 Alphabetic symbol ordering
-Relocatable symbols
-
-EXTI0_IRQHandler 0000001A
-
-Symbol: EXTI0_IRQHandler
- Definitions
- At line 319 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 89 in file Start\startup_stm32f40_41xxx.s
- At line 236 in file Start\startup_stm32f40_41xxx.s
-
-EXTI15_10_IRQHandler 0000001A
-
-Symbol: EXTI15_10_IRQHandler
- Definitions
- At line 353 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 123 in file Start\startup_stm32f40_41xxx.s
- At line 270 in file Start\startup_stm32f40_41xxx.s
-
-EXTI1_IRQHandler 0000001A
-
-Symbol: EXTI1_IRQHandler
- Definitions
- At line 320 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 90 in file Start\startup_stm32f40_41xxx.s
- At line 237 in file Start\startup_stm32f40_41xxx.s
-
-EXTI2_IRQHandler 0000001A
-
-Symbol: EXTI2_IRQHandler
- Definitions
- At line 321 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 91 in file Start\startup_stm32f40_41xxx.s
- At line 238 in file Start\startup_stm32f40_41xxx.s
-
-EXTI3_IRQHandler 0000001A
-
-Symbol: EXTI3_IRQHandler
- Definitions
- At line 322 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 92 in file Start\startup_stm32f40_41xxx.s
- At line 239 in file Start\startup_stm32f40_41xxx.s
-
-EXTI4_IRQHandler 0000001A
-
-Symbol: EXTI4_IRQHandler
- Definitions
- At line 323 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 93 in file Start\startup_stm32f40_41xxx.s
- At line 240 in file Start\startup_stm32f40_41xxx.s
-
-EXTI9_5_IRQHandler 0000001A
-
-Symbol: EXTI9_5_IRQHandler
- Definitions
- At line 336 in file Start\startup_stm32f40_41xxx.s
-
-
-
-ARM Macro Assembler Page 7 Alphabetic symbol ordering
-Relocatable symbols
-
- Uses
- At line 106 in file Start\startup_stm32f40_41xxx.s
- At line 253 in file Start\startup_stm32f40_41xxx.s
-
-FLASH_IRQHandler 0000001A
-
-Symbol: FLASH_IRQHandler
- Definitions
- At line 317 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 87 in file Start\startup_stm32f40_41xxx.s
- At line 234 in file Start\startup_stm32f40_41xxx.s
-
-FPU_IRQHandler 0000001A
-
-Symbol: FPU_IRQHandler
- Definitions
- At line 394 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 164 in file Start\startup_stm32f40_41xxx.s
- At line 311 in file Start\startup_stm32f40_41xxx.s
-
-FSMC_IRQHandler 0000001A
-
-Symbol: FSMC_IRQHandler
- Definitions
- At line 361 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 131 in file Start\startup_stm32f40_41xxx.s
- At line 278 in file Start\startup_stm32f40_41xxx.s
-
-HASH_RNG_IRQHandler 0000001A
-
-Symbol: HASH_RNG_IRQHandler
- Definitions
- At line 393 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 163 in file Start\startup_stm32f40_41xxx.s
- At line 310 in file Start\startup_stm32f40_41xxx.s
-
-HardFault_Handler 0000000A
-
-Symbol: HardFault_Handler
- Definitions
- At line 191 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 68 in file Start\startup_stm32f40_41xxx.s
- At line 192 in file Start\startup_stm32f40_41xxx.s
-
-I2C1_ER_IRQHandler 0000001A
-
-Symbol: I2C1_ER_IRQHandler
- Definitions
- At line 345 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 115 in file Start\startup_stm32f40_41xxx.s
- At line 262 in file Start\startup_stm32f40_41xxx.s
-
-I2C1_EV_IRQHandler 0000001A
-
-
-
-ARM Macro Assembler Page 8 Alphabetic symbol ordering
-Relocatable symbols
-
-
-Symbol: I2C1_EV_IRQHandler
- Definitions
- At line 344 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 114 in file Start\startup_stm32f40_41xxx.s
- At line 261 in file Start\startup_stm32f40_41xxx.s
-
-I2C2_ER_IRQHandler 0000001A
-
-Symbol: I2C2_ER_IRQHandler
- Definitions
- At line 347 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 117 in file Start\startup_stm32f40_41xxx.s
- At line 264 in file Start\startup_stm32f40_41xxx.s
-
-I2C2_EV_IRQHandler 0000001A
-
-Symbol: I2C2_EV_IRQHandler
- Definitions
- At line 346 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 116 in file Start\startup_stm32f40_41xxx.s
- At line 263 in file Start\startup_stm32f40_41xxx.s
-
-I2C3_ER_IRQHandler 0000001A
-
-Symbol: I2C3_ER_IRQHandler
- Definitions
- At line 386 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 156 in file Start\startup_stm32f40_41xxx.s
- At line 303 in file Start\startup_stm32f40_41xxx.s
-
-I2C3_EV_IRQHandler 0000001A
-
-Symbol: I2C3_EV_IRQHandler
- Definitions
- At line 385 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 155 in file Start\startup_stm32f40_41xxx.s
- At line 302 in file Start\startup_stm32f40_41xxx.s
-
-MemManage_Handler 0000000C
-
-Symbol: MemManage_Handler
- Definitions
- At line 196 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 69 in file Start\startup_stm32f40_41xxx.s
- At line 197 in file Start\startup_stm32f40_41xxx.s
-
-NMI_Handler 00000008
-
-Symbol: NMI_Handler
- Definitions
- At line 186 in file Start\startup_stm32f40_41xxx.s
- Uses
-
-
-
-ARM Macro Assembler Page 9 Alphabetic symbol ordering
-Relocatable symbols
-
- At line 67 in file Start\startup_stm32f40_41xxx.s
- At line 187 in file Start\startup_stm32f40_41xxx.s
-
-OTG_FS_IRQHandler 0000001A
-
-Symbol: OTG_FS_IRQHandler
- Definitions
- At line 380 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 150 in file Start\startup_stm32f40_41xxx.s
- At line 297 in file Start\startup_stm32f40_41xxx.s
-
-OTG_FS_WKUP_IRQHandler 0000001A
-
-Symbol: OTG_FS_WKUP_IRQHandler
- Definitions
- At line 355 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 125 in file Start\startup_stm32f40_41xxx.s
- At line 272 in file Start\startup_stm32f40_41xxx.s
-
-OTG_HS_EP1_IN_IRQHandler 0000001A
-
-Symbol: OTG_HS_EP1_IN_IRQHandler
- Definitions
- At line 388 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 158 in file Start\startup_stm32f40_41xxx.s
- At line 305 in file Start\startup_stm32f40_41xxx.s
-
-OTG_HS_EP1_OUT_IRQHandler 0000001A
-
-Symbol: OTG_HS_EP1_OUT_IRQHandler
- Definitions
- At line 387 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 157 in file Start\startup_stm32f40_41xxx.s
- At line 304 in file Start\startup_stm32f40_41xxx.s
-
-OTG_HS_IRQHandler 0000001A
-
-Symbol: OTG_HS_IRQHandler
- Definitions
- At line 390 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 160 in file Start\startup_stm32f40_41xxx.s
- At line 307 in file Start\startup_stm32f40_41xxx.s
-
-OTG_HS_WKUP_IRQHandler 0000001A
-
-Symbol: OTG_HS_WKUP_IRQHandler
- Definitions
- At line 389 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 159 in file Start\startup_stm32f40_41xxx.s
- At line 306 in file Start\startup_stm32f40_41xxx.s
-
-PVD_IRQHandler 0000001A
-
-
-
-
-ARM Macro Assembler Page 10 Alphabetic symbol ordering
-Relocatable symbols
-
-Symbol: PVD_IRQHandler
- Definitions
- At line 314 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 84 in file Start\startup_stm32f40_41xxx.s
- At line 231 in file Start\startup_stm32f40_41xxx.s
-
-PendSV_Handler 00000016
-
-Symbol: PendSV_Handler
- Definitions
- At line 219 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 79 in file Start\startup_stm32f40_41xxx.s
- At line 220 in file Start\startup_stm32f40_41xxx.s
-
-RCC_IRQHandler 0000001A
-
-Symbol: RCC_IRQHandler
- Definitions
- At line 318 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 88 in file Start\startup_stm32f40_41xxx.s
- At line 235 in file Start\startup_stm32f40_41xxx.s
-
-RTC_Alarm_IRQHandler 0000001A
-
-Symbol: RTC_Alarm_IRQHandler
- Definitions
- At line 354 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 124 in file Start\startup_stm32f40_41xxx.s
- At line 271 in file Start\startup_stm32f40_41xxx.s
-
-RTC_WKUP_IRQHandler 0000001A
-
-Symbol: RTC_WKUP_IRQHandler
- Definitions
- At line 316 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 86 in file Start\startup_stm32f40_41xxx.s
- At line 233 in file Start\startup_stm32f40_41xxx.s
-
-Reset_Handler 00000000
-
-Symbol: Reset_Handler
- Definitions
- At line 173 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 66 in file Start\startup_stm32f40_41xxx.s
- At line 174 in file Start\startup_stm32f40_41xxx.s
-
-SDIO_IRQHandler 0000001A
-
-Symbol: SDIO_IRQHandler
- Definitions
- At line 362 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 132 in file Start\startup_stm32f40_41xxx.s
-
-
-
-ARM Macro Assembler Page 11 Alphabetic symbol ordering
-Relocatable symbols
-
- At line 279 in file Start\startup_stm32f40_41xxx.s
-
-SPI1_IRQHandler 0000001A
-
-Symbol: SPI1_IRQHandler
- Definitions
- At line 348 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 118 in file Start\startup_stm32f40_41xxx.s
- At line 265 in file Start\startup_stm32f40_41xxx.s
-
-SPI2_IRQHandler 0000001A
-
-Symbol: SPI2_IRQHandler
- Definitions
- At line 349 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 119 in file Start\startup_stm32f40_41xxx.s
- At line 266 in file Start\startup_stm32f40_41xxx.s
-
-SPI3_IRQHandler 0000001A
-
-Symbol: SPI3_IRQHandler
- Definitions
- At line 364 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 134 in file Start\startup_stm32f40_41xxx.s
- At line 281 in file Start\startup_stm32f40_41xxx.s
-
-SVC_Handler 00000012
-
-Symbol: SVC_Handler
- Definitions
- At line 210 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 76 in file Start\startup_stm32f40_41xxx.s
- At line 211 in file Start\startup_stm32f40_41xxx.s
-
-SysTick_Handler 00000018
-
-Symbol: SysTick_Handler
- Definitions
- At line 223 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 80 in file Start\startup_stm32f40_41xxx.s
- At line 224 in file Start\startup_stm32f40_41xxx.s
-
-TAMP_STAMP_IRQHandler 0000001A
-
-Symbol: TAMP_STAMP_IRQHandler
- Definitions
- At line 315 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 85 in file Start\startup_stm32f40_41xxx.s
- At line 232 in file Start\startup_stm32f40_41xxx.s
-
-TIM1_BRK_TIM9_IRQHandler 0000001A
-
-Symbol: TIM1_BRK_TIM9_IRQHandler
-
-
-
-ARM Macro Assembler Page 12 Alphabetic symbol ordering
-Relocatable symbols
-
- Definitions
- At line 337 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 107 in file Start\startup_stm32f40_41xxx.s
- At line 254 in file Start\startup_stm32f40_41xxx.s
-
-TIM1_CC_IRQHandler 0000001A
-
-Symbol: TIM1_CC_IRQHandler
- Definitions
- At line 340 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 110 in file Start\startup_stm32f40_41xxx.s
- At line 257 in file Start\startup_stm32f40_41xxx.s
-
-TIM1_TRG_COM_TIM11_IRQHandler 0000001A
-
-Symbol: TIM1_TRG_COM_TIM11_IRQHandler
- Definitions
- At line 339 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 109 in file Start\startup_stm32f40_41xxx.s
- At line 256 in file Start\startup_stm32f40_41xxx.s
-
-TIM1_UP_TIM10_IRQHandler 0000001A
-
-Symbol: TIM1_UP_TIM10_IRQHandler
- Definitions
- At line 338 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 108 in file Start\startup_stm32f40_41xxx.s
- At line 255 in file Start\startup_stm32f40_41xxx.s
-
-TIM2_IRQHandler 0000001A
-
-Symbol: TIM2_IRQHandler
- Definitions
- At line 341 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 111 in file Start\startup_stm32f40_41xxx.s
- At line 258 in file Start\startup_stm32f40_41xxx.s
-
-TIM3_IRQHandler 0000001A
-
-Symbol: TIM3_IRQHandler
- Definitions
- At line 342 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 112 in file Start\startup_stm32f40_41xxx.s
- At line 259 in file Start\startup_stm32f40_41xxx.s
-
-TIM4_IRQHandler 0000001A
-
-Symbol: TIM4_IRQHandler
- Definitions
- At line 343 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 113 in file Start\startup_stm32f40_41xxx.s
- At line 260 in file Start\startup_stm32f40_41xxx.s
-
-
-
-ARM Macro Assembler Page 13 Alphabetic symbol ordering
-Relocatable symbols
-
-
-TIM5_IRQHandler 0000001A
-
-Symbol: TIM5_IRQHandler
- Definitions
- At line 363 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 133 in file Start\startup_stm32f40_41xxx.s
- At line 280 in file Start\startup_stm32f40_41xxx.s
-
-TIM6_DAC_IRQHandler 0000001A
-
-Symbol: TIM6_DAC_IRQHandler
- Definitions
- At line 367 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 137 in file Start\startup_stm32f40_41xxx.s
- At line 284 in file Start\startup_stm32f40_41xxx.s
-
-TIM7_IRQHandler 0000001A
-
-Symbol: TIM7_IRQHandler
- Definitions
- At line 368 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 138 in file Start\startup_stm32f40_41xxx.s
- At line 285 in file Start\startup_stm32f40_41xxx.s
-
-TIM8_BRK_TIM12_IRQHandler 0000001A
-
-Symbol: TIM8_BRK_TIM12_IRQHandler
- Definitions
- At line 356 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 126 in file Start\startup_stm32f40_41xxx.s
- At line 273 in file Start\startup_stm32f40_41xxx.s
-
-TIM8_CC_IRQHandler 0000001A
-
-Symbol: TIM8_CC_IRQHandler
- Definitions
- At line 359 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 129 in file Start\startup_stm32f40_41xxx.s
- At line 276 in file Start\startup_stm32f40_41xxx.s
-
-TIM8_TRG_COM_TIM14_IRQHandler 0000001A
-
-Symbol: TIM8_TRG_COM_TIM14_IRQHandler
- Definitions
- At line 358 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 128 in file Start\startup_stm32f40_41xxx.s
- At line 275 in file Start\startup_stm32f40_41xxx.s
-
-TIM8_UP_TIM13_IRQHandler 0000001A
-
-Symbol: TIM8_UP_TIM13_IRQHandler
- Definitions
-
-
-
-ARM Macro Assembler Page 14 Alphabetic symbol ordering
-Relocatable symbols
-
- At line 357 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 127 in file Start\startup_stm32f40_41xxx.s
- At line 274 in file Start\startup_stm32f40_41xxx.s
-
-UART4_IRQHandler 0000001A
-
-Symbol: UART4_IRQHandler
- Definitions
- At line 365 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 135 in file Start\startup_stm32f40_41xxx.s
- At line 282 in file Start\startup_stm32f40_41xxx.s
-
-UART5_IRQHandler 0000001A
-
-Symbol: UART5_IRQHandler
- Definitions
- At line 366 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 136 in file Start\startup_stm32f40_41xxx.s
- At line 283 in file Start\startup_stm32f40_41xxx.s
-
-USART1_IRQHandler 0000001A
-
-Symbol: USART1_IRQHandler
- Definitions
- At line 350 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 120 in file Start\startup_stm32f40_41xxx.s
- At line 267 in file Start\startup_stm32f40_41xxx.s
-
-USART2_IRQHandler 0000001A
-
-Symbol: USART2_IRQHandler
- Definitions
- At line 351 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 121 in file Start\startup_stm32f40_41xxx.s
- At line 268 in file Start\startup_stm32f40_41xxx.s
-
-USART3_IRQHandler 0000001A
-
-Symbol: USART3_IRQHandler
- Definitions
- At line 352 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 122 in file Start\startup_stm32f40_41xxx.s
- At line 269 in file Start\startup_stm32f40_41xxx.s
-
-USART6_IRQHandler 0000001A
-
-Symbol: USART6_IRQHandler
- Definitions
- At line 384 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 154 in file Start\startup_stm32f40_41xxx.s
- At line 301 in file Start\startup_stm32f40_41xxx.s
-
-
-
-
-ARM Macro Assembler Page 15 Alphabetic symbol ordering
-Relocatable symbols
-
-UsageFault_Handler 00000010
-
-Symbol: UsageFault_Handler
- Definitions
- At line 206 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 71 in file Start\startup_stm32f40_41xxx.s
- At line 207 in file Start\startup_stm32f40_41xxx.s
-
-WWDG_IRQHandler 0000001A
-
-Symbol: WWDG_IRQHandler
- Definitions
- At line 313 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 83 in file Start\startup_stm32f40_41xxx.s
- At line 230 in file Start\startup_stm32f40_41xxx.s
-
-94 symbols
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-Absolute symbols
-
-Heap_Size 00000200
-
-Symbol: Heap_Size
- Definitions
- At line 48 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 52 in file Start\startup_stm32f40_41xxx.s
-Comment: Heap_Size used once
-Stack_Size 00000400
-
-Symbol: Stack_Size
- Definitions
- At line 37 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 40 in file Start\startup_stm32f40_41xxx.s
-Comment: Stack_Size used once
-__Vectors_Size 00000188
-
-Symbol: __Vectors_Size
- Definitions
- At line 168 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 63 in file Start\startup_stm32f40_41xxx.s
-Comment: __Vectors_Size used once
-3 symbols
-
-
-
-ARM Macro Assembler Page 1 Alphabetic symbol ordering
-External symbols
-
-SystemInit 00000000
-
-Symbol: SystemInit
- Definitions
- At line 175 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 178 in file Start\startup_stm32f40_41xxx.s
-Comment: SystemInit used once
-__main 00000000
-
-Symbol: __main
- Definitions
- At line 176 in file Start\startup_stm32f40_41xxx.s
- Uses
- At line 180 in file Start\startup_stm32f40_41xxx.s
-Comment: __main used once
-2 symbols
-445 symbols in table
diff --git a/底盘/底盘-old/底盘/Motor/GM6020.c b/底盘/底盘-old/底盘/Motor/GM6020.c
deleted file mode 100644
index ad02c90..0000000
--- a/底盘/底盘-old/底盘/Motor/GM6020.c
+++ /dev/null
@@ -1,194 +0,0 @@
-#include "stm32f4xx.h" // Device header
-#include "stm32f4xx_conf.h"
-#include "GM6020.h"
-
-#define GM6020_Control_ID_L 0x1FF//GM6020低位ID发送报文标识符(GM6020低位标识符和M3508高位标识符相同)
-#define GM6020_Control_ID_H 0x2FF//GM6020低位ID发送报文标识符
-
-
-
-
-GM6020_Motor GM6020_MotorStatus[7];//GM6020电机状态数组
-
-/*
- *函数简介:CAN1总线设置GM6020低位ID电压
- *参数说明:Voltage1~4分别对应ID1~4
- *返回类型:1-发送成功,0-发送失败
- *备注:只能配置ID1~4(标识符0x1FF)
- *备注:默认标准格式数据帧,4字节数据段
- *备注:注意GM6020的ID1~4报文标识符与M3508的ID5~8报文标识符相同
- *备注:给电机一定的电压,会促使电机产生速度
- */
-uint8_t GM6020_CAN1SetLIDVoltage(int16_t Voltage1,int16_t Voltage2,int16_t Voltage3,int16_t Voltage4)
-{
- CanTxMsg TxMessage;
- TxMessage.StdId=GM6020_Control_ID_L;//低位ID标准标识符0x1FF
- TxMessage.RTR=CAN_RTR_Data;//数据帧
- TxMessage.IDE=CAN_Id_Standard;//标准格式
- TxMessage.DLC=0x08;//4字节数据段
- TxMessage.Data[0]=Voltage1>>8;//ID1电压高八位
- TxMessage.Data[1]=Voltage1;//ID1电压低八位
- TxMessage.Data[2]=Voltage2>>8;//ID2电压高八位
- TxMessage.Data[3]=Voltage2;//ID2电压低八位
- TxMessage.Data[4]=Voltage3>>8;//ID3电压高八位
- TxMessage.Data[5]=Voltage3;//ID3电压低八位
- TxMessage.Data[6]=Voltage4>>8;//ID4电压高八位
- TxMessage.Data[7]=Voltage4;//ID4电压低八位
-
- uint8_t mbox=CAN_Transmit(CAN1,&TxMessage);//发送数据并获取邮箱号
- uint16_t i=0;
- while((CAN_TransmitStatus(CAN1,mbox)==CAN_TxStatus_Failed)&&(i<0XFFF))i++;//等待发送结束
- if(i>=0xFFF)return 0;//发送失败
- return 1;//发送成功
-}
-
-/*
- *函数简介:CAN1总线设置GM6020高位ID电压
- *参数说明:Voltage5~7分别对应ID5~7
- *返回类型:1-发送成功,0-发送失败
- *备注:只能配置ID5~7(标识符0x2FF)
- *备注:默认标准格式数据帧,4字节数据段
- *备注:给电机一定的电压,会促使电机产生速度
- */
-uint8_t GM6020_CAN1SetHIDVoltage(int16_t Voltage5,int16_t Voltage6,int16_t Voltage7)
-{
- CanTxMsg TxMessage;
- TxMessage.StdId=GM6020_Control_ID_H;//高位ID标准标识符0x2FF
- TxMessage.RTR=CAN_RTR_Data;//数据帧
- TxMessage.IDE=CAN_Id_Standard;//标准格式
- TxMessage.DLC=0x08;//4字节数据段
- TxMessage.Data[0]=Voltage5>>8;//ID5电压高八位
- TxMessage.Data[1]=Voltage5;//ID5电压低八位
- TxMessage.Data[2]=Voltage6>>8;//ID6电压高八位
- TxMessage.Data[3]=Voltage6;//ID6电压低八位
- TxMessage.Data[4]=Voltage7>>8;//ID7电压高八位
- TxMessage.Data[5]=Voltage7;//ID7电压低八位
- TxMessage.Data[6]=0;//空位,默认给0
- TxMessage.Data[7]=0;//空位,默认给0
-
- uint8_t mbox=CAN_Transmit(CAN1,&TxMessage);//发送数据并获取邮箱号
- uint16_t i=0;
- while((CAN_TransmitStatus(CAN1,mbox)==CAN_TxStatus_Failed)&&(i<0XFFF))i++;//等待发送结束
- if(i>=0xFFF)return 0;//发送失败
- return 1;//发送成功
-}
-
-/*
- *函数简介:CAN2总线设置GM6020低位ID电压
- *参数说明:Voltage1~4分别对应ID1~4
- *返回类型:1-发送成功,0-发送失败
- *备注:只能配置ID1~4(标识符0x1FF)
- *备注:默认标准格式数据帧,4字节数据段
- *备注:注意GM6020的ID1~4报文标识符与M3508的ID5~8报文标识符相同
- *备注:给电机一定的电压,会促使电机产生速度
- */
-uint8_t GM6020_CAN2SetLIDVoltage(int16_t Voltage1,int16_t Voltage2,int16_t Voltage3,int16_t Voltage4)
-{
- CanTxMsg TxMessage;
- TxMessage.StdId=GM6020_Control_ID_L;//低位ID标准标识符0x1FF
- TxMessage.RTR=CAN_RTR_Data;//数据帧
- TxMessage.IDE=CAN_Id_Standard;//标准格式
- TxMessage.DLC=0x08;//4字节数据段
- TxMessage.Data[0]=Voltage1>>8;//ID1电压高八位
- TxMessage.Data[1]=Voltage1;//ID1电压低八位
- TxMessage.Data[2]=Voltage2>>8;//ID2电压高八位
- TxMessage.Data[3]=Voltage2;//ID2电压低八位
- TxMessage.Data[4]=Voltage3>>8;//ID3电压高八位
- TxMessage.Data[5]=Voltage3;//ID3电压低八位
- TxMessage.Data[6]=Voltage4>>8;//ID4电压高八位
- TxMessage.Data[7]=Voltage4;//ID4电压低八位
-
- uint8_t mbox=CAN_Transmit(CAN2,&TxMessage);//发送数据并获取邮箱号
- uint16_t i=0;
- while((CAN_TransmitStatus(CAN2,mbox)==CAN_TxStatus_Failed)&&(i<0XFFF))i++;//等待发送结束
- if(i>=0xFFF)return 0;//发送失败
- return 1;//发送成功
-}
-
-/*
- *函数简介:CAN2总线设置GM6020高位ID电压
- *参数说明:Voltage5~7分别对应ID5~7
- *返回类型:1-发送成功,0-发送失败
- *备注:只能配置ID5~7(标识符0x2FF)
- *备注:默认标准格式数据帧,4字节数据段
- *备注:给电机一定的电压,会促使电机产生速度
- */
-uint8_t GM6020_CAN2SetHIDVoltage(int16_t Voltage5,int16_t Voltage6,int16_t Voltage7)
-{
- CanTxMsg TxMessage;
- TxMessage.StdId=GM6020_Control_ID_H;//高位ID标准标识符0x2FF
- TxMessage.RTR=CAN_RTR_Data;//数据帧
- TxMessage.IDE=CAN_Id_Standard;//标准格式
- TxMessage.DLC=0x08;//4字节数据段
- TxMessage.Data[0]=Voltage5>>8;//ID5电压高八位
- TxMessage.Data[1]=Voltage5;//ID5电压低八位
- TxMessage.Data[2]=Voltage6>>8;//ID6电压高八位
- TxMessage.Data[3]=Voltage6;//ID6电压低八位
- TxMessage.Data[4]=Voltage7>>8;//ID7电压高八位
- TxMessage.Data[5]=Voltage7;//ID7电压低八位
- TxMessage.Data[6]=0;//空位,默认给0
- TxMessage.Data[7]=0;//空位,默认给0
-
- uint8_t mbox=CAN_Transmit(CAN2,&TxMessage);//发送数据并获取邮箱号
- uint16_t i=0;
- while((CAN_TransmitStatus(CAN2,mbox)==CAN_TxStatus_Failed)&&(i<0XFFF))i++;//等待发送结束
- if(i>=0xFFF)return 0;//发送失败
- return 1;//发送成功
-}
-
-/*
- *函数简介:对yaw进行处理，使得底盘yaw与实际yaw一致
- *参数说明:
- *返回类型:
- *备注:
-
-uint8_t GM6020_yawtra(GM6020_ID ID,uint8_t *Data)
-{
-
-}
-*/
-
-/*
- *函数简介:GM6020数据处理
- *参数说明:GM6020电机ID号枚举,GM6020_1~7对应ID号0x205~0x20B
- *参数说明:反馈数据(8字节)
- *返回类型:无
- *备注:保存到GM6020_MotorStatus结构体数组
- */
-void GM6020_CANDataProcess(GM6020_ID ID,uint8_t *Data)
-{
- float Gear_ratio = 0.56666666666666666666666666666667f;//齿轮比17/30
- int Fir = 0;
- uint16_t GM6020_NowAngle=(uint16_t)((((uint16_t)Data[0])<<8)|Data[1]);//本次机械角度原始数据
- if(GM6020_NowAngle-GM6020_MotorStatus[ID-0x205].Angle>4000 && GM6020_MotorStatus[ID-0x205].First_Flag==1 && GM6020_MotorStatus[ID-0x205].r>0)
- GM6020_MotorStatus[ID-0x205].r--;//本次机械角度原始数据和上次机械角度原始数据出现跃变
- else if(GM6020_MotorStatus[ID-0x205].Angle-GM6020_NowAngle>4000 && GM6020_MotorStatus[ID-0x205].First_Flag==1 && GM6020_MotorStatus[ID-0x205].r<1)
- GM6020_MotorStatus[ID-0x205].r++;
- else if(GM6020_MotorStatus[ID-0x205].First_Flag!=1)GM6020_MotorStatus[ID-0x205].First_Flag++;
-
- GM6020_MotorStatus[ID-0x205].Angle=GM6020_NowAngle;//机械角度
- GM6020_MotorStatus[ID-0x205].Position=(8192*GM6020_MotorStatus[ID-0x205].r+GM6020_NowAngle)*Gear_ratio;//角度位置
- GM6020_MotorStatus[ID-0x205].Speed=(int16_t)((((uint16_t)Data[2])<<8)|Data[3]);//转速
- GM6020_MotorStatus[ID-0x205].Current=(int16_t)((((uint16_t)Data[4])<<8)|Data[5]);//实际转矩电流
- GM6020_MotorStatus[ID-0x205].Temperature=Data[6];//电机温度
-
- if(Fir==0)
- {
- GM6020_MotorStatus[ID-0x205].Gimbal_direction=GM6020_NowAngle;
- Fir=1;
- }
-
- if(GM6020_MotorStatus[ID-0x205].r==0)
- GM6020_MotorStatus[ID-0x205].Chassis_positive_direction = GM6020_MotorStatus[ID-0x205].Angle*Gear_ratio;
- else if(GM6020_MotorStatus[ID-0x205].r>0)
- GM6020_MotorStatus[ID-0x205].Chassis_positive_direction = (GM6020_MotorStatus[ID-0x205].r*8192+GM6020_MotorStatus[ID-0x205].Angle)*Gear_ratio;
- else if(GM6020_MotorStatus[ID-0x205].r<0)
- GM6020_MotorStatus[ID-0x205].Chassis_positive_direction = (-GM6020_MotorStatus[ID-0x205].r*8192+(8192-GM6020_MotorStatus[ID-0x205].Angle))*Gear_ratio;
- if(GM6020_MotorStatus[ID-0x205].Chassis_positive_direction>=360.0f)
- GM6020_MotorStatus[ID-0x205].Chassis_positive_direction-=360.0f;
- else if(GM6020_MotorStatus[ID-0x205].Chassis_positive_direction<=-360.0f)
- GM6020_MotorStatus[ID-0x205].Chassis_positive_direction+=360.0f;//对yaw进行处理，使得底盘yaw与实际yaw一致
-
-
-}
-
diff --git a/底盘/底盘-old/底盘/Motor/GM6020.h b/底盘/底盘-old/底盘/Motor/GM6020.h
deleted file mode 100644
index 6cf38e6..0000000
--- a/底盘/底盘-old/底盘/Motor/GM6020.h
+++ /dev/null
@@ -1,38 +0,0 @@
-#ifndef __GM6020_H
-#define __GM6020_H
-
-//float Gear_ratio = 0.56666666666666666666666666666667f;//齿轮比17/30
-
-typedef enum
-{
- GM6020_1=0x205,//ID1
- GM6020_2=0x206,//ID2
- GM6020_3=0x207,//ID3
- GM6020_4=0x208,//ID4
- GM6020_5=0x209,//ID5
- GM6020_6=0x20A,//ID6
- GM6020_7=0x20B,//ID7
-}GM6020_ID;//GM6020电机ID号枚举
-
-typedef struct
-{
- uint16_t Angle;//GM6020电机机械角度
- uint8_t First_Flag;//GM6020电机首次接收标志位
- int64_t r;//GM6020电机转过圈数(默认圈数只会出现0,1)
- int64_t Position;//GM6020电机角度位置原始数据
- int16_t Speed;//GM6020电机转速
- int16_t Current;//GM6020电机实际转矩电流
- uint8_t Temperature;//GM6020电机电机温度
- uint8_t Chassis_positive_direction;//底盘正方向
- uint8_t Gimbal_direction;//云台初始方向
-}GM6020_Motor;//GM6020电机状态结构体
-
-extern GM6020_Motor GM6020_MotorStatus[];//GM6020电机状态数组
-
-uint8_t GM6020_CAN1SetLIDVoltage(int16_t Voltage1,int16_t Voltage2,int16_t Voltage3,int16_t Voltage4);//CAN1总线设置GM6020低位ID电压
-uint8_t GM6020_CAN1SetHIDVoltage(int16_t Voltage5,int16_t Voltage6,int16_t Voltage7);//CAN1总线设置GM6020高位ID电压
-uint8_t GM6020_CAN2SetLIDVoltage(int16_t Voltage1,int16_t Voltage2,int16_t Voltage3,int16_t Voltage4);//CAN2总线设置GM6020低位ID电压
-uint8_t GM6020_CAN2SetHIDVoltage(int16_t Voltage5,int16_t Voltage6,int16_t Voltage7);//CAN2总线设置GM6020高位ID电压
-void GM6020_CANDataProcess(GM6020_ID ID,uint8_t *Data);//GM6020数据处理
-
-#endif
diff --git a/底盘/底盘-old/底盘/Motor/M3508.c b/底盘/底盘-old/底盘/Motor/M3508.c
deleted file mode 100644
index 220c240..0000000
--- a/底盘/底盘-old/底盘/Motor/M3508.c
+++ /dev/null
@@ -1,231 +0,0 @@
-#include "stm32f4xx.h" // Device header
-#include "stm32f4xx_conf.h"
-#include "M3508.h"
-#include "Delay.h"
-
-#define M3508_Speed 8000 //PWM最高转速
-
-#define M3508_PWMMode 0 //PWM模式(0-单向,1-双向)
-#define M3508_PWM0Checksum 500 //单向模式电调校验值,对应1000us
-#define M3508_PWM1Checksum 727 //双向模式电调校验值,对应1500us
-#define M3508_PWMTime 100 //校验完成等待时间
-
-//M3508和M2006标识符完全相同
-#define M3508_Control_ID_L 0x200//M3508低位ID发送报文标识符
-#define M3508_Control_ID_H 0x1FF//M3508高位ID发送报文标识符(M3508高位标识符和GM6020低位标识符相同)
-
-#define M3508_ReductionRatio (3591.0f/187.0f)//M3508减速比3591:187(≈19:1)
-#define M3508_TorqueConstant 0.3f//M3508转矩常数0.3N·m/A
-
-int16_t M3508_PWMNowDuty=0;//PWM当前占空比
-M3508_Motor M3508_MotorStatus[8];//M3508电机状态数组
-
-/*
- *函数简介:PWM控制M3508电机初始化
- *参数说明:无
- *返回类型:无
- *备注:默认使用PWM1(C1为PE9),默认500Hz
- *备注:需要校准"电调校验值"和"校验完成等待时间"
- */
-void M3508_PWMInit(void)
-{
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1,ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOE,ENABLE);//开启时钟
-
- TIM_InternalClockConfig(TIM1);//选择时基单元TIM1
-
- GPIO_InitTypeDef GPIO_InitStructure;
- GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//复用推挽
- GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
- GPIO_InitStructure.GPIO_Pin=GPIO_Pin_9;
- GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
- GPIO_Init(GPIOE,&GPIO_InitStructure);//配置C1-PE9
-
- GPIO_PinAFConfig(GPIOE,GPIO_PinSource9,GPIO_AF_TIM1);//开启C1的TIM1复用模式
-
- TIM_TimeBaseInitTypeDef TIM_InitStructure;
- TIM_InitStructure.TIM_ClockDivision=TIM_CKD_DIV1;//配置时钟分频为1分频
- TIM_InitStructure.TIM_CounterMode=TIM_CounterMode_Up;//配置计数器模式为向上计数
- TIM_InitStructure.TIM_Period=1000-1;//ARR,PWM为千分位2ms
- TIM_InitStructure.TIM_Prescaler=336-1;//PSC
- TIM_InitStructure.TIM_RepetitionCounter=0;//配置重复计数单元的置为0
- TIM_TimeBaseInit(TIM1,&TIM_InitStructure);
-
- TIM_OCInitTypeDef TIM_OCInitStructure;
- TIM_OCStructInit(&TIM_OCInitStructure);
- TIM_OCInitStructure.TIM_OCMode=TIM_OCMode_PWM1;//配置输出比较模式
- TIM_OCInitStructure.TIM_OCPolarity=TIM_OCPolarity_High;//配置输出比较的极性
- TIM_OCInitStructure.TIM_OutputState=TIM_OutputState_Enable;//输出使能
- TIM_OCInitStructure.TIM_Pulse=0;//配置输出比较寄存器CCR的值
- TIM_OC1Init(TIM1,&TIM_OCInitStructure);//配置C1输出PWM
-
- TIM_Cmd(TIM1,ENABLE);//启动定时器
- TIM_CtrlPWMOutputs(TIM1,ENABLE);//开启TIM1的PWM输出
-
- if(M3508_PWMMode==0)
- {
- TIM_SetCompare1(TIM1,M3508_PWM0Checksum);//电调校准
- Delay_ms(M3508_PWMTime);//等待校准完成
- M3508_PWMNowDuty=M3508_PWM0Checksum+40;//校验当前占空比
- }
- else
- {
- TIM_SetCompare1(TIM1,M3508_PWM1Checksum);//电调校准
- Delay_ms(M3508_PWMTime);//等待校准完成
- M3508_PWMNowDuty=M3508_PWM1Checksum;//校验当前占空比
- }
-}
-
-/*
- *函数简介:PWM设置M3508转速
- *参数说明:速度,单向模式0~vm,双向模式-vm~+vm
- *参数说明:标志位,决定是否使用缓启动
- *返回类型:无
- *备注:无
- */
-void M3508_PWMSetSpeed(int16_t Speed,uint8_t Flag)
-{
- uint16_t Duty=0;
- if(M3508_PWMMode==0)//单向模式(0-2000,1080->v=0,1920->v=vm)
- {
- Duty=M3508_PWM0Checksum+40+Speed*840/M3508_Speed/2;
- if(Flag==0)//硬启动
- TIM_SetCompare1(TIM1,Duty);
- else//从当前速度缓启动到目标速度,10分位
- for(uint8_t i=0;i<=10;i++)
- {
- TIM_SetCompare1(TIM1,(int)(M3508_PWMNowDuty+(Duty-M3508_PWMNowDuty)*i/10));
- Delay_ms(20);
- }
- M3508_PWMNowDuty=Duty;//获取当前占空比
- }
- else//双向模式
- {
- if(Speed<0)//反转(0-1500,1080->v=-vm,1480->v=0)
- {
- Duty=M3508_PWM1Checksum-10+Speed*400/M3508_Speed/2;
- if(Flag==0)//硬启动
- TIM_SetCompare1(TIM1,Duty);
- else//缓启动,10分位
- for(uint8_t i=0;i<=10;i++)
- {
- TIM_SetCompare1(TIM1,(int)(M3508_PWMNowDuty+(Duty-M3508_PWMNowDuty)*i/10));
- Delay_ms(20);
- }
- }
- else//正转(1500-2000,1520->v=0,1920->v=vm)
- {
- Duty=M3508_PWM1Checksum+10+Speed*400/M3508_Speed/2;
- if(Flag==0)//硬启动
- TIM_SetCompare1(TIM1,Duty);
- else//从当前速度缓启动到目标速度,10分位
- for(uint8_t i=0;i<=10;i++)
- {
- TIM_SetCompare1(TIM1,(int)(M3508_PWMNowDuty+(Duty-M3508_PWMNowDuty)*i/10));
- Delay_ms(20);
- }
- }
- M3508_PWMNowDuty=Duty;//获取当前占空比
- }
-}
-
-/*
- *函数简介:CAN总线设置M3508低位ID电流
- *参数说明:Currrent1~4分别对应ID1~4
- *返回类型:1-发送成功,0-发送失败
- *备注:只能配置ID1~4(标识符0x200)
- *备注:默认标准格式数据帧,8字节数据段
- *备注:注意M3508的报文标识符与M2006的报文标识符完全相同
- *备注:给电机一定的电流,会促使电机产生加速度
- */
-uint8_t M3508_CANSetLIDCurrent(int16_t Current1,int16_t Current2,int16_t Current3,int16_t Current4)
-{
- CanTxMsg TxMessage;
- TxMessage.StdId=M3508_Control_ID_L;//低位ID标准标识符0x200
- TxMessage.RTR=CAN_RTR_Data;//数据帧
- TxMessage.IDE=CAN_Id_Standard;//标准格式
- TxMessage.DLC=0x08;//8字节数据段
- TxMessage.Data[0]=Current1>>8;//ID1电流高八位
- TxMessage.Data[1]=Current1;//ID1电流低八位
- TxMessage.Data[2]=Current2>>8;//ID2电流高八位
- TxMessage.Data[3]=Current2;//ID2电流低八位
- TxMessage.Data[4]=Current3>>8;//ID3电流高八位
- TxMessage.Data[5]=Current3;//ID3电流低八位
- TxMessage.Data[6]=Current4>>8;//ID4电流高八位
- TxMessage.Data[7]=Current4;//ID4电流低八位
-
- uint8_t mbox=CAN_Transmit(CAN1,&TxMessage);//发送数据并获取邮箱号
- uint16_t i=0;
- while((CAN_TransmitStatus(CAN1,mbox)==CAN_TxStatus_Failed)&&(i<0XFFF))i++;//等待发送结束
- if(i>=0xFFF)return 0;//发送失败
- return 1;//发送成功
-}
-
-/*
- *函数简介:CAN总线设置M3508高位ID电流
- *参数说明:Currrent5~8分别对应ID5~8
- *返回类型:1-发送成功,0-发送失败
- *备注:只能配置ID5~8(标识符0x1FF)
- *备注:默认标准格式数据帧,8字节数据段
- *备注:注意M3508的报文标识符与M2006的报文标识符完全相同
- *备注:注意M3508的ID5~8报文标识符与GM6020的ID1~4报文标识符相同
- *备注:给电机一定的电流,会促使电机产生加速度
- */
-uint8_t M3508_CANSetHIDCurrent(int16_t Current5,int16_t Current6,int16_t Current7,int16_t Current8)
-{
- CanTxMsg TxMessage;
- TxMessage.StdId=M3508_Control_ID_H;//高位ID标准标识符0x1FF
- TxMessage.RTR=CAN_RTR_Data;//数据帧
- TxMessage.IDE=CAN_Id_Standard;//标准格式
- TxMessage.DLC=0x08;//8字节数据段
- TxMessage.Data[0]=Current5>>8;//ID5电流高八位
- TxMessage.Data[1]=Current5;//ID5电流低八位
- TxMessage.Data[2]=Current6>>8;//ID6电流高八位
- TxMessage.Data[3]=Current6;//ID6电流低八位
- TxMessage.Data[4]=Current7>>8;//ID7电流高八位
- TxMessage.Data[5]=Current7;//ID7电流低八位
- TxMessage.Data[6]=Current8>>8;//ID8电流高八位
- TxMessage.Data[7]=Current8;//ID8电流低八位
-
- uint8_t mbox=CAN_Transmit(CAN1,&TxMessage);//发送数据并获取邮箱号
- uint16_t i=0;
- while((CAN_TransmitStatus(CAN1,mbox)==CAN_TxStatus_Failed)&&(i<0XFFF))i++;//等待发送结束
- if(i>=0xFFF)return 0;//发送失败
- return 1;//发送成功
-}
-
-/*
- *函数简介:M3508数据处理
- *参数说明:M3508电机ID号枚举,M3508_1~8对应ID号0x201~0x208
- *参数说明:反馈数据(8字节)
- *返回类型:无
- *备注:保存到M3508_MotorStatus结构体数组
- *备注:M3508减速比3591:187(≈19:1),转矩常数0.3N·m/A
- */
-void M3508_CANDataProcess(M3508_ID ID,uint8_t *Data)
-{
- uint16_t M3508_RotorNowAngle=(uint16_t)((((uint16_t)Data[0])<<8)|Data[1]);//本次转子机械角度原始数据
- if(M3508_RotorNowAngle-M3508_MotorStatus[ID-0x201].RawRotorAngle>4000 && M3508_MotorStatus[ID-0x201].First_Flag==1)M3508_MotorStatus[ID-0x201].Rotor_r--;//本次转子机械角度原始数据和上次转子机械角度原始数据出现跃变
- else if(M3508_MotorStatus[ID-0x201].RawRotorAngle-M3508_RotorNowAngle>4000 && M3508_MotorStatus[ID-0x201].First_Flag==1)M3508_MotorStatus[ID-0x201].Rotor_r++;
- else if(M3508_MotorStatus[ID-0x201].First_Flag!=1)M3508_MotorStatus[ID-0x201].First_Flag=1;
-
- M3508_MotorStatus[ID-0x201].RawRotorAngle=M3508_RotorNowAngle;//转子机械角度原始数据
- M3508_MotorStatus[ID-0x201].RotorAngle=M3508_RotorNowAngle*0.0439453125f;//=M3508_RotorNowAngle/8192.0f*360.0f;//转子机械角度
- M3508_MotorStatus[ID-0x201].RawRotorPosition=8192*M3508_MotorStatus[ID-0x201].Rotor_r+M3508_RotorNowAngle;//转子角度位置原始数据
- M3508_MotorStatus[ID-0x201].RotorPosition=360.0f*M3508_MotorStatus[ID-0x201].Rotor_r+M3508_MotorStatus[ID-0x201].RotorAngle;//转子角度位置
- M3508_MotorStatus[ID-0x201].RotorSpeed=(int16_t)((((uint16_t)Data[2])<<8)|Data[3]);//转子转速原始数据
-
- M3508_MotorStatus[ID-0x201].ShaftPosition=M3508_MotorStatus[ID-0x201].RotorPosition*0.0520746310219994f;//=M3508_MotorStatus[ID-0x201].RotorPosition/M3508_ReductionRatio;//转轴角度位置
- M3508_MotorStatus[ID-0x201].Shaft_r=(int64_t)(M3508_MotorStatus[ID-0x201].ShaftPosition)/360;
- if(M3508_MotorStatus[ID-0x201].ShaftPosition<0 && M3508_MotorStatus[ID-0x201].ShaftPosition-360.0f*M3508_MotorStatus[ID-0x201].Shaft_r<0)M3508_MotorStatus[ID-0x201].Shaft_r--;//获取转轴圈数
- M3508_MotorStatus[ID-0x201].ShaftAngle=M3508_MotorStatus[ID-0x201].ShaftPosition-360.0f*M3508_MotorStatus[ID-0x201].Shaft_r;//转轴机械角度
- M3508_MotorStatus[ID-0x201].ShaftSpeed=M3508_MotorStatus[ID-0x201].RotorSpeed*0.0520746310219994f;//=M3508_MotorStatus[ID-0x201].RotorSpeed/M3508_ReductionRatio;//转轴转速
-
- M3508_MotorStatus[ID-0x201].RawCurrent=(int16_t)((((uint16_t)Data[4])<<8)|Data[5]);//转矩电流原始数据
- M3508_MotorStatus[ID-0x201].Current=M3508_MotorStatus[ID-0x201].RawCurrent*0.001220703125f;//=M3508_MotorStatus[ID-0x201].RawCurrent/16384.0f*20.0f;//转矩电流
-
- M3508_MotorStatus[ID-0x201].Power=M3508_MotorStatus[ID-0x201].ShaftSpeed*M3508_MotorStatus[ID-0x201].Current*0.031413612565445f;//=M3508_MotorStatus[ID-0x201].ShaftSpeed*M3508_MotorStatus[ID-0x201].Current*M3508_TorqueConstant/9.55f;//电机功率(功率P(kW)=转轴转速v(RPM)*转矩T(N·m)/9550,转矩T=转矩电流*转矩常数)
- if(M3508_MotorStatus[ID-0x201].Power<0)M3508_MotorStatus[ID-0x201].Power*=-1;//功率去负数化
- M3508_MotorStatus[ID-0x201].Temperature=Data[6];//电机温度
-}
diff --git a/底盘/底盘-old/底盘/Motor/M3508.h b/底盘/底盘-old/底盘/Motor/M3508.h
deleted file mode 100644
index 9fd0b1f..0000000
--- a/底盘/底盘-old/底盘/Motor/M3508.h
+++ /dev/null
@@ -1,46 +0,0 @@
-#ifndef __M3508_H
-#define __M3508_H
-
-typedef enum
-{
- M3508_1=0x201,//ID1
- M3508_2=0x202,//ID2
- M3508_3=0x203,//ID3
- M3508_4=0x204,//ID4
- M3508_5=0x205,//ID5
- M3508_6=0x206,//ID6
- M3508_7=0x207,//ID7
- M3508_8=0x208,//ID8
-}M3508_ID;//M3508电机ID号枚举
-
-typedef struct
-{
- uint8_t First_Flag;//M3508电机首次接收标志位
- int64_t Rotor_r;//M3508电机转子转过圈数
- uint16_t RawRotorAngle;//M3508电机转子机械角度原始数据(范围0~8191,对应0~360°,注意:8192对应360°)
- float RotorAngle;//M3508电机转子机械角度(单位°)
- int64_t RawRotorPosition;//M3508电机转子角度位置原始数据
- float RotorPosition;//M3508电机转子角度位置(单位°)
- int16_t RotorSpeed;//M3508电机转子转速(单位RPM)
-
- int64_t Shaft_r;//M3508电机转轴转过圈数
- float ShaftAngle;//M3508电机转轴机械角度(单位°)
- float ShaftPosition;//M3508电机转轴角度位置(单位°)
- float ShaftSpeed;//M3508电机转轴转速(单位RPM)
-
- int16_t RawCurrent;//M3508电机转矩电流原始数据(范围-16384~16384,对应-20A~20A,注意:16384对应20A)
- float Current;//M3508电机转矩电流(单位A)
-
- float Power;//M3508电机功率(单位W)
- uint8_t Temperature;//M3508电机电机温度(单位℃)
-}M3508_Motor;//M3508电机状态结构体(减速比3591:187(≈19:1),转矩系数0.3N·m/A)
-
-extern M3508_Motor M3508_MotorStatus[];//M3508电机状态数组
-
-void M3508_PWMInit(void);//PWM控制M3508电机初始化
-void M3508_PWMSetSpeed(int16_t Speed,uint8_t Flag);//PWM设置M3508转速
-uint8_t M3508_CANSetLIDCurrent(int16_t Current1,int16_t Current2,int16_t Current3,int16_t Current4);//CAN总线设置M3508低位ID电流
-uint8_t M3508_CANSetHIDCurrent(int16_t Current5,int16_t Current6,int16_t Current7,int16_t Current8);//CAN总线设置M3508高位ID电流
-void M3508_CANDataProcess(M3508_ID ID,uint8_t *Data);//M3508数据处理
-
-#endif
diff --git a/底盘/底盘-old/底盘/Objects/ExtDll.iex b/底盘/底盘-old/底盘/Objects/ExtDll.iex
deleted file mode 100644
index 6c0896e..0000000
--- a/底盘/底盘-old/底盘/Objects/ExtDll.iex
+++ /dev/null
@@ -1,2 +0,0 @@
-[EXTDLL]
-Count=0
diff --git a/底盘/底盘-old/底盘/Objects/Project.axf b/底盘/底盘-old/底盘/Objects/Project.axf
deleted file mode 100644
index 67c2f53..0000000
Binary files a/底盘/底盘-old/底盘/Objects/Project.axf and /dev/null differ
diff --git a/底盘/底盘-old/底盘/Objects/Project.build_log.htm b/底盘/底盘-old/底盘/Objects/Project.build_log.htm
deleted file mode 100644
index ee22d46..0000000
--- a/底盘/底盘-old/底盘/Objects/Project.build_log.htm
+++ /dev/null
@@ -1,133 +0,0 @@
-
-
-
-Vision Build Log
-Tool Versions:
-IDE-Version: Vision V5.38.0.0
-Copyright (C) 2022 ARM Ltd and ARM Germany GmbH. All rights reserved.
-License Information: peng ge, 1, LIC=IK1BF-6ED2S-X70RZ-J8MCT-Q76GB-XPREM
-
-Tool Versions:
-Toolchain: MDK-ARM Plus Version: 5.38.0.0
-Toolchain Path: C:\Keil_v5\ARM\ARMCOMPLIER506\Bin
-C Compiler: Armcc.exe V5.06 update 7 (build 960)
-Assembler: Armasm.exe V5.06 update 7 (build 960)
-Linker/Locator: ArmLink.exe V5.06 update 7 (build 960)
-Library Manager: ArmAr.exe V5.06 update 7 (build 960)
-Hex Converter: FromElf.exe V5.06 update 7 (build 960)
-CPU DLL: SARMCM3.DLL V5.38.0.0
-Dialog DLL: DCM.DLL V1.17.5.0
-Target DLL: CMSIS_AGDI.dll V1.33.15.0
-Dialog DLL: TCM.DLL V1.56.4.0
-
-Project:
-f:\Mas_Infantry_Control-main\Դ\V1.0\new-infantry\\\Project.uvprojx
-Project File Date: 01/24/2025
-
-Output:
-*** Using Compiler 'V5.06 update 7 (build 960)', folder: 'C:\Keil_v5\ARM\ARMCOMPLIER506\Bin'
-Rebuild target 'Target 1'
-assembling startup_stm32f40_41xxx.s...
-compiling misc.c...
-compiling stm32f4xx_crc.c...
-compiling stm32f4xx_dfsdm.c...
-compiling stm32f4xx_cryp_des.c...
-compiling stm32f4xx_dbgmcu.c...
-compiling stm32f4xx_cryp_tdes.c...
-compiling system_stm32f4xx.c...
-compiling stm32f4xx_dac.c...
-compiling stm32f4xx_cec.c...
-compiling stm32f4xx_cryp.c...
-compiling stm32f4xx_adc.c...
-compiling stm32f4xx_can.c...
-compiling stm32f4xx_dcmi.c...
-compiling stm32f4xx_dma.c...
-compiling stm32f4xx_cryp_aes.c...
-compiling stm32f4xx_dma2d.c...
-compiling stm32f4xx_dsi.c...
-compiling stm32f4xx_exti.c...
-compiling stm32f4xx_flash_ramfunc.c...
-compiling stm32f4xx_fmpi2c.c...
-compiling stm32f4xx_gpio.c...
-compiling stm32f4xx_flash.c...
-compiling stm32f4xx_hash.c...
-compiling stm32f4xx_hash_sha1.c...
-compiling stm32f4xx_iwdg.c...
-compiling stm32f4xx_lptim.c...
-compiling stm32f4xx_hash_md5.c...
-compiling stm32f4xx_fsmc.c...
-compiling stm32f4xx_i2c.c...
-compiling stm32f4xx_ltdc.c...
-compiling stm32f4xx_pwr.c...
-compiling stm32f4xx_qspi.c...
-compiling stm32f4xx_rng.c...
-compiling stm32f4xx_rcc.c...
-compiling stm32f4xx_sai.c...
-compiling stm32f4xx_sdio.c...
-compiling stm32f4xx_syscfg.c...
-compiling stm32f4xx_spdifrx.c...
-compiling stm32f4xx_wwdg.c...
-compiling stm32f4xx_rtc.c...
-compiling TIM.c...
-compiling stm32f4xx_spi.c...
-compiling Delay.c...
-compiling UART.c...
-compiling stm32f4xx_usart.c...
-compiling stm32f4xx_tim.c...
-compiling CAN.c...
-compiling LED.c...
-compiling Buzzer.c...
-compiling Remote.c...
-compiling M3508.c...
-compiling LinkCheck.c...
-compiling Warming.c...
-compiling CloseLoopControl.c...
-compiling GM6020.c...
-compiling RefereeSystem.c...
-CarBody\RefereeSystem.c(213): warning: #1-D: last line of file ends without a newline
- // */
-CarBody\RefereeSystem.c: 1 warning, 0 errors
-compiling CToC.c...
-.\CarBody\RefereeSystem.h(64): warning: #1295-D: Deprecated declaration HandPowercontrol - give arg types
- void HandPowercontrol();
-Function\CToC.c: 1 warning, 0 errors
-compiling RefereeSystem_CRCTable.c...
-compiling PID.c...
-compiling UI.c...
-CarBody\RefereeSystem.h(64): warning: #1295-D: Deprecated declaration HandPowercontrol - give arg types
- void HandPowercontrol();
-CarBody\UI.c: 1 warning, 0 errors
-compiling Ultra_CAP.c...
-compiling Mecanum.c...
-CarBody\RefereeSystem.h(64): warning: #1295-D: Deprecated declaration HandPowercontrol - give arg types
- void HandPowercontrol();
-CarBody\Mecanum.c: 1 warning, 0 errors
-compiling UI_Base.c...
-CarBody\RefereeSystem.h(64): warning: #1295-D: Deprecated declaration HandPowercontrol - give arg types
- void HandPowercontrol();
-CarBody\UI_Base.c: 1 warning, 0 errors
-compiling UI_Library.c...
-compiling main.c...
-.\CarBody\RefereeSystem.h(64): warning: #1295-D: Deprecated declaration HandPowercontrol - give arg types
- void HandPowercontrol();
-User\main.c: 1 warning, 0 errors
-compiling stm32f4xx_it.c...
-linking...
-Program Size: Code=18272 RO-data=1224 RW-data=396 ZI-data=2508
-".\Objects\Project.axf" - 0 Error(s), 6 Warning(s).
-
-Software Packages used:
-
-Package Vendor: Keil
- https://www.keil.com/pack/Keil.STM32F4xx_DFP.2.17.1.pack
- Keil.STM32F4xx_DFP.2.17.1
- STMicroelectronics STM32F4 Series Device Support, Drivers and Examples
-
-Collection of Component include folders:
- C:/Keil_v5/ARM/PACK/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include
-
-Collection of Component Files used:
-Build Time Elapsed: 00:00:07
-
-
-
diff --git a/底盘/底盘-old/底盘/Objects/Project.htm b/底盘/底盘-old/底盘/Objects/Project.htm
deleted file mode 100644
index e54779c..0000000
--- a/底盘/底盘-old/底盘/Objects/Project.htm
+++ /dev/null
@@ -1,1645 +0,0 @@
-
-
-Static Call Graph - [.\Objects\Project.axf]
-
-Static Call Graph for image .\Objects\Project.axf
-
#<CALLGRAPH># ARM Linker, 5060960: Last Updated: Fri Mar 28 09:20:47 2025
-
-
Maximum Stack Usage = 232 bytes + Unknown(Cycles, Untraceable Function Pointers)
-Call chain for Maximum Stack Depth:
-TIM6_DAC_IRQHandler ⇒ Mecanum_PowerMoveControl ⇒ Mecanum_ControlSpeed ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ _double_round
-
-
-Mutually Recursive functions
-
ADC_IRQHandler ⇒ ADC_IRQHandler
-
-
-
-Function Pointers
-
- - ADC_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- BusFault_Handler from stm32f4xx_it.o(i.BusFault_Handler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- CAN1_RX0_IRQHandler from can.o(i.CAN1_RX0_IRQHandler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- CAN1_RX1_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- CAN1_SCE_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- CAN1_TX_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- CAN2_RX0_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- CAN2_RX1_IRQHandler from can.o(i.CAN2_RX1_IRQHandler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- CAN2_SCE_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- CAN2_TX_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- CRYP_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DCMI_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA1_Stream0_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA1_Stream1_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA1_Stream2_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA1_Stream3_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA1_Stream4_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA1_Stream5_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA1_Stream6_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA1_Stream7_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA2_Stream0_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA2_Stream1_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA2_Stream2_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA2_Stream3_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA2_Stream4_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA2_Stream5_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA2_Stream6_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DMA2_Stream7_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- DebugMon_Handler from stm32f4xx_it.o(i.DebugMon_Handler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- ETH_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- ETH_WKUP_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- EXTI0_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- EXTI15_10_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- EXTI1_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- EXTI2_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- EXTI3_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- EXTI4_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- EXTI9_5_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- FLASH_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- FPU_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- FSMC_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- HASH_RNG_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- HardFault_Handler from stm32f4xx_it.o(i.HardFault_Handler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- I2C1_ER_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- I2C1_EV_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- I2C2_ER_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- I2C2_EV_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- I2C3_ER_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- I2C3_EV_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- MemManage_Handler from stm32f4xx_it.o(i.MemManage_Handler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- NMI_Handler from stm32f4xx_it.o(i.NMI_Handler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- OTG_FS_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- OTG_FS_WKUP_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- OTG_HS_EP1_IN_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- OTG_HS_EP1_OUT_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- OTG_HS_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- OTG_HS_WKUP_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- PVD_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- PendSV_Handler from stm32f4xx_it.o(i.PendSV_Handler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- RCC_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- RTC_Alarm_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- RTC_WKUP_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- Reset_Handler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- SDIO_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- SPI1_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- SPI2_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- SPI3_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- SVC_Handler from stm32f4xx_it.o(i.SVC_Handler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- SysTick_Handler from stm32f4xx_it.o(i.SysTick_Handler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- SystemInit from system_stm32f4xx.o(i.SystemInit) referenced from startup_stm32f40_41xxx.o(.text)
-
- TAMP_STAMP_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM1_BRK_TIM9_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM1_CC_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM1_TRG_COM_TIM11_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM1_UP_TIM10_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM2_IRQHandler from tim.o(i.TIM2_IRQHandler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM3_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM4_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM5_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM6_DAC_IRQHandler from closeloopcontrol.o(i.TIM6_DAC_IRQHandler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM7_IRQHandler from remote.o(i.TIM7_IRQHandler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM8_BRK_TIM12_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM8_CC_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM8_TRG_COM_TIM14_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- TIM8_UP_TIM13_IRQHandler from linkcheck.o(i.TIM8_UP_TIM13_IRQHandler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- UART4_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- UART5_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- USART1_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- USART2_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- USART3_IRQHandler from remote.o(i.USART3_IRQHandler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- USART6_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- UsageFault_Handler from stm32f4xx_it.o(i.UsageFault_Handler) referenced from startup_stm32f40_41xxx.o(RESET)
-
- WWDG_IRQHandler from startup_stm32f40_41xxx.o(.text) referenced from startup_stm32f40_41xxx.o(RESET)
-
- __main from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f40_41xxx.o(.text)
-
- main from main.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
-
-
-
-Global Symbols
-
-__main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(.text)
-
-_main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))
-
-
_main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
-
[Calls]
-
-__main_after_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
-
[Called By]
-
-_main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))
-
-
_main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))
-
-
_main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))
-
-
__rt_lib_shutdown_fini (Thumb, 0 bytes, Stack size unknown bytes, entry12b.o(.ARM.Collect$$$$0000000E))
-
-
__rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000F))
-
-
__rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$00000011))
-
-
Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-ADC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-CAN2_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-CAN2_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-CAN2_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-CRYP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DCMI_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA1_Stream0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA1_Stream1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA1_Stream2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA1_Stream3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA1_Stream4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA1_Stream5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA1_Stream6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA1_Stream7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA2_Stream0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA2_Stream1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA2_Stream2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA2_Stream3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA2_Stream4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA2_Stream5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA2_Stream6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-DMA2_Stream7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-ETH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-ETH_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-FPU_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-FSMC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-HASH_RNG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-I2C3_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-I2C3_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-OTG_FS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-OTG_FS_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-OTG_HS_EP1_IN_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-OTG_HS_EP1_OUT_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-OTG_HS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-OTG_HS_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-RTC_Alarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-RTC_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-SDIO_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-SPI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-TAMP_STAMP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-TIM1_BRK_TIM9_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-TIM1_TRG_COM_TIM11_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-TIM1_UP_TIM10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-TIM5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-TIM8_BRK_TIM12_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-TIM8_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-TIM8_TRG_COM_TIM14_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-UART4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-UART5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-USART1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-USART6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f40_41xxx.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-__aeabi_ldivmod (Thumb, 98 bytes, Stack size 24 bytes, ldiv.o(.text))
-
[Stack]
- Max Depth = 64
- Call Chain = __aeabi_ldivmod ⇒ __aeabi_uldivmod
-
-
[Calls]
-
[Called By]- >> M3508_CANDataProcess
-
-
-strlen (Thumb, 14 bytes, Stack size 0 bytes, strlen.o(.text))
-
[Called By]
- >> ui_proc_string_frame
-
-
-strcpy (Thumb, 18 bytes, Stack size 0 bytes, strcpy.o(.text))
-
[Called By]
- >> _ui_init_default_Ungroup_1
-
- >> _ui_init_default_Ungroup_0
-
-
-__aeabi_dadd (Thumb, 322 bytes, Stack size 48 bytes, dadd.o(.text))
-
[Stack]
- Max Depth = 88
- Call Chain = __aeabi_dadd ⇒ _double_epilogue ⇒ _double_round
-
-
[Calls]- >> __aeabi_lasr
-
- >> __aeabi_llsl
-
- >> _double_round
-
- >> _double_epilogue
-
-
[Called By]- >> Mecanum_ControlSpeed
-
- >> __aeabi_drsub
-
- >> __aeabi_dsub
-
-
-__aeabi_dsub (Thumb, 6 bytes, Stack size 0 bytes, dadd.o(.text), UNUSED)
-
[Calls]
-
-__aeabi_drsub (Thumb, 6 bytes, Stack size 0 bytes, dadd.o(.text), UNUSED)
-
[Calls]
-
-__aeabi_l2f (Thumb, 44 bytes, Stack size 16 bytes, ffltl.o(.text))
-
[Stack]
- Max Depth = 20
- Call Chain = __aeabi_l2f ⇒ _float_epilogue
-
-
[Calls]
-
[Called By]- >> Mecanum_PowerMoveControl
-
- >> M3508_CANDataProcess
-
- >> GM6020_CANDataProcess
-
-
-__aeabi_f2lz (Thumb, 66 bytes, Stack size 8 bytes, ffixl.o(.text))
-
[Stack]
- Max Depth = 8
- Call Chain = __aeabi_f2lz
-
-
[Calls]
-
[Called By]- >> M3508_CANDataProcess
-
- >> GM6020_CANDataProcess
-
-
-__aeabi_f2d (Thumb, 38 bytes, Stack size 0 bytes, f2d.o(.text))
-
[Called By]
- >> Mecanum_ControlSpeed
-
-
-__aeabi_d2f (Thumb, 56 bytes, Stack size 8 bytes, d2f.o(.text))
-
[Stack]
- Max Depth = 8
- Call Chain = __aeabi_d2f
-
-
[Calls]
-
[Called By]- >> Mecanum_ControlSpeed
-
-
-__aeabi_uldivmod (Thumb, 98 bytes, Stack size 40 bytes, uldiv.o(.text))
-
[Stack]
- Max Depth = 40
- Call Chain = __aeabi_uldivmod
-
-
[Calls]- >> __aeabi_llsr
-
- >> __aeabi_llsl
-
-
[Called By]
-
-__aeabi_llsl (Thumb, 30 bytes, Stack size 0 bytes, llshl.o(.text))
-
[Called By]
- >> __aeabi_dadd
-
- >> __aeabi_f2lz
-
- >> __aeabi_uldivmod
-
- >> _double_epilogue
-
-
-_ll_shift_l (Thumb, 0 bytes, Stack size 0 bytes, llshl.o(.text), UNUSED)
-
-
__aeabi_lasr (Thumb, 36 bytes, Stack size 0 bytes, llsshr.o(.text))
-
[Called By]
-
-_ll_sshift_r (Thumb, 0 bytes, Stack size 0 bytes, llsshr.o(.text), UNUSED)
-
-
__I$use$fp (Thumb, 0 bytes, Stack size 0 bytes, iusefp.o(.text), UNUSED)
-
-
_float_round (Thumb, 18 bytes, Stack size 0 bytes, fepilogue.o(.text))
-
[Called By]
-
-_float_epilogue (Thumb, 92 bytes, Stack size 4 bytes, fepilogue.o(.text))
-
[Stack]
- Max Depth = 4
- Call Chain = _float_epilogue
-
-
[Called By]
-
-_double_round (Thumb, 30 bytes, Stack size 8 bytes, depilogue.o(.text))
-
[Stack]
- Max Depth = 8
- Call Chain = _double_round
-
-
[Called By]- >> __aeabi_dadd
-
- >> _double_epilogue
-
-
-_double_epilogue (Thumb, 156 bytes, Stack size 32 bytes, depilogue.o(.text))
-
[Stack]
- Max Depth = 40
- Call Chain = _double_epilogue ⇒ _double_round
-
-
[Calls]- >> __aeabi_llsr
-
- >> __aeabi_llsl
-
- >> _double_round
-
-
[Called By]
-
-__scatterload (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
-
[Calls]
- >> __main_after_scatterload
-
-
[Called By]
-
-__scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)
-
-
__aeabi_llsr (Thumb, 32 bytes, Stack size 0 bytes, llushr.o(.text))
-
[Called By]
- >> __aeabi_uldivmod
-
- >> _double_epilogue
-
-
-_ll_ushift_r (Thumb, 0 bytes, Stack size 0 bytes, llushr.o(.text), UNUSED)
-
-
__decompress (Thumb, 0 bytes, Stack size unknown bytes, __dczerorl.o(.text), UNUSED)
-
-
__decompress0 (Thumb, 58 bytes, Stack size unknown bytes, __dczerorl.o(.text), UNUSED)
-
-
BusFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.BusFault_Handler))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-Buzzer_Init (Thumb, 156 bytes, Stack size 48 bytes, buzzer.o(i.Buzzer_Init))
-
[Stack]
- Max Depth = 68
- Call Chain = Buzzer_Init ⇒ GPIO_PinAFConfig
-
-
[Calls]- >> GPIO_PinAFConfig
-
- >> GPIO_Init
-
- >> RCC_APB1PeriphClockCmd
-
- >> RCC_AHB1PeriphClockCmd
-
- >> TIM_TimeBaseInit
-
- >> TIM_OCStructInit
-
- >> TIM_OC3Init
-
- >> TIM_InternalClockConfig
-
- >> TIM_Cmd
-
-
[Called By]
-
-Buzzer_ON (Thumb, 50 bytes, Stack size 8 bytes, buzzer.o(i.Buzzer_ON))
-
[Stack]
- Max Depth = 8
- Call Chain = Buzzer_ON
-
-
[Calls]- >> TIM_SetCompare3
-
- >> TIM_PrescalerConfig
-
- >> TIM_Cmd
-
-
[Called By]- >> Warming_LinkError
-
- >> Warming_BuzzerClean
-
-
-CAN1_RX0_IRQHandler (Thumb, 198 bytes, Stack size 16 bytes, can.o(i.CAN1_RX0_IRQHandler))
-
[Stack]
- Max Depth = 104
- Call Chain = CAN1_RX0_IRQHandler ⇒ M3508_CANDataProcess ⇒ __aeabi_ldivmod ⇒ __aeabi_uldivmod
-
-
[Calls]- >> CAN_GetITStatus
-
- >> CAN_ClearITPendingBit
-
- >> Warming_BuzzerClean
-
- >> M3508_CANDataProcess
-
- >> LinkCheck_ON
-
- >> LinkCheck_OFF
-
- >> GM6020_CANDataProcess
-
- >> CAN_CAN2ChangeID
-
- >> CAN_CAN1Receive
-
- >> CAN_CAN1ChangeID
-
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-CAN2_RX1_IRQHandler (Thumb, 212 bytes, Stack size 16 bytes, can.o(i.CAN2_RX1_IRQHandler))
-
[Stack]
- Max Depth = 84
- Call Chain = CAN2_RX1_IRQHandler ⇒ GM6020_CANDataProcess ⇒ __aeabi_l2f ⇒ _float_epilogue
-
-
[Calls]- >> CAN_GetITStatus
-
- >> CAN_ClearITPendingBit
-
- >> Warming_BuzzerClean
-
- >> LinkCheck_ON
-
- >> LinkCheck_OFF
-
- >> GM6020_CANDataProcess
-
- >> CToC_CANDataProcess
-
- >> CAN_CAN2Receive
-
- >> CAN_CAN2ChangeID
-
- >> CAN_CAN1ChangeID
-
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-CAN_CAN1ChangeID (Thumb, 50 bytes, Stack size 0 bytes, can.o(i.CAN_CAN1ChangeID))
-
[Called By]
- >> CAN2_RX1_IRQHandler
-
- >> CAN1_RX0_IRQHandler
-
-
-CAN_CAN1Receive (Thumb, 54 bytes, Stack size 32 bytes, can.o(i.CAN_CAN1Receive))
-
[Stack]
- Max Depth = 40
- Call Chain = CAN_CAN1Receive ⇒ CAN_Receive
-
-
[Calls]- >> CAN_Receive
-
- >> CAN_MessagePending
-
-
[Called By]
-
-CAN_CAN2ChangeID (Thumb, 50 bytes, Stack size 0 bytes, can.o(i.CAN_CAN2ChangeID))
-
[Called By]
- >> CAN2_RX1_IRQHandler
-
- >> CAN1_RX0_IRQHandler
-
-
-CAN_CAN2Receive (Thumb, 54 bytes, Stack size 32 bytes, can.o(i.CAN_CAN2Receive))
-
[Stack]
- Max Depth = 40
- Call Chain = CAN_CAN2Receive ⇒ CAN_Receive
-
-
[Calls]- >> CAN_Receive
-
- >> CAN_MessagePending
-
-
[Called By]
-
-CAN_CANInit (Thumb, 376 bytes, Stack size 48 bytes, can.o(i.CAN_CANInit))
-
[Stack]
- Max Depth = 68
- Call Chain = CAN_CANInit ⇒ GPIO_PinAFConfig
-
-
[Calls]- >> CAN_Init
-
- >> CAN_ITConfig
-
- >> CAN_FilterInit
-
- >> NVIC_PriorityGroupConfig
-
- >> NVIC_Init
-
- >> GPIO_PinAFConfig
-
- >> GPIO_Init
-
- >> RCC_APB1PeriphClockCmd
-
- >> RCC_AHB1PeriphClockCmd
-
-
[Called By]
-
-CAN_ClearITPendingBit (Thumb, 162 bytes, Stack size 0 bytes, stm32f4xx_can.o(i.CAN_ClearITPendingBit))
-
[Called By]
- >> CAN2_RX1_IRQHandler
-
- >> CAN1_RX0_IRQHandler
-
-
-CAN_FilterInit (Thumb, 258 bytes, Stack size 8 bytes, stm32f4xx_can.o(i.CAN_FilterInit))
-
[Stack]
- Max Depth = 8
- Call Chain = CAN_FilterInit
-
-
[Called By]
-
-CAN_GetITStatus (Thumb, 284 bytes, Stack size 16 bytes, stm32f4xx_can.o(i.CAN_GetITStatus))
-
[Stack]
- Max Depth = 16
- Call Chain = CAN_GetITStatus
-
-
[Calls]
-
[Called By]- >> CAN2_RX1_IRQHandler
-
- >> CAN1_RX0_IRQHandler
-
-
-CAN_ITConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f4xx_can.o(i.CAN_ITConfig))
-
[Called By]
-
-CAN_Init (Thumb, 276 bytes, Stack size 12 bytes, stm32f4xx_can.o(i.CAN_Init))
-
[Stack]
- Max Depth = 12
- Call Chain = CAN_Init
-
-
[Called By]
-
-CAN_MessagePending (Thumb, 30 bytes, Stack size 0 bytes, stm32f4xx_can.o(i.CAN_MessagePending))
-
[Called By]
- >> CAN_CAN2Receive
-
- >> CAN_CAN1Receive
-
-
-CAN_Receive (Thumb, 232 bytes, Stack size 8 bytes, stm32f4xx_can.o(i.CAN_Receive))
-
[Stack]
- Max Depth = 8
- Call Chain = CAN_Receive
-
-
[Called By]- >> CAN_CAN2Receive
-
- >> CAN_CAN1Receive
-
-
-CAN_Transmit (Thumb, 294 bytes, Stack size 8 bytes, stm32f4xx_can.o(i.CAN_Transmit))
-
[Stack]
- Max Depth = 8
- Call Chain = CAN_Transmit
-
-
[Called By]- >> CToC_SlaveSendRefereeSystemData
-
- >> M3508_CANSetLIDCurrent
-
- >> Ultra_CAP_SetVoltage
-
- >> Ultra_CAP_SetPower
-
- >> Ultra_CAP_SetCurrent
-
- >> Ultra_CAP_Enable
-
-
-CAN_TransmitStatus (Thumb, 138 bytes, Stack size 8 bytes, stm32f4xx_can.o(i.CAN_TransmitStatus))
-
[Stack]
- Max Depth = 8
- Call Chain = CAN_TransmitStatus
-
-
[Called By]- >> CToC_SlaveSendRefereeSystemData
-
- >> M3508_CANSetLIDCurrent
-
- >> Ultra_CAP_SetVoltage
-
- >> Ultra_CAP_SetPower
-
- >> Ultra_CAP_SetCurrent
-
- >> Ultra_CAP_Enable
-
-
-CToC_CANDataProcess (Thumb, 108 bytes, Stack size 0 bytes, ctoc.o(i.CToC_CANDataProcess))
-
[Called By]
-
-CToC_SlaveSendRefereeSystemData (Thumb, 116 bytes, Stack size 32 bytes, ctoc.o(i.CToC_SlaveSendRefereeSystemData))
-
[Stack]
- Max Depth = 40
- Call Chain = CToC_SlaveSendRefereeSystemData ⇒ CAN_TransmitStatus
-
-
[Calls]- >> CAN_TransmitStatus
-
- >> CAN_Transmit
-
-
[Called By]
-
-CloseLoopControl_Init (Thumb, 122 bytes, Stack size 24 bytes, closeloopcontrol.o(i.CloseLoopControl_Init))
-
[Stack]
- Max Depth = 40
- Call Chain = CloseLoopControl_Init ⇒ NVIC_Init
-
-
[Calls]- >> NVIC_PriorityGroupConfig
-
- >> NVIC_Init
-
- >> RCC_APB1PeriphClockCmd
-
- >> Mecanum_Init
-
- >> TIM_TimeBaseInit
-
- >> TIM_InternalClockConfig
-
- >> TIM_ITConfig
-
- >> TIM_Cmd
-
- >> TIM_ClearFlag
-
-
[Called By]
-
-DMA_ClearFlag (Thumb, 38 bytes, Stack size 0 bytes, stm32f4xx_dma.o(i.DMA_ClearFlag))
-
[Called By]
- >> Remote_TransferReset
-
-
-DMA_Cmd (Thumb, 22 bytes, Stack size 0 bytes, stm32f4xx_dma.o(i.DMA_Cmd))
-
[Called By]
- >> Remote_TransferReset
-
-
-DMA_GetCmdStatus (Thumb, 20 bytes, Stack size 0 bytes, stm32f4xx_dma.o(i.DMA_GetCmdStatus))
-
[Called By]
- >> Remote_TransferReset
-
-
-DMA_GetCurrDataCounter (Thumb, 8 bytes, Stack size 0 bytes, stm32f4xx_dma.o(i.DMA_GetCurrDataCounter))
-
[Called By]
-
-DMA_GetCurrentMemoryTarget (Thumb, 20 bytes, Stack size 0 bytes, stm32f4xx_dma.o(i.DMA_GetCurrentMemoryTarget))
-
[Called By]
-
-DMA_GetFlagStatus (Thumb, 54 bytes, Stack size 12 bytes, stm32f4xx_dma.o(i.DMA_GetFlagStatus))
-
[Stack]
- Max Depth = 12
- Call Chain = DMA_GetFlagStatus
-
-
[Called By]- >> Remote_TransferReset
-
-
-DMA_SetCurrDataCounter (Thumb, 4 bytes, Stack size 0 bytes, stm32f4xx_dma.o(i.DMA_SetCurrDataCounter))
-
[Called By]
- >> Remote_TransferReset
-
-
-DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.DebugMon_Handler))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-Delay_ms (Thumb, 24 bytes, Stack size 8 bytes, delay.o(i.Delay_ms))
-
[Stack]
- Max Depth = 8
- Call Chain = Delay_ms
-
-
[Calls]
-
[Called By]
-
-Delay_s (Thumb, 24 bytes, Stack size 8 bytes, delay.o(i.Delay_s))
-
[Stack]
- Max Depth = 16
- Call Chain = Delay_s ⇒ Delay_ms
-
-
[Calls]
-
[Called By]
-
-Delay_us (Thumb, 74 bytes, Stack size 0 bytes, delay.o(i.Delay_us))
-
[Called By]
-
-GM6020_CANDataProcess (Thumb, 898 bytes, Stack size 48 bytes, gm6020.o(i.GM6020_CANDataProcess))
-
[Stack]
- Max Depth = 68
- Call Chain = GM6020_CANDataProcess ⇒ __aeabi_l2f ⇒ _float_epilogue
-
-
[Calls]- >> __aeabi_l2f
-
- >> __aeabi_f2lz
-
-
[Called By]- >> CAN2_RX1_IRQHandler
-
- >> CAN1_RX0_IRQHandler
-
-
-GPIO_Init (Thumb, 144 bytes, Stack size 20 bytes, stm32f4xx_gpio.o(i.GPIO_Init))
-
[Stack]
- Max Depth = 20
- Call Chain = GPIO_Init
-
-
[Called By]- >> Buzzer_Init
-
- >> LED_Init
-
- >> CAN_CANInit
-
- >> UART2_Init
-
-
-GPIO_PinAFConfig (Thumb, 70 bytes, Stack size 20 bytes, stm32f4xx_gpio.o(i.GPIO_PinAFConfig))
-
[Stack]
- Max Depth = 20
- Call Chain = GPIO_PinAFConfig
-
-
[Called By]- >> Buzzer_Init
-
- >> CAN_CANInit
-
- >> UART2_Init
-
-
-GPIO_ResetBits (Thumb, 6 bytes, Stack size 0 bytes, stm32f4xx_gpio.o(i.GPIO_ResetBits))
-
[Called By]
- >> LED_ROFF
-
- >> LED_Init
-
- >> LED_GOFF
-
- >> LED_BOFF
-
-
-GPIO_SetBits (Thumb, 4 bytes, Stack size 0 bytes, stm32f4xx_gpio.o(i.GPIO_SetBits))
-
[Called By]
-
-HardFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.HardFault_Handler))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-LED_BOFF (Thumb, 14 bytes, Stack size 8 bytes, led.o(i.LED_BOFF))
-
[Stack]
- Max Depth = 8
- Call Chain = LED_BOFF
-
-
[Calls]
-
[Called By]
-
-LED_BON (Thumb, 14 bytes, Stack size 8 bytes, led.o(i.LED_BON))
-
[Stack]
- Max Depth = 8
- Call Chain = LED_BON
-
-
[Calls]
-
[Called By]
-
-LED_GOFF (Thumb, 14 bytes, Stack size 8 bytes, led.o(i.LED_GOFF))
-
[Stack]
- Max Depth = 8
- Call Chain = LED_GOFF
-
-
[Calls]
-
[Called By]
-
-LED_Init (Thumb, 80 bytes, Stack size 16 bytes, led.o(i.LED_Init))
-
[Stack]
- Max Depth = 36
- Call Chain = LED_Init ⇒ GPIO_Init
-
-
[Calls]- >> GPIO_ResetBits
-
- >> GPIO_Init
-
- >> RCC_AHB1PeriphClockCmd
-
-
[Called By]
-
-LED_ROFF (Thumb, 14 bytes, Stack size 8 bytes, led.o(i.LED_ROFF))
-
[Stack]
- Max Depth = 8
- Call Chain = LED_ROFF
-
-
[Calls]
-
[Called By]- >> Warming_RemoteNoCheck
-
- >> Warming_LEDClean
-
-
-LED_RON (Thumb, 14 bytes, Stack size 8 bytes, led.o(i.LED_RON))
-
[Stack]
- Max Depth = 8
- Call Chain = LED_RON
-
-
[Calls]
-
[Called By]- >> Warming_RemoteNoCheck
-
- >> Warming_RemoteDataERROR
-
-
-LinkCheck_Init (Thumb, 120 bytes, Stack size 24 bytes, linkcheck.o(i.LinkCheck_Init))
-
[Stack]
- Max Depth = 92
- Call Chain = LinkCheck_Init ⇒ CAN_CANInit ⇒ GPIO_PinAFConfig
-
-
[Calls]- >> NVIC_PriorityGroupConfig
-
- >> NVIC_Init
-
- >> RCC_APB1PeriphClockCmd
-
- >> CAN_CANInit
-
- >> TIM_TimeBaseInit
-
- >> TIM_InternalClockConfig
-
- >> TIM_ITConfig
-
- >> TIM_Cmd
-
- >> TIM_ClearFlag
-
-
[Called By]
-
-LinkCheck_OFF (Thumb, 12 bytes, Stack size 8 bytes, linkcheck.o(i.LinkCheck_OFF))
-
[Stack]
- Max Depth = 8
- Call Chain = LinkCheck_OFF
-
-
[Calls]
-
[Called By]- >> CAN2_RX1_IRQHandler
-
- >> CAN1_RX0_IRQHandler
-
-
-LinkCheck_ON (Thumb, 20 bytes, Stack size 8 bytes, linkcheck.o(i.LinkCheck_ON))
-
[Stack]
- Max Depth = 8
- Call Chain = LinkCheck_ON
-
-
[Calls]- >> TIM_SetCounter
-
- >> TIM_Cmd
-
-
[Called By]- >> CAN2_RX1_IRQHandler
-
- >> CAN1_RX0_IRQHandler
-
-
-M3508_CANDataProcess (Thumb, 998 bytes, Stack size 24 bytes, m3508.o(i.M3508_CANDataProcess))
-
[Stack]
- Max Depth = 88
- Call Chain = M3508_CANDataProcess ⇒ __aeabi_ldivmod ⇒ __aeabi_uldivmod
-
-
[Calls]- >> __aeabi_l2f
-
- >> __aeabi_f2lz
-
- >> __aeabi_ldivmod
-
-
[Called By]
-
-M3508_CANSetLIDCurrent (Thumb, 146 bytes, Stack size 48 bytes, m3508.o(i.M3508_CANSetLIDCurrent))
-
[Stack]
- Max Depth = 56
- Call Chain = M3508_CANSetLIDCurrent ⇒ CAN_TransmitStatus
-
-
[Calls]- >> CAN_TransmitStatus
-
- >> CAN_Transmit
-
-
[Called By]- >> Mecanum_ControlSpeed
-
- >> Warming_MotorControl
-
-
-Mecanum_ControlSpeed (Thumb, 510 bytes, Stack size 56 bytes, mecanum.o(i.Mecanum_ControlSpeed))
-
[Stack]
- Max Depth = 144
- Call Chain = Mecanum_ControlSpeed ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ _double_round
-
-
[Calls]- >> __aeabi_f2d
-
- >> __aeabi_dadd
-
- >> __aeabi_d2f
-
- >> PID_PositionCalc
-
- >> M3508_CANSetLIDCurrent
-
- >> __hardfp_fabs
-
-
[Called By]- >> Mecanum_PowerMoveControl
-
-
-Mecanum_Init (Thumb, 308 bytes, Stack size 8 bytes, mecanum.o(i.Mecanum_Init))
-
[Stack]
- Max Depth = 8
- Call Chain = Mecanum_Init
-
-
[Calls]- >> PID_PositionStructureInit
-
- >> PID_PositionSetParameter
-
- >> PID_PositionSetOUTRange
-
- >> PID_PositionSetEkRange
-
-
[Called By]- >> CloseLoopControl_Init
-
-
-Mecanum_PowerMoveControl (Thumb, 1880 bytes, Stack size 80 bytes, mecanum.o(i.Mecanum_PowerMoveControl))
-
[Stack]
- Max Depth = 224
- Call Chain = Mecanum_PowerMoveControl ⇒ Mecanum_ControlSpeed ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ _double_round
-
-
[Calls]- >> Mecanum_ControlSpeed
-
- >> PID_PositionSetOUTRange
-
- >> PID_PositionCalc
-
- >> __aeabi_l2f
-
- >> __hardfp_sqrtf
-
- >> __hardfp_sinf
-
- >> __hardfp_cosf
-
-
[Called By]
-
-MemManage_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.MemManage_Handler))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.NMI_Handler))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-NVIC_Init (Thumb, 106 bytes, Stack size 16 bytes, misc.o(i.NVIC_Init))
-
[Stack]
- Max Depth = 16
- Call Chain = NVIC_Init
-
-
[Called By]- >> CloseLoopControl_Init
-
- >> LinkCheck_Init
-
- >> CAN_CANInit
-
- >> UART2_Init
-
-
-NVIC_PriorityGroupConfig (Thumb, 10 bytes, Stack size 0 bytes, misc.o(i.NVIC_PriorityGroupConfig))
-
[Called By]
- >> CloseLoopControl_Init
-
- >> LinkCheck_Init
-
- >> CAN_CANInit
-
- >> UART2_Init
-
-
-PID_PositionCalc (Thumb, 230 bytes, Stack size 0 bytes, pid.o(i.PID_PositionCalc))
-
[Called By]
- >> Mecanum_ControlSpeed
-
- >> Mecanum_PowerMoveControl
-
-
-PID_PositionSetEkRange (Thumb, 10 bytes, Stack size 0 bytes, pid.o(i.PID_PositionSetEkRange))
-
[Called By]
-
-PID_PositionSetOUTRange (Thumb, 10 bytes, Stack size 0 bytes, pid.o(i.PID_PositionSetOUTRange))
-
[Called By]
- >> Mecanum_PowerMoveControl
-
- >> Mecanum_Init
-
-
-PID_PositionSetParameter (Thumb, 14 bytes, Stack size 0 bytes, pid.o(i.PID_PositionSetParameter))
-
[Called By]
-
-PID_PositionStructureInit (Thumb, 78 bytes, Stack size 0 bytes, pid.o(i.PID_PositionStructureInit))
-
[Called By]
-
-PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.PendSV_Handler))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-RCC_AHB1PeriphClockCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f4xx_rcc.o(i.RCC_AHB1PeriphClockCmd))
-
[Called By]
- >> Buzzer_Init
-
- >> LED_Init
-
- >> CAN_CANInit
-
- >> UART2_Init
-
-
-RCC_APB1PeriphClockCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f4xx_rcc.o(i.RCC_APB1PeriphClockCmd))
-
[Called By]
- >> CloseLoopControl_Init
-
- >> LinkCheck_Init
-
- >> Buzzer_Init
-
- >> CAN_CANInit
-
-
-RCC_APB2PeriphClockCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f4xx_rcc.o(i.RCC_APB2PeriphClockCmd))
-
[Called By]
-
-RCC_GetClocksFreq (Thumb, 214 bytes, Stack size 20 bytes, stm32f4xx_rcc.o(i.RCC_GetClocksFreq))
-
[Stack]
- Max Depth = 20
- Call Chain = RCC_GetClocksFreq
-
-
[Called By]
-
-RefereeSystem_GetCRC16CheckSum (Thumb, 38 bytes, Stack size 12 bytes, refereesystem.o(i.RefereeSystem_GetCRC16CheckSum))
-
[Stack]
- Max Depth = 12
- Call Chain = RefereeSystem_GetCRC16CheckSum
-
-
[Called By]- >> ui_proc_string_frame
-
- >> ui_proc_2_frame
-
-
-RefereeSystem_GetCRC8CheckSum (Thumb, 32 bytes, Stack size 12 bytes, refereesystem.o(i.RefereeSystem_GetCRC8CheckSum))
-
[Stack]
- Max Depth = 12
- Call Chain = RefereeSystem_GetCRC8CheckSum
-
-
[Called By]- >> ui_proc_string_frame
-
- >> ui_proc_2_frame
-
-
-RefereeSystem_Init (Thumb, 2 bytes, Stack size 0 bytes, refereesystem.o(i.RefereeSystem_Init))
-
[Called By]
-
-Remote_DataProcess (Thumb, 234 bytes, Stack size 8 bytes, remote.o(i.Remote_DataProcess))
-
[Stack]
- Max Depth = 8
- Call Chain = Remote_DataProcess
-
-
[Calls]- >> DMA_GetCurrentMemoryTarget
-
-
[Called By]
-
-Remote_TransferReset (Thumb, 62 bytes, Stack size 8 bytes, remote.o(i.Remote_TransferReset))
-
[Stack]
- Max Depth = 20
- Call Chain = Remote_TransferReset ⇒ DMA_GetFlagStatus
-
-
[Calls]- >> DMA_SetCurrDataCounter
-
- >> DMA_GetFlagStatus
-
- >> DMA_GetCmdStatus
-
- >> DMA_Cmd
-
- >> DMA_ClearFlag
-
-
[Called By]
-
-SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.SVC_Handler))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-SysTick_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.SysTick_Handler))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-SystemInit (Thumb, 88 bytes, Stack size 8 bytes, system_stm32f4xx.o(i.SystemInit))
-
[Stack]
- Max Depth = 20
- Call Chain = SystemInit ⇒ SetSysClock
-
-
[Calls]
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(.text)
-
-TIM2_IRQHandler (Thumb, 24 bytes, Stack size 8 bytes, tim.o(i.TIM2_IRQHandler))
-
[Stack]
- Max Depth = 20
- Call Chain = TIM2_IRQHandler ⇒ TIM_GetITStatus
-
-
[Calls]- >> TIM_GetITStatus
-
- >> TIM_ClearITPendingBit
-
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-TIM6_DAC_IRQHandler (Thumb, 190 bytes, Stack size 8 bytes, closeloopcontrol.o(i.TIM6_DAC_IRQHandler))
-
[Stack]
- Max Depth = 232
- Call Chain = TIM6_DAC_IRQHandler ⇒ Mecanum_PowerMoveControl ⇒ Mecanum_ControlSpeed ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ _double_round
-
-
[Calls]- >> UI_Updata
-
- >> UI_RemoteNoCheck
-
- >> UI_Init
-
- >> Mecanum_PowerMoveControl
-
- >> Warming_UIShow
-
- >> Warming_MotorControl
-
- >> Warming_LinkError
-
- >> TIM_GetITStatus
-
- >> TIM_ClearITPendingBit
-
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-TIM7_IRQHandler (Thumb, 40 bytes, Stack size 8 bytes, remote.o(i.TIM7_IRQHandler))
-
[Stack]
- Max Depth = 24
- Call Chain = TIM7_IRQHandler ⇒ Warming_RemoteNoCheck ⇒ LED_RON
-
-
[Calls]- >> Warming_RemoteNoCheck
-
- >> TIM_GetITStatus
-
- >> TIM_ClearITPendingBit
-
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-TIM8_UP_TIM13_IRQHandler (Thumb, 30 bytes, Stack size 8 bytes, linkcheck.o(i.TIM8_UP_TIM13_IRQHandler))
-
[Stack]
- Max Depth = 20
- Call Chain = TIM8_UP_TIM13_IRQHandler ⇒ TIM_GetITStatus
-
-
[Calls]- >> TIM_GetITStatus
-
- >> TIM_ClearITPendingBit
-
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-TIM_ClearFlag (Thumb, 6 bytes, Stack size 0 bytes, stm32f4xx_tim.o(i.TIM_ClearFlag))
-
[Called By]
- >> CloseLoopControl_Init
-
- >> LinkCheck_Init
-
-
-TIM_ClearITPendingBit (Thumb, 6 bytes, Stack size 0 bytes, stm32f4xx_tim.o(i.TIM_ClearITPendingBit))
-
[Called By]
- >> TIM6_DAC_IRQHandler
-
- >> TIM8_UP_TIM13_IRQHandler
-
- >> TIM7_IRQHandler
-
- >> TIM2_IRQHandler
-
-
-TIM_Cmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f4xx_tim.o(i.TIM_Cmd))
-
[Called By]
- >> CloseLoopControl_Init
-
- >> LinkCheck_Init
-
- >> USART3_IRQHandler
-
- >> Buzzer_ON
-
- >> Buzzer_Init
-
- >> LinkCheck_ON
-
- >> LinkCheck_OFF
-
-
-TIM_GetITStatus (Thumb, 34 bytes, Stack size 12 bytes, stm32f4xx_tim.o(i.TIM_GetITStatus))
-
[Stack]
- Max Depth = 12
- Call Chain = TIM_GetITStatus
-
-
[Called By]- >> TIM6_DAC_IRQHandler
-
- >> TIM8_UP_TIM13_IRQHandler
-
- >> TIM7_IRQHandler
-
- >> TIM2_IRQHandler
-
-
-TIM_ITConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f4xx_tim.o(i.TIM_ITConfig))
-
[Called By]
- >> CloseLoopControl_Init
-
- >> LinkCheck_Init
-
-
-TIM_InternalClockConfig (Thumb, 12 bytes, Stack size 0 bytes, stm32f4xx_tim.o(i.TIM_InternalClockConfig))
-
[Called By]
- >> CloseLoopControl_Init
-
- >> LinkCheck_Init
-
- >> Buzzer_Init
-
-
-TIM_OC3Init (Thumb, 150 bytes, Stack size 16 bytes, stm32f4xx_tim.o(i.TIM_OC3Init))
-
[Stack]
- Max Depth = 16
- Call Chain = TIM_OC3Init
-
-
[Called By]
-
-TIM_OCStructInit (Thumb, 20 bytes, Stack size 0 bytes, stm32f4xx_tim.o(i.TIM_OCStructInit))
-
[Called By]
-
-TIM_PrescalerConfig (Thumb, 6 bytes, Stack size 0 bytes, stm32f4xx_tim.o(i.TIM_PrescalerConfig))
-
[Called By]
-
-TIM_SetCompare3 (Thumb, 4 bytes, Stack size 0 bytes, stm32f4xx_tim.o(i.TIM_SetCompare3))
-
[Called By]
-
-TIM_SetCounter (Thumb, 4 bytes, Stack size 0 bytes, stm32f4xx_tim.o(i.TIM_SetCounter))
-
[Called By]
- >> USART3_IRQHandler
-
- >> LinkCheck_ON
-
-
-TIM_TimeBaseInit (Thumb, 104 bytes, Stack size 0 bytes, stm32f4xx_tim.o(i.TIM_TimeBaseInit))
-
[Called By]
- >> CloseLoopControl_Init
-
- >> LinkCheck_Init
-
- >> Buzzer_Init
-
-
-UART1_SendArray (Thumb, 26 bytes, Stack size 16 bytes, uart.o(i.UART1_SendArray))
-
[Stack]
- Max Depth = 24
- Call Chain = UART1_SendArray ⇒ UART1_SendByte
-
-
[Calls]
-
[Called By]- >> _ui_update_default_Ungroup_2_ERROR
-
- >> _ui_update_default_Ungroup_2_Shift_Open
-
- >> _ui_update_default_Ungroup_2_Shift_Close
-
- >> _ui_update_default_Ungroup_2_NOCheck
-
- >> _ui_update_default_Ungroup_2_Ctrl_Open
-
- >> _ui_update_default_Ungroup_2_Ctrl_Close
-
- >> _ui_init_default_Ungroup_2
-
- >> _ui_init_default_Ungroup_1
-
- >> _ui_init_default_Ungroup_0
-
-
-UART1_SendByte (Thumb, 28 bytes, Stack size 8 bytes, uart.o(i.UART1_SendByte))
-
[Stack]
- Max Depth = 8
- Call Chain = UART1_SendByte
-
-
[Calls]- >> USART_SendData
-
- >> USART_GetFlagStatus
-
-
[Called By]
-
-UART2_Init (Thumb, 194 bytes, Stack size 32 bytes, uart.o(i.UART2_Init))
-
[Stack]
- Max Depth = 100
- Call Chain = UART2_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq
-
-
[Calls]- >> NVIC_PriorityGroupConfig
-
- >> NVIC_Init
-
- >> GPIO_PinAFConfig
-
- >> GPIO_Init
-
- >> RCC_APB2PeriphClockCmd
-
- >> RCC_AHB1PeriphClockCmd
-
- >> USART_Init
-
- >> USART_ITConfig
-
- >> USART_Cmd
-
-
[Called By]
-
-UI_Init (Thumb, 44 bytes, Stack size 8 bytes, ui.o(i.UI_Init))
-
[Stack]
- Max Depth = 40
- Call Chain = UI_Init ⇒ _ui_init_default_Ungroup_2 ⇒ UART1_SendArray ⇒ UART1_SendByte
-
-
[Calls]- >> Delay_ms
-
- >> _ui_init_default_Ungroup_2
-
- >> _ui_init_default_Ungroup_1
-
- >> _ui_init_default_Ungroup_0
-
-
[Called By]
-
-UI_RemoteNoCheck (Thumb, 22 bytes, Stack size 8 bytes, ui.o(i.UI_RemoteNoCheck))
-
[Stack]
- Max Depth = 40
- Call Chain = UI_RemoteNoCheck ⇒ _ui_update_default_Ungroup_2_NOCheck ⇒ UART1_SendArray ⇒ UART1_SendByte
-
-
[Calls]- >> _ui_update_default_Ungroup_2_NOCheck
-
-
[Called By]
-
-UI_Updata (Thumb, 88 bytes, Stack size 8 bytes, ui.o(i.UI_Updata))
-
[Stack]
- Max Depth = 40
- Call Chain = UI_Updata ⇒ _ui_update_default_Ungroup_2_Shift_Open ⇒ UART1_SendArray ⇒ UART1_SendByte
-
-
[Calls]- >> _ui_update_default_Ungroup_2_Shift_Open
-
- >> _ui_update_default_Ungroup_2_Shift_Close
-
- >> _ui_update_default_Ungroup_2_NOCheck
-
- >> _ui_update_default_Ungroup_2_Ctrl_Open
-
- >> _ui_update_default_Ungroup_2_Ctrl_Close
-
-
[Called By]
-
-USART3_IRQHandler (Thumb, 126 bytes, Stack size 8 bytes, remote.o(i.USART3_IRQHandler))
-
[Stack]
- Max Depth = 28
- Call Chain = USART3_IRQHandler ⇒ Remote_TransferReset ⇒ DMA_GetFlagStatus
-
-
[Calls]- >> DMA_GetCurrDataCounter
-
- >> Warming_RemoteDataERROR
-
- >> Warming_LEDClean
-
- >> Remote_TransferReset
-
- >> Remote_DataProcess
-
- >> USART_ClearITPendingBit
-
- >> TIM_SetCounter
-
- >> TIM_Cmd
-
-
[Address Reference Count : 1]- startup_stm32f40_41xxx.o(RESET)
-
-USART_ClearITPendingBit (Thumb, 30 bytes, Stack size 8 bytes, stm32f4xx_usart.o(i.USART_ClearITPendingBit))
-
[Stack]
- Max Depth = 8
- Call Chain = USART_ClearITPendingBit
-
-
[Called By]
-
-USART_Cmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f4xx_usart.o(i.USART_Cmd))
-
[Called By]
-
-USART_GetFlagStatus (Thumb, 26 bytes, Stack size 0 bytes, stm32f4xx_usart.o(i.USART_GetFlagStatus))
-
[Called By]
-
-USART_ITConfig (Thumb, 74 bytes, Stack size 20 bytes, stm32f4xx_usart.o(i.USART_ITConfig))
-
[Stack]
- Max Depth = 20
- Call Chain = USART_ITConfig
-
-
[Called By]
-
-USART_Init (Thumb, 204 bytes, Stack size 48 bytes, stm32f4xx_usart.o(i.USART_Init))
-
[Stack]
- Max Depth = 68
- Call Chain = USART_Init ⇒ RCC_GetClocksFreq
-
-
[Calls]
-
[Called By]
-
-USART_SendData (Thumb, 8 bytes, Stack size 0 bytes, stm32f4xx_usart.o(i.USART_SendData))
-
[Called By]
-
-Ultra_CAP_Enable (Thumb, 102 bytes, Stack size 40 bytes, ultra_cap.o(i.Ultra_CAP_Enable))
-
[Stack]
- Max Depth = 48
- Call Chain = Ultra_CAP_Enable ⇒ CAN_TransmitStatus
-
-
[Calls]- >> CAN_TransmitStatus
-
- >> CAN_Transmit
-
-
[Called By]
-
-Ultra_CAP_Init (Thumb, 34 bytes, Stack size 8 bytes, ultra_cap.o(i.Ultra_CAP_Init))
-
[Stack]
- Max Depth = 64
- Call Chain = Ultra_CAP_Init ⇒ Ultra_CAP_SetVoltage ⇒ CAN_TransmitStatus
-
-
[Calls]- >> Ultra_CAP_SetVoltage
-
- >> Ultra_CAP_SetPower
-
- >> Ultra_CAP_SetCurrent
-
- >> Ultra_CAP_Enable
-
-
[Called By]
-
-Ultra_CAP_SetCurrent (Thumb, 132 bytes, Stack size 48 bytes, ultra_cap.o(i.Ultra_CAP_SetCurrent))
-
[Stack]
- Max Depth = 56
- Call Chain = Ultra_CAP_SetCurrent ⇒ CAN_TransmitStatus
-
-
[Calls]- >> CAN_TransmitStatus
-
- >> CAN_Transmit
-
-
[Called By]
-
-Ultra_CAP_SetPower (Thumb, 130 bytes, Stack size 48 bytes, ultra_cap.o(i.Ultra_CAP_SetPower))
-
[Stack]
- Max Depth = 56
- Call Chain = Ultra_CAP_SetPower ⇒ CAN_TransmitStatus
-
-
[Calls]- >> CAN_TransmitStatus
-
- >> CAN_Transmit
-
-
[Called By]
-
-Ultra_CAP_SetVoltage (Thumb, 132 bytes, Stack size 48 bytes, ultra_cap.o(i.Ultra_CAP_SetVoltage))
-
[Stack]
- Max Depth = 56
- Call Chain = Ultra_CAP_SetVoltage ⇒ CAN_TransmitStatus
-
-
[Calls]- >> CAN_TransmitStatus
-
- >> CAN_Transmit
-
-
[Called By]
-
-UsageFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f4xx_it.o(i.UsageFault_Handler))
-
[Address Reference Count : 1]
- startup_stm32f40_41xxx.o(RESET)
-
-Warming_BuzzerClean (Thumb, 10 bytes, Stack size 8 bytes, warming.o(i.Warming_BuzzerClean))
-
[Stack]
- Max Depth = 16
- Call Chain = Warming_BuzzerClean ⇒ Buzzer_ON
-
-
[Calls]
-
[Called By]- >> CAN2_RX1_IRQHandler
-
- >> CAN1_RX0_IRQHandler
-
-
-Warming_Init (Thumb, 12 bytes, Stack size 8 bytes, warming.o(i.Warming_Init))
-
[Stack]
- Max Depth = 76
- Call Chain = Warming_Init ⇒ Buzzer_Init ⇒ GPIO_PinAFConfig
-
-
[Calls]- >> Buzzer_Init
-
- >> LED_Init
-
-
[Called By]
-
-Warming_LEDClean (Thumb, 16 bytes, Stack size 8 bytes, warming.o(i.Warming_LEDClean))
-
[Stack]
- Max Depth = 16
- Call Chain = Warming_LEDClean ⇒ LED_ROFF
-
-
[Calls]- >> LED_ROFF
-
- >> LED_GOFF
-
- >> LED_BOFF
-
-
[Called By]
-
-Warming_LinkError (Thumb, 134 bytes, Stack size 8 bytes, warming.o(i.Warming_LinkError))
-
[Stack]
- Max Depth = 16
- Call Chain = Warming_LinkError ⇒ Buzzer_ON
-
-
[Calls]
-
[Called By]
-
-Warming_MotorControl (Thumb, 16 bytes, Stack size 8 bytes, warming.o(i.Warming_MotorControl))
-
[Stack]
- Max Depth = 64
- Call Chain = Warming_MotorControl ⇒ M3508_CANSetLIDCurrent ⇒ CAN_TransmitStatus
-
-
[Calls]- >> M3508_CANSetLIDCurrent
-
-
[Called By]
-
-Warming_RemoteDataERROR (Thumb, 8 bytes, Stack size 8 bytes, warming.o(i.Warming_RemoteDataERROR))
-
[Stack]
- Max Depth = 16
- Call Chain = Warming_RemoteDataERROR ⇒ LED_RON
-
-
[Calls]
-
[Called By]
-
-Warming_RemoteNoCheck (Thumb, 84 bytes, Stack size 8 bytes, warming.o(i.Warming_RemoteNoCheck))
-
[Stack]
- Max Depth = 16
- Call Chain = Warming_RemoteNoCheck ⇒ LED_RON
-
-
[Calls]- >> LED_RON
-
- >> LED_ROFF
-
-
[Called By]
-
-Warming_UIShow (Thumb, 8 bytes, Stack size 8 bytes, warming.o(i.Warming_UIShow))
-
[Stack]
- Max Depth = 40
- Call Chain = Warming_UIShow ⇒ _ui_update_default_Ungroup_2_ERROR ⇒ UART1_SendArray ⇒ UART1_SendByte
-
-
[Calls]- >> _ui_update_default_Ungroup_2_ERROR
-
-
[Called By]
-
-__ARM_fpclassifyf (Thumb, 38 bytes, Stack size 0 bytes, fpclassifyf.o(i.__ARM_fpclassifyf))
-
[Called By]
-
-__hardfp_cosf (Thumb, 280 bytes, Stack size 8 bytes, cosf.o(i.__hardfp_cosf))
-
[Stack]
- Max Depth = 28
- Call Chain = __hardfp_cosf ⇒ __mathlib_rredf2
-
-
[Calls]- >> __set_errno
-
- >> __mathlib_rredf2
-
- >> __mathlib_flt_invalid
-
- >> __mathlib_flt_infnan
-
-
[Called By]- >> Mecanum_PowerMoveControl
-
-
-__hardfp_fabs (Thumb, 20 bytes, Stack size 8 bytes, fabs.o(i.__hardfp_fabs))
-
[Stack]
- Max Depth = 8
- Call Chain = __hardfp_fabs
-
-
[Called By]- >> Mecanum_ControlSpeed
-
-
-__hardfp_sinf (Thumb, 344 bytes, Stack size 16 bytes, sinf.o(i.__hardfp_sinf))
-
[Stack]
- Max Depth = 36
- Call Chain = __hardfp_sinf ⇒ __mathlib_rredf2
-
-
[Calls]- >> __set_errno
-
- >> __mathlib_rredf2
-
- >> __mathlib_flt_underflow
-
- >> __mathlib_flt_invalid
-
- >> __mathlib_flt_infnan
-
- >> __ARM_fpclassifyf
-
-
[Called By]- >> Mecanum_PowerMoveControl
-
-
-__hardfp_sqrtf (Thumb, 58 bytes, Stack size 16 bytes, sqrtf.o(i.__hardfp_sqrtf))
-
[Stack]
- Max Depth = 16
- Call Chain = __hardfp_sqrtf
-
-
[Calls]
-
[Called By]- >> Mecanum_PowerMoveControl
-
-
-__mathlib_flt_infnan (Thumb, 6 bytes, Stack size 0 bytes, funder.o(i.__mathlib_flt_infnan))
-
[Called By]
- >> __hardfp_sinf
-
- >> __hardfp_cosf
-
-
-__mathlib_flt_invalid (Thumb, 10 bytes, Stack size 0 bytes, funder.o(i.__mathlib_flt_invalid))
-
[Called By]
- >> __hardfp_sinf
-
- >> __hardfp_cosf
-
-
-__mathlib_flt_underflow (Thumb, 10 bytes, Stack size 0 bytes, funder.o(i.__mathlib_flt_underflow))
-
[Called By]
-
-__mathlib_rredf2 (Thumb, 316 bytes, Stack size 20 bytes, rredf.o(i.__mathlib_rredf2))
-
[Stack]
- Max Depth = 20
- Call Chain = __mathlib_rredf2
-
-
[Called By]- >> __hardfp_sinf
-
- >> __hardfp_cosf
-
-
-__scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)
-
-
__scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)
-
-
__scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)
-
-
__set_errno (Thumb, 6 bytes, Stack size 0 bytes, errno.o(i.__set_errno))
-
[Called By]
- >> __hardfp_sqrtf
-
- >> __hardfp_sinf
-
- >> __hardfp_cosf
-
-
-_ui_init_default_Ungroup_0 (Thumb, 168 bytes, Stack size 8 bytes, ui_library.o(i._ui_init_default_Ungroup_0))
-
[Stack]
- Max Depth = 32
- Call Chain = _ui_init_default_Ungroup_0 ⇒ UART1_SendArray ⇒ UART1_SendByte
-
-
[Calls]- >> UART1_SendArray
-
- >> strcpy
-
- >> ui_proc_string_frame
-
-
[Called By]
-
-_ui_init_default_Ungroup_1 (Thumb, 170 bytes, Stack size 8 bytes, ui_library.o(i._ui_init_default_Ungroup_1))
-
[Stack]
- Max Depth = 32
- Call Chain = _ui_init_default_Ungroup_1 ⇒ UART1_SendArray ⇒ UART1_SendByte
-
-
[Calls]- >> UART1_SendArray
-
- >> strcpy
-
- >> ui_proc_string_frame
-
-
[Called By]
-
-_ui_init_default_Ungroup_2 (Thumb, 374 bytes, Stack size 8 bytes, ui_library.o(i._ui_init_default_Ungroup_2))
-
[Stack]
- Max Depth = 32
- Call Chain = _ui_init_default_Ungroup_2 ⇒ UART1_SendArray ⇒ UART1_SendByte
-
-
[Calls]- >> UART1_SendArray
-
- >> ui_proc_2_frame
-
-
[Called By]
-
-_ui_update_default_Ungroup_2_Ctrl_Close (Thumb, 146 bytes, Stack size 8 bytes, ui_library.o(i._ui_update_default_Ungroup_2_Ctrl_Close))
-
[Stack]
- Max Depth = 32
- Call Chain = _ui_update_default_Ungroup_2_Ctrl_Close ⇒ UART1_SendArray ⇒ UART1_SendByte
-
-
[Calls]- >> UART1_SendArray
-
- >> ui_proc_2_frame
-
-
[Called By]
-
-_ui_update_default_Ungroup_2_Ctrl_Open (Thumb, 146 bytes, Stack size 8 bytes, ui_library.o(i._ui_update_default_Ungroup_2_Ctrl_Open))
-
[Stack]
- Max Depth = 32
- Call Chain = _ui_update_default_Ungroup_2_Ctrl_Open ⇒ UART1_SendArray ⇒ UART1_SendByte
-
-
[Calls]- >> UART1_SendArray
-
- >> ui_proc_2_frame
-
-
[Called By]
-
-_ui_update_default_Ungroup_2_ERROR (Thumb, 250 bytes, Stack size 8 bytes, ui_library.o(i._ui_update_default_Ungroup_2_ERROR))
-
[Stack]
- Max Depth = 32
- Call Chain = _ui_update_default_Ungroup_2_ERROR ⇒ UART1_SendArray ⇒ UART1_SendByte
-
-
[Calls]- >> UART1_SendArray
-
- >> ui_proc_2_frame
-
-
[Called By]
-
-_ui_update_default_Ungroup_2_NOCheck (Thumb, 254 bytes, Stack size 8 bytes, ui_library.o(i._ui_update_default_Ungroup_2_NOCheck))
-
[Stack]
- Max Depth = 32
- Call Chain = _ui_update_default_Ungroup_2_NOCheck ⇒ UART1_SendArray ⇒ UART1_SendByte
-
-
[Calls]- >> UART1_SendArray
-
- >> ui_proc_2_frame
-
-
[Called By]- >> UI_Updata
-
- >> UI_RemoteNoCheck
-
-
-_ui_update_default_Ungroup_2_Shift_Close (Thumb, 148 bytes, Stack size 8 bytes, ui_library.o(i._ui_update_default_Ungroup_2_Shift_Close))
-
[Stack]
- Max Depth = 32
- Call Chain = _ui_update_default_Ungroup_2_Shift_Close ⇒ UART1_SendArray ⇒ UART1_SendByte
-
-
[Calls]- >> UART1_SendArray
-
- >> ui_proc_2_frame
-
-
[Called By]
-
-_ui_update_default_Ungroup_2_Shift_Open (Thumb, 148 bytes, Stack size 8 bytes, ui_library.o(i._ui_update_default_Ungroup_2_Shift_Open))
-
[Stack]
- Max Depth = 32
- Call Chain = _ui_update_default_Ungroup_2_Shift_Open ⇒ UART1_SendArray ⇒ UART1_SendByte
-
-
[Calls]- >> UART1_SendArray
-
- >> ui_proc_2_frame
-
-
[Called By]
-
-main (Thumb, 50 bytes, Stack size 0 bytes, main.o(i.main))
-
[Stack]
- Max Depth = 100
- Call Chain = main ⇒ UART2_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq
-
-
[Calls]- >> RefereeSystem_Init
-
- >> CloseLoopControl_Init
-
- >> CToC_SlaveSendRefereeSystemData
-
- >> Warming_Init
-
- >> LinkCheck_Init
-
- >> LED_BON
-
- >> UART2_Init
-
- >> Delay_us
-
- >> Delay_s
-
- >> Ultra_CAP_Init
-
-
[Address Reference Count : 1]- entry9a.o(.ARM.Collect$$$$0000000B)
-
-ui_proc_2_frame (Thumb, 96 bytes, Stack size 8 bytes, ui_base.o(i.ui_proc_2_frame))
-
[Stack]
- Max Depth = 20
- Call Chain = ui_proc_2_frame ⇒ RefereeSystem_GetCRC8CheckSum
-
-
[Calls]- >> RefereeSystem_GetCRC8CheckSum
-
- >> RefereeSystem_GetCRC16CheckSum
-
-
[Called By]- >> _ui_update_default_Ungroup_2_ERROR
-
- >> _ui_update_default_Ungroup_2_Shift_Open
-
- >> _ui_update_default_Ungroup_2_Shift_Close
-
- >> _ui_update_default_Ungroup_2_NOCheck
-
- >> _ui_update_default_Ungroup_2_Ctrl_Open
-
- >> _ui_update_default_Ungroup_2_Ctrl_Close
-
- >> _ui_init_default_Ungroup_2
-
-
-ui_proc_string_frame (Thumb, 114 bytes, Stack size 8 bytes, ui_base.o(i.ui_proc_string_frame))
-
[Stack]
- Max Depth = 20
- Call Chain = ui_proc_string_frame ⇒ RefereeSystem_GetCRC8CheckSum
-
-
[Calls]- >> RefereeSystem_GetCRC8CheckSum
-
- >> RefereeSystem_GetCRC16CheckSum
-
- >> strlen
-
-
[Called By]- >> _ui_init_default_Ungroup_1
-
- >> _ui_init_default_Ungroup_0
-
-
-
-Local Symbols
-
-SetSysClock (Thumb, 220 bytes, Stack size 12 bytes, system_stm32f4xx.o(i.SetSysClock))
-
[Stack]
- Max Depth = 12
- Call Chain = SetSysClock
-
-
[Called By]
-
-CheckITStatus (Thumb, 18 bytes, Stack size 0 bytes, stm32f4xx_can.o(i.CheckITStatus))
-
[Called By]
-
-
-Undefined Global Symbols
-
diff --git a/底盘/底盘-old/底盘/Objects/Project.lnp b/底盘/底盘-old/底盘/Objects/Project.lnp
deleted file mode 100644
index 04faafc..0000000
--- a/底盘/底盘-old/底盘/Objects/Project.lnp
+++ /dev/null
@@ -1,72 +0,0 @@
---cpu=Cortex-M4.fp.sp
-".\objects\startup_stm32f40_41xxx.o"
-".\objects\system_stm32f4xx.o"
-".\objects\misc.o"
-".\objects\stm32f4xx_adc.o"
-".\objects\stm32f4xx_can.o"
-".\objects\stm32f4xx_cec.o"
-".\objects\stm32f4xx_crc.o"
-".\objects\stm32f4xx_cryp.o"
-".\objects\stm32f4xx_cryp_aes.o"
-".\objects\stm32f4xx_cryp_des.o"
-".\objects\stm32f4xx_cryp_tdes.o"
-".\objects\stm32f4xx_dac.o"
-".\objects\stm32f4xx_dbgmcu.o"
-".\objects\stm32f4xx_dcmi.o"
-".\objects\stm32f4xx_dfsdm.o"
-".\objects\stm32f4xx_dma.o"
-".\objects\stm32f4xx_dma2d.o"
-".\objects\stm32f4xx_dsi.o"
-".\objects\stm32f4xx_exti.o"
-".\objects\stm32f4xx_flash.o"
-".\objects\stm32f4xx_flash_ramfunc.o"
-".\objects\stm32f4xx_fmpi2c.o"
-".\objects\stm32f4xx_fsmc.o"
-".\objects\stm32f4xx_gpio.o"
-".\objects\stm32f4xx_hash.o"
-".\objects\stm32f4xx_hash_md5.o"
-".\objects\stm32f4xx_hash_sha1.o"
-".\objects\stm32f4xx_i2c.o"
-".\objects\stm32f4xx_iwdg.o"
-".\objects\stm32f4xx_lptim.o"
-".\objects\stm32f4xx_ltdc.o"
-".\objects\stm32f4xx_pwr.o"
-".\objects\stm32f4xx_qspi.o"
-".\objects\stm32f4xx_rcc.o"
-".\objects\stm32f4xx_rng.o"
-".\objects\stm32f4xx_rtc.o"
-".\objects\stm32f4xx_sai.o"
-".\objects\stm32f4xx_sdio.o"
-".\objects\stm32f4xx_spdifrx.o"
-".\objects\stm32f4xx_spi.o"
-".\objects\stm32f4xx_syscfg.o"
-".\objects\stm32f4xx_tim.o"
-".\objects\stm32f4xx_usart.o"
-".\objects\stm32f4xx_wwdg.o"
-".\objects\delay.o"
-".\objects\tim.o"
-".\objects\uart.o"
-".\objects\can.o"
-".\objects\led.o"
-".\objects\buzzer.o"
-".\objects\remote.o"
-".\objects\m3508.o"
-".\objects\gm6020.o"
-".\objects\linkcheck.o"
-".\objects\warming.o"
-".\objects\ctoc.o"
-".\objects\closeloopcontrol.o"
-".\objects\pid.o"
-".\objects\mecanum.o"
-".\objects\refereesystem.o"
-".\objects\refereesystem_crctable.o"
-".\objects\ultra_cap.o"
-".\objects\ui.o"
-".\objects\ui_base.o"
-".\objects\ui_library.o"
-".\objects\main.o"
-".\objects\stm32f4xx_it.o"
---library_type=microlib --strict --scatter ".\Objects\Project.sct"
---summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
---info sizes --info totals --info unused --info veneers
---list ".\Listings\Project.map" -o .\Objects\Project.axf
\ No newline at end of file
diff --git a/底盘/底盘-old/底盘/Objects/Project.sct b/底盘/底盘-old/底盘/Objects/Project.sct
deleted file mode 100644
index 3bb4046..0000000
--- a/底盘/底盘-old/底盘/Objects/Project.sct
+++ /dev/null
@@ -1,16 +0,0 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x08000000 0x00100000 { ; load region size_region
- ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- .ANY (+XO)
- }
- RW_IRAM1 0x20000000 0x00020000 { ; RW data
- .ANY (+RW +ZI)
- }
-}
-
diff --git a/底盘/底盘-old/底盘/Objects/Project_Target 1.dep b/底盘/底盘-old/底盘/Objects/Project_Target 1.dep
deleted file mode 100644
index ccff4e7..0000000
--- a/底盘/底盘-old/底盘/Objects/Project_Target 1.dep
+++ /dev/null
@@ -1,2507 +0,0 @@
-Dependencies for Project 'Project', Target 'Target 1': (DO NOT MODIFY !)
-CompilerVersion: 5060960::V5.06 update 7 (build 960)::.\ARMCOMPLIER506
-F (.\Start\core_cm4.h)(0x64D03162)()
-F (.\Start\core_cmFunc.h)(0x64D03162)()
-F (.\Start\core_cmInstr.h)(0x64D03162)()
-F (.\Start\core_cmSimd.h)(0x64D03162)()
-F (.\Start\startup_stm32f40_41xxx.s)(0x64D03132)(--cpu Cortex-M4.fp.sp -g --apcs=interwork --pd "__MICROLIB SETA 1"
-IC:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.17.1\Drivers\CMSIS\Device\ST\STM32F4xx\Include
--pd "__UVISION_VERSION SETA 538" --pd "STM32F407xx SETA 1"
--list .\listings\startup_stm32f40_41xxx.lst --xref -o .\objects\startup_stm32f40_41xxx.o --depend .\objects\startup_stm32f40_41xxx.d)
-F (.\Start\stm32f4xx.h)(0x64F48C00)()
-F (.\Start\system_stm32f4xx.c)(0x6548FDF8)(--c99 -c --cpu Cortex-M4.fp.sp -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Start -I .\Library -I .\System -I .\Algorithm -I .\Hardware -I .\Motor -I .\Function -I .\Control -I .\CarBody -I .\User --diag_suppress=188 --no-multibyte-chars --diag_suppress=186
-IC:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.17.1\Drivers\CMSIS\Device\ST\STM32F4xx\Include
-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx
-o .\objects\system_stm32f4xx.o --omf_browse .\objects\system_stm32f4xx.crf --depend .\objects\system_stm32f4xx.d)
-I (Start\stm32f4xx.h)(0x64F48C00)
-I (Start\core_cm4.h)(0x64D03162)
-I (C:\Keil_v5\ARM\ARMCOMPLIER506\include\stdint.h)(0x5E8E3CC2)
-I (.\Start\core_cmInstr.h)(0x64D03162)
-I (.\Start\core_cmFunc.h)(0x64D03162)
-I (.\Start\core_cmSimd.h)(0x64D03162)
-I (Start\system_stm32f4xx.h)(0x64D03132)
-I (.\User\stm32f4xx_conf.h)(0x64D03180)
-I (.\Library\stm32f4xx_adc.h)(0x64D03164)
-I (.\Start\stm32f4xx.h)(0x64F48C00)
-I (.\Library\stm32f4xx_crc.h)(0x64D03164)
-I (.\Library\stm32f4xx_dbgmcu.h)(0x64D03164)
-I (.\Library\stm32f4xx_dma.h)(0x64D03164)
-I (.\Library\stm32f4xx_exti.h)(0x64D03164)
-I (.\Library\stm32f4xx_flash.h)(0x64D03164)
-I (.\Library\stm32f4xx_gpio.h)(0x64D03164)
-I (.\Library\stm32f4xx_i2c.h)(0x64D03164)
-I (.\Library\stm32f4xx_iwdg.h)(0x64D03164)
-I (.\Library\stm32f4xx_pwr.h)(0x64D03164)
-I (.\Library\stm32f4xx_rcc.h)(0x64D03164)
-I (.\Library\stm32f4xx_rtc.h)(0x64D03164)
-I (.\Library\stm32f4xx_sdio.h)(0x64D03164)
-I (.\Library\stm32f4xx_spi.h)(0x64D03164)
-I (.\Library\stm32f4xx_syscfg.h)(0x64D03164)
-I (.\Library\stm32f4xx_tim.h)(0x64D03164)
-I (.\Library\stm32f4xx_usart.h)(0x64D03164)
-I (.\Library\stm32f4xx_wwdg.h)(0x64D03164)
-I (.\Library\misc.h)(0x64D03164)
-I (.\Library\stm32f4xx_cryp.h)(0x64D03164)
-I (.\Library\stm32f4xx_hash.h)(0x64D03164)
-I (.\Library\stm32f4xx_rng.h)(0x64D03164)
-I (.\Library\stm32f4xx_can.h)(0x64D03164)
-I (.\Library\stm32f4xx_dac.h)(0x64D03164)
-I (.\Library\stm32f4xx_dcmi.h)(0x64D03164)
-I (.\Library\stm32f4xx_fsmc.h)(0x64D03164)
-F (.\Start\system_stm32f4xx.h)(0x64D03132)()
-F (.\Library\misc.c)(0x64D03164)(--c99 -c --cpu Cortex-M4.fp.sp -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Start -I .\Library -I .\System -I .\Algorithm -I .\Hardware -I .\Motor -I .\Function -I .\Control -I .\CarBody -I .\User --diag_suppress=188 --no-multibyte-chars --diag_suppress=186
-IC:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.17.1\Drivers\CMSIS\Device\ST\STM32F4xx\Include
-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx
-o .\objects\misc.o --omf_browse .\objects\misc.crf --depend .\objects\misc.d)
-I (Library\misc.h)(0x64D03164)
-I (.\Start\stm32f4xx.h)(0x64F48C00)
-I (.\Start\core_cm4.h)(0x64D03162)
-I (C:\Keil_v5\ARM\ARMCOMPLIER506\include\stdint.h)(0x5E8E3CC2)
-I (.\Start\core_cmInstr.h)(0x64D03162)
-I (.\Start\core_cmFunc.h)(0x64D03162)
-I (.\Start\core_cmSimd.h)(0x64D03162)
-I (.\Start\system_stm32f4xx.h)(0x64D03132)
-I (.\User\stm32f4xx_conf.h)(0x64D03180)
-I (.\Library\stm32f4xx_adc.h)(0x64D03164)
-I (.\Library\stm32f4xx_crc.h)(0x64D03164)
-I (.\Library\stm32f4xx_dbgmcu.h)(0x64D03164)
-I (.\Library\stm32f4xx_dma.h)(0x64D03164)
-I (.\Library\stm32f4xx_exti.h)(0x64D03164)
-I (.\Library\stm32f4xx_flash.h)(0x64D03164)
-I (.\Library\stm32f4xx_gpio.h)(0x64D03164)
-I (.\Library\stm32f4xx_i2c.h)(0x64D03164)
-I (.\Library\stm32f4xx_iwdg.h)(0x64D03164)
-I (.\Library\stm32f4xx_pwr.h)(0x64D03164)
-I (.\Library\stm32f4xx_rcc.h)(0x64D03164)
-I (.\Library\stm32f4xx_rtc.h)(0x64D03164)
-I (.\Library\stm32f4xx_sdio.h)(0x64D03164)
-I (.\Library\stm32f4xx_spi.h)(0x64D03164)
-I (.\Library\stm32f4xx_syscfg.h)(0x64D03164)
-I (.\Library\stm32f4xx_tim.h)(0x64D03164)
-I (.\Library\stm32f4xx_usart.h)(0x64D03164)
-I (.\Library\stm32f4xx_wwdg.h)(0x64D03164)
-I (.\Library\misc.h)(0x64D03164)
-I (.\Library\stm32f4xx_cryp.h)(0x64D03164)
-I (.\Library\stm32f4xx_hash.h)(0x64D03164)
-I (.\Library\stm32f4xx_rng.h)(0x64D03164)
-I (.\Library\stm32f4xx_can.h)(0x64D03164)
-I (.\Library\stm32f4xx_dac.h)(0x64D03164)
-I (.\Library\stm32f4xx_dcmi.h)(0x64D03164)
-I (.\Library\stm32f4xx_fsmc.h)(0x64D03164)
-F (.\Library\misc.h)(0x64D03164)()
-F (.\Library\stm32f4xx_adc.c)(0x64D03164)(--c99 -c --cpu Cortex-M4.fp.sp -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Start -I .\Library -I .\System -I .\Algorithm -I .\Hardware -I .\Motor -I .\Function -I .\Control -I .\CarBody -I .\User --diag_suppress=188 --no-multibyte-chars --diag_suppress=186
-IC:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.17.1\Drivers\CMSIS\Device\ST\STM32F4xx\Include
-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx
-o .\objects\stm32f4xx_adc.o --omf_browse .\objects\stm32f4xx_adc.crf --depend .\objects\stm32f4xx_adc.d)
-I (Library\stm32f4xx_adc.h)(0x64D03164)
-I (.\Start\stm32f4xx.h)(0x64F48C00)
-I (.\Start\core_cm4.h)(0x64D03162)
-I (C:\Keil_v5\ARM\ARMCOMPLIER506\include\stdint.h)(0x5E8E3CC2)
-I (.\Start\core_cmInstr.h)(0x64D03162)
-I (.\Start\core_cmFunc.h)(0x64D03162)
-I (.\Start\core_cmSimd.h)(0x64D03162)
-I (.\Start\system_stm32f4xx.h)(0x64D03132)
-I (.\User\stm32f4xx_conf.h)(0x64D03180)
-I (.\Library\stm32f4xx_adc.h)(0x64D03164)
-I (.\Library\stm32f4xx_crc.h)(0x64D03164)
-I (.\Library\stm32f4xx_dbgmcu.h)(0x64D03164)
-I (.\Library\stm32f4xx_dma.h)(0x64D03164)
-I (.\Library\stm32f4xx_exti.h)(0x64D03164)
-I (.\Library\stm32f4xx_flash.h)(0x64D03164)
-I (.\Library\stm32f4xx_gpio.h)(0x64D03164)
-I (.\Library\stm32f4xx_i2c.h)(0x64D03164)
-I (.\Library\stm32f4xx_iwdg.h)(0x64D03164)
-I (.\Library\stm32f4xx_pwr.h)(0x64D03164)
-I (.\Library\stm32f4xx_rcc.h)(0x64D03164)
-I (.\Library\stm32f4xx_rtc.h)(0x64D03164)
-I (.\Library\stm32f4xx_sdio.h)(0x64D03164)
-I (.\Library\stm32f4xx_spi.h)(0x64D03164)
-I (.\Library\stm32f4xx_syscfg.h)(0x64D03164)
-I (.\Library\stm32f4xx_tim.h)(0x64D03164)
-I (.\Library\stm32f4xx_usart.h)(0x64D03164)
-I (.\Library\stm32f4xx_wwdg.h)(0x64D03164)
-I (.\Library\misc.h)(0x64D03164)
-I (.\Library\stm32f4xx_cryp.h)(0x64D03164)
-I (.\Library\stm32f4xx_hash.h)(0x64D03164)
-I (.\Library\stm32f4xx_rng.h)(0x64D03164)
-I (.\Library\stm32f4xx_can.h)(0x64D03164)
-I (.\Library\stm32f4xx_dac.h)(0x64D03164)
-I (.\Library\stm32f4xx_dcmi.h)(0x64D03164)
-I (.\Library\stm32f4xx_fsmc.h)(0x64D03164)
-F (.\Library\stm32f4xx_adc.h)(0x64D03164)()
-F (.\Library\stm32f4xx_can.c)(0x64D03164)(--c99 -c --cpu Cortex-M4.fp.sp -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Start -I .\Library -I .\System -I .\Algorithm -I .\Hardware -I .\Motor -I .\Function -I .\Control -I .\CarBody -I .\User --diag_suppress=188 --no-multibyte-chars --diag_suppress=186
-IC:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.17.1\Drivers\CMSIS\Device\ST\STM32F4xx\Include
-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx
-o .\objects\stm32f4xx_can.o --omf_browse .\objects\stm32f4xx_can.crf --depend .\objects\stm32f4xx_can.d)
-I (Library\stm32f4xx_can.h)(0x64D03164)
-I (.\Start\stm32f4xx.h)(0x64F48C00)
-I (.\Start\core_cm4.h)(0x64D03162)
-I (C:\Keil_v5\ARM\ARMCOMPLIER506\include\stdint.h)(0x5E8E3CC2)
-I (.\Start\core_cmInstr.h)(0x64D03162)
-I (.\Start\core_cmFunc.h)(0x64D03162)
-I (.\Start\core_cmSimd.h)(0x64D03162)
-I (.\Start\system_stm32f4xx.h)(0x64D03132)
-I (.\User\stm32f4xx_conf.h)(0x64D03180)
-I (.\Library\stm32f4xx_adc.h)(0x64D03164)
-I (.\Library\stm32f4xx_crc.h)(0x64D03164)
-I (.\Library\stm32f4xx_dbgmcu.h)(0x64D03164)
-I (.\Library\stm32f4xx_dma.h)(0x64D03164)
-I (.\Library\stm32f4xx_exti.h)(0x64D03164)
-I (.\Library\stm32f4xx_flash.h)(0x64D03164)
-I (.\Library\stm32f4xx_gpio.h)(0x64D03164)
-I (.\Library\stm32f4xx_i2c.h)(0x64D03164)
-I (.\Library\stm32f4xx_iwdg.h)(0x64D03164)
-I (.\Library\stm32f4xx_pwr.h)(0x64D03164)
-I (.\Library\stm32f4xx_rcc.h)(0x64D03164)
-I (.\Library\stm32f4xx_rtc.h)(0x64D03164)
-I (.\Library\stm32f4xx_sdio.h)(0x64D03164)
-I (.\Library\stm32f4xx_spi.h)(0x64D03164)
-I (.\Library\stm32f4xx_syscfg.h)(0x64D03164)
-I (.\Library\stm32f4xx_tim.h)(0x64D03164)
-I (.\Library\stm32f4xx_usart.h)(0x64D03164)
-I (.\Library\stm32f4xx_wwdg.h)(0x64D03164)
-I (.\Library\misc.h)(0x64D03164)
-I (.\Library\stm32f4xx_cryp.h)(0x64D03164)
-I (.\Library\stm32f4xx_hash.h)(0x64D03164)
-I (.\Library\stm32f4xx_rng.h)(0x64D03164)
-I (.\Library\stm32f4xx_can.h)(0x64D03164)
-I (.\Library\stm32f4xx_dac.h)(0x64D03164)
-I (.\Library\stm32f4xx_dcmi.h)(0x64D03164)
-I (.\Library\stm32f4xx_fsmc.h)(0x64D03164)
-F (.\Library\stm32f4xx_can.h)(0x64D03164)()
-F (.\Library\stm32f4xx_cec.c)(0x64D03164)(--c99 -c --cpu Cortex-M4.fp.sp -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Start -I .\Library -I .\System -I .\Algorithm -I .\Hardware -I .\Motor -I .\Function -I .\Control -I .\CarBody -I .\User --diag_suppress=188 --no-multibyte-chars --diag_suppress=186
-IC:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.17.1\Drivers\CMSIS\Device\ST\STM32F4xx\Include
-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx
-o .\objects\stm32f4xx_cec.o --omf_browse .\objects\stm32f4xx_cec.crf --depend .\objects\stm32f4xx_cec.d)
-I (Library\stm32f4xx_cec.h)(0x64D03164)
-I (.\Start\stm32f4xx.h)(0x64F48C00)
-I (.\Start\core_cm4.h)(0x64D03162)
-I (C:\Keil_v5\ARM\ARMCOMPLIER506\include\stdint.h)(0x5E8E3CC2)
-I (.\Start\core_cmInstr.h)(0x64D03162)
-I (.\Start\core_cmFunc.h)(0x64D03162)
-I (.\Start\core_cmSimd.h)(0x64D03162)
-I (.\Start\system_stm32f4xx.h)(0x64D03132)
-I (.\User\stm32f4xx_conf.h)(0x64D03180)
-I (.\Library\stm32f4xx_adc.h)(0x64D03164)
-I (.\Library\stm32f4xx_crc.h)(0x64D03164)
-I (.\Library\stm32f4xx_dbgmcu.h)(0x64D03164)
-I (.\Library\stm32f4xx_dma.h)(0x64D03164)
-I (.\Library\stm32f4xx_exti.h)(0x64D03164)
-I (.\Library\stm32f4xx_flash.h)(0x64D03164)
-I (.\Library\stm32f4xx_gpio.h)(0x64D03164)
-I (.\Library\stm32f4xx_i2c.h)(0x64D03164)
-I (.\Library\stm32f4xx_iwdg.h)(0x64D03164)
-I (.\Library\stm32f4xx_pwr.h)(0x64D03164)
-I (.\Library\stm32f4xx_rcc.h)(0x64D03164)
-I (.\Library\stm32f4xx_rtc.h)(0x64D03164)
-I (.\Library\stm32f4xx_sdio.h)(0x64D03164)
-I (.\Library\stm32f4xx_spi.h)(0x64D03164)
-I (.\Library\stm32f4xx_syscfg.h)(0x64D03164)
-I (.\Library\stm32f4xx_tim.h)(0x64D03164)
-I (.\Library\stm32f4xx_usart.h)(0x64D03164)
-I (.\Library\stm32f4xx_wwdg.h)(0x64D03164)
-I (.\Library\misc.h)(0x64D03164)
-I (.\Library\stm32f4xx_cryp.h)(0x64D03164)
-I (.\Library\stm32f4xx_hash.h)(0x64D03164)
-I (.\Library\stm32f4xx_rng.h)(0x64D03164)
-I (.\Library\stm32f4xx_can.h)(0x64D03164)
-I (.\Library\stm32f4xx_dac.h)(0x64D03164)
-I (.\Library\stm32f4xx_dcmi.h)(0x64D03164)
-I (.\Library\stm32f4xx_fsmc.h)(0x64D03164)
-F (.\Library\stm32f4xx_cec.h)(0x64D03164)()
-F (.\Library\stm32f4xx_crc.c)(0x64D03164)(--c99 -c --cpu Cortex-M4.fp.sp -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Start -I .\Library -I .\System -I .\Algorithm -I .\Hardware -I .\Motor -I .\Function -I .\Control -I .\CarBody -I .\User --diag_suppress=188 --no-multibyte-chars --diag_suppress=186
-IC:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.17.1\Drivers\CMSIS\Device\ST\STM32F4xx\Include
-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx
-o .\objects\stm32f4xx_crc.o --omf_browse .\objects\stm32f4xx_crc.crf --depend .\objects\stm32f4xx_crc.d)
-I (Library\stm32f4xx_crc.h)(0x64D03164)
-I (.\Start\stm32f4xx.h)(0x64F48C00)
-I (.\Start\core_cm4.h)(0x64D03162)
-I (C:\Keil_v5\ARM\ARMCOMPLIER506\include\stdint.h)(0x5E8E3CC2)
-I (.\Start\core_cmInstr.h)(0x64D03162)
-I (.\Start\core_cmFunc.h)(0x64D03162)
-I (.\Start\core_cmSimd.h)(0x64D03162)
-I (.\Start\system_stm32f4xx.h)(0x64D03132)
-I (.\User\stm32f4xx_conf.h)(0x64D03180)
-I (.\Library\stm32f4xx_adc.h)(0x64D03164)
-I (.\Library\stm32f4xx_crc.h)(0x64D03164)
-I (.\Library\stm32f4xx_dbgmcu.h)(0x64D03164)
-I (.\Library\stm32f4xx_dma.h)(0x64D03164)
-I (.\Library\stm32f4xx_exti.h)(0x64D03164)
-I (.\Library\stm32f4xx_flash.h)(0x64D03164)
-I (.\Library\stm32f4xx_gpio.h)(0x64D03164)
-I (.\Library\stm32f4xx_i2c.h)(0x64D03164)
-I (.\Library\stm32f4xx_iwdg.h)(0x64D03164)
-I (.\Library\stm32f4xx_pwr.h)(0x64D03164)
-I (.\Library\stm32f4xx_rcc.h)(0x64D03164)
-I (.\Library\stm32f4xx_rtc.h)(0x64D03164)
-I (.\Library\stm32f4xx_sdio.h)(0x64D03164)
-I (.\Library\stm32f4xx_spi.h)(0x64D03164)
-I (.\Library\stm32f4xx_syscfg.h)(0x64D03164)
-I (.\Library\stm32f4xx_tim.h)(0x64D03164)
-I (.\Library\stm32f4xx_usart.h)(0x64D03164)
-I (.\Library\stm32f4xx_wwdg.h)(0x64D03164)
-I (.\Library\misc.h)(0x64D03164)
-I (.\Library\stm32f4xx_cryp.h)(0x64D03164)
-I (.\Library\stm32f4xx_hash.h)(0x64D03164)
-I (.\Library\stm32f4xx_rng.h)(0x64D03164)
-I (.\Library\stm32f4xx_can.h)(0x64D03164)
-I (.\Library\stm32f4xx_dac.h)(0x64D03164)
-I (.\Library\stm32f4xx_dcmi.h)(0x64D03164)
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-I (Library\stm32f4xx_flash_ramfunc.h)(0x64D03164)
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-I (.\Library\stm32f4xx_adc.h)(0x64D03164)
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-I (.\Library\stm32f4xx_dbgmcu.h)(0x64D03164)
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-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx
-o .\objects\warming.o --omf_browse .\objects\warming.crf --depend .\objects\warming.d)
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-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx
-o .\objects\ctoc.o --omf_browse .\objects\ctoc.crf --depend .\objects\ctoc.d)
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-o .\objects\closeloopcontrol.o --omf_browse .\objects\closeloopcontrol.crf --depend .\objects\closeloopcontrol.d)
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-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx
-o .\objects\mecanum.o --omf_browse .\objects\mecanum.crf --depend .\objects\mecanum.d)
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-I (CarBody\RefereeSystem.h)(0x67E443EF)
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-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx
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-I (.\CarBody\Ultra_CAP.h)(0x66A1111C)
-I (.\CarBody\UI.h)(0x66A113C6)
-F (.\User\RM_C.h)(0x66A234BA)()
-F (.\User\Parameter.h)(0x67DE905C)()
-F (.\User\stm32f4xx_conf.h)(0x64D03180)()
-F (.\User\stm32f4xx_it.c)(0x64D032D2)(--c99 -c --cpu Cortex-M4.fp.sp -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I .\Start -I .\Library -I .\System -I .\Algorithm -I .\Hardware -I .\Motor -I .\Function -I .\Control -I .\CarBody -I .\User --diag_suppress=188 --no-multibyte-chars --diag_suppress=186
-IC:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.17.1\Drivers\CMSIS\Device\ST\STM32F4xx\Include
-D__UVISION_VERSION="538" -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx
-o .\objects\stm32f4xx_it.o --omf_browse .\objects\stm32f4xx_it.crf --depend .\objects\stm32f4xx_it.d)
-I (User\stm32f4xx_it.h)(0x64D03180)
-I (.\Start\stm32f4xx.h)(0x64F48C00)
-I (.\Start\core_cm4.h)(0x64D03162)
-I (C:\Keil_v5\ARM\ARMCOMPLIER506\include\stdint.h)(0x5E8E3CC2)
-I (.\Start\core_cmInstr.h)(0x64D03162)
-I (.\Start\core_cmFunc.h)(0x64D03162)
-I (.\Start\core_cmSimd.h)(0x64D03162)
-I (.\Start\system_stm32f4xx.h)(0x64D03132)
-I (.\User\stm32f4xx_conf.h)(0x64D03180)
-I (.\Library\stm32f4xx_adc.h)(0x64D03164)
-I (.\Library\stm32f4xx_crc.h)(0x64D03164)
-I (.\Library\stm32f4xx_dbgmcu.h)(0x64D03164)
-I (.\Library\stm32f4xx_dma.h)(0x64D03164)
-I (.\Library\stm32f4xx_exti.h)(0x64D03164)
-I (.\Library\stm32f4xx_flash.h)(0x64D03164)
-I (.\Library\stm32f4xx_gpio.h)(0x64D03164)
-I (.\Library\stm32f4xx_i2c.h)(0x64D03164)
-I (.\Library\stm32f4xx_iwdg.h)(0x64D03164)
-I (.\Library\stm32f4xx_pwr.h)(0x64D03164)
-I (.\Library\stm32f4xx_rcc.h)(0x64D03164)
-I (.\Library\stm32f4xx_rtc.h)(0x64D03164)
-I (.\Library\stm32f4xx_sdio.h)(0x64D03164)
-I (.\Library\stm32f4xx_spi.h)(0x64D03164)
-I (.\Library\stm32f4xx_syscfg.h)(0x64D03164)
-I (.\Library\stm32f4xx_tim.h)(0x64D03164)
-I (.\Library\stm32f4xx_usart.h)(0x64D03164)
-I (.\Library\stm32f4xx_wwdg.h)(0x64D03164)
-I (.\Library\misc.h)(0x64D03164)
-I (.\Library\stm32f4xx_cryp.h)(0x64D03164)
-I (.\Library\stm32f4xx_hash.h)(0x64D03164)
-I (.\Library\stm32f4xx_rng.h)(0x64D03164)
-I (.\Library\stm32f4xx_can.h)(0x64D03164)
-I (.\Library\stm32f4xx_dac.h)(0x64D03164)
-I (.\Library\stm32f4xx_dcmi.h)(0x64D03164)
-I (.\Library\stm32f4xx_fsmc.h)(0x64D03164)
-F (.\User\stm32f4xx_it.h)(0x64D03180)()
diff --git a/底盘/底盘-old/底盘/Objects/buzzer.crf b/底盘/底盘-old/底盘/Objects/buzzer.crf
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index f4eae21..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/can.crf b/底盘/底盘-old/底盘/Objects/can.crf
deleted file mode 100644
index 27d0ccc..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/closeloopcontrol.crf b/底盘/底盘-old/底盘/Objects/closeloopcontrol.crf
deleted file mode 100644
index a574696..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/ctoc.crf b/底盘/底盘-old/底盘/Objects/ctoc.crf
deleted file mode 100644
index 6e30c26..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/delay.crf b/底盘/底盘-old/底盘/Objects/delay.crf
deleted file mode 100644
index c95450a..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/gm6020.crf b/底盘/底盘-old/底盘/Objects/gm6020.crf
deleted file mode 100644
index 47b672b..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/led.crf b/底盘/底盘-old/底盘/Objects/led.crf
deleted file mode 100644
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diff --git a/底盘/底盘-old/底盘/Objects/linkcheck.crf b/底盘/底盘-old/底盘/Objects/linkcheck.crf
deleted file mode 100644
index 5a91fb6..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/m3508.crf b/底盘/底盘-old/底盘/Objects/m3508.crf
deleted file mode 100644
index c3817b8..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/main.crf b/底盘/底盘-old/底盘/Objects/main.crf
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index affe933..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/mecanum.crf b/底盘/底盘-old/底盘/Objects/mecanum.crf
deleted file mode 100644
index 16bc362..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/misc.crf b/底盘/底盘-old/底盘/Objects/misc.crf
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diff --git a/底盘/底盘-old/底盘/Objects/pid.crf b/底盘/底盘-old/底盘/Objects/pid.crf
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index 1bfdb89..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/refereesystem.crf b/底盘/底盘-old/底盘/Objects/refereesystem.crf
deleted file mode 100644
index febbe49..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/refereesystem_crctable.crf b/底盘/底盘-old/底盘/Objects/refereesystem_crctable.crf
deleted file mode 100644
index 0f79598..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/remote.crf b/底盘/底盘-old/底盘/Objects/remote.crf
deleted file mode 100644
index 7142000..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_adc.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_adc.crf
deleted file mode 100644
index 8066a2b..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_can.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_can.crf
deleted file mode 100644
index d5b22ef..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_cec.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_cec.crf
deleted file mode 100644
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_crc.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_crc.crf
deleted file mode 100644
index 7473390..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_cryp.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_cryp.crf
deleted file mode 100644
index db01715..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_cryp_aes.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_cryp_aes.crf
deleted file mode 100644
index d2c8ff4..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_cryp_des.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_cryp_des.crf
deleted file mode 100644
index 90c6a2b..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_cryp_tdes.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_cryp_tdes.crf
deleted file mode 100644
index 936bbda..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_dac.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_dac.crf
deleted file mode 100644
index 16009c9..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_dbgmcu.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_dbgmcu.crf
deleted file mode 100644
index b89f698..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_dcmi.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_dcmi.crf
deleted file mode 100644
index e69db3c..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_dfsdm.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_dfsdm.crf
deleted file mode 100644
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_dma.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_dma.crf
deleted file mode 100644
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_dma2d.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_dma2d.crf
deleted file mode 100644
index 036f431..0000000
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_dsi.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_dsi.crf
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_exti.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_exti.crf
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_flash.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_flash.crf
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_flash_ramfunc.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_flash_ramfunc.crf
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_fmpi2c.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_fmpi2c.crf
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_fsmc.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_fsmc.crf
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_gpio.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_gpio.crf
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_hash.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_hash.crf
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_hash_md5.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_hash_md5.crf
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_hash_sha1.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_hash_sha1.crf
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_i2c.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_i2c.crf
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_it.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_it.crf
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_iwdg.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_iwdg.crf
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_lptim.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_lptim.crf
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_ltdc.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_ltdc.crf
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_pwr.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_pwr.crf
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_qspi.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_qspi.crf
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_rcc.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_rcc.crf
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_rtc.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_rtc.crf
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_sdio.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_sdio.crf
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_spdifrx.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_spdifrx.crf
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diff --git a/底盘/底盘-old/底盘/Objects/stm32f4xx_spi.crf b/底盘/底盘-old/底盘/Objects/stm32f4xx_spi.crf
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deleted file mode 100644
index 81c2361..0000000
--- a/底盘/底盘-old/底盘/Project.uvguix.Lenovo
+++ /dev/null
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diff --git a/底盘/底盘-old/底盘/Project.uvguix.peng1 b/底盘/底盘-old/底盘/Project.uvguix.peng1
deleted file mode 100644
index f130534..0000000
--- a/底盘/底盘-old/底盘/Project.uvguix.peng1
+++ /dev/null
@@ -1,3709 +0,0 @@
-
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- -6.1
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- ### uVision Project, (C) Keil Software
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- 1936
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- 1935
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- 2506
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diff --git a/底盘/底盘-old/底盘/Project.uvprojx b/底盘/底盘-old/底盘/Project.uvprojx
deleted file mode 100644
index f9f7b88..0000000
--- a/底盘/底盘-old/底盘/Project.uvprojx
+++ /dev/null
@@ -1,1118 +0,0 @@
-
-
-
- 2.1
-
- ### uVision Project, (C) Keil Software
-
-
-
- Target 1
- 0x4
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- --diag_suppress=188 --no-multibyte-chars --diag_suppress=186
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-
- Mecanum.h
- 5
- .\CarBody\Mecanum.h
-
-
- RefereeSystem.c
- 1
- .\CarBody\RefereeSystem.c
-
-
- RefereeSystem.h
- 5
- .\CarBody\RefereeSystem.h
-
-
- RefereeSystem_CRCTable.c
- 1
- .\CarBody\RefereeSystem_CRCTable.c
-
-
- RefereeSystem_CRCTable.h
- 5
- .\CarBody\RefereeSystem_CRCTable.h
-
-
- Ultra_CAP.c
- 1
- .\CarBody\Ultra_CAP.c
-
-
- Ultra_CAP.h
- 5
- .\CarBody\Ultra_CAP.h
-
-
- UI.c
- 1
- .\CarBody\UI.c
-
-
- UI.h
- 5
- .\CarBody\UI.h
-
-
- UI_Base.c
- 1
- .\CarBody\UI_Base.c
-
-
- UI_Base.h
- 5
- .\CarBody\UI_Base.h
-
-
- UI_Library.c
- 1
- .\CarBody\UI_Library.c
-
-
- UI_Library.h
- 5
- .\CarBody\UI_Library.h
-
-
-
-
- User
-
-
- main.c
- 1
- .\User\main.c
-
-
- RM_C.h
- 5
- .\User\RM_C.h
-
-
- Parameter.h
- 5
- .\User\Parameter.h
-
-
- stm32f4xx_conf.h
- 5
- .\User\stm32f4xx_conf.h
-
-
- stm32f4xx_it.c
- 1
- .\User\stm32f4xx_it.c
-
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diff --git a/底盘/底盘-old/底盘/Start/core_cm4.h b/底盘/底盘-old/底盘/Start/core_cm4.h
deleted file mode 100644
index 9749c27..0000000
--- a/底盘/底盘-old/底盘/Start/core_cm4.h
+++ /dev/null
@@ -1,1858 +0,0 @@
-/**************************************************************************//**
- * @file core_cm4.h
- * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version V4.10
- * @date 18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M4
- @{
- */
-
-/* CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
-#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
- __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x04) /*!< Cortex-M Core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TMS470__ )
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __CSMC__ )
- #define __packed
- #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
- #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
- #define __STATIC_INLINE static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __TMS470__ )
- #if defined __TI_VFP_SUPPORT__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __CSMC__ ) /* Cosmic */
- #if ( __CSMC__ & 0x400) // FPU present for parser
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-#endif
-
-#include /* standard types definitions */
-#include /* Core Instruction Access */
-#include /* Core Function Access */
-#include /* Compiler specific SIMD Intrinsics */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM4_REV
- #define __CM4_REV 0x0000
- #warning "__CM4_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- IO Type Qualifiers are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/*@} end of group Cortex_M4 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core FPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/** \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31 /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30 /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29 /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28 /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-#define APSR_Q_Pos 27 /*!< APSR: Q Position */
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos 16 /*!< APSR: GE Position */
-#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
-
-
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31 /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29 /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28 /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
-#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos 24 /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
-#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/** \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24];
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24];
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24];
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24];
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56];
- __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644];
- __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/** \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[5];
- __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/** \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1];
- __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/** \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __O union
- {
- __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864];
- __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15];
- __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15];
- __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29];
- __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43];
- __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6];
- __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1];
- __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1];
- __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1];
- __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/** \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2];
- __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55];
- __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131];
- __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759];
- __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1];
- __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39];
- __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8];
- __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/** \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if (__FPU_PRESENT == 1)
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_FPU Floating Point Unit (FPU)
- \brief Type definitions for the Floating Point Unit (FPU)
- @{
- */
-
-/** \brief Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
- uint32_t RESERVED0[1];
- __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
- __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
- __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
- __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
- __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register */
-#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register */
-#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register */
-#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-#endif
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/** \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-#if (__FPU_PRESENT == 1)
- #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
- #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/** \brief Set Priority Grouping
-
- The function sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/** \brief Get Priority Grouping
-
- The function reads the priority grouping field from the NVIC Interrupt Controller.
-
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/** \brief Enable External Interrupt
-
- The function enables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief Disable External Interrupt
-
- The function disables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief Get Pending Interrupt
-
- The function reads the pending register in the NVIC and returns the pending bit
- for the specified interrupt.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief Set Pending Interrupt
-
- The function sets the pending bit of an external interrupt.
-
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief Clear Pending Interrupt
-
- The function clears the pending bit of an external interrupt.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/** \brief Get Active Interrupt
-
- The function reads the active register in NVIC and returns the active bit.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/** \brief Set Interrupt Priority
-
- The function sets the priority of an interrupt.
-
- \note The priority cannot be set for every core interrupt.
-
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if((int32_t)IRQn < 0) {
- SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else {
- NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/** \brief Get Interrupt Priority
-
- The function reads the priority of an interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
-
-
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented
- priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if((int32_t)IRQn < 0) {
- return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
- }
- else {
- return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/** \brief Encode Priority
-
- The function encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/** \brief Decode Priority
-
- The function decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/** \brief System Reset
-
- The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1) { __NOP(); } /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief System Tick Configuration
-
- The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
-
- \param [in] ticks Number of ticks between two interrupts.
-
- \return 0 Function succeeded.
- \return 1 Function failed.
-
- \note When the variable __Vendor_SysTickConfig is set to 1, then the
- function SysTick_Config is not included. In this case, the file device.h
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief ITM Send Character
-
- The function transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
- \param [in] ch Character to transmit.
-
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
- ITM->PORT[0].u8 = (uint8_t)ch;
- }
- return (ch);
-}
-
-
-/** \brief ITM Receive Character
-
- The function inputs a character via the external variable \ref ITM_RxBuffer.
-
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/** \brief ITM Check Character
-
- The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/底盘/底盘-old/底盘/Start/core_cmFunc.h b/底盘/底盘-old/底盘/Start/core_cmFunc.h
deleted file mode 100644
index b6ad0a4..0000000
--- a/底盘/底盘-old/底盘/Start/core_cmFunc.h
+++ /dev/null
@@ -1,664 +0,0 @@
-/**************************************************************************//**
- * @file core_cmFunc.h
- * @brief CMSIS Cortex-M Core Function Access Header File
- * @version V4.10
- * @date 18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* intrinsic void __enable_irq(); */
-/* intrinsic void __disable_irq(); */
-
-/** \brief Get Control Register
-
- This function returns the content of the Control Register.
-
- \return Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
-
-
-/** \brief Set Control Register
-
- This function writes the given value to the Control Register.
-
- \param [in] control Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-
-/** \brief Get IPSR Register
-
- This function returns the content of the IPSR Register.
-
- \return IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
- register uint32_t __regIPSR __ASM("ipsr");
- return(__regIPSR);
-}
-
-
-/** \brief Get APSR Register
-
- This function returns the content of the APSR Register.
-
- \return APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
- register uint32_t __regAPSR __ASM("apsr");
- return(__regAPSR);
-}
-
-
-/** \brief Get xPSR Register
-
- This function returns the content of the xPSR Register.
-
- \return xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
- register uint32_t __regXPSR __ASM("xpsr");
- return(__regXPSR);
-}
-
-
-/** \brief Get Process Stack Pointer
-
- This function returns the current value of the Process Stack Pointer (PSP).
-
- \return PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- return(__regProcessStackPointer);
-}
-
-
-/** \brief Set Process Stack Pointer
-
- This function assigns the given value to the Process Stack Pointer (PSP).
-
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief Get Main Stack Pointer
-
- This function returns the current value of the Main Stack Pointer (MSP).
-
- \return MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- return(__regMainStackPointer);
-}
-
-
-/** \brief Set Main Stack Pointer
-
- This function assigns the given value to the Main Stack Pointer (MSP).
-
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief Get Priority Mask
-
- This function returns the current state of the priority mask bit from the Priority Mask Register.
-
- \return Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-
-
-/** \brief Set Priority Mask
-
- This function assigns the given value to the Priority Mask Register.
-
- \param [in] priMask Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-
-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief Enable FIQ
-
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq __enable_fiq
-
-
-/** \brief Disable FIQ
-
- This function disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq __disable_fiq
-
-
-/** \brief Get Base Priority
-
- This function returns the current value of the Base Priority register.
-
- \return Base Priority register value
- */
-__STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- register uint32_t __regBasePri __ASM("basepri");
- return(__regBasePri);
-}
-
-
-/** \brief Set Base Priority
-
- This function assigns the given value to the Base Priority register.
-
- \param [in] basePri Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
- register uint32_t __regBasePri __ASM("basepri");
- __regBasePri = (basePri & 0xff);
-}
-
-
-/** \brief Set Base Priority with condition
-
- This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
- or the new value increases the BASEPRI priority level.
-
- \param [in] basePri Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
- register uint32_t __regBasePriMax __ASM("basepri_max");
- __regBasePriMax = (basePri & 0xff);
-}
-
-
-/** \brief Get Fault Mask
-
- This function returns the current value of the Fault Mask register.
-
- \return Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- return(__regFaultMask);
-}
-
-
-/** \brief Set Fault Mask
-
- This function assigns the given value to the Fault Mask register.
-
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
-
-/** \brief Get FPSCR
-
- This function returns the current value of the Floating Point Status/Control register.
-
- \return Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- return(__regfpscr);
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Set FPSCR
-
- This function assigns the given value to the Floating Point Status/Control register.
-
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief Enable IRQ Interrupts
-
- This function enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
- __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/** \brief Disable IRQ Interrupts
-
- This function disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
-{
- __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/** \brief Get Control Register
-
- This function returns the content of the Control Register.
-
- \return Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Control Register
-
- This function writes the given value to the Control Register.
-
- \param [in] control Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-/** \brief Get IPSR Register
-
- This function returns the content of the IPSR Register.
-
- \return IPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Get APSR Register
-
- This function returns the content of the APSR Register.
-
- \return APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Get xPSR Register
-
- This function returns the content of the xPSR Register.
-
- \return xPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Get Process Stack Pointer
-
- This function returns the current value of the Process Stack Pointer (PSP).
-
- \return PSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Process Stack Pointer
-
- This function assigns the given value to the Process Stack Pointer (PSP).
-
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
-}
-
-
-/** \brief Get Main Stack Pointer
-
- This function returns the current value of the Main Stack Pointer (MSP).
-
- \return MSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Main Stack Pointer
-
- This function assigns the given value to the Main Stack Pointer (MSP).
-
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
-}
-
-
-/** \brief Get Priority Mask
-
- This function returns the current state of the priority mask bit from the Priority Mask Register.
-
- \return Priority Mask value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Priority Mask
-
- This function assigns the given value to the Priority Mask Register.
-
- \param [in] priMask Priority Mask
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Enable FIQ
-
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
-{
- __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/** \brief Disable FIQ
-
- This function disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
-{
- __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/** \brief Get Base Priority
-
- This function returns the current value of the Base Priority register.
-
- \return Base Priority register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Base Priority
-
- This function assigns the given value to the Base Priority register.
-
- \param [in] basePri Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
-}
-
-
-/** \brief Set Base Priority with condition
-
- This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
- or the new value increases the BASEPRI priority level.
-
- \param [in] basePri Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
-{
- __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
-}
-
-
-/** \brief Get Fault Mask
-
- This function returns the current value of the Fault Mask register.
-
- \return Fault Mask register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Fault Mask
-
- This function assigns the given value to the Fault Mask register.
-
- \param [in] faultMask Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
-
-/** \brief Get FPSCR
-
- This function returns the current value of the Floating Point Status/Control register.
-
- \return Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- uint32_t result;
-
- /* Empty asm statement works as a scheduling barrier */
- __ASM volatile ("");
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
- __ASM volatile ("");
- return(result);
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Set FPSCR
-
- This function assigns the given value to the Floating Point Status/Control register.
-
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- /* Empty asm statement works as a scheduling barrier */
- __ASM volatile ("");
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
- __ASM volatile ("");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-#endif /* __CORE_CMFUNC_H */
diff --git a/底盘/底盘-old/底盘/Start/core_cmInstr.h b/底盘/底盘-old/底盘/Start/core_cmInstr.h
deleted file mode 100644
index fca425c..0000000
--- a/底盘/底盘-old/底盘/Start/core_cmInstr.h
+++ /dev/null
@@ -1,916 +0,0 @@
-/**************************************************************************//**
- * @file core_cmInstr.h
- * @brief CMSIS Cortex-M Core Instruction Access Header File
- * @version V4.10
- * @date 18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ########################## Core Instruction Access ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
- Access to dedicated instructions
- @{
-*/
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief No Operation
-
- No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP __nop
-
-
-/** \brief Wait For Interrupt
-
- Wait For Interrupt is a hint instruction that suspends execution
- until one of a number of events occurs.
- */
-#define __WFI __wfi
-
-
-/** \brief Wait For Event
-
- Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-#define __WFE __wfe
-
-
-/** \brief Send Event
-
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV __sev
-
-
-/** \brief Instruction Synchronization Barrier
-
- Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or
- memory, after the instruction has been completed.
- */
-#define __ISB() do {\
- __schedule_barrier();\
- __isb(0xF);\
- __schedule_barrier();\
- } while (0)
-
-/** \brief Data Synchronization Barrier
-
- This function acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() do {\
- __schedule_barrier();\
- __dsb(0xF);\
- __schedule_barrier();\
- } while (0)
-
-/** \brief Data Memory Barrier
-
- This function ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-#define __DMB() do {\
- __schedule_barrier();\
- __dmb(0xF);\
- __schedule_barrier();\
- } while (0)
-
-/** \brief Reverse byte order (32 bit)
-
- This function reverses the byte order in integer value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __REV __rev
-
-
-/** \brief Reverse byte order (16 bit)
-
- This function reverses the byte order in two unsigned short values.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
- rev16 r0, r0
- bx lr
-}
-#endif
-
-/** \brief Reverse byte order in signed short value
-
- This function reverses the byte order in a signed short value with sign extension to integer.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
- revsh r0, r0
- bx lr
-}
-#endif
-
-
-/** \brief Rotate Right in unsigned value (32 bit)
-
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
- \param [in] value Value to rotate
- \param [in] value Number of Bits to rotate
- \return Rotated value
- */
-#define __ROR __ror
-
-
-/** \brief Breakpoint
-
- This function causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __breakpoint(value)
-
-
-/** \brief Reverse bit order of value
-
- This function reverses the bit order of the given value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
- #define __RBIT __rbit
-#else
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
- uint32_t result;
- int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
-
- result = value; // r will be reversed bits of v; first get LSB of v
- for (value >>= 1; value; value >>= 1)
- {
- result <<= 1;
- result |= value & 1;
- s--;
- }
- result <<= s; // shift when v's highest bits are zero
- return(result);
-}
-#endif
-
-
-/** \brief Count leading zeros
-
- This function counts the number of leading zeros of a data value.
-
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-#define __CLZ __clz
-
-
-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief LDR Exclusive (8 bit)
-
- This function executes a exclusive LDR instruction for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief LDR Exclusive (16 bit)
-
- This function executes a exclusive LDR instruction for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
-
-
-/** \brief LDR Exclusive (32 bit)
-
- This function executes a exclusive LDR instruction for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief STR Exclusive (8 bit)
-
- This function executes a exclusive STR instruction for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXB(value, ptr) __strex(value, ptr)
-
-
-/** \brief STR Exclusive (16 bit)
-
- This function executes a exclusive STR instruction for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXH(value, ptr) __strex(value, ptr)
-
-
-/** \brief STR Exclusive (32 bit)
-
- This function executes a exclusive STR instruction for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXW(value, ptr) __strex(value, ptr)
-
-
-/** \brief Remove the exclusive lock
-
- This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX __clrex
-
-
-/** \brief Signed Saturate
-
- This function saturates a signed value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT __ssat
-
-
-/** \brief Unsigned Saturate
-
- This function saturates an unsigned value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT __usat
-
-
-/** \brief Rotate Right with Extend (32 bit)
-
- This function moves each bit of a bitstring right by one bit.
- The carry input is shifted in at the left end of the bitstring.
-
- \param [in] value Value to rotate
- \return Rotated value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
-{
- rrx r0, r0
- bx lr
-}
-#endif
-
-
-/** \brief LDRT Unprivileged (8 bit)
-
- This function executes a Unprivileged LDRT instruction for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
-
-
-/** \brief LDRT Unprivileged (16 bit)
-
- This function executes a Unprivileged LDRT instruction for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
-
-
-/** \brief LDRT Unprivileged (32 bit)
-
- This function executes a Unprivileged LDRT instruction for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
-
-
-/** \brief STRT Unprivileged (8 bit)
-
- This function executes a Unprivileged STRT instruction for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-#define __STRBT(value, ptr) __strt(value, ptr)
-
-
-/** \brief STRT Unprivileged (16 bit)
-
- This function executes a Unprivileged STRT instruction for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-#define __STRHT(value, ptr) __strt(value, ptr)
-
-
-/** \brief STRT Unprivileged (32 bit)
-
- This function executes a Unprivileged STRT instruction for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-#define __STRT(value, ptr) __strt(value, ptr)
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constrant "l"
- * Otherwise, use general registers, specified by constrant "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/** \brief No Operation
-
- No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
-{
- __ASM volatile ("nop");
-}
-
-
-/** \brief Wait For Interrupt
-
- Wait For Interrupt is a hint instruction that suspends execution
- until one of a number of events occurs.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
-{
- __ASM volatile ("wfi");
-}
-
-
-/** \brief Wait For Event
-
- Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
-{
- __ASM volatile ("wfe");
-}
-
-
-/** \brief Send Event
-
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
-{
- __ASM volatile ("sev");
-}
-
-
-/** \brief Instruction Synchronization Barrier
-
- Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or
- memory, after the instruction has been completed.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
-{
- __ASM volatile ("isb 0xF":::"memory");
-}
-
-
-/** \brief Data Synchronization Barrier
-
- This function acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
-{
- __ASM volatile ("dsb 0xF":::"memory");
-}
-
-
-/** \brief Data Memory Barrier
-
- This function ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
-{
- __ASM volatile ("dmb 0xF":::"memory");
-}
-
-
-/** \brief Reverse byte order (32 bit)
-
- This function reverses the byte order in integer value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
- return __builtin_bswap32(value);
-#else
- uint32_t result;
-
- __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-#endif
-}
-
-
-/** \brief Reverse byte order (16 bit)
-
- This function reverses the byte order in two unsigned short values.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/** \brief Reverse byte order in signed short value
-
- This function reverses the byte order in a signed short value with sign extension to integer.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- return (short)__builtin_bswap16(value);
-#else
- uint32_t result;
-
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-#endif
-}
-
-
-/** \brief Rotate Right in unsigned value (32 bit)
-
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
- \param [in] value Value to rotate
- \param [in] value Number of Bits to rotate
- \return Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
- return (op1 >> op2) | (op1 << (32 - op2));
-}
-
-
-/** \brief Breakpoint
-
- This function causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __ASM volatile ("bkpt "#value)
-
-
-/** \brief Reverse bit order of value
-
- This function reverses the bit order of the given value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
- uint32_t result;
-
-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
- int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
-
- result = value; // r will be reversed bits of v; first get LSB of v
- for (value >>= 1; value; value >>= 1)
- {
- result <<= 1;
- result |= value & 1;
- s--;
- }
- result <<= s; // shift when v's highest bits are zero
-#endif
- return(result);
-}
-
-
-/** \brief Count leading zeros
-
- This function counts the number of leading zeros of a data value.
-
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-#define __CLZ __builtin_clz
-
-
-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief LDR Exclusive (8 bit)
-
- This function executes a exclusive LDR instruction for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint8_t) result); /* Add explicit type cast here */
-}
-
-
-/** \brief LDR Exclusive (16 bit)
-
- This function executes a exclusive LDR instruction for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint16_t) result); /* Add explicit type cast here */
-}
-
-
-/** \brief LDR Exclusive (32 bit)
-
- This function executes a exclusive LDR instruction for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- return(result);
-}
-
-
-/** \brief STR Exclusive (8 bit)
-
- This function executes a exclusive STR instruction for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/** \brief STR Exclusive (16 bit)
-
- This function executes a exclusive STR instruction for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/** \brief STR Exclusive (32 bit)
-
- This function executes a exclusive STR instruction for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- return(result);
-}
-
-
-/** \brief Remove the exclusive lock
-
- This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
-{
- __ASM volatile ("clrex" ::: "memory");
-}
-
-
-/** \brief Signed Saturate
-
- This function saturates a signed value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/** \brief Unsigned Saturate
-
- This function saturates an unsigned value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/** \brief Rotate Right with Extend (32 bit)
-
- This function moves each bit of a bitstring right by one bit.
- The carry input is shifted in at the left end of the bitstring.
-
- \param [in] value Value to rotate
- \return Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/** \brief LDRT Unprivileged (8 bit)
-
- This function executes a Unprivileged LDRT instruction for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint8_t) result); /* Add explicit type cast here */
-}
-
-
-/** \brief LDRT Unprivileged (16 bit)
-
- This function executes a Unprivileged LDRT instruction for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint16_t) result); /* Add explicit type cast here */
-}
-
-
-/** \brief LDRT Unprivileged (32 bit)
-
- This function executes a Unprivileged LDRT instruction for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
- return(result);
-}
-
-
-/** \brief STRT Unprivileged (8 bit)
-
- This function executes a Unprivileged STRT instruction for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
-{
- __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
-}
-
-
-/** \brief STRT Unprivileged (16 bit)
-
- This function executes a Unprivileged STRT instruction for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
-{
- __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
-}
-
-
-/** \brief STRT Unprivileged (32 bit)
-
- This function executes a Unprivileged STRT instruction for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
-{
- __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
-}
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */
diff --git a/底盘/底盘-old/底盘/Start/core_cmSimd.h b/底盘/底盘-old/底盘/Start/core_cmSimd.h
deleted file mode 100644
index 7b8e37f..0000000
--- a/底盘/底盘-old/底盘/Start/core_cmSimd.h
+++ /dev/null
@@ -1,697 +0,0 @@
-/**************************************************************************//**
- * @file core_cmSimd.h
- * @brief CMSIS Cortex-M SIMD Header File
- * @version V4.10
- * @date 18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CMSIMD_H
-#define __CORE_CMSIMD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- ******************************************************************************/
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
- Access to dedicated SIMD instructions
- @{
-*/
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-#define __SADD8 __sadd8
-#define __QADD8 __qadd8
-#define __SHADD8 __shadd8
-#define __UADD8 __uadd8
-#define __UQADD8 __uqadd8
-#define __UHADD8 __uhadd8
-#define __SSUB8 __ssub8
-#define __QSUB8 __qsub8
-#define __SHSUB8 __shsub8
-#define __USUB8 __usub8
-#define __UQSUB8 __uqsub8
-#define __UHSUB8 __uhsub8
-#define __SADD16 __sadd16
-#define __QADD16 __qadd16
-#define __SHADD16 __shadd16
-#define __UADD16 __uadd16
-#define __UQADD16 __uqadd16
-#define __UHADD16 __uhadd16
-#define __SSUB16 __ssub16
-#define __QSUB16 __qsub16
-#define __SHSUB16 __shsub16
-#define __USUB16 __usub16
-#define __UQSUB16 __uqsub16
-#define __UHSUB16 __uhsub16
-#define __SASX __sasx
-#define __QASX __qasx
-#define __SHASX __shasx
-#define __UASX __uasx
-#define __UQASX __uqasx
-#define __UHASX __uhasx
-#define __SSAX __ssax
-#define __QSAX __qsax
-#define __SHSAX __shsax
-#define __USAX __usax
-#define __UQSAX __uqsax
-#define __UHSAX __uhsax
-#define __USAD8 __usad8
-#define __USADA8 __usada8
-#define __SSAT16 __ssat16
-#define __USAT16 __usat16
-#define __UXTB16 __uxtb16
-#define __UXTAB16 __uxtab16
-#define __SXTB16 __sxtb16
-#define __SXTAB16 __sxtab16
-#define __SMUAD __smuad
-#define __SMUADX __smuadx
-#define __SMLAD __smlad
-#define __SMLADX __smladx
-#define __SMLALD __smlald
-#define __SMLALDX __smlaldx
-#define __SMUSD __smusd
-#define __SMUSDX __smusdx
-#define __SMLSD __smlsd
-#define __SMLSDX __smlsdx
-#define __SMLSLD __smlsld
-#define __SMLSLDX __smlsldx
-#define __SEL __sel
-#define __QADD __qadd
-#define __QSUB __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
- ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
-
-#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
- ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
-
-#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
- ((int64_t)(ARG3) << 32) ) >> 32))
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ // Little endian
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else // Big endian
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ // Little endian
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else // Big endian
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ // Little endian
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else // Big endian
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ // Little endian
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else // Big endian
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- if (ARG3 == 0) \
- __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
- else \
- __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/* not yet supported */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include
-
-#endif
-
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CMSIMD_H */
diff --git a/底盘/底盘-old/底盘/Start/startup_stm32f401xx.s b/底盘/底盘-old/底盘/Start/startup_stm32f401xx.s
deleted file mode 100644
index 6f44c76..0000000
--- a/底盘/底盘-old/底盘/Start/startup_stm32f401xx.s
+++ /dev/null
@@ -1,379 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f401xx.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F401xx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure the system clock
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD 0 ; Reserved
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD 0 ; Reserved
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD FPU_IRQHandler ; FPU
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SPI4_IRQHandler ; SPI4
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-DMA1_Stream7_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-ETH_IRQHandler
-OTG_FS_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-FPU_IRQHandler
-SPI4_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/底盘/底盘-old/底盘/Start/startup_stm32f40_41xxx.s b/底盘/底盘-old/底盘/Start/startup_stm32f40_41xxx.s
deleted file mode 100644
index 817309a..0000000
--- a/底盘/底盘-old/底盘/Start/startup_stm32f40_41xxx.s
+++ /dev/null
@@ -1,429 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f40_41xxx.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure the system clock and the external SRAM mounted on
-;* STM324xG-EVAL board to be used as data memory (optional,
-;* to be enabled by user)
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD CAN1_TX_IRQHandler ; CAN1 TX
- DCD CAN1_RX0_IRQHandler ; CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FSMC_IRQHandler ; FSMC
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD ETH_IRQHandler ; Ethernet
- DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD DCMI_IRQHandler ; DCMI
- DCD CRYP_IRQHandler ; CRYP crypto
- DCD HASH_RNG_IRQHandler ; Hash and Rng
- DCD FPU_IRQHandler ; FPU
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT CAN1_TX_IRQHandler [WEAK]
- EXPORT CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
- EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT FSMC_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT ETH_IRQHandler [WEAK]
- EXPORT ETH_WKUP_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
- EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_HS_IRQHandler [WEAK]
- EXPORT DCMI_IRQHandler [WEAK]
- EXPORT CRYP_IRQHandler [WEAK]
- EXPORT HASH_RNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-DMA1_Stream7_IRQHandler
-FSMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-ETH_IRQHandler
-ETH_WKUP_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-OTG_HS_EP1_OUT_IRQHandler
-OTG_HS_EP1_IN_IRQHandler
-OTG_HS_WKUP_IRQHandler
-OTG_HS_IRQHandler
-DCMI_IRQHandler
-CRYP_IRQHandler
-HASH_RNG_IRQHandler
-FPU_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/底盘/底盘-old/底盘/Start/startup_stm32f40xx.s b/底盘/底盘-old/底盘/Start/startup_stm32f40xx.s
deleted file mode 100644
index 836de4d..0000000
--- a/底盘/底盘-old/底盘/Start/startup_stm32f40xx.s
+++ /dev/null
@@ -1,430 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f40xx.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
-;* Same as startup_stm32f40_41xxx.s and maintained for legacy purpose
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure the system clock and the external SRAM mounted on
-;* STM324xG-EVAL board to be used as data memory (optional,
-;* to be enabled by user)
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD CAN1_TX_IRQHandler ; CAN1 TX
- DCD CAN1_RX0_IRQHandler ; CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FSMC_IRQHandler ; FSMC
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD ETH_IRQHandler ; Ethernet
- DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD DCMI_IRQHandler ; DCMI
- DCD CRYP_IRQHandler ; CRYP crypto
- DCD HASH_RNG_IRQHandler ; Hash and Rng
- DCD FPU_IRQHandler ; FPU
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT CAN1_TX_IRQHandler [WEAK]
- EXPORT CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
- EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT FSMC_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT ETH_IRQHandler [WEAK]
- EXPORT ETH_WKUP_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
- EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_HS_IRQHandler [WEAK]
- EXPORT DCMI_IRQHandler [WEAK]
- EXPORT CRYP_IRQHandler [WEAK]
- EXPORT HASH_RNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-DMA1_Stream7_IRQHandler
-FSMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-ETH_IRQHandler
-ETH_WKUP_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-OTG_HS_EP1_OUT_IRQHandler
-OTG_HS_EP1_IN_IRQHandler
-OTG_HS_WKUP_IRQHandler
-OTG_HS_IRQHandler
-DCMI_IRQHandler
-CRYP_IRQHandler
-HASH_RNG_IRQHandler
-FPU_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/底盘/底盘-old/底盘/Start/startup_stm32f410xx.s b/底盘/底盘-old/底盘/Start/startup_stm32f410xx.s
deleted file mode 100644
index 8854ffb..0000000
--- a/底盘/底盘-old/底盘/Start/startup_stm32f410xx.s
+++ /dev/null
@@ -1,383 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f410xx.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F410xx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_IRQHandler ; TIM1 Update
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD 0 ; Reserved
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TIM5_IRQHandler ; TIM5
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
- DCD 0 ; Reserved
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD RNG_IRQHandler ; RNG
- DCD FPU_IRQHandler ; FPU
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SPI5_IRQHandler ; SPI5
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event
- DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error
- DCD LPTIM1_IRQHandler ; LP TIM1
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT RNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT SPI5_IRQHandler [WEAK]
- EXPORT FMPI2C1_EV_IRQHandler [WEAK]
- EXPORT FMPI2C1_ER_IRQHandler [WEAK]
- EXPORT LPTIM1_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-DMA1_Stream7_IRQHandler
-TIM5_IRQHandler
-TIM6_DAC_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-RNG_IRQHandler
-FPU_IRQHandler
-SPI5_IRQHandler
-FMPI2C1_EV_IRQHandler
-FMPI2C1_ER_IRQHandler
-LPTIM1_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/底盘/底盘-old/底盘/Start/startup_stm32f411xe.s b/底盘/底盘-old/底盘/Start/startup_stm32f411xe.s
deleted file mode 100644
index e5a1811..0000000
--- a/底盘/底盘-old/底盘/Start/startup_stm32f411xe.s
+++ /dev/null
@@ -1,380 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f411xe.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F411xExx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD 0 ; Reserved
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD 0 ; Reserved
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD FPU_IRQHandler ; FPU
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SPI4_IRQHandler ; SPI4
- DCD SPI5_IRQHandler ; SPI5
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SPI5_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-DMA1_Stream7_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-OTG_FS_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-FPU_IRQHandler
-SPI4_IRQHandler
-SPI5_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/底盘/底盘-old/底盘/Start/startup_stm32f412xg.s b/底盘/底盘-old/底盘/Start/startup_stm32f412xg.s
deleted file mode 100644
index cb7d9d7..0000000
--- a/底盘/底盘-old/底盘/Start/startup_stm32f412xg.s
+++ /dev/null
@@ -1,434 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f412xg.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F412xG devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD CAN1_TX_IRQHandler ; CAN1 TX
- DCD CAN1_RX0_IRQHandler ; CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD 0 ; Reserved
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TIM6_IRQHandler ; TIM6
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global interrupt
- DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global interrupt
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD RNG_IRQHandler ; RNG
- DCD FPU_IRQHandler ; FPU
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SPI4_IRQHandler ; SPI4
- DCD SPI5_IRQHandler ; SPI5
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD QUADSPI_IRQHandler ; QuadSPI
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event
- DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT CAN1_TX_IRQHandler [WEAK]
- EXPORT CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
- EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT TIM6_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
- EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT RNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SPI5_IRQHandler [WEAK]
- EXPORT QUADSPI_IRQHandler [WEAK]
- EXPORT FMPI2C1_EV_IRQHandler [WEAK]
- EXPORT FMPI2C1_ER_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-DMA1_Stream7_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-DFSDM1_FLT0_IRQHandler
-DFSDM1_FLT1_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-RNG_IRQHandler
-FPU_IRQHandler
-SPI4_IRQHandler
-SPI5_IRQHandler
-QUADSPI_IRQHandler
-FMPI2C1_EV_IRQHandler
-FMPI2C1_ER_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/底盘/底盘-old/底盘/Start/startup_stm32f413_423xx.s b/底盘/底盘-old/底盘/Start/startup_stm32f413_423xx.s
deleted file mode 100644
index c7908a6..0000000
--- a/底盘/底盘-old/底盘/Start/startup_stm32f413_423xx.s
+++ /dev/null
@@ -1,475 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f423xx.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F423xx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD CAN1_TX_IRQHandler ; CAN1 TX
- DCD CAN1_RX0_IRQHandler ; CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FSMC_IRQHandler ; FSMC
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6, DAC1 and DAC2
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global interrupt
- DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global interrupt
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD CAN3_TX_IRQHandler ; CAN3 TX
- DCD CAN3_RX0_IRQHandler ; CAN3 RX0
- DCD CAN3_RX1_IRQHandler ; CAN3 RX1
- DCD CAN3_SCE_IRQHandler ; CAN3 SCE
- DCD 0 ; Reserved
- DCD AES_IRQHandler ; AES
- DCD RNG_IRQHandler ; RNG
- DCD FPU_IRQHandler ; FPU
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
- DCD SPI4_IRQHandler ; SPI4
- DCD SPI5_IRQHandler ; SPI5
- DCD 0 ; Reserved
- DCD SAI1_IRQHandler ; SAI1
- DCD UART9_IRQHandler ; UART9
- DCD UART10_IRQHandler ; UART10
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD QUADSPI_IRQHandler ; QuadSPI
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event
- DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error
- DCD LPTIM1_IRQHandler ; LPTIM1
- DCD DFSDM2_FLT0_IRQHandler ; DFSDM2 Filter0
- DCD DFSDM2_FLT1_IRQHandler ; DFSDM2 Filter1
- DCD DFSDM2_FLT2_IRQHandler ; DFSDM2 Filter2
- DCD DFSDM2_FLT3_IRQHandler ; DFSDM2 Filter3
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT CAN1_TX_IRQHandler [WEAK]
- EXPORT CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
- EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT FSMC_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
- EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT CAN3_TX_IRQHandler [WEAK]
- EXPORT CAN3_RX0_IRQHandler [WEAK]
- EXPORT CAN3_RX1_IRQHandler [WEAK]
- EXPORT CAN3_SCE_IRQHandler [WEAK]
- EXPORT AES_IRQHandler [WEAK]
- EXPORT RNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
- EXPORT UART8_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SPI5_IRQHandler [WEAK]
- EXPORT SAI1_IRQHandler [WEAK]
- EXPORT UART9_IRQHandler [WEAK]
- EXPORT UART10_IRQHandler [WEAK]
- EXPORT QUADSPI_IRQHandler [WEAK]
- EXPORT FMPI2C1_EV_IRQHandler [WEAK]
- EXPORT FMPI2C1_ER_IRQHandler [WEAK]
- EXPORT LPTIM1_IRQHandler [WEAK]
- EXPORT DFSDM2_FLT0_IRQHandler [WEAK]
- EXPORT DFSDM2_FLT1_IRQHandler [WEAK]
- EXPORT DFSDM2_FLT2_IRQHandler [WEAK]
- EXPORT DFSDM2_FLT3_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-DMA1_Stream7_IRQHandler
-FSMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-DFSDM1_FLT0_IRQHandler
-DFSDM1_FLT1_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-CAN3_TX_IRQHandler
-CAN3_RX0_IRQHandler
-CAN3_RX1_IRQHandler
-CAN3_SCE_IRQHandler
-AES_IRQHandler
-RNG_IRQHandler
-FPU_IRQHandler
-UART7_IRQHandler
-UART8_IRQHandler
-SPI4_IRQHandler
-SPI5_IRQHandler
-SAI1_IRQHandler
-UART9_IRQHandler
-UART10_IRQHandler
-QUADSPI_IRQHandler
-FMPI2C1_EV_IRQHandler
-FMPI2C1_ER_IRQHandler
-LPTIM1_IRQHandler
-DFSDM2_FLT0_IRQHandler
-DFSDM2_FLT1_IRQHandler
-DFSDM2_FLT2_IRQHandler
-DFSDM2_FLT3_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/底盘/底盘-old/底盘/Start/startup_stm32f427_437xx.s b/底盘/底盘-old/底盘/Start/startup_stm32f427_437xx.s
deleted file mode 100644
index a3f3d1c..0000000
--- a/底盘/底盘-old/底盘/Start/startup_stm32f427_437xx.s
+++ /dev/null
@@ -1,451 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f427_437xx.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F427xx/437xx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure the system clock and the external SRAM/SDRAM mounted
-;* on STM324x7I-EVAL board to be used as data memory
-;* (optional, to be enabled by user)
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD CAN1_TX_IRQHandler ; CAN1 TX
- DCD CAN1_RX0_IRQHandler ; CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FMC_IRQHandler ; FMC
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD ETH_IRQHandler ; Ethernet
- DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD DCMI_IRQHandler ; DCMI
- DCD CRYP_IRQHandler ; CRYP crypto
- DCD HASH_RNG_IRQHandler ; Hash and Rng
- DCD FPU_IRQHandler ; FPU
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
- DCD SPI4_IRQHandler ; SPI4
- DCD SPI5_IRQHandler ; SPI5
- DCD SPI6_IRQHandler ; SPI6
- DCD SAI1_IRQHandler ; SAI1
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA2D_IRQHandler ; DMA2D
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT CAN1_TX_IRQHandler [WEAK]
- EXPORT CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
- EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT FMC_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT ETH_IRQHandler [WEAK]
- EXPORT ETH_WKUP_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
- EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_HS_IRQHandler [WEAK]
- EXPORT DCMI_IRQHandler [WEAK]
- EXPORT CRYP_IRQHandler [WEAK]
- EXPORT HASH_RNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
- EXPORT UART8_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SPI5_IRQHandler [WEAK]
- EXPORT SPI6_IRQHandler [WEAK]
- EXPORT SAI1_IRQHandler [WEAK]
- EXPORT DMA2D_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-DMA1_Stream7_IRQHandler
-FMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-ETH_IRQHandler
-ETH_WKUP_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-OTG_HS_EP1_OUT_IRQHandler
-OTG_HS_EP1_IN_IRQHandler
-OTG_HS_WKUP_IRQHandler
-OTG_HS_IRQHandler
-DCMI_IRQHandler
-CRYP_IRQHandler
-HASH_RNG_IRQHandler
-FPU_IRQHandler
-UART7_IRQHandler
-UART8_IRQHandler
-SPI4_IRQHandler
-SPI5_IRQHandler
-SPI6_IRQHandler
-SAI1_IRQHandler
-DMA2D_IRQHandler
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/底盘/底盘-old/底盘/Start/startup_stm32f427x.s b/底盘/底盘-old/底盘/Start/startup_stm32f427x.s
deleted file mode 100644
index 4250781..0000000
--- a/底盘/底盘-old/底盘/Start/startup_stm32f427x.s
+++ /dev/null
@@ -1,452 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f427x.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F427xx/437xx devices vector table for MDK-ARM toolchain.
-;* Same as startup_stm32f427_437xx.s and maintained for legacy purpose
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure the system clock and the external SRAM/SDRAM mounted
-;* on STM324x9I-EVAL/STM324x7I-EVALs board to be used as data memory
-;* (optional, to be enabled by user)
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD CAN1_TX_IRQHandler ; CAN1 TX
- DCD CAN1_RX0_IRQHandler ; CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FMC_IRQHandler ; FMC
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD ETH_IRQHandler ; Ethernet
- DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD DCMI_IRQHandler ; DCMI
- DCD CRYP_IRQHandler ; CRYP crypto
- DCD HASH_RNG_IRQHandler ; Hash and Rng
- DCD FPU_IRQHandler ; FPU
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
- DCD SPI4_IRQHandler ; SPI4
- DCD SPI5_IRQHandler ; SPI5
- DCD SPI6_IRQHandler ; SPI6
- DCD SAI1_IRQHandler ; SAI1
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA2D_IRQHandler ; DMA2D
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT CAN1_TX_IRQHandler [WEAK]
- EXPORT CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
- EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT FMC_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT ETH_IRQHandler [WEAK]
- EXPORT ETH_WKUP_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
- EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_HS_IRQHandler [WEAK]
- EXPORT DCMI_IRQHandler [WEAK]
- EXPORT CRYP_IRQHandler [WEAK]
- EXPORT HASH_RNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
- EXPORT UART8_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SPI5_IRQHandler [WEAK]
- EXPORT SPI6_IRQHandler [WEAK]
- EXPORT SAI1_IRQHandler [WEAK]
- EXPORT DMA2D_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-DMA1_Stream7_IRQHandler
-FMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-ETH_IRQHandler
-ETH_WKUP_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-OTG_HS_EP1_OUT_IRQHandler
-OTG_HS_EP1_IN_IRQHandler
-OTG_HS_WKUP_IRQHandler
-OTG_HS_IRQHandler
-DCMI_IRQHandler
-CRYP_IRQHandler
-HASH_RNG_IRQHandler
-FPU_IRQHandler
-UART7_IRQHandler
-UART8_IRQHandler
-SPI4_IRQHandler
-SPI5_IRQHandler
-SPI6_IRQHandler
-SAI1_IRQHandler
-DMA2D_IRQHandler
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/底盘/底盘-old/底盘/Start/startup_stm32f429_439xx.s b/底盘/底盘-old/底盘/Start/startup_stm32f429_439xx.s
deleted file mode 100644
index a520435..0000000
--- a/底盘/底盘-old/底盘/Start/startup_stm32f429_439xx.s
+++ /dev/null
@@ -1,455 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f429_439xx.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F429xx/439xx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure the system clock and the external SRAM/SDRAM mounted
-;* on STM324x9I-EVAL boards to be used as data memory
-;* (optional, to be enabled by user)
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD CAN1_TX_IRQHandler ; CAN1 TX
- DCD CAN1_RX0_IRQHandler ; CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FMC_IRQHandler ; FMC
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD ETH_IRQHandler ; Ethernet
- DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD DCMI_IRQHandler ; DCMI
- DCD CRYP_IRQHandler ; CRYP crypto
- DCD HASH_RNG_IRQHandler ; Hash and Rng
- DCD FPU_IRQHandler ; FPU
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
- DCD SPI4_IRQHandler ; SPI4
- DCD SPI5_IRQHandler ; SPI5
- DCD SPI6_IRQHandler ; SPI6
- DCD SAI1_IRQHandler ; SAI1
- DCD LTDC_IRQHandler ; LTDC
- DCD LTDC_ER_IRQHandler ; LTDC error
- DCD DMA2D_IRQHandler ; DMA2D
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT CAN1_TX_IRQHandler [WEAK]
- EXPORT CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
- EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT FMC_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT ETH_IRQHandler [WEAK]
- EXPORT ETH_WKUP_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
- EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_HS_IRQHandler [WEAK]
- EXPORT DCMI_IRQHandler [WEAK]
- EXPORT CRYP_IRQHandler [WEAK]
- EXPORT HASH_RNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
- EXPORT UART8_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SPI5_IRQHandler [WEAK]
- EXPORT SPI6_IRQHandler [WEAK]
- EXPORT SAI1_IRQHandler [WEAK]
- EXPORT LTDC_IRQHandler [WEAK]
- EXPORT LTDC_ER_IRQHandler [WEAK]
- EXPORT DMA2D_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-DMA1_Stream7_IRQHandler
-FMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-ETH_IRQHandler
-ETH_WKUP_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-OTG_HS_EP1_OUT_IRQHandler
-OTG_HS_EP1_IN_IRQHandler
-OTG_HS_WKUP_IRQHandler
-OTG_HS_IRQHandler
-DCMI_IRQHandler
-CRYP_IRQHandler
-HASH_RNG_IRQHandler
-FPU_IRQHandler
-UART7_IRQHandler
-UART8_IRQHandler
-SPI4_IRQHandler
-SPI5_IRQHandler
-SPI6_IRQHandler
-SAI1_IRQHandler
-LTDC_IRQHandler
-LTDC_ER_IRQHandler
-DMA2D_IRQHandler
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/底盘/底盘-old/底盘/Start/startup_stm32f446xx.s b/底盘/底盘-old/底盘/Start/startup_stm32f446xx.s
deleted file mode 100644
index 01b9988..0000000
--- a/底盘/底盘-old/底盘/Start/startup_stm32f446xx.s
+++ /dev/null
@@ -1,447 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f446xx.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F446x devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD CAN1_TX_IRQHandler ; CAN1 TX
- DCD CAN1_RX0_IRQHandler ; CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FMC_IRQHandler ; FMC
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD DCMI_IRQHandler ; DCMI
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD FPU_IRQHandler ; FPU
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SAI1_IRQHandler ; SAI1
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SAI2_IRQHandler ; SAI2
- DCD QuadSPI_IRQHandler ; QuadSPI
- DCD CEC_IRQHandler ; CEC
- DCD SPDIF_RX_IRQHandler ; SPDIF RX
- DCD FMPI2C1_Event_IRQHandler ; I2C 4 Event
- DCD FMPI2C1_Error_IRQHandler ; I2C 4 Error
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT CAN1_TX_IRQHandler [WEAK]
- EXPORT CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
- EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT FMC_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
- EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_HS_IRQHandler [WEAK]
- EXPORT DCMI_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SAI1_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SAI1_IRQHandler [WEAK]
- EXPORT SAI2_IRQHandler [WEAK]
- EXPORT QuadSPI_IRQHandler [WEAK]
- EXPORT CEC_IRQHandler [WEAK]
- EXPORT SPDIF_RX_IRQHandler [WEAK]
- EXPORT FMPI2C1_Event_IRQHandler [WEAK]
- EXPORT FMPI2C1_Error_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-DMA1_Stream7_IRQHandler
-FMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-OTG_HS_EP1_OUT_IRQHandler
-OTG_HS_EP1_IN_IRQHandler
-OTG_HS_WKUP_IRQHandler
-OTG_HS_IRQHandler
-DCMI_IRQHandler
-FPU_IRQHandler
-SPI4_IRQHandler
-SAI1_IRQHandler
-SAI2_IRQHandler
-QuadSPI_IRQHandler
-CEC_IRQHandler
-SPDIF_RX_IRQHandler
-FMPI2C1_Event_IRQHandler
-FMPI2C1_Error_IRQHandler
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/底盘/底盘-old/底盘/Start/startup_stm32f469_479xx.s b/底盘/底盘-old/底盘/Start/startup_stm32f469_479xx.s
deleted file mode 100644
index c823897..0000000
--- a/底盘/底盘-old/底盘/Start/startup_stm32f469_479xx.s
+++ /dev/null
@@ -1,458 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name : startup_stm32f469_479xx.s
-;* Author : MCD Application Team
-;* @version : V1.8.1
-;* @date : 27-January-2022
-;* Description : STM32F469xx/479xx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2016 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD CAN1_TX_IRQHandler ; CAN1 TX
- DCD CAN1_RX0_IRQHandler ; CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FMC_IRQHandler ; FMC
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD ETH_IRQHandler ; Ethernet
- DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD DCMI_IRQHandler ; DCMI
- DCD CRYP_IRQHandler ; CRYPTO
- DCD HASH_RNG_IRQHandler ; Hash and Rng
- DCD FPU_IRQHandler ; FPU
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
- DCD SPI4_IRQHandler ; SPI4
- DCD SPI5_IRQHandler ; SPI5
- DCD SPI6_IRQHandler ; SPI6
- DCD SAI1_IRQHandler ; SAI1
- DCD LTDC_IRQHandler ; LTDC
- DCD LTDC_ER_IRQHandler ; LTDC error
- DCD DMA2D_IRQHandler ; DMA2D
- DCD QUADSPI_IRQHandler ; QUADSPI
- DCD DSI_IRQHandler ; DSI
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT CAN1_TX_IRQHandler [WEAK]
- EXPORT CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
- EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT FMC_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT ETH_IRQHandler [WEAK]
- EXPORT ETH_WKUP_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
- EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_HS_IRQHandler [WEAK]
- EXPORT DCMI_IRQHandler [WEAK]
- EXPORT CRYP_IRQHandler [WEAK]
- EXPORT HASH_RNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
- EXPORT UART8_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SPI5_IRQHandler [WEAK]
- EXPORT SPI6_IRQHandler [WEAK]
- EXPORT SAI1_IRQHandler [WEAK]
- EXPORT LTDC_IRQHandler [WEAK]
- EXPORT LTDC_ER_IRQHandler [WEAK]
- EXPORT DMA2D_IRQHandler [WEAK]
- EXPORT QUADSPI_IRQHandler [WEAK]
- EXPORT DSI_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-DMA1_Stream7_IRQHandler
-FMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-ETH_IRQHandler
-ETH_WKUP_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-OTG_HS_EP1_OUT_IRQHandler
-OTG_HS_EP1_IN_IRQHandler
-OTG_HS_WKUP_IRQHandler
-OTG_HS_IRQHandler
-DCMI_IRQHandler
-CRYP_IRQHandler
-HASH_RNG_IRQHandler
-FPU_IRQHandler
-UART7_IRQHandler
-UART8_IRQHandler
-SPI4_IRQHandler
-SPI5_IRQHandler
-SPI6_IRQHandler
-SAI1_IRQHandler
-LTDC_IRQHandler
-LTDC_ER_IRQHandler
-DMA2D_IRQHandler
-QUADSPI_IRQHandler
-DSI_IRQHandler
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
diff --git a/底盘/底盘-old/底盘/Start/stm32f4xx.h b/底盘/底盘-old/底盘/Start/stm32f4xx.h
deleted file mode 100644
index dcc202b..0000000
--- a/底盘/底盘-old/底盘/Start/stm32f4xx.h
+++ /dev/null
@@ -1,12059 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
- * This file contains all the peripheral register's definitions, bits
- * definitions and memory mapping for STM32F4xx devices.
- *
- * The file is the unique include file that the application programmer
- * is using in the C source code, usually in main.c. This file contains:
- * - Configuration section that allows to select:
- * - The device used in the target application
- * - To use or not the peripherals drivers in application code(i.e.
- * code will be based on direct access to peripherals registers
- * rather than drivers API), this option is controlled by
- * "#define USE_STDPERIPH_DRIVER"
- * - To change few application-specific parameters such as the HSE
- * crystal frequency
- * - Data structures and the address mapping for all peripherals
- * - Peripherals registers declarations and bits definition
- * - Macros to access peripherals registers hardware
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f4xx
- * @{
- */
-
-#ifndef __STM32F4xx_H
-#define __STM32F4xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Library_configuration_section
- * @{
- */
-
-/* Uncomment the line below according to the target STM32 device used in your
- application
- */
-
-#if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F410xx) && \
- !defined(STM32F411xE) && !defined(STM32F412xG) && !defined(STM32F413_423xx) && !defined(STM32F446xx) && !defined(STM32F469_479xx)
- /* #define STM32F40_41xxx */ /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG,
- STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE,
- STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
-
- /* #define STM32F427_437xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II,
- STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices */
-
- /* #define STM32F429_439xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI,
- STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI,
- STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI,
- STM32F439IG and STM32F439II Devices */
-
- /* #define STM32F401xx */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB, STM32F401VC,
- STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CExx, STM32F401RE and STM32F401VE Devices */
-
- /* #define STM32F410xx */ /*!< STM32F410Tx, STM32F410Cx and STM32F410Rx */
-
- /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
-
- /* #define STM32F412xG */ /*!< STM32F412CEU, STM32F412CGU, STM32F412ZET, STM32F412ZGT, STM32F412ZEJ, STM32F412ZGJ,
- STM32F412VET, STM32F412VGT, STM32F412VEH, STM32F412VGH, STM32F412RET, STM32F412RGT,
- STM32F412REY and STM32F412RGY Devices */
-
- /* #define STM32F413_423xx */ /*!< STM32F413CGU, STM32F413CHU, STM32F413MGY, STM32F413MHY, STM32F413RGT, STM32F413VGT,
- STM32F413ZGT, STM32F413RHT, STM32F413VHT, STM32F413ZHT, STM32F413VGH, STM32F413ZGJ,
- STM32F413VHH, STM32F413ZHJ, STM32F423CHU, STM32F423RHT, STM32F423VHT, STM32F423ZHT,
- STM32F423VHH and STM32F423ZHJ devices */
-
- /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC
- and STM32F446ZE Devices */
-
- /* #define STM32F469_479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG,
- STM32F479NG, STM32F479AE, STM32F479IE, STM32F479BE, STM32F479NE Devices */
-
-#endif /* STM32F40_41xxx && STM32F427_437xx && STM32F429_439xx && STM32F401xx && STM32F410xx && STM32F411xE && STM32F412xG && STM32F413_423xx && STM32F446xx && STM32F469_479xx */
-
-/* Old STM32F40XX definition, maintained for legacy purpose */
-#ifdef STM32F40XX
- #define STM32F40_41xxx
-#endif /* STM32F40XX */
-
-/* Old STM32F427X definition, maintained for legacy purpose */
-#ifdef STM32F427X
- #define STM32F427_437xx
-#endif /* STM32F427X */
-
-/* Tip: To avoid modifying this file each time you need to switch between these
- devices, you can define the device in your toolchain compiler preprocessor.
- */
-
-#if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F410xx) && \
- !defined(STM32F411xE) && !defined(STM32F412xG) && !defined(STM32F413_423xx) && !defined(STM32F446xx) && !defined(STM32F469_479xx)
- #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
-#endif /* STM32F40_41xxx && STM32F427_437xx && STM32F429_439xx && STM32F401xx && STM32F410xx && STM32F411xE && STM32F412xG && STM32F413_23xx && STM32F446xx && STM32F469_479xx */
-
-#if !defined (USE_STDPERIPH_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
- In this case, these drivers will not be included and the application code will
- be based on direct access to peripherals registers
- */
- /*#define USE_STDPERIPH_DRIVER */
-#endif /* USE_STDPERIPH_DRIVER */
-
-/**
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)
- used in your application
-
- Tip: To avoid modifying this file each time you need to use different HSE, you
- can define the HSE value in your toolchain compiler preprocessor.
- */
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || \
- defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
- #if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)12000000) /*!< Value of the External oscillator in Hz */
- #endif /* HSE_VALUE */
-#elif defined (STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
- #if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
- #endif /* HSE_VALUE */
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */
-/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
- Timeout value
- */
-#if !defined (HSE_STARTUP_TIMEOUT)
- #define HSE_STARTUP_TIMEOUT ((uint16_t)0x05000) /*!< Time out for HSE start up */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
- * @brief STM32F4XX Standard Peripherals Library version number V1.8.0
- */
-#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */
-#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
-#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
- |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
- |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
- |(__STM32F4XX_STDPERIPH_VERSION_RC))
-
-/**
- * @}
- */
-
-/** @addtogroup Configuration_section_for_CMSIS
- * @{
- */
-
-/**
- * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
- */
-#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device
- * in @ref Library_configuration_section
- */
-typedef enum IRQn
-{
-/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
-/****** STM32 specific Interrupt Numbers **********************************************************************/
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
- TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
- RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
- FLASH_IRQn = 4, /*!< FLASH global Interrupt */
- RCC_IRQn = 5, /*!< RCC global Interrupt */
- EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
- EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
- EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
- EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
- EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
- DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
- DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
- DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
- DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
- DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
- DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
- DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
- ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
-
-#if defined(STM32F40_41xxx)
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FSMC_IRQn = 48, /*!< FSMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
- DCMI_IRQn = 78, /*!< DCMI global interrupt */
- CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
- HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
- FPU_IRQn = 81 /*!< FPU global interrupt */
-#endif /* STM32F40_41xxx */
-
-#if defined(STM32F427_437xx)
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FMC_IRQn = 48, /*!< FMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
- DCMI_IRQn = 78, /*!< DCMI global interrupt */
- CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
- HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- UART7_IRQn = 82, /*!< UART7 global interrupt */
- UART8_IRQn = 83, /*!< UART8 global interrupt */
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
- SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
- SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
- DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
-#endif /* STM32F427_437xx */
-
-#if defined(STM32F429_439xx)
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FMC_IRQn = 48, /*!< FMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
- DCMI_IRQn = 78, /*!< DCMI global interrupt */
- CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
- HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- UART7_IRQn = 82, /*!< UART7 global interrupt */
- UART8_IRQn = 83, /*!< UART8 global interrupt */
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
- SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
- SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
- LTDC_IRQn = 88, /*!< LTDC global Interrupt */
- LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
- DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
-#endif /* STM32F429_439xx */
-
-#if defined(STM32F410xx)
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global Interrupt and DAC Global Interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- RNG_IRQn = 80, /*!< RNG global Interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
- FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
- FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
- LPTIM1_IRQn = 97 /*!< LPTIM1 interrupt */
-#endif /* STM32F410xx */
-
-#if defined(STM32F401xx) || defined(STM32F411xE)
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
-#if defined(STM32F401xx)
- SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
-#endif /* STM32F411xE */
-#if defined(STM32F411xE)
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SPI5_IRQn = 85 /*!< SPI5 global Interrupt */
-#endif /* STM32F411xE */
-#endif /* STM32F401xx || STM32F411xE */
-
-#if defined(STM32F469_479xx)
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FMC_IRQn = 48, /*!< FMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
- DCMI_IRQn = 78, /*!< DCMI global interrupt */
- CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
- HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- UART7_IRQn = 82, /*!< UART7 global interrupt */
- UART8_IRQn = 83, /*!< UART8 global interrupt */
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
- SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
- SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
- LTDC_IRQn = 88, /*!< LTDC global Interrupt */
- LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
- DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
- QUADSPI_IRQn = 91, /*!< QUADSPI global Interrupt */
- DSI_IRQn = 92 /*!< DSI global Interrupt */
-#endif /* STM32F469_479xx */
-
-#if defined(STM32F446xx)
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FMC_IRQn = 48, /*!< FMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
- DCMI_IRQn = 78, /*!< DCMI global interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
- SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
- QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
- CEC_IRQn = 93, /*!< QuadSPI global Interrupt */
- SPDIF_RX_IRQn = 94, /*!< QuadSPI global Interrupt */
- FMPI2C1_EV_IRQn = 95, /*!< FMPI2C Event Interrupt */
- FMPI2C1_ER_IRQn = 96 /*!< FMPCI2C Error Interrupt */
-#endif /* STM32F446xx */
-
-#if defined(STM32F412xG)
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FSMC_IRQn = 48, /*!< FSMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- TIM6_IRQn = 54, /*!< TIM6 global interrupt */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
- DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- RNG_IRQn = 80, /*!< RNG global Interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
- QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
- FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
- FMPI2C1_ER_IRQn = 96 /*!< FMPI2C1 Error Interrupt */
-#endif /* STM32F412xG */
-
-#if defined(STM32F413_423xx)
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC1&2 global Interrupt */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
- DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- CAN3_TX_IRQn = 74, /*!< CAN3 TX Interrupt */
- CAN3_RX0_IRQn = 75, /*!< CAN3 RX0 Interrupt */
- CAN3_RX1_IRQn = 76, /*!< CAN3 RX1 Interrupt */
- CAN3_SCE_IRQn = 77, /*!< CAN3 SCE Interrupt */
- RNG_IRQn = 80, /*!< RNG global Interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- UART7_IRQn = 82, /*!< UART7 global interrupt */
- UART8_IRQn = 83, /*!< UART8 global interrupt */
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
- SAI1_IRQn = 87, /*!< Serial Audio Interface 1 global interrupt */
- UART9_IRQn = 88, /*!< UART9 global Interrupt */
- UART10_IRQn = 89, /*!< UART10 global Interrupt */
- QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
- FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
- FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
- LPTIM1_IRQn = 97, /*!< LP TIM1 interrupt */
- DFSDM2_FLT0_IRQn = 98, /*!< DFSDM2 Filter 0 global Interrupt */
- DFSDM2_FLT1_IRQn = 99, /*!< DFSDM2 Filter 1 global Interrupt */
- DFSDM2_FLT2_IRQn = 100, /*!< DFSDM2 Filter 2 global Interrupt */
- DFSDM2_FLT3_IRQn = 101 /*!< DFSDM2 Filter 3 global Interrupt */
-#endif /* STM32F413_423xx */
-} IRQn_Type;
-
-/**
- * @}
- */
-
-#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include
-
-/** @addtogroup Exported_types
- * @{
- */
-/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
-typedef int32_t s32;
-typedef int16_t s16;
-typedef int8_t s8;
-
-typedef const int32_t sc32; /*!< Read Only */
-typedef const int16_t sc16; /*!< Read Only */
-typedef const int8_t sc8; /*!< Read Only */
-
-typedef __IO int32_t vs32;
-typedef __IO int16_t vs16;
-typedef __IO int8_t vs8;
-
-typedef __I int32_t vsc32; /*!< Read Only */
-typedef __I int16_t vsc16; /*!< Read Only */
-typedef __I int8_t vsc8; /*!< Read Only */
-
-typedef uint32_t u32;
-typedef uint16_t u16;
-typedef uint8_t u8;
-
-typedef const uint32_t uc32; /*!< Read Only */
-typedef const uint16_t uc16; /*!< Read Only */
-typedef const uint8_t uc8; /*!< Read Only */
-
-typedef __IO uint32_t vu32;
-typedef __IO uint16_t vu16;
-typedef __IO uint8_t vu8;
-
-typedef __I uint32_t vuc32; /*!< Read Only */
-typedef __I uint16_t vuc16; /*!< Read Only */
-typedef __I uint8_t vuc8; /*!< Read Only */
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Analog to Digital Converter
- */
-
-typedef struct
-{
- __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
- __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
- __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
- __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
- __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
- __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
- __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
- __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
- __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
- __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
- __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
- __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
- __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
- __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
- __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38 */
- __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
- __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
- __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
- __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
- __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
- __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
- __IO uint32_t CDR; /*!< ADC common regular data register for dual
- AND triple modes, Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/**
- * @brief Controller Area Network TxMailBox
- */
-
-typedef struct
-{
- __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
- __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
- __IO uint32_t TDLR; /*!< CAN mailbox data low register */
- __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FIFOMailBox
- */
-
-typedef struct
-{
- __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
- __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
- __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
- __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FilterRegister
- */
-
-typedef struct
-{
- __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
- __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/**
- * @brief Controller Area Network
- */
-
-typedef struct
-{
- __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
- __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
- __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
- __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
- __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
- __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
- __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
- __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
- uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
- CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
- CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
- uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
- __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
- __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
- uint32_t RESERVED2; /*!< Reserved, 0x208 */
- __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
- uint32_t RESERVED3; /*!< Reserved, 0x210 */
- __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
- uint32_t RESERVED4; /*!< Reserved, 0x218 */
- __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
- uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
- CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
-} CAN_TypeDef;
-
-#if defined(STM32F446xx)
-/**
- * @brief Consumer Electronics Control
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
- __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
- __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
- __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
- __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
- __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
-}CEC_TypeDef;
-#endif /* STM32F446xx */
-
-/**
- * @brief CRC calculation unit
- */
-
-typedef struct
-{
- __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
- __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
- uint8_t RESERVED0; /*!< Reserved, 0x05 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
-} CRC_TypeDef;
-
-/**
- * @brief Digital to Analog Converter
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
- __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
- __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
- __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
- __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
- __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
- __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
- __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
- __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
- __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
- __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
- __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
- __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
- __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
-} DAC_TypeDef;
-
-#if defined(STM32F412xG) || defined(STM32F413_423xx)
-/**
- * @brief DFSDM module registers
- */
-typedef struct
-{
- __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
- __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
- __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
- __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
- __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
- __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
- __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
- __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
- __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
- __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
- __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
- __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
- __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
- __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
- __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
-} DFSDM_Filter_TypeDef;
-
-/**
- * @brief DFSDM channel configuration registers
- */
-typedef struct
-{
- __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
- __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
- __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
- short circuit detector register, Address offset: 0x08 */
- __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
- __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
-} DFSDM_Channel_TypeDef;
-
-/* Legacy Defines */
-#define DFSDM_TypeDef DFSDM_Filter_TypeDef
-#endif /* STM32F412xG || STM32F413_423xx */
-/**
- * @brief Debug MCU
- */
-
-typedef struct
-{
- __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
- __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
- __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
- __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/**
- * @brief DCMI
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
- __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
- __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
- __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
- __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
- __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
- __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
- __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
- __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
- __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
- __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/**
- * @brief DMA Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DMA stream x configuration register */
- __IO uint32_t NDTR; /*!< DMA stream x number of data register */
- __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
- __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
- __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
- __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
- __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
- __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
- __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
- __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-/**
- * @brief DMA2D Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
- __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
- __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
- __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
- __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
- __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
- __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
- __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
- __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
- __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
- __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
- __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
- __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
- __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
- __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
- __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
- __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
- __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
- __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
- __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
- uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
- __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
- __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
-} DMA2D_TypeDef;
-
-#if defined(STM32F469_479xx)
-/**
- * @brief DSI Controller
- */
-
-typedef struct
-{
- __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
- __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
- __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
- __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
- __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
- __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
- __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
- uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
- __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
- __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
- __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
- __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
- __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
- __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
- __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
- __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
- __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
- __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
- __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
- __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
- __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
- __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
- __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
- __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
- __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
- __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
- __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
- __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
- __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
- __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
- __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
- __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
- __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
- __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
- __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
- __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
- __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
- uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
- __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
- __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
- uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
- __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
- uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */
- __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
- uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */
- __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
- __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
- uint32_t RESERVED5; /*!< Reserved, 0x114 */
- __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
- uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
- __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
- __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
- __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
- __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
- __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
- __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
- __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
- __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
- __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
- __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
- __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
- uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */
- __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
- uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */
- __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
- __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
- __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
- __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
- __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
- uint32_t RESERVED9; /*!< Reserved, 0x414 */
- __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
- uint32_t RESERVED10; /*!< Reserved, 0x42C */
- __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
-} DSI_TypeDef;
-#endif /* STM32F469_479xx */
-
-/**
- * @brief Ethernet MAC
- */
-
-typedef struct
-{
- __IO uint32_t MACCR;
- __IO uint32_t MACFFR;
- __IO uint32_t MACHTHR;
- __IO uint32_t MACHTLR;
- __IO uint32_t MACMIIAR;
- __IO uint32_t MACMIIDR;
- __IO uint32_t MACFCR;
- __IO uint32_t MACVLANTR; /* 8 */
- uint32_t RESERVED0[2];
- __IO uint32_t MACRWUFFR; /* 11 */
- __IO uint32_t MACPMTCSR;
- uint32_t RESERVED1[2];
- __IO uint32_t MACSR; /* 15 */
- __IO uint32_t MACIMR;
- __IO uint32_t MACA0HR;
- __IO uint32_t MACA0LR;
- __IO uint32_t MACA1HR;
- __IO uint32_t MACA1LR;
- __IO uint32_t MACA2HR;
- __IO uint32_t MACA2LR;
- __IO uint32_t MACA3HR;
- __IO uint32_t MACA3LR; /* 24 */
- uint32_t RESERVED2[40];
- __IO uint32_t MMCCR; /* 65 */
- __IO uint32_t MMCRIR;
- __IO uint32_t MMCTIR;
- __IO uint32_t MMCRIMR;
- __IO uint32_t MMCTIMR; /* 69 */
- uint32_t RESERVED3[14];
- __IO uint32_t MMCTGFSCCR; /* 84 */
- __IO uint32_t MMCTGFMSCCR;
- uint32_t RESERVED4[5];
- __IO uint32_t MMCTGFCR;
- uint32_t RESERVED5[10];
- __IO uint32_t MMCRFCECR;
- __IO uint32_t MMCRFAECR;
- uint32_t RESERVED6[10];
- __IO uint32_t MMCRGUFCR;
- uint32_t RESERVED7[334];
- __IO uint32_t PTPTSCR;
- __IO uint32_t PTPSSIR;
- __IO uint32_t PTPTSHR;
- __IO uint32_t PTPTSLR;
- __IO uint32_t PTPTSHUR;
- __IO uint32_t PTPTSLUR;
- __IO uint32_t PTPTSAR;
- __IO uint32_t PTPTTHR;
- __IO uint32_t PTPTTLR;
- __IO uint32_t RESERVED8;
- __IO uint32_t PTPTSSR;
- uint32_t RESERVED9[565];
- __IO uint32_t DMABMR;
- __IO uint32_t DMATPDR;
- __IO uint32_t DMARPDR;
- __IO uint32_t DMARDLAR;
- __IO uint32_t DMATDLAR;
- __IO uint32_t DMASR;
- __IO uint32_t DMAOMR;
- __IO uint32_t DMAIER;
- __IO uint32_t DMAMFBOCR;
- __IO uint32_t DMARSWTR;
- uint32_t RESERVED10[8];
- __IO uint32_t DMACHTDR;
- __IO uint32_t DMACHRDR;
- __IO uint32_t DMACHTBAR;
- __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/**
- * @brief External Interrupt/Event Controller
- */
-
-typedef struct
-{
- __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
- __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
- __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
- __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
- __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
- __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/**
- * @brief FLASH Registers
- */
-
-typedef struct
-{
- __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
- __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
- __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
- __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
- __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
- __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
- __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
-/**
- * @brief Flexible Static Memory Controller
- */
-
-typedef struct
-{
- __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
-} FSMC_Bank1_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank1E
- */
-
-typedef struct
-{
- __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FSMC_Bank1E_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank2
- */
-
-typedef struct
-{
- __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
- __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
- __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
- __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
- uint32_t RESERVED0; /*!< Reserved, 0x70 */
- __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
-} FSMC_Bank2_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank3
- */
-
-typedef struct
-{
- __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
- __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
- __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
- __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
- uint32_t RESERVED0; /*!< Reserved, 0x90 */
- __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
-} FSMC_Bank3_TypeDef;
-
-/**
- * @brief Flexible Static Memory Controller Bank4
- */
-
-typedef struct
-{
- __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
- __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
- __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
- __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
- __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
-} FSMC_Bank4_TypeDef;
-#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-/**
- * @brief Flexible Memory Controller
- */
-
-typedef struct
-{
- __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
-} FMC_Bank1_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank1E
- */
-
-typedef struct
-{
- __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FMC_Bank1E_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank2
- */
-
-typedef struct
-{
- __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
- __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
- __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
- __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
- uint32_t RESERVED0; /*!< Reserved, 0x70 */
- __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
-} FMC_Bank2_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank3
- */
-
-typedef struct
-{
- __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
- __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
- __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
- __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
- uint32_t RESERVED0; /*!< Reserved, 0x90 */
- __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
-} FMC_Bank3_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank4
- */
-
-typedef struct
-{
- __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
- __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
- __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
- __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
- __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
-} FMC_Bank4_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank5_6
- */
-
-typedef struct
-{
- __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
- __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
- __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
- __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
- __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
-} FMC_Bank5_6_TypeDef;
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-/**
- * @brief General Purpose I/O
- */
-
-typedef struct
-{
- __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
- __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
- __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
- __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
- __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
- __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
- __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
- __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/**
- * @brief System configuration controller
- */
-
-typedef struct
-{
- __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
- __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-#if defined (STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
- uint32_t RESERVED; /*!< Reserved, 0x18 */
- __IO uint32_t CFGR2; /*!< Reserved, 0x1C */
- __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
- uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
- __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
-#else /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx || STM32F469_479xx */
- uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
- __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
-#endif /* STM32F410xx || defined(STM32F412xG) || defined(STM32F413_423xx) */
-#if defined(STM32F413_423xx)
- __IO uint32_t MCHDLYCR; /*!< SYSCFG multi-channel delay register, Address offset: 0x30 */
-#endif /* STM32F413_423xx */
-} SYSCFG_TypeDef;
-
-/**
- * @brief Inter-integrated Circuit Interface
- */
-
-typedef struct
-{
- __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
- __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
- uint16_t RESERVED7; /*!< Reserved, 0x1E */
- __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
- uint16_t RESERVED8; /*!< Reserved, 0x22 */
- __IO uint16_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
- uint16_t RESERVED9; /*!< Reserved, 0x26 */
-} I2C_TypeDef;
-
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-/**
- * @brief Inter-integrated Circuit Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
- __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
- __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
- __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
- __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
- __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
- __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
- __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
- __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
- __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
-}FMPI2C_TypeDef;
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
-
-/**
- * @brief Independent WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
- __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
- __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
- __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/**
- * @brief LCD-TFT Display Controller
- */
-
-typedef struct
-{
- uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
- __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
- __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
- __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
- __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
- __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
- uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
- __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
- uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
- __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
- uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
- __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
- __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
- __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
- __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
- __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
- __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
-} LTDC_TypeDef;
-
-/**
- * @brief LCD-TFT Display layer x Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
- __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
- __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
- __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
- __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
- __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
- __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
- __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
- uint32_t RESERVED0[2]; /*!< Reserved */
- __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
- __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
- __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
- uint32_t RESERVED1[3]; /*!< Reserved */
- __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
-
-} LTDC_Layer_TypeDef;
-
-/**
- * @brief Power Control
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
- __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/**
- * @brief Reset and Clock Control
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
- __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
- __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
- __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
- __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
- __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
- __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
- uint32_t RESERVED0; /*!< Reserved, 0x1C */
- __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
- __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
- uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
- __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
- __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
- __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
- uint32_t RESERVED2; /*!< Reserved, 0x3C */
- __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
- __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
- uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
- __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
- __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
- __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
- uint32_t RESERVED4; /*!< Reserved, 0x5C */
- __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
- __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
- uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
- __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
- __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
- uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
- __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
- __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
- __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
- __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
- __IO uint32_t CKGATENR; /*!< RCC Clocks Gated Enable Register, Address offset: 0x90 */ /* Only for STM32F412xG, STM32413_423xx and STM32F446xx devices */
- __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */ /* Only for STM32F410xx, STM32F412xG, STM32413_423xx and STM32F446xx devices */
-
-} RCC_TypeDef;
-
-/**
- * @brief Real-Time Clock
- */
-
-typedef struct
-{
- __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
- __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
- __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
- __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
- __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
- __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
- __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
- __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
- __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
- __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
- __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
- __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
- __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
- __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
- __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
- __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
- __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
- __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
- uint32_t RESERVED7; /*!< Reserved, 0x4C */
- __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
- __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
- __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
- __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
- __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
- __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
- __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
- __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
- __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
- __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
- __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
- __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
- __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
- __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
- __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
- __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
- __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
- __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
- __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
- __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
-} RTC_TypeDef;
-
-
-/**
- * @brief Serial Audio Interface
- */
-
-typedef struct
-{
- __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
-} SAI_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
- __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
- __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
- __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
- __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
- __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
- __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
- __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
-} SAI_Block_TypeDef;
-
-/**
- * @brief SD host Interface
- */
-
-typedef struct
-{
- __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
- __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
- __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
- __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
- __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
- __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
- __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
- __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
- __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
- __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
- __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
- __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
- __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
- __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
- __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
- __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
- uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
- __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
- uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
- __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/**
- * @brief Serial Peripheral Interface
- */
-
-typedef struct
-{
- __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
- __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
- uint16_t RESERVED7; /*!< Reserved, 0x1E */
- __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
- uint16_t RESERVED8; /*!< Reserved, 0x22 */
-} SPI_TypeDef;
-
-#if defined(STM32F446xx)
-/**
- * @brief SPDIFRX Interface
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
- __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
- uint16_t RESERVED0; /*!< Reserved, 0x06 */
- __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
- __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
- uint16_t RESERVED1; /*!< Reserved, 0x0E */
- __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
- __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
- __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
- uint16_t RESERVED2; /*!< Reserved, 0x1A */
-} SPDIFRX_TypeDef;
-#endif /* STM32F446xx */
-
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-/**
- * @brief QUAD Serial Peripheral Interface
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
- __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
- __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
- __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
- __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
- __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
- __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
- __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
- __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
- __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
- __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
- __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
-} QUADSPI_TypeDef;
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F446xx)
-/**
- * @brief SPDIF-RX Interface
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
- __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
- uint16_t RESERVED0; /*!< Reserved, 0x06 */
- __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
- __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
- uint16_t RESERVED1; /*!< Reserved, 0x0E */
- __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
- __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
- __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
- uint16_t RESERVED2; /*!< Reserved, 0x1A */
-} SPDIF_TypeDef;
-#endif /* STM32F446xx */
-
-/**
- * @brief TIM
- */
-
-typedef struct
-{
- __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
- __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
- uint16_t RESERVED7; /*!< Reserved, 0x1E */
- __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
- uint16_t RESERVED8; /*!< Reserved, 0x22 */
- __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
- __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
- uint16_t RESERVED9; /*!< Reserved, 0x2A */
- __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
- __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
- uint16_t RESERVED10; /*!< Reserved, 0x32 */
- __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
- __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
- __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
- __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
- __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
- uint16_t RESERVED11; /*!< Reserved, 0x46 */
- __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
- uint16_t RESERVED12; /*!< Reserved, 0x4A */
- __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
- uint16_t RESERVED13; /*!< Reserved, 0x4E */
- __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
- uint16_t RESERVED14; /*!< Reserved, 0x52 */
-} TIM_TypeDef;
-
-/**
- * @brief Universal Synchronous Asynchronous Receiver Transmitter
- */
-
-typedef struct
-{
- __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
-} USART_TypeDef;
-
-/**
- * @brief Window WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
- __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/**
- * @brief Crypto Processor
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
- __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
- __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
- __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
- __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
- __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
- __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
- __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
- __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
- __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
- __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
- __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
- __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
- __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
- __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
- __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
- __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
- __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
- __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
- __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
- __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
- __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
- __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
- __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
- __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
- __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
- __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
- __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
- __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
- __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
- __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
- __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
- __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
- __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
- __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
- __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
-} CRYP_TypeDef;
-
-/**
- * @brief HASH
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
- __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
- __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
- __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
- __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
- __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
- uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
- __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
-} HASH_TypeDef;
-
-/**
- * @brief HASH_DIGEST
- */
-
-typedef struct
-{
- __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
-} HASH_DIGEST_TypeDef;
-
-/**
- * @brief RNG
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
- __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
- __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
-} RNG_TypeDef;
-
-#if defined(STM32F410xx) || defined(STM32F413_423xx)
-/**
- * @brief LPTIMER
- */
-typedef struct
-{
- __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
- __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
- __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
- __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
- __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
- __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
- __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
- __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
- __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
-} LPTIM_TypeDef;
-#endif /* STM32F410xx || STM32F413_423xx */
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_memory_map
- * @{
- */
-
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
-#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
-#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
-#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
-#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
-#elif defined(STM32F469_479xx)
-#define SRAM2_BASE ((uint32_t)0x20028000) /*!< SRAM2(16 KB) base address in the alias region */
-#define SRAM3_BASE ((uint32_t)0x20030000) /*!< SRAM3(64 KB) base address in the alias region */
-#elif defined(STM32F413_423xx)
-#define SRAM2_BASE ((uint32_t)0x20040000) /*!< SRAM2(16 KB) base address in the alias region */
-#else /* STM32F411xE || STM32F410xx || STM32F412xG */
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-#if defined (STM32F40_41xxx) || (STM32F427_437xx) || (STM32F429_439xx) || (STM32F410xx) || (STM32F412xG) || (STM32F413_423xx) || (STM32F446xx) || (STM32F469_479xx)
-#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
-#endif /* STM32F40_41xxx || (STM32F427_437xx || STM32F429_439xx || STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
-#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
-#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< QuadSPI registers base address */
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
-
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
-#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
-#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
-#define SRAM3_BB_BASE ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */
-#elif defined(STM32F469_479xx)
-#define SRAM2_BB_BASE ((uint32_t)0x22500000) /*!< SRAM2(16 KB) base address in the bit-band region */
-#define SRAM3_BB_BASE ((uint32_t)0x22600000) /*!< SRAM3(64 KB) base address in the bit-band region */
-#elif defined(STM32F413_423xx)
-#define SRAM2_BB_BASE ((uint32_t)0x22800000) /*!< SRAM2(64 KB) base address in the bit-band region */
-#else /* STM32F411xE || STM32F410xx || STM32F412xG */
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
-
-/* Legacy defines */
-#define SRAM_BASE SRAM1_BASE
-#define SRAM_BB_BASE SRAM1_BB_BASE
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
-#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
-#if defined(STM32F410xx) || defined(STM32F413_423xx)
-#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400)
-#endif /* STM32F410xx || STM32F413_423xx */
-#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
-#if defined(STM32F446xx)
-#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000)
-#endif /* STM32F446xx */
-#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000)
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
-#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
-#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
-#if defined(STM32F413_423xx)
-#define CAN3_BASE (APB1PERIPH_BASE + 0x6C00)
-#endif /* STM32F413_423xx */
-#if defined(STM32F446xx)
-#define CEC_BASE (APB1PERIPH_BASE + 0x6C00)
-#endif /* STM32F446xx */
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
-#define UART7_BASE (APB1PERIPH_BASE + 0x7800)
-#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
-#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
-#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
-#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
-#define UART9_BASE (APB2PERIPH_BASE + 0x1800U)
-#define UART10_BASE (APB2PERIPH_BASE + 0x1C00U)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
-#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
-#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
-#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
-#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
-#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
-#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
-#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
-#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
-#define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
-#define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
-#define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
-#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
-#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
-#if defined(STM32F446xx)
-#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00)
-#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
-#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
-#endif /* STM32F446xx */
-#define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
-#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
-#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
-#if defined(STM32F469_479xx)
-#define DSI_BASE (APB2PERIPH_BASE + 0x6C00)
-#endif /* STM32F469_479xx */
-#if defined(STM32F412xG) || defined(STM32F413_423xx)
-#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000)
-#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
-#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
-#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40)
-#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60)
-#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100)
-#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180)
-#define DFSDM1_0 ((DFSDM_TypeDef *) DFSDM1_Filter0_BASE)
-#define DFSDM1_1 ((DFSDM_TypeDef *) DFSDM1_Filter1_BASE)
-/* Legacy Defines */
-#define DFSDM0 DFSDM1_0
-#define DFSDM1 DFSDM1_1
-#if defined(STM32F413_423xx)
-#define DFSDM2_BASE (APB2PERIPH_BASE + 0x6400U)
-#define DFSDM2_Channel0_BASE (DFSDM2_BASE + 0x00U)
-#define DFSDM2_Channel1_BASE (DFSDM2_BASE + 0x20U)
-#define DFSDM2_Channel2_BASE (DFSDM2_BASE + 0x40U)
-#define DFSDM2_Channel3_BASE (DFSDM2_BASE + 0x60U)
-#define DFSDM2_Channel4_BASE (DFSDM2_BASE + 0x80U)
-#define DFSDM2_Channel5_BASE (DFSDM2_BASE + 0xA0U)
-#define DFSDM2_Channel6_BASE (DFSDM2_BASE + 0xC0U)
-#define DFSDM2_Channel7_BASE (DFSDM2_BASE + 0xE0U)
-#define DFSDM2_Filter0_BASE (DFSDM2_BASE + 0x100U)
-#define DFSDM2_Filter1_BASE (DFSDM2_BASE + 0x180U)
-#define DFSDM2_Filter2_BASE (DFSDM2_BASE + 0x200U)
-#define DFSDM2_Filter3_BASE (DFSDM2_BASE + 0x280U)
-#define DFSDM2_0 ((DFSDM_TypeDef *) DFSDM2_Filter0_BASE)
-#define DFSDM2_1 ((DFSDM_TypeDef *) DFSDM2_Filter1_BASE)
-#define DFSDM2_2 ((DFSDM_TypeDef *) DFSDM2_Filter2_BASE)
-#define DFSDM2_3 ((DFSDM_TypeDef *) DFSDM2_Filter3_BASE)
-#endif /* STM32F413_423xx */
-#endif /* STM32F412xG || STM32F413_423xx */
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
-#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
-#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
-#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
-#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
-#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
-#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
-#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
-#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
-#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
-#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
-#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
-#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
-#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
-#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
-#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
-#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
-#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
-#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
-#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
-#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
-#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
-#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
-#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
-#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
-#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
-#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
-#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
-#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
-#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
-#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
-#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
-#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
-#define ETH_MAC_BASE (ETH_BASE)
-#define ETH_MMC_BASE (ETH_BASE + 0x0100)
-#define ETH_PTP_BASE (ETH_BASE + 0x0700)
-#define ETH_DMA_BASE (ETH_BASE + 0x1000)
-#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)
-
-/*!< AHB2 peripherals */
-#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
-#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
-#define HASH_BASE (AHB2PERIPH_BASE + 0x60400)
-#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710)
-#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
-
-#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
-/*!< FSMC Bankx registers base address */
-#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
-#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
-#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
-#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
-#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
-#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-/*!< FMC Bankx registers base address */
-#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
-#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
-#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)
-#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
-#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
-#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE ((uint32_t )0xE0042000)
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_declaration
- * @{
- */
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#if defined(STM32F446xx)
-#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
-#endif /* STM32F446xx */
-#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define UART4 ((USART_TypeDef *) UART4_BASE)
-#define UART5 ((USART_TypeDef *) UART5_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
-#if defined(STM32F410xx) || defined(STM32F413_423xx)
-#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
-#endif /* STM32F410xx || STM32F413_423xx */
-#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
-#if defined(STM32F413_423xx)
-#define CAN3 ((CAN_TypeDef *) CAN3_BASE)
-#endif /* STM32F413_423xx */
-#if defined(STM32F446xx)
-#define CEC ((CEC_TypeDef *) CEC_BASE)
-#endif /* STM32F446xx */
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define UART7 ((USART_TypeDef *) UART7_BASE)
-#define UART8 ((USART_TypeDef *) UART8_BASE)
-#define UART9 ((USART_TypeDef *) UART9_BASE)
-#define UART10 ((USART_TypeDef *) UART10_BASE)
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define USART6 ((USART_TypeDef *) USART6_BASE)
-#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
-#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
-#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
-#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
-#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
-#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
-#if defined(STM32F446xx)
-#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
-#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
-#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
-#endif /* STM32F446xx */
-#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
-#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
-#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
-#if defined(STM32F469_479xx)
-#define DSI ((DSI_TypeDef *)DSI_BASE)
-#endif /* STM32F469_479xx */
-#if defined(STM32F412xG) || defined(STM32F413_423xx)
-#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
-#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
-#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
-#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
-#define DFSDM1_Filter0 ((DFSDM_TypeDef *) DFSDM_Filter0_BASE)
-#define DFSDM1_Filter1 ((DFSDM_TypeDef *) DFSDM_Filter1_BASE)
-#if defined(STM32F413_423xx)
-#define DFSDM2_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)
-#define DFSDM2_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)
-#define DFSDM2_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel2_BASE)
-#define DFSDM2_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel3_BASE)
-#define DFSDM2_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel4_BASE)
-#define DFSDM2_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel5_BASE)
-#define DFSDM2_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel6_BASE)
-#define DFSDM2_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel7_BASE)
-#define DFSDM2_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter0_BASE)
-#define DFSDM2_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter1_BASE)
-#define DFSDM2_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter2_BASE)
-#define DFSDM2_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter3_BASE)
-#endif /* STM32F413_423xx */
-#endif /* STM32F412xG || STM32F413_423xx */
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
-#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
-#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define ETH ((ETH_TypeDef *) ETH_BASE)
-#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
-#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
-#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
-#define HASH ((HASH_TypeDef *) HASH_BASE)
-#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
-#define RNG ((RNG_TypeDef *) RNG_BASE)
-
-#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
-#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
-#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
-#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
-#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
-#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
-#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
-#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
-#define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
-#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
-#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
-#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_constants
- * @{
- */
-
- /** @addtogroup Peripheral_Registers_Bits_Definition
- * @{
- */
-
-/******************************************************************************/
-/* Peripheral Registers_Bits_Definition */
-/******************************************************************************/
-
-/******************************************************************************/
-/* */
-/* Analog to Digital Converter */
-/* */
-/******************************************************************************/
-/******************** Bit definition for ADC_SR register ********************/
-#define ADC_SR_AWD ((uint8_t)0x01) /*!CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- #endif
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x24003010;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-
-#if defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM)
- SystemInit_ExtMemCtl();
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
- /* Configure the System clock source, PLL Multiplier and Divider factors,
- AHB/APBx prescalers and Flash settings ----------------------------------*/
- SetSysClock();
-
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
- * 16 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
- * 25 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate(void)
-{
- uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
- uint32_t pllr = 2;
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock source */
- SystemCoreClock = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock source */
- SystemCoreClock = HSE_VALUE;
- break;
- case 0x08: /* PLL P used as system clock source */
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
- SYSCLK = PLL_VCO / PLL_P
- */
- pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
- if (pllsource != 0)
- {
- /* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
- else
- {
- /* HSI used as PLL clock source */
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
-#elif defined(STM32F410xx) || defined(STM32F411xE)
-#if defined(USE_HSE_BYPASS)
- if (pllsource != 0)
- {
- /* HSE used as PLL clock source */
- pllvco = (HSE_BYPASS_INPUT_FREQUENCY / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
-#else
- if (pllsource == 0)
- {
- /* HSI used as PLL clock source */
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
-#endif /* USE_HSE_BYPASS */
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
- pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
- SystemCoreClock = pllvco/pllp;
- break;
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
- case 0x0C: /* PLL R used as system clock source */
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
- SYSCLK = PLL_VCO / PLL_R
- */
- pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
- if (pllsource != 0)
- {
- /* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
- else
- {
- /* HSI used as PLL clock source */
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
-
- pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >>28) + 1 ) *2;
- SystemCoreClock = pllvco/pllr;
- break;
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
- default:
- SystemCoreClock = HSI_VALUE;
- break;
- }
- /* Compute HCLK frequency --------------------------------------------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @brief Configures the System clock source, PLL Multiplier and Divider factors,
- * AHB/APBx prescalers and Flash settings
- * @Note This function should be called only once the RCC clock configuration
- * is reset to the default reset state (done in SystemInit() function).
- * @param None
- * @retval None
- */
-static void SetSysClock(void)
-{
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)|| defined(STM32F469_479xx)
-/******************************************************************************/
-/* PLL (clocked by HSE) used as System clock source */
-/******************************************************************************/
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Select regulator voltage output Scale 1 mode */
- RCC->APB1ENR |= RCC_APB1ENR_PWREN;
- PWR->CR |= PWR_CR_VOS;
-
- /* HCLK = SYSCLK / 1*/
- RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
-
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
- /* PCLK2 = HCLK / 2*/
- RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
-
- /* PCLK1 = HCLK / 4*/
- RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
-#endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx || STM32F412xG || STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F401xx) || defined(STM32F413_423xx)
- /* PCLK2 = HCLK / 1*/
- RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK / 2*/
- RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
-#endif /* STM32F401xx || STM32F413_423xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F469_479xx)
- /* Configure the main PLL */
- RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
- (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
-#endif /* STM32F40_41xxx || STM32F401xx || STM32F427_437x || STM32F429_439xx || STM32F469_479xx */
-
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
- /* Configure the main PLL */
- RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
- (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24) | (PLL_R << 28);
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
-
- /* Enable the main PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till the main PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
- /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
- PWR->CR |= PWR_CR_ODEN;
- while((PWR->CSR & PWR_CSR_ODRDY) == 0)
- {
- }
- PWR->CR |= PWR_CR_ODSWEN;
- while((PWR->CSR & PWR_CSR_ODSWRDY) == 0)
- {
- }
- /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
- FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
-#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F40_41xxx) || defined(STM32F412xG)
- /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
- FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
-#endif /* STM32F40_41xxx || STM32F412xG */
-
-#if defined(STM32F413_423xx)
- /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
- FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS;
-#endif /* STM32F413_423xx */
-
-#if defined(STM32F401xx)
- /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
- FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
-#endif /* STM32F401xx */
-
- /* Select the main PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= RCC_CFGR_SW_PLL;
-
- /* Wait till the main PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-#elif defined(STM32F410xx) || defined(STM32F411xE)
-#if defined(USE_HSE_BYPASS)
-/******************************************************************************/
-/* PLL (clocked by HSE) used as System clock source */
-/******************************************************************************/
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* Enable HSE and HSE BYPASS */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON | RCC_CR_HSEBYP);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Select regulator voltage output Scale 1 mode */
- RCC->APB1ENR |= RCC_APB1ENR_PWREN;
- PWR->CR |= PWR_CR_VOS;
-
- /* HCLK = SYSCLK / 1*/
- RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK / 2*/
- RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK / 4*/
- RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
-
- /* Configure the main PLL */
- RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
- (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
-
- /* Enable the main PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till the main PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
- FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS;
-
- /* Select the main PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= RCC_CFGR_SW_PLL;
-
- /* Wait till the main PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-#else /* HSI will be used as PLL clock source */
- /* Select regulator voltage output Scale 1 mode */
- RCC->APB1ENR |= RCC_APB1ENR_PWREN;
- PWR->CR |= PWR_CR_VOS;
-
- /* HCLK = SYSCLK / 1*/
- RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK / 2*/
- RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK / 4*/
- RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
-
- /* Configure the main PLL */
- RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (PLL_Q << 24);
-
- /* Enable the main PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till the main PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
- FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS;
-
- /* Select the main PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= RCC_CFGR_SW_PLL;
-
- /* Wait till the main PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
- {
- }
-#endif /* USE_HSE_BYPASS */
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F469_479xx */
-}
-#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F469xx) || defined(STM32F479xx)
-/**
- * @brief Setup the external memory controller.
- * Called in startup_stm32f4xx.s before jump to main.
- * This function configures the external memories (SRAM/SDRAM)
- * This SRAM/SDRAM will be used as program data memory (including heap and stack).
- * @param None
- * @retval None
- */
-void SystemInit_ExtMemCtl(void)
-{
- __IO uint32_t tmp = 0x00;
-
- register uint32_t tmpreg = 0, timeout = 0xFFFF;
- register uint32_t index;
-
- /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
- RCC->AHB1ENR |= 0x000001F8;
-
- /* Delay after an RCC peripheral clock enabling */
- tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
-
- /* Connect PDx pins to FMC Alternate function */
- GPIOD->AFR[0] = 0x00CCC0CC;
- GPIOD->AFR[1] = 0xCCCCCCCC;
- /* Configure PDx pins in Alternate function mode */
- GPIOD->MODER = 0xAAAA0A8A;
- /* Configure PDx pins speed to 100 MHz */
- GPIOD->OSPEEDR = 0xFFFF0FCF;
- /* Configure PDx pins Output type to push-pull */
- GPIOD->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PDx pins */
- GPIOD->PUPDR = 0x00000000;
-
- /* Connect PEx pins to FMC Alternate function */
- GPIOE->AFR[0] = 0xC00CC0CC;
- GPIOE->AFR[1] = 0xCCCCCCCC;
- /* Configure PEx pins in Alternate function mode */
- GPIOE->MODER = 0xAAAA828A;
- /* Configure PEx pins speed to 100 MHz */
- GPIOE->OSPEEDR = 0xFFFFC3CF;
- /* Configure PEx pins Output type to push-pull */
- GPIOE->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PEx pins */
- GPIOE->PUPDR = 0x00000000;
-
- /* Connect PFx pins to FMC Alternate function */
- GPIOF->AFR[0] = 0xCCCCCCCC;
- GPIOF->AFR[1] = 0xCCCCCCCC;
- /* Configure PFx pins in Alternate function mode */
- GPIOF->MODER = 0xAA800AAA;
- /* Configure PFx pins speed to 50 MHz */
- GPIOF->OSPEEDR = 0xAA800AAA;
- /* Configure PFx pins Output type to push-pull */
- GPIOF->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PFx pins */
- GPIOF->PUPDR = 0x00000000;
-
- /* Connect PGx pins to FMC Alternate function */
- GPIOG->AFR[0] = 0xCCCCCCCC;
- GPIOG->AFR[1] = 0xCCCCCCCC;
- /* Configure PGx pins in Alternate function mode */
- GPIOG->MODER = 0xAAAAAAAA;
- /* Configure PGx pins speed to 50 MHz */
- GPIOG->OSPEEDR = 0xAAAAAAAA;
- /* Configure PGx pins Output type to push-pull */
- GPIOG->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PGx pins */
- GPIOG->PUPDR = 0x00000000;
-
- /* Connect PHx pins to FMC Alternate function */
- GPIOH->AFR[0] = 0x00C0CC00;
- GPIOH->AFR[1] = 0xCCCCCCCC;
- /* Configure PHx pins in Alternate function mode */
- GPIOH->MODER = 0xAAAA08A0;
- /* Configure PHx pins speed to 50 MHz */
- GPIOH->OSPEEDR = 0xAAAA08A0;
- /* Configure PHx pins Output type to push-pull */
- GPIOH->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PHx pins */
- GPIOH->PUPDR = 0x00000000;
-
- /* Connect PIx pins to FMC Alternate function */
- GPIOI->AFR[0] = 0xCCCCCCCC;
- GPIOI->AFR[1] = 0x00000CC0;
- /* Configure PIx pins in Alternate function mode */
- GPIOI->MODER = 0x0028AAAA;
- /* Configure PIx pins speed to 50 MHz */
- GPIOI->OSPEEDR = 0x0028AAAA;
- /* Configure PIx pins Output type to push-pull */
- GPIOI->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PIx pins */
- GPIOI->PUPDR = 0x00000000;
-
-/*-- FMC Configuration -------------------------------------------------------*/
- /* Enable the FMC interface clock */
- RCC->AHB3ENR |= 0x00000001;
- /* Delay after an RCC peripheral clock enabling */
- tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
- FMC_Bank5_6->SDCR[0] = 0x000019E4;
- FMC_Bank5_6->SDTR[0] = 0x01115351;
-
- /* SDRAM initialization sequence */
- /* Clock enable command */
- FMC_Bank5_6->SDCMR = 0x00000011;
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- while((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* Delay */
- for (index = 0; index<1000; index++);
-
- /* PALL command */
- FMC_Bank5_6->SDCMR = 0x00000012;
- timeout = 0xFFFF;
- while((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* Auto refresh command */
- FMC_Bank5_6->SDCMR = 0x00000073;
- timeout = 0xFFFF;
- while((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* MRD register program */
- FMC_Bank5_6->SDCMR = 0x00046014;
- timeout = 0xFFFF;
- while((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* Set refresh count */
- tmpreg = FMC_Bank5_6->SDRTR;
- FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
-
- /* Disable write protection */
- tmpreg = FMC_Bank5_6->SDCR[0];
- FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
- /* Configure and enable Bank1_SRAM2 */
- FMC_Bank1->BTCR[2] = 0x00001011;
- FMC_Bank1->BTCR[3] = 0x00000201;
- FMC_Bank1E->BWTR[2] = 0x0fffffff;
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-#if defined(STM32F469xx) || defined(STM32F479xx)
- /* Configure and enable Bank1_SRAM2 */
- FMC_Bank1->BTCR[2] = 0x00001091;
- FMC_Bank1->BTCR[3] = 0x00110212;
- FMC_Bank1E->BWTR[2] = 0x0fffffff;
-#endif /* STM32F469xx || STM32F479xx */
-
- (void)(tmp);
-}
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-#elif defined (DATA_IN_ExtSRAM)
-/**
- * @brief Setup the external memory controller. Called in startup_stm32f4xx.s
- * before jump to __main
- * @param None
- * @retval None
- */
-/**
- * @brief Setup the external memory controller.
- * Called in startup_stm32f4xx.s before jump to main.
- * This function configures the external SRAM mounted on STM324xG_EVAL/STM324x7I boards
- * This SRAM will be used as program data memory (including heap and stack).
- * @param None
- * @retval None
- */
-void SystemInit_ExtMemCtl(void)
-{
-/*-- GPIOs Configuration -----------------------------------------------------*/
-/*
- +-------------------+--------------------+------------------+--------------+
- + SRAM pins assignment +
- +-------------------+--------------------+------------------+--------------+
- | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 |
- | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 |
- | PD4 <-> FMC_NOE | PE3 <-> FMC_A19 | PF2 <-> FMC_A2 | PG2 <-> FMC_A12 |
- | PD5 <-> FMC_NWE | PE4 <-> FMC_A20 | PF3 <-> FMC_A3 | PG3 <-> FMC_A13 |
- | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF4 <-> FMC_A4 | PG4 <-> FMC_A14 |
- | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF5 <-> FMC_A5 | PG5 <-> FMC_A15 |
- | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF12 <-> FMC_A6 | PG9 <-> FMC_NE2 |
- | PD11 <-> FMC_A16 | PE10 <-> FMC_D7 | PF13 <-> FMC_A7 |-----------------+
- | PD12 <-> FMC_A17 | PE11 <-> FMC_D8 | PF14 <-> FMC_A8 |
- | PD13 <-> FMC_A18 | PE12 <-> FMC_D9 | PF15 <-> FMC_A9 |
- | PD14 <-> FMC_D0 | PE13 <-> FMC_D10 |-----------------+
- | PD15 <-> FMC_D1 | PE14 <-> FMC_D11 |
- | | PE15 <-> FMC_D12 |
- +------------------+------------------+
-*/
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
- RCC->AHB1ENR |= 0x00000078;
-
- /* Connect PDx pins to FMC Alternate function */
- GPIOD->AFR[0] = 0x00cc00cc;
- GPIOD->AFR[1] = 0xcccccccc;
- /* Configure PDx pins in Alternate function mode */
- GPIOD->MODER = 0xaaaa0a0a;
- /* Configure PDx pins speed to 100 MHz */
- GPIOD->OSPEEDR = 0xffff0f0f;
- /* Configure PDx pins Output type to push-pull */
- GPIOD->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PDx pins */
- GPIOD->PUPDR = 0x00000000;
-
- /* Connect PEx pins to FMC Alternate function */
- GPIOE->AFR[0] = 0xcccccccc;
- GPIOE->AFR[1] = 0xcccccccc;
- /* Configure PEx pins in Alternate function mode */
- GPIOE->MODER = 0xaaaaaaaa;
- /* Configure PEx pins speed to 100 MHz */
- GPIOE->OSPEEDR = 0xffffffff;
- /* Configure PEx pins Output type to push-pull */
- GPIOE->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PEx pins */
- GPIOE->PUPDR = 0x00000000;
-
- /* Connect PFx pins to FMC Alternate function */
- GPIOF->AFR[0] = 0x00cccccc;
- GPIOF->AFR[1] = 0xcccc0000;
- /* Configure PFx pins in Alternate function mode */
- GPIOF->MODER = 0xaa000aaa;
- /* Configure PFx pins speed to 100 MHz */
- GPIOF->OSPEEDR = 0xff000fff;
- /* Configure PFx pins Output type to push-pull */
- GPIOF->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PFx pins */
- GPIOF->PUPDR = 0x00000000;
-
- /* Connect PGx pins to FMC Alternate function */
- GPIOG->AFR[0] = 0x00cccccc;
- GPIOG->AFR[1] = 0x000000c0;
- /* Configure PGx pins in Alternate function mode */
- GPIOG->MODER = 0x00080aaa;
- /* Configure PGx pins speed to 100 MHz */
- GPIOG->OSPEEDR = 0x000c0fff;
- /* Configure PGx pins Output type to push-pull */
- GPIOG->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PGx pins */
- GPIOG->PUPDR = 0x00000000;
-
-/*-- FMC Configuration ------------------------------------------------------*/
- /* Enable the FMC/FSMC interface clock */
- RCC->AHB3ENR |= 0x00000001;
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
- /* Configure and enable Bank1_SRAM2 */
- FMC_Bank1->BTCR[2] = 0x00001011;
- FMC_Bank1->BTCR[3] = 0x00000201;
- FMC_Bank1E->BWTR[2] = 0x0fffffff;
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F40_41xxx)
- /* Configure and enable Bank1_SRAM2 */
- FSMC_Bank1->BTCR[2] = 0x00001011;
- FSMC_Bank1->BTCR[3] = 0x00000201;
- FSMC_Bank1E->BWTR[2] = 0x0fffffff;
-#endif /* STM32F40_41xxx */
-
-/*
- Bank1_SRAM2 is configured as follow:
- In case of FSMC configuration
- NORSRAMTimingStructure.FSMC_AddressSetupTime = 1;
- NORSRAMTimingStructure.FSMC_AddressHoldTime = 0;
- NORSRAMTimingStructure.FSMC_DataSetupTime = 2;
- NORSRAMTimingStructure.FSMC_BusTurnAroundDuration = 0;
- NORSRAMTimingStructure.FSMC_CLKDivision = 0;
- NORSRAMTimingStructure.FSMC_DataLatency = 0;
- NORSRAMTimingStructure.FSMC_AccessMode = FMC_AccessMode_A;
-
- FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
- FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
- FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
- FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
- FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
- FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
- FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
- FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
- FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
- FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
- FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
- FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
- FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
- FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
- FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &NORSRAMTimingStructure;
-
- In case of FMC configuration
- NORSRAMTimingStructure.FMC_AddressSetupTime = 1;
- NORSRAMTimingStructure.FMC_AddressHoldTime = 0;
- NORSRAMTimingStructure.FMC_DataSetupTime = 2;
- NORSRAMTimingStructure.FMC_BusTurnAroundDuration = 0;
- NORSRAMTimingStructure.FMC_CLKDivision = 0;
- NORSRAMTimingStructure.FMC_DataLatency = 0;
- NORSRAMTimingStructure.FMC_AccessMode = FMC_AccessMode_A;
-
- FMC_NORSRAMInitStructure.FMC_Bank = FMC_Bank1_NORSRAM2;
- FMC_NORSRAMInitStructure.FMC_DataAddressMux = FMC_DataAddressMux_Disable;
- FMC_NORSRAMInitStructure.FMC_MemoryType = FMC_MemoryType_SRAM;
- FMC_NORSRAMInitStructure.FMC_MemoryDataWidth = FMC_MemoryDataWidth_16b;
- FMC_NORSRAMInitStructure.FMC_BurstAccessMode = FMC_BurstAccessMode_Disable;
- FMC_NORSRAMInitStructure.FMC_AsynchronousWait = FMC_AsynchronousWait_Disable;
- FMC_NORSRAMInitStructure.FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low;
- FMC_NORSRAMInitStructure.FMC_WrapMode = FMC_WrapMode_Disable;
- FMC_NORSRAMInitStructure.FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState;
- FMC_NORSRAMInitStructure.FMC_WriteOperation = FMC_WriteOperation_Enable;
- FMC_NORSRAMInitStructure.FMC_WaitSignal = FMC_WaitSignal_Disable;
- FMC_NORSRAMInitStructure.FMC_ExtendedMode = FMC_ExtendedMode_Disable;
- FMC_NORSRAMInitStructure.FMC_WriteBurst = FMC_WriteBurst_Disable;
- FMC_NORSRAMInitStructure.FMC_ContinousClock = FMC_CClock_SyncOnly;
- FMC_NORSRAMInitStructure.FMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
- FMC_NORSRAMInitStructure.FMC_WriteTimingStruct = &NORSRAMTimingStructure;
-*/
-
-}
-#elif defined (DATA_IN_ExtSDRAM)
-/**
- * @brief Setup the external memory controller.
- * Called in startup_stm32f4xx.s before jump to main.
- * This function configures the external SDRAM mounted on STM324x9I_EVAL board
- * This SDRAM will be used as program data memory (including heap and stack).
- * @param None
- * @retval None
- */
-void SystemInit_ExtMemCtl(void)
-{
- register uint32_t tmpreg = 0, timeout = 0xFFFF;
- register uint32_t index;
-
- /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
- clock */
- RCC->AHB1ENR |= 0x000001FC;
-
- /* Connect PCx pins to FMC Alternate function */
- GPIOC->AFR[0] = 0x0000000c;
- GPIOC->AFR[1] = 0x00007700;
- /* Configure PCx pins in Alternate function mode */
- GPIOC->MODER = 0x00a00002;
- /* Configure PCx pins speed to 50 MHz */
- GPIOC->OSPEEDR = 0x00a00002;
- /* Configure PCx pins Output type to push-pull */
- GPIOC->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PCx pins */
- GPIOC->PUPDR = 0x00500000;
-
- /* Connect PDx pins to FMC Alternate function */
- GPIOD->AFR[0] = 0x000000CC;
- GPIOD->AFR[1] = 0xCC000CCC;
- /* Configure PDx pins in Alternate function mode */
- GPIOD->MODER = 0xA02A000A;
- /* Configure PDx pins speed to 50 MHz */
- GPIOD->OSPEEDR = 0xA02A000A;
- /* Configure PDx pins Output type to push-pull */
- GPIOD->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PDx pins */
- GPIOD->PUPDR = 0x00000000;
-
- /* Connect PEx pins to FMC Alternate function */
- GPIOE->AFR[0] = 0xC00000CC;
- GPIOE->AFR[1] = 0xCCCCCCCC;
- /* Configure PEx pins in Alternate function mode */
- GPIOE->MODER = 0xAAAA800A;
- /* Configure PEx pins speed to 50 MHz */
- GPIOE->OSPEEDR = 0xAAAA800A;
- /* Configure PEx pins Output type to push-pull */
- GPIOE->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PEx pins */
- GPIOE->PUPDR = 0x00000000;
-
- /* Connect PFx pins to FMC Alternate function */
- GPIOF->AFR[0] = 0xcccccccc;
- GPIOF->AFR[1] = 0xcccccccc;
- /* Configure PFx pins in Alternate function mode */
- GPIOF->MODER = 0xAA800AAA;
- /* Configure PFx pins speed to 50 MHz */
- GPIOF->OSPEEDR = 0xAA800AAA;
- /* Configure PFx pins Output type to push-pull */
- GPIOF->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PFx pins */
- GPIOF->PUPDR = 0x00000000;
-
- /* Connect PGx pins to FMC Alternate function */
- GPIOG->AFR[0] = 0xcccccccc;
- GPIOG->AFR[1] = 0xcccccccc;
- /* Configure PGx pins in Alternate function mode */
- GPIOG->MODER = 0xaaaaaaaa;
- /* Configure PGx pins speed to 50 MHz */
- GPIOG->OSPEEDR = 0xaaaaaaaa;
- /* Configure PGx pins Output type to push-pull */
- GPIOG->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PGx pins */
- GPIOG->PUPDR = 0x00000000;
-
- /* Connect PHx pins to FMC Alternate function */
- GPIOH->AFR[0] = 0x00C0CC00;
- GPIOH->AFR[1] = 0xCCCCCCCC;
- /* Configure PHx pins in Alternate function mode */
- GPIOH->MODER = 0xAAAA08A0;
- /* Configure PHx pins speed to 50 MHz */
- GPIOH->OSPEEDR = 0xAAAA08A0;
- /* Configure PHx pins Output type to push-pull */
- GPIOH->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PHx pins */
- GPIOH->PUPDR = 0x00000000;
-
- /* Connect PIx pins to FMC Alternate function */
- GPIOI->AFR[0] = 0xCCCCCCCC;
- GPIOI->AFR[1] = 0x00000CC0;
- /* Configure PIx pins in Alternate function mode */
- GPIOI->MODER = 0x0028AAAA;
- /* Configure PIx pins speed to 50 MHz */
- GPIOI->OSPEEDR = 0x0028AAAA;
- /* Configure PIx pins Output type to push-pull */
- GPIOI->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PIx pins */
- GPIOI->PUPDR = 0x00000000;
-
-/*-- FMC Configuration ------------------------------------------------------*/
- /* Enable the FMC interface clock */
- RCC->AHB3ENR |= 0x00000001;
-
- /* Configure and enable SDRAM bank1 */
- FMC_Bank5_6->SDCR[0] = 0x000039D0;
- FMC_Bank5_6->SDTR[0] = 0x01115351;
-
- /* SDRAM initialization sequence */
- /* Clock enable command */
- FMC_Bank5_6->SDCMR = 0x00000011;
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- while((tmpreg != 0) & (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* Delay */
- for (index = 0; index<1000; index++);
-
- /* PALL command */
- FMC_Bank5_6->SDCMR = 0x00000012;
- timeout = 0xFFFF;
- while((tmpreg != 0) & (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* Auto refresh command */
- FMC_Bank5_6->SDCMR = 0x00000073;
- timeout = 0xFFFF;
- while((tmpreg != 0) & (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* MRD register program */
- FMC_Bank5_6->SDCMR = 0x00046014;
- timeout = 0xFFFF;
- while((tmpreg != 0) & (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* Set refresh count */
- tmpreg = FMC_Bank5_6->SDRTR;
- FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
-
- /* Disable write protection */
- tmpreg = FMC_Bank5_6->SDCR[0];
- FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
-
-/*
- Bank1_SDRAM is configured as follow:
-
- FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;
- FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 6;
- FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;
- FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 6;
- FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;
- FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;
- FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;
-
- FMC_SDRAMInitStructure.FMC_Bank = SDRAM_BANK;
- FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
- FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_11b;
- FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b;
- FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
- FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3;
- FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
- FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2;
- FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_disable;
- FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;
- FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
-*/
-
-}
-#endif /* DATA_IN_ExtSDRAM && DATA_IN_ExtSRAM */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/底盘/底盘-old/底盘/Start/system_stm32f4xx.h b/底盘/底盘-old/底盘/Start/system_stm32f4xx.h
deleted file mode 100644
index f82217c..0000000
--- a/底盘/底盘-old/底盘/Start/system_stm32f4xx.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f4xx.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f4xx_system
- * @{
- */
-
-/**
- * @brief Define to prevent recursive inclusion
- */
-#ifndef __SYSTEM_STM32F4XX_H
-#define __SYSTEM_STM32F4XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup STM32F4xx_System_Includes
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @addtogroup STM32F4xx_System_Exported_types
- * @{
- */
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Exported_Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Exported_Functions
- * @{
- */
-
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32F4XX_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/底盘/底盘-old/底盘/System/CAN.c b/底盘/底盘-old/底盘/System/CAN.c
deleted file mode 100644
index be9f7c8..0000000
--- a/底盘/底盘-old/底盘/System/CAN.c
+++ /dev/null
@@ -1,220 +0,0 @@
-#include "stm32f4xx.h" // Device header
-#include "stm32f4xx_conf.h"
-#include "CAN.h"
-#include "M3508.h"
-#include "GM6020.h"
-#include "LinkCheck.h"
-#include "CToC.h"
-#include "Warming.h"
-
-uint8_t CAN_CAN1DeviceNumber=4;//CAN1总线上设备数量
-uint8_t CAN_CAN2DeviceNumber=3;//CAN2总线上设备数量
-uint8_t CAN_DeviceNumber=7;//CAN总线上设备数量
-uint32_t CAN_CAN1IDList[10][2]={{CAN_M3508,M3508_1},{CAN_M3508,M3508_2},{CAN_M3508,M3508_3},{CAN_M3508,M3508_4},0};//CAN1总线上设备ID列表
-uint32_t CAN_CAN2IDList[10][2]={{CAN_GM6020,GM6020_1},{CAN_RoboMasterC,CToC_SlaveID1},{CAN_RoboMasterC,CToC_SlaveID2},0};
-
-//uint32_t CAN_CAN2IDList[10][2]={{CAN_GM6020,GM6020_1},{CAN_RoboMasterC,CToC_SlaveID1},{CAN_RoboMasterC,CToC_SlaveID2},0};//CAN2总线上设备ID列表
-uint8_t CAN_IDSelect=0;//CAN总线上ID列表选择位
-
-/*
- *函数简介:CAN总线初始化
- *参数说明:无
- *返回类型:无
- *备注:默认使用CAN1(CAN1-Tx为PD1,CAN1-Rx为PD0),CAN2(CAN2-Tx为PB6,CAN2-Rx为PB5)
- *备注:CAN波特率1M,默认1Tq=1/14us≈0.07us
- *备注:使用CAN2需要在打开CAN2时钟之前打开CAN1时钟,且CAN2筛选器编号为15~27
- */
-void CAN_CANInit(void)
-{
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1,ENABLE);
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2,ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB,ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD,ENABLE);//开启时钟
-
- GPIO_InitTypeDef GPIO_InitStructure;
- GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//复用推挽
- GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
- GPIO_InitStructure.GPIO_Pin=GPIO_Pin_0 | GPIO_Pin_1;
- GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
- GPIO_Init(GPIOD,&GPIO_InitStructure);//配置PD0(CAN1-Rx)和PD1(CAN1-Tx)
- GPIO_InitStructure.GPIO_Pin=GPIO_Pin_5 | GPIO_Pin_6;
- GPIO_Init(GPIOB,&GPIO_InitStructure);//配置PB5(CAN2-Rx)和PB6(CAN2-Tx)
-
- GPIO_PinAFConfig(GPIOD,GPIO_PinSource0,GPIO_AF_CAN1);//开启PD0的CAN1复用模式
- GPIO_PinAFConfig(GPIOD,GPIO_PinSource1,GPIO_AF_CAN1);//开启PD1的CAN1复用模式
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource5,GPIO_AF_CAN2);//开启PB5的CAN2复用模式
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource6,GPIO_AF_CAN2);//开启PB6的CAN2复用模式
-
- CAN_InitTypeDef CAN_InitStructure;
- CAN_InitStructure.CAN_Mode=CAN_Mode_Normal;//正常模式
- CAN_InitStructure.CAN_Prescaler=3;//时钟分频,1Tq=Prescaler/T_PCLK=Prescaler/42M
- CAN_InitStructure.CAN_SJW=CAN_SJW_1tq;//SJW极限值
- CAN_InitStructure.CAN_BS1=CAN_BS1_10tq;//PBS1段长度
- CAN_InitStructure.CAN_BS2=CAN_BS2_3tq;//PBS2段长度,1/Baudrate=T_1bit=(1+BS1+BS2)Tq
- CAN_InitStructure.CAN_TTCM=DISABLE;//关闭时间触发功能
- CAN_InitStructure.CAN_ABOM=ENABLE;//开启自动离线管理功能
- CAN_InitStructure.CAN_AWUM=ENABLE;//开启自动唤醒功能
- CAN_InitStructure.CAN_NART=ENABLE;//禁止自动重传功能
- CAN_InitStructure.CAN_RFLM=DISABLE;//关闭锁定FIFO功能
- CAN_InitStructure.CAN_TXFP=DISABLE;//配置报文优先级判定为标识符决定
- CAN_Init(CAN1,&CAN_InitStructure);
- CAN_Init(CAN2,&CAN_InitStructure);
-
- CAN_FilterInitTypeDef CAN_FilterInitStructure;
- CAN_FilterInitStructure.CAN_FilterNumber=0;//筛选器编号0(编号0~14属于CAN1,编号15~27属于CAN2)
- CAN_FilterInitStructure.CAN_FilterFIFOAssignment=CAN_Filter_FIFO0;//存入FIFO0
- CAN_FilterInitStructure.CAN_FilterMode=CAN_FilterMode_IdMask;//掩码模式
- CAN_FilterInitStructure.CAN_FilterScale=CAN_FilterScale_16bit;//筛选器尺度为16bits
- CAN_FilterInitStructure.CAN_FilterIdHigh=(CAN_CAN1IDList[0][1]<<5);//标识符=STID[15:5]+RTR[4:4](0)+IDE[3:3](0)+EXID[2:0](000)
- CAN_FilterInitStructure.CAN_FilterIdLow=(CAN_CAN1IDList[0][1]<<5);//筛选器尺度为16bits,故没有高低位之分
- CAN_FilterInitStructure.CAN_FilterMaskIdHigh=0xFFE3;//掩码(1111 1111 0000 0011),1对应位必须匹配,0对应位无需匹配
- CAN_FilterInitStructure.CAN_FilterMaskIdLow=0xFFE3;//筛选器尺度为16bits,故没有高低位之分
- CAN_FilterInitStructure.CAN_FilterActivation=ENABLE;//使能筛选器
- CAN_FilterInit(&CAN_FilterInitStructure);
- CAN_FilterInitStructure.CAN_FilterNumber=15;//筛选器编号15(编号0~14属于CAN1,编号15~27属于CAN2)
- CAN_FilterInitStructure.CAN_FilterFIFOAssignment=CAN_Filter_FIFO1;//存入FIFO1
- CAN_FilterInitStructure.CAN_FilterIdHigh=(0x000<<5);//标识符=STID[15:5](189/0001 1000 1001)+RTR[4:4](0)+IDE[3:3](0)+EXID[2:0](000)
- CAN_FilterInitStructure.CAN_FilterIdLow=(0x000<<5);//CAN2先给0,默认从CAN1开始串行接收
- CAN_FilterInit(&CAN_FilterInitStructure);
-
- CAN_ITConfig(CAN1,CAN_IT_FMP0,ENABLE);//打通CAN1_FIFO0到NVIC的通道
- CAN_ITConfig(CAN2,CAN_IT_FMP1,ENABLE);//打通CAN2_FIFO1到NVIC的通道
-
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//选择NVIC分组2(2位抢占优先级，2位响应优先级)
-
- NVIC_InitTypeDef NVIC_InitStructure;
- NVIC_InitStructure.NVIC_IRQChannel=CAN1_RX0_IRQn;//选择CAN1_FIFO0接收中断通道
- NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;//使能中断通道
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=1;//抢占优先级为1
- NVIC_InitStructure.NVIC_IRQChannelSubPriority=1;//响应优先级为1
- NVIC_Init(&NVIC_InitStructure);//初始化CAN1_FIFO0的NVIC
- NVIC_InitStructure.NVIC_IRQChannel=CAN2_RX1_IRQn;//选择CAN2_FIFO1接收中断通道
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=1;//抢占优先级为1
- NVIC_InitStructure.NVIC_IRQChannelSubPriority=1;//响应优先级为1
- NVIC_Init(&NVIC_InitStructure);//初始化CAN2_FIFO1的NVIC
-}
-
-/*
- *函数简介:CAN1总线接收报文
- *参数说明:报文存储数组
- *返回类型:报文ID
- *备注:默认8字节标准数据帧
- *备注:没有接收到数据,直接退出,返回0
- */
-uint32_t CAN_CAN1Receive(uint8_t *Data)
-{
- CanRxMsg RxMessage;
- if(CAN_MessagePending(CAN1,CAN_FIFO0)==0)return 0;//没有接收到数据,直接退出
- CAN_Receive(CAN1,CAN_FIFO0,&RxMessage);//读取数据
- for(uint32_t i=0;i<8;i++)
- Data[i]=RxMessage.Data[i];//储存数据
- return RxMessage.StdId;//返回ID
-}
-
-/*
- *函数简介:CAN2总线接收报文
- *参数说明:报文存储数组
- *返回类型:报文ID
- *备注:默认8字节数据
- *备注:没有接收到数据,直接退出,返回0
- */
-uint32_t CAN_CAN2Receive(uint8_t *Data)
-{
- CanRxMsg RxMessage;
- if(CAN_MessagePending(CAN2,CAN_FIFO1)==0)return 0;//没有接收到数据,直接退出
- CAN_Receive(CAN2,CAN_FIFO1,&RxMessage);//读取数据
- for(uint32_t i=0;i<8;i++)
- Data[i]=RxMessage.Data[i];
- return RxMessage.StdId;
-}
-
-/*
- *函数简介:CAN1总线更改接收ID
- *参数说明:接收ID
- *返回类型:无
- *备注:无
- */
-void CAN_CAN1ChangeID(uint32_t ID)
-{
- CAN1->FMR |= 0x00000001;//配置CAN_FMR寄存器FINIT位进入初始化模式
- CAN1->sFilterRegister[0].FR1 = ((uint32_t)0xFFE3<<16) | (ID<<5);//配置CAN_F0R1寄存器更改ID低位
- CAN1->sFilterRegister[0].FR2 = ((uint32_t)0xFFE3<<16) | (ID<<5);//配置CAN_F0R2寄存器更改ID高位(16bits尺度下无高低位区别)
- CAN1->FMR &= ~(0x00000001);//配置CAN_FMR寄存器FINIT位回到工作模式
-}
-
-/*
- *函数简介:CAN2总线更改接收ID
- *参数说明:接收ID
- *返回类型:无
- *备注:无
- */
-void CAN_CAN2ChangeID(uint32_t ID)
-{
- CAN1->FMR |= 0x00000001;
- CAN1->sFilterRegister[15].FR1 = ((uint32_t)0xFFE3<<16) | (ID<<5);
- CAN1->sFilterRegister[15].FR2 = ((uint32_t)0xFFE3<<16) | (ID<<5);
- CAN1->FMR &= ~(0x00000001);
-}
-
-/*
- *函数简介:CAN1_FIFO0接收中断函数
- *参数说明:无
- *返回类型:无
- *备注:进入中断时关闭连接检测计时,离开中断时重新打开连接检测计时
- *备注:某一设备掉线时,CAN_IDSelect会停留在当前设备在ID列表的索引
- */
-void CAN1_RX0_IRQHandler(void)
-{
- if(CAN_GetITStatus(CAN1,CAN_IT_FMP0)==SET)//查询接收中断标志位
- {
- uint8_t Data[8];//接收数据
- uint32_t ID=CAN_CAN1Receive(Data);//接收数据帧的ID
-
- Warming_BuzzerClean();//清除报错蜂鸣器状态
- LinkCheck_OFF();//关闭连接检测定时
- if(LinkCheck_Error==1)//如果此时处于连接断开状态
- LinkCheck_Error=0;//回到正常连接状态
-
- if(CAN_CAN1IDList[CAN_IDSelect][0]==CAN_M3508)M3508_CANDataProcess(ID,Data);//处理M3508的数据
- else if(CAN_CAN1IDList[CAN_IDSelect][0]==CAN_GM6020)GM6020_CANDataProcess(ID,Data);//处理GM6020的数据
-
- CAN_IDSelect=(CAN_IDSelect+1)%CAN_DeviceNumber;//更换CAN总线ID切换选择位
- if(CAN_IDSelect>=0 && CAN_IDSelect=0 && CAN_IDSelectLOAD=us*21; //时间加载，我们要延时n倍的us, 1us是一个fac_ua周期，所以总共要延时的周期值为二者相乘最后送到Load中。
- SysTick->VAL=0x00; //清空计数器
- SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; //开启使能位 开始倒数
- do temp=SysTick->CTRL;
- while((temp&0x01) && !(temp&(1<<16))); //用来判断 systick 定时器是否还处于开启状态，然后在等待时间到达，也就是数到0的时候,此时第十六位设置为1
- SysTick->CTRL&=~SysTick_CTRL_ENABLE_Msk; //关闭计数器使能位
- SysTick->VAL=0x00; //清空计数器
-}
-
-/*
- *函数简介:毫秒级延时
- *参数说明:延时时长,单位ms
- *返回类型:无
- *备注:参数范围:0~4294967295
- */
-void Delay_ms(uint32_t ms)
-{
- while(ms--)
- Delay_us(1000);
-}
-
-/*
- *函数简介:秒级延时
- *参数说明:延时时长,单位s
- *返回类型:无
- *备注:参数范围:0~4294967295
- */
-void Delay_s(uint32_t s)
-{
- while(s--)
- Delay_ms(1000);
-}
diff --git a/底盘/底盘-old/底盘/System/Delay.h b/底盘/底盘-old/底盘/System/Delay.h
deleted file mode 100644
index 2bd1c08..0000000
--- a/底盘/底盘-old/底盘/System/Delay.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef __DELAY_H
-#define __DELAY_H
-
-void Delay_us(uint32_t us);//微秒级延时
-void Delay_ms(uint32_t ms);//毫秒级延时
-void Delay_s(uint32_t s);//秒级延时
-
-#endif
diff --git a/底盘/底盘-old/底盘/System/TIM.c b/底盘/底盘-old/底盘/System/TIM.c
deleted file mode 100644
index f248de9..0000000
--- a/底盘/底盘-old/底盘/System/TIM.c
+++ /dev/null
@@ -1,72 +0,0 @@
-#include "stm32f4xx.h" // Device header
-#include "stm32f4xx_conf.h"
-#include "CAN.h"
-
-/*==================== 定时器资源分配 ====================
- TIM1(高级) ················PWM1~PWM4
- TIM2 ················定时器
- TIM3 ················
- TIM4 ················蜂鸣器发声
- TIM5 ················混色LED三色控制
- TIM6(基本) ················PID闭环
- TIM7(基本) ················遥控器连接检测
- TIM8(高级) ················PWM5~PWM7
- TIM9 ················
- TIM10 ················
- TIM11 ················
- TIM12 ················
- TIM13 ················CAN总线设备连接检测
- TIM14 ················
- =============================================================*/
-
-/*
- *函数简介:TIM2定时器初始化
- *参数说明:无
- *返回类型:无
- *备注:默认定时1ms
- *备注:Freq=Sys_APB1TIM/(PSC+1)/(ARR+1)=84MHz/(PSC+1)/(ARR+1)
- */
-void TIM_Init(void)
-{
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2,ENABLE);//开启时钟
-
- TIM_InternalClockConfig(TIM2);//选择时基单元的时钟(此处为内部时钟),TIM_ITRxExternalClockConfig()接ITRx时钟,TIM_TIxExternalClockConfig()接TIx捕获通道时钟,TIM_ETRClockMode1Config()接ETR时钟(选择外部时钟模式1),TIM_ETRClockMode2Config()接ETR时钟(选择外部时钟模式2)
-
- TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure;//配置时基单元（配置参数）
- TIM_TimeBaseInitStructure.TIM_ClockDivision=TIM_CKD_DIV1;//配置时钟分频为1分频
- TIM_TimeBaseInitStructure.TIM_CounterMode=TIM_CounterMode_Up;//配置计数器模式为向上计数
- TIM_TimeBaseInitStructure.TIM_Period=200-1;//配置自动重装值ARR
- TIM_TimeBaseInitStructure.TIM_Prescaler=420-1;//配置分频值PSC,默认频率800Hz
- TIM_TimeBaseInitStructure.TIM_RepetitionCounter=0;//配置重复计数单元的置为0
- TIM_TimeBaseInit(TIM2,&TIM_TimeBaseInitStructure);//初始化TIM2
-
- TIM_ClearFlag(TIM2,TIM_FLAG_Update);//清除配置时基单元产生的中断标志位
-
- TIM_ITConfig(TIM2,TIM_IT_Update,ENABLE);//使能更新中断
-
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//选择NVIC分组
-
- NVIC_InitTypeDef NVIC_InitStructure;//配置NVIC（配置参数）
- NVIC_InitStructure.NVIC_IRQChannel=TIM2_IRQn;//选择中断通道为TIM2
- NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;//使能中断通道
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=1;//TIM2的抢占优先级
- NVIC_InitStructure.NVIC_IRQChannelSubPriority=2;//TIM2的响应优先级
- NVIC_Init(&NVIC_InitStructure);//初始化NVIC
-
- TIM_Cmd(TIM2,ENABLE);//启动定时器
-}
-
-/*
- *函数简介:TIM2定时器更新中断函数
- *参数说明:无
- *返回类型:无
- *备注:无
- */
-void TIM2_IRQHandler(void)
-{
- if(TIM_GetITStatus(TIM2,TIM_IT_Update)==SET)//检测TIM2更新
- {
- TIM_ClearITPendingBit(TIM2,TIM_IT_Update);//清除标志位
- //函数体
- }
-}
diff --git a/底盘/底盘-old/底盘/System/TIM.h b/底盘/底盘-old/底盘/System/TIM.h
deleted file mode 100644
index 883a125..0000000
--- a/底盘/底盘-old/底盘/System/TIM.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __TIM_H
-#define __TIM_H
-
-void TIM_Init(void);//TIM2定时器初始化
-
-#endif
diff --git a/底盘/底盘-old/底盘/System/UART.c b/底盘/底盘-old/底盘/System/UART.c
deleted file mode 100644
index 15fd36c..0000000
--- a/底盘/底盘-old/底盘/System/UART.c
+++ /dev/null
@@ -1,557 +0,0 @@
-#include "stm32f4xx.h" // Device header
-#include "stm32f4xx_conf.h"
-#include
-#include
-
-//重定向串口选择,选择哪个串口就把哪个取消注释
-//#define UART1_Redirect//选择UART1重定向
-//#define UART2_Redirect//选择UART2重定向
-
-uint8_t UART1_RxData;//接收数据缓存区
-uint8_t UART1_RxFlag;//接收完成标志位
-
-uint8_t UART2_RxData;//接收数据缓存区
-uint8_t UART2_RxFlag;//接收完成标志位
-
-
-/*
- *函数简介:串口专用指数函数
- *参数说明:底数x
- *参数说明:指数y
- *返回类型:x^y
- *备注:x,y均为整数
- */
-uint32_t USART_Pow(uint32_t x,uint32_t y)
-{
- uint32_t Result=1;
- while(y--)
- Result*=x;
- return Result;
-}
-
-/*
- *函数简介:UART1串口发送初始化
- *参数说明:无
- *返回类型:无
- *备注:UART1为USART6,默认Tx引脚PG14
- */
-void UART1_SendInit(void)
-{
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6,ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOG,ENABLE);//开启时钟
-
- GPIO_InitTypeDef GPIO_InitStructure;
- GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//复用推挽
- GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
- GPIO_InitStructure.GPIO_Pin=GPIO_Pin_14;
- GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
- GPIO_Init(GPIOG,&GPIO_InitStructure);//初始化UART1-Tx(PG14)
-
- GPIO_PinAFConfig(GPIOG,GPIO_PinSource14,GPIO_AF_USART6);//开启PG14的USART6复用模式
-
- USART_InitTypeDef USART_InitStructure;
- USART_InitStructure.USART_BaudRate=115200;//配置波特率115200
- USART_InitStructure.USART_HardwareFlowControl=USART_HardwareFlowControl_None;//配置无硬件流控制
- USART_InitStructure.USART_Mode=USART_Mode_Tx;//配置为发送模式
- USART_InitStructure.USART_Parity=USART_Parity_No;//配置为无校验位
- USART_InitStructure.USART_StopBits=USART_StopBits_1;//配置停止位为1
- USART_InitStructure.USART_WordLength=USART_WordLength_8b;//配置字长8bit
- USART_Init(USART6,&USART_InitStructure);//初始化USART6
-
- USART_Cmd(USART6,ENABLE);//启动USART6
-}
-
-/*
- *函数简介:UART1串口接收初始化
- *参数说明:无
- *返回类型:无
- *备注:UART1为USART6,默认Rx引脚PG9
- */
-void UART1_ReceiveInit(void)
-{
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6,ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOG,ENABLE);//开启时钟
-
- GPIO_InitTypeDef GPIO_InitStructure;
- GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//复用推挽
- GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
- GPIO_InitStructure.GPIO_Pin=GPIO_Pin_9;
- GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
- GPIO_Init(GPIOG,&GPIO_InitStructure);//初始化UART1-Rx(PG9)
-
- GPIO_PinAFConfig(GPIOG,GPIO_PinSource9,GPIO_AF_USART6);//开启PG9的USART6复用模式
-
- USART_InitTypeDef USART_InitStructure;
- USART_InitStructure.USART_BaudRate=115200;//配置波特率115200
- USART_InitStructure.USART_HardwareFlowControl=USART_HardwareFlowControl_None;//配置无硬件流控制
- USART_InitStructure.USART_Mode=USART_Mode_Rx;//配置为接收模式
- USART_InitStructure.USART_Parity=USART_Parity_No;//配置为无校验位
- USART_InitStructure.USART_StopBits=USART_StopBits_1;//配置停止位为1
- USART_InitStructure.USART_WordLength=USART_WordLength_8b;//配置字长8bit
- USART_Init(USART6,&USART_InitStructure);//初始化USART6
-
- USART_ITConfig(USART6,USART_IT_RXNE,ENABLE);//打通USART6到NVIC的串口接收中断通道
-
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//选择NVIC分组2(2位抢占优先级，2位响应优先级)
-
- NVIC_InitTypeDef NVIC_InitStructure;
- NVIC_InitStructure.NVIC_IRQChannel=USART6_IRQn;//选择USART6中断通道
- NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;//使能中断通道
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=1;//抢占优先级为1
- NVIC_InitStructure.NVIC_IRQChannelSubPriority=1;//响应优先级为1
- NVIC_Init(&NVIC_InitStructure);//初始化USART6的NVIC
-
- USART_Cmd(USART6,ENABLE);//启动USART6
-}
-
-/*
- *函数简介:UART1串口初始化
- *参数说明:无
- *返回类型:无
- *备注:UART1为USART6,默认Tx引脚PG14,Rx引脚PG9
- */
-void UART1_Init(void)
-{
-
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6,ENABLE);
- //RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOG,ENABLE); //开启时钟
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA,ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB,ENABLE); // 开启时钟
-
- GPIO_PinAFConfig(GPIOA,GPIO_PinSource9,GPIO_AF_USART1);//开启PA9的USART1复用模式
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource7,GPIO_AF_USART1);//开启PB7的USART1复用模式
-
- GPIO_InitTypeDef GPIO_InitStructure;
- GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//复用推挽
- GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
-
- GPIO_InitStructure.GPIO_Pin=GPIO_Pin_9;
- GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
- GPIO_Init(GPIOA,&GPIO_InitStructure);//初始化UART2-Tx(PA9)
- GPIO_InitStructure.GPIO_Pin=GPIO_Pin_7;
- GPIO_Init(GPIOB,&GPIO_InitStructure);//初始化UART2-Rx(PB7)
- /*
- GPIO_InitStructure.GPIO_Pin=GPIO_Pin_14 | GPIO_Pin_9;
- GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
- GPIO_Init(GPIOG,&GPIO_InitStructure);//初始化UART1-Tx(PG14),UART1-Rx(PG9)
- */
- GPIO_PinAFConfig(GPIOA,GPIO_PinSource9,GPIO_AF_USART1);//开启PA9的USART1复用模式
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource7,GPIO_AF_USART1);//开启PB7的USART1复用模式
-
- //GPIO_PinAFConfig(GPIOG,GPIO_PinSource14,GPIO_AF_USART6);//开启PG14的USART6复用模式
- //GPIO_PinAFConfig(GPIOG,GPIO_PinSource9,GPIO_AF_USART6);//开启PG9的USART6复用模式
-
- USART_InitTypeDef USART_InitStructure;
- USART_InitStructure.USART_BaudRate=115200;//配置波特率115200
- USART_InitStructure.USART_HardwareFlowControl=USART_HardwareFlowControl_None;//配置无硬件流控制
- USART_InitStructure.USART_Mode=USART_Mode_Tx | USART_Mode_Rx;//配置为接发模式
- USART_InitStructure.USART_Parity=USART_Parity_No;//配置为无校验位
- USART_InitStructure.USART_StopBits=USART_StopBits_1;//配置停止位为1
- USART_InitStructure.USART_WordLength=USART_WordLength_8b;//配置字长8bit
- USART_Init(USART6,&USART_InitStructure);//初始化USART6
-
- USART_ITConfig(USART6,USART_IT_RXNE,ENABLE);//打通USART6到NVIC的串口接收中断通道
-
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//选择NVIC分组2(2位抢占优先级，2位响应优先级)
-
- NVIC_InitTypeDef NVIC_InitStructure;
- NVIC_InitStructure.NVIC_IRQChannel=USART6_IRQn;//选择USART6中断通道
- NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;//使能中断通道
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=1;//抢占优先级为1
- NVIC_InitStructure.NVIC_IRQChannelSubPriority=1;//响应优先级为1
- NVIC_Init(&NVIC_InitStructure);//初始化USART6的NVICrobot_status_t
-
- USART_Cmd(USART6,ENABLE);//启动USART6
-}
-
-/*
- *函数简介:UART1发送一个字节
- *参数说明:8bits数据
- *返回类型:无
- *备注:无
- */
-void UART1_SendByte(uint8_t Byte)
-{
- USART_SendData(USART6,Byte);
- while(USART_GetFlagStatus(USART6,USART_FLAG_TXE)==RESET);//等待发送完成
-}
-
-/*
- *函数简介:UART1发送一个数组
- *参数说明:8bits数组
- *参数说明:数组长度
- *返回类型:无
- *备注:无
- */
-void UART1_SendArray(uint8_t *Array,uint16_t Length)
-{
- for(uint16_t i=0;i=Number位数)
- *返回类型:无
- *备注:无
- */
-void UART1_SendNumber(uint32_t Number,uint8_t Length)
-{
- for(uint8_t i=0;iDR=ch;
- while(!(USART6->SR&(1<<7))){}
- return ch;
- }
-
- /*
- *函数简介:重写fgetc函数(重定向scanf，即移植scanf)
- *参数说明:无
- *返回类型:无
- *备注:看不懂
- *备注:默认重定向UART1(即USART6),若想修改重定向串口,请更改最上方宏定义的注释
- */
- int fgetc(FILE *stream)
- {
- while(!(USART6->SR&1<<5)){}
- return USART6->DR;
- }
-#endif
-
-/*
- *函数简介:UART1的printf函数
- *参数说明:无
- *返回类型:无
- *备注:等价printf函数,支持多串口
- *备注:看不懂
- */
-void UART1_Printf(char *format,...)
-{
- char Strings[100];
- va_list arg;//定义参数列表变量arg
- va_start(arg,format);//从format位置接收参数，放在arg里
- vsprintf(Strings,format,arg);//将格式化字符串打印到Strings
- va_end(arg);//释放参数表arg
- UART1_SendString(Strings);//发送字符串Strings
-}
-
-/*
- *函数简介:UART1获取接收完成标志位
- *参数说明:无
- *返回类型:1-接收完成,0-接收未完成
- *备注:接收完成会软件清零标志位
- */
-uint8_t UART1_GetRxFlag(void)
-{
- if(UART1_RxFlag==1)
- {
- UART1_RxFlag=0;//复位
- return 1;
- }
- return 0;
-}
-
-/*
- *函数简介:UART2串口发送初始化
- *参数说明:无
- *返回类型:无
- *备注:UART2为USART1,默认Tx引脚PA9
- */
-void UART2_SendInit(void)
-{
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1,ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA,ENABLE);//开启时钟
-
- GPIO_InitTypeDef GPIO_InitStructure;
- GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//复用推挽
- GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
- GPIO_InitStructure.GPIO_Pin=GPIO_Pin_9;
- GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
- GPIO_Init(GPIOA,&GPIO_InitStructure);//初始化UART2-Tx(PA9)
-
- GPIO_PinAFConfig(GPIOA,GPIO_PinSource9,GPIO_AF_USART1);//开启PA9的USART1复用模式
-
- USART_InitTypeDef USART_InitStructure;
- USART_InitStructure.USART_BaudRate=115200;//配置波特率115200
- USART_InitStructure.USART_HardwareFlowControl=USART_HardwareFlowControl_None;//配置无硬件流控制
- USART_InitStructure.USART_Mode=USART_Mode_Tx;//配置为发送模式
- USART_InitStructure.USART_Parity=USART_Parity_No;//配置为无校验位
- USART_InitStructure.USART_StopBits=USART_StopBits_1;//配置停止位为1
- USART_InitStructure.USART_WordLength=USART_WordLength_8b;//配置字长8bit
- USART_Init(USART1,&USART_InitStructure);//初始化USART1
-
- USART_Cmd(USART1,ENABLE);//启动USART1
-}
-
-/*
- *函数简介:UART2串口接收初始化
- *参数说明:无
- *返回类型:无
- *备注:UART2为USART1,默认Rx引脚PB7
- */
-void UART2_ReceiveInit(void)
-{
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1,ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB,ENABLE);//开启时钟
-
- GPIO_InitTypeDef GPIO_InitStructure;
- GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//复用推挽
- GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
- GPIO_InitStructure.GPIO_Pin=GPIO_Pin_7;
- GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
- GPIO_Init(GPIOB,&GPIO_InitStructure);//初始化UART2-Rx(PB7)
-
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource7,GPIO_AF_USART1);//开启PB7的USART1复用模式
-
- USART_InitTypeDef USART_InitStructure;
- USART_InitStructure.USART_BaudRate=115200;//配置波特率115200
- USART_InitStructure.USART_HardwareFlowControl=USART_HardwareFlowControl_None;//配置无硬件流控制
- USART_InitStructure.USART_Mode=USART_Mode_Rx;//配置为接收模式
- USART_InitStructure.USART_Parity=USART_Parity_No;//配置为无校验位
- USART_InitStructure.USART_StopBits=USART_StopBits_1;//配置停止位为1
- USART_InitStructure.USART_WordLength=USART_WordLength_8b;//配置字长8bit
- USART_Init(USART1,&USART_InitStructure);//初始化USART1
-
- USART_ITConfig(USART1,USART_IT_RXNE,ENABLE);//打通USART1到NVIC的串口接收中断通道
-
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//选择NVIC分组2(2位抢占优先级，2位响应优先级)
-
- NVIC_InitTypeDef NVIC_InitStructure;
- NVIC_InitStructure.NVIC_IRQChannel=USART1_IRQn;//选择USART1中断通道
- NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;//使能中断通道
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=1;//抢占优先级为1
- NVIC_InitStructure.NVIC_IRQChannelSubPriority=1;//响应优先级为1
- NVIC_Init(&NVIC_InitStructure);//初始化USART1的NVIC
-
- USART_Cmd(USART1,ENABLE);//启动USART1
-}
-
-/*
- *函数简介:UART2串口初始化
- *参数说明:无
- *返回类型:无
- *备注:UART2为USART1,默认Tx引脚PA9,Rx引脚PB7
- */
-void UART2_Init(void)
-{
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1,ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA,ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB,ENABLE);//开启时钟
-
- GPIO_InitTypeDef GPIO_InitStructure;
- GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_OType=GPIO_OType_PP;//复用推挽
- GPIO_InitStructure.GPIO_PuPd=GPIO_PuPd_UP;//默认上拉
- GPIO_InitStructure.GPIO_Pin=GPIO_Pin_9;
- GPIO_InitStructure.GPIO_Speed=GPIO_Speed_100MHz;
- GPIO_Init(GPIOA,&GPIO_InitStructure);//初始化UART2-Tx(PA9)
- GPIO_InitStructure.GPIO_Pin=GPIO_Pin_7;
- GPIO_Init(GPIOB,&GPIO_InitStructure);//初始化UART2-Rx(PB7)
-
- GPIO_PinAFConfig(GPIOA,GPIO_PinSource9,GPIO_AF_USART1);//开启PA9的USART1复用模式
- GPIO_PinAFConfig(GPIOB,GPIO_PinSource7,GPIO_AF_USART1);//开启PB7的USART1复用模式
-
- USART_InitTypeDef USART_InitStructure;
- USART_InitStructure.USART_BaudRate=115200;//配置波特率115200
- USART_InitStructure.USART_HardwareFlowControl=USART_HardwareFlowControl_None;//配置无硬件流控制
- USART_InitStructure.USART_Mode=USART_Mode_Tx | USART_Mode_Rx;//配置为接发模式
- USART_InitStructure.USART_Parity=USART_Parity_No;//配置为无校验位
- USART_InitStructure.USART_StopBits=USART_StopBits_1;//配置停止位为1
- USART_InitStructure.USART_WordLength=USART_WordLength_8b;//配置字长8bit
- USART_Init(USART1,&USART_InitStructure);//初始化USART1
-
- USART_ITConfig(USART1,USART_IT_RXNE,ENABLE);//打通USART1到NVIC的串口接收中断通道
-
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//选择NVIC分组2(2位抢占优先级，2位响应优先级)
-
- NVIC_InitTypeDef NVIC_InitStructure;
- NVIC_InitStructure.NVIC_IRQChannel=USART1_IRQn;//选择USART1中断通道
- NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;//使能中断通道
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=1;//抢占优先级为1
- NVIC_InitStructure.NVIC_IRQChannelSubPriority=1;//响应优先级为1
- NVIC_Init(&NVIC_InitStructure);//初始化USART1的NVIC
-
- USART_Cmd(USART1,ENABLE);//启动USART1
-}
-
-/*
- *函数简介:UART2发送一个字节
- *参数说明:8bits数据
- *返回类型:无
- *备注:无
- */
-void UART2_SendByte(uint8_t Byte)
-{
- USART_SendData(USART1,Byte);
- while(USART_GetFlagStatus(USART1,USART_FLAG_TXE)==RESET);//等待发送完成
-}
-
-/*
- *函数简介:UART2发送一个数组
- *参数说明:8bits数组
- *参数说明:数组长度
- *返回类型:无
- *备注:无
- */
-void UART2_SendArray(uint8_t *Array,uint16_t Length)
-{
- for(uint16_t i=0;i=Number位数)
- *返回类型:无
- *备注:无
- */
-void UART2_SendNumber(uint32_t Number,uint8_t Length)
-{
- for(uint8_t i=0;iDR=ch;
- while(!(USART1->SR&(1<<7))){}
- return ch;
- }
-
- /*
- *函数简介:重写fgetc函数(重定向scanf，即移植scanf)
- *参数说明:无
- *返回类型:无
- *备注:看不懂
- *备注:默认重定向UART1(即USART6),若想修改重定向串口,请更改最上方宏定义的注释
- */
- int fgetc(FILE *stream)
- {
- while(!(USART1->SR&1<<5)){}
- return USART1->DR;
- }
-#endif
-
-/*
- *函数简介:UART2的printf函数
- *参数说明:无
- *返回类型:无
- *备注:等价printf函数,支持多串口
- *备注:看不懂
- */
-void UART2_Printf(char *format,...)
-{
- char Strings[100];
- va_list arg;//定义参数列表变量arg
- va_start(arg,format);//从format位置接收参数，放在arg里
- vsprintf(Strings,format,arg);//将格式化字符串打印到Strings
- va_end(arg);//释放参数表arg
- UART2_SendString(Strings);//发送字符串Strings
-}
-
-/*
- *函数简介:UART2获取接收完成标志位
- *参数说明:无
- *返回类型:1-接收完成,0-接收未完成
- *备注:接收完成会软件清零标志位
- */
-uint8_t UART2_GetRxFlag(void)
-{
- if(UART2_RxFlag==1)
- {
- UART2_RxFlag=0;//复位
- return 1;
- }
- return 0;
-}
-
-/*
- *函数简介:UART1普通串口中断函数
- *参数说明:无
- *返回类型:无
- *备注:接收完成置UART1_RxFlag为1,需软件清0
- */
-/**************************************************
-void USART6_IRQHandler(void)
-{
- if(USART_GetITStatus(USART6,USART_IT_RXNE)==SET)//查询接收中断标志位
- {
- UART1_RxData=USART_ReceiveData(USART6);//将数据存入缓存区
- //函数体
- UART1_RxFlag=1;//置接收完成标志位
- }
-
- USART_ClearITPendingBit(USART6,USART_IT_RXNE);//清除接收中断标志位
-}
-**************************************************/
-
-/*
- *函数简介:UART2普通串口中断函数
- *参数说明:无
- *返回类型:无
- *备注:接收完成置UART2_RxFlag为1,需软件清0
- */
-/**************************************************
-void USART1_IRQHandler(void)
-{
- if(USART_GetITStatus(USART1,USART_IT_RXNE)==SET)//查询接收中断标志位
- {
- UART2_RxData=USART_ReceiveData(USART1);//将数据存入缓存区
- //函数体
- UART2_RxFlag=1;//置接收完成标志位
- }
-
- USART_ClearITPendingBit(USART1,USART_IT_RXNE);//清除接收中断标志位
-}
-**************************************************/
diff --git a/底盘/底盘-old/底盘/System/UART.h b/底盘/底盘-old/底盘/System/UART.h
deleted file mode 100644
index b5c5ba4..0000000
--- a/底盘/底盘-old/底盘/System/UART.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef __UART_H
-#define __UART_H
-
-extern uint8_t UART1_RxData;//接收数据缓存区
-extern uint8_t UART1_RxFlag;//接收完成标志位
-extern uint8_t UART2_RxData;//接收数据缓存区
-extern uint8_t UART2_RxFlag;//接收完成标志位
-
-void UART1_SendInit(void);//UART1串口发送初始化
-void UART1_ReceiveInit(void);//UART1串口接收初始化
-void UART1_Init(void);//UART1串口初始化
-void UART1_SendByte(uint8_t Byte);//UART1发送一个字节
-void UART1_SendArray(uint8_t *Array,uint16_t Length);//UART1发送一个数组
-void UART1_SendString(char *String);//UART1发送一个字符串
-void UART1_SendNumber(uint32_t Number,uint8_t Length);//UART1以文本形式发送一个数字
-void UART1_Printf(char *format,...);//UART1的printf函数
-uint8_t UART1_GetRxFlag(void);//UART1获取接收完成标志位
-void UART2_SendInit(void);//UART2串口发送初始化
-void UART2_ReceiveInit(void);//UART2串口接收初始化
-void UART2_Init(void);//UART2串口初始化
-void UART2_SendByte(uint8_t Byte);//UART2发送一个字节
-void UART2_SendArray(uint8_t *Array,uint16_t Length);//UART2发送一个数组
-void UART2_SendString(char *String);//UART2发送一个字符串
-void UART2_SendNumber(uint32_t Number,uint8_t Length);//UART2以文本形式发送一个数字
-void UART2_Printf(char *format,...);//UART2的printf函数
-uint8_t UART2_GetRxFlag(void);//UART2获取接收完成标志位
-
-#endif
diff --git a/底盘/底盘-old/底盘/User/Parameter.h b/底盘/底盘-old/底盘/User/Parameter.h
deleted file mode 100644
index 0592cfb..0000000
--- a/底盘/底盘-old/底盘/User/Parameter.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef __PARAMETER_H
-#define __PARAMETER_H
-
-/*=============================================结构参数=============================================*/
-#define Yaw_GM6020PositionValue 850//Yaw轴编码器值
-
-/*=============================================麦轮参数=============================================*/
-#define Mecanum_WheelRadius 7.0f//麦轮半径(单位cm)
-
-#define Mecanum_rx 24.00f//底盘中心到轮子中心的距离的x轴分量(单位cm)
-#define Mecanum_ry 24.00f//底盘中心到轮子中心的距离的y轴分量(单位cm)
-
-#define Mecanum_LeverSpeedMapRate (1.2f/660.0f)//拨杆速度映射比例
-#define Mecanum_LGyroScopeAngularVelocity 5.0f//小陀螺角速度
-#define Mecanum_RGyroScopeAngularVelocity 5.0f//小陀螺角速度
-#define Mecanum_NormalSpeedRate 2.0f//底盘正常速度和超功率速度的比值
-
-#endif
diff --git a/底盘/底盘-old/底盘/User/RM_C.h b/底盘/底盘-old/底盘/User/RM_C.h
deleted file mode 100644
index 8c6e53c..0000000
--- a/底盘/底盘-old/底盘/User/RM_C.h
+++ /dev/null
@@ -1,36 +0,0 @@
-#ifndef __RM_C_H
-#define __RM_C_H
-
-/*==========延时==========*/
-#include "Delay.h" //延时
-
-/*==========硬件驱动==========*/
-#include "TIM.h" //定时器
-#include "LED.h" //LED
-#include "Buzzer.h" //蜂鸣器
-#include "Remote.h" //遥控器
-#include "M3508.h" //M3508
-#include "GM6020.h" //GM6020
-
-/*==========通讯协议==========*/
-#include "UART.h" //串口
-#include "CAN.h" //CAN
-
-/*==========控制算法==========*/
-#include "PID.h" //PID
-
-/*==========功能==========*/
-#include "LinkCheck.h" //CAN连接检测
-#include "CloseLoopControl.h" //闭环控制
-#include "CToC.h" //板间通讯
-#include "Warming.h" //报警
-
-/*==========车体==========*/
-#include "Parameter.h" //参数
-#include "Mecanum.h" //底盘
-#include "RefereeSystem.h" //裁判系统
-#include "RefereeSystem_CRCTable.h" //裁判系统CRC数组
-#include "Ultra_CAP.h" //超电
-#include "UI.h" //UI
-
-#endif
diff --git a/底盘/底盘-old/底盘/User/main.c b/底盘/底盘-old/底盘/User/main.c
deleted file mode 100644
index 4cdbac0..0000000
--- a/底盘/底盘-old/底盘/User/main.c
+++ /dev/null
@@ -1,26 +0,0 @@
-#include "stm32f4xx.h" // Device header
-#include "stm32f4xx_conf.h"
-#include
-#include "RM_C.h"
-
-
-
-int main()
-{
- Warming_Init();//报警初始化
- LED_BON();//蓝灯点亮表示代码在运行
- Delay_s(2);//延时,等待校准和模块启动
- RefereeSystem_Init();//裁判系统数据接收初始化
- LinkCheck_Init();//连接检测初始化
- Ultra_CAP_Init();//超电初始化
- CloseLoopControl_Init();//闭环控制初始化
-
- UART2_Init();
-
- while(1)
- {
-
- CToC_SlaveSendRefereeSystemData();//向主机发送裁判系统数据
- Delay_us(2000);
- }
-}
diff --git a/底盘/底盘-old/底盘/User/stm32f4xx_conf.h b/底盘/底盘-old/底盘/User/stm32f4xx_conf.h
deleted file mode 100644
index 9540684..0000000
--- a/底盘/底盘-old/底盘/User/stm32f4xx_conf.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/**
- ******************************************************************************
- * @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_conf.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief Library configuration file.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_CONF_H
-#define __STM32F4xx_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment the line below to enable peripheral header file inclusion */
-#include "stm32f4xx_adc.h"
-#include "stm32f4xx_crc.h"
-#include "stm32f4xx_dbgmcu.h"
-#include "stm32f4xx_dma.h"
-#include "stm32f4xx_exti.h"
-#include "stm32f4xx_flash.h"
-#include "stm32f4xx_gpio.h"
-#include "stm32f4xx_i2c.h"
-#include "stm32f4xx_iwdg.h"
-#include "stm32f4xx_pwr.h"
-#include "stm32f4xx_rcc.h"
-#include "stm32f4xx_rtc.h"
-#include "stm32f4xx_sdio.h"
-#include "stm32f4xx_spi.h"
-#include "stm32f4xx_syscfg.h"
-#include "stm32f4xx_tim.h"
-#include "stm32f4xx_usart.h"
-#include "stm32f4xx_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-#if defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#include "stm32f4xx_cryp.h"
-#include "stm32f4xx_hash.h"
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_can.h"
-#include "stm32f4xx_dac.h"
-#include "stm32f4xx_dcmi.h"
-#include "stm32f4xx_dma2d.h"
-#include "stm32f4xx_fmc.h"
-#include "stm32f4xx_ltdc.h"
-#include "stm32f4xx_sai.h"
-#endif /* STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F427_437xx)
-#include "stm32f4xx_cryp.h"
-#include "stm32f4xx_hash.h"
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_can.h"
-#include "stm32f4xx_dac.h"
-#include "stm32f4xx_dcmi.h"
-#include "stm32f4xx_dma2d.h"
-#include "stm32f4xx_fmc.h"
-#include "stm32f4xx_sai.h"
-#endif /* STM32F427_437xx */
-
-#if defined(STM32F40_41xxx)
-#include "stm32f4xx_cryp.h"
-#include "stm32f4xx_hash.h"
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_can.h"
-#include "stm32f4xx_dac.h"
-#include "stm32f4xx_dcmi.h"
-#include "stm32f4xx_fsmc.h"
-#endif /* STM32F40_41xxx */
-
-#if defined(STM32F410xx)
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_dac.h"
-#endif /* STM32F410xx */
-
-#if defined(STM32F411xE)
-#include "stm32f4xx_flash_ramfunc.h"
-#endif /* STM32F411xE */
-
-#if defined(STM32F446xx) || defined(STM32F469_479xx)
-#include "stm32f4xx_qspi.h"
-#endif /* STM32F446xx || STM32F469_479xx */
-
-#if defined(STM32F410xx) || defined(STM32F446xx)
-#include "stm32f4xx_fmpi2c.h"
-#endif /* STM32F410xx || STM32F446xx */
-
-#if defined(STM32F446xx)
-#include "stm32f4xx_spdifrx.h"
-#include "stm32f4xx_cec.h"
-#endif /* STM32F446xx */
-
-#if defined(STM32F469_479xx)
-#include "stm32f4xx_dsi.h"
-#endif /* STM32F469_479xx */
-
-#if defined(STM32F410xx)
-#include "stm32f4xx_lptim.h"
-#endif /* STM32F410xx */
-
-#if defined(STM32F412xG)
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_can.h"
-#include "stm32f4xx_qspi.h"
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_fsmc.h"
-#include "stm32f4xx_dfsdm.h"
-#endif /* STM32F412xG */
-
-#if defined(STM32F413_423xx)
-#include "stm32f4xx_cryp.h"
-#include "stm32f4xx_fmpi2c.h"
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_can.h"
-#include "stm32f4xx_qspi.h"
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_fsmc.h"
-#include "stm32f4xx_dfsdm.h"
-#endif /* STM32F413_423xx */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* If an external clock source is used, then the value of the following define
- should be set to the value of the external clock source, else, if no external
- clock is used, keep this define commented */
-/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */
-
-
-/* Uncomment the line below to expanse the "assert_param" macro in the
- Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT 1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
-
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr: If expr is false, it calls assert_failed function
- * which reports the name of the source file and the source
- * line number of the call that failed.
- * If expr is true, it returns no value.
- * @retval None
- */
- #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
-#else
- #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F4xx_CONF_H */
-
diff --git a/底盘/底盘-old/底盘/User/stm32f4xx_it.c b/底盘/底盘-old/底盘/User/stm32f4xx_it.c
deleted file mode 100644
index 50a40d1..0000000
--- a/底盘/底盘-old/底盘/User/stm32f4xx_it.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/**
- ******************************************************************************
- * @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_it.c
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief Main Interrupt Service Routines.
- * This file provides template for all exceptions handler and
- * peripherals interrupt service routine.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_it.h"
-
-/** @addtogroup Template_Project
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/* Cortex-M4 Processor Exceptions Handlers */
-/******************************************************************************/
-
-/**
- * @brief This function handles NMI exception.
- * @param None
- * @retval None
- */
-void NMI_Handler(void)
-{
-}
-
-/**
- * @brief This function handles Hard Fault exception.
- * @param None
- * @retval None
- */
-void HardFault_Handler(void)
-{
- /* Go to infinite loop when Hard Fault exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles Memory Manage exception.
- * @param None
- * @retval None
- */
-void MemManage_Handler(void)
-{
- /* Go to infinite loop when Memory Manage exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles Bus Fault exception.
- * @param None
- * @retval None
- */
-void BusFault_Handler(void)
-{
- /* Go to infinite loop when Bus Fault exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles Usage Fault exception.
- * @param None
- * @retval None
- */
-void UsageFault_Handler(void)
-{
- /* Go to infinite loop when Usage Fault exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles SVCall exception.
- * @param None
- * @retval None
- */
-void SVC_Handler(void)
-{
-}
-
-/**
- * @brief This function handles Debug Monitor exception.
- * @param None
- * @retval None
- */
-void DebugMon_Handler(void)
-{
-}
-
-/**
- * @brief This function handles PendSVC exception.
- * @param None
- * @retval None
- */
-void PendSV_Handler(void)
-{
-}
-
-/**
- * @brief This function handles SysTick Handler.
- * @param None
- * @retval None
- */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/* STM32F4xx Peripherals Interrupt Handlers */
-/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
-/* available peripheral interrupt handler's name please refer to the startup */
-/* file (startup_stm32f4xx.s). */
-/******************************************************************************/
-
-/**
- * @brief This function handles PPP interrupt request.
- * @param None
- * @retval None
- */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
- * @}
- */
-
-
diff --git a/底盘/底盘-old/底盘/User/stm32f4xx_it.h b/底盘/底盘-old/底盘/User/stm32f4xx_it.h
deleted file mode 100644
index dd54f16..0000000
--- a/底盘/底盘-old/底盘/User/stm32f4xx_it.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/**
- ******************************************************************************
- * @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_it.h
- * @author MCD Application Team
- * @version V1.8.1
- * @date 27-January-2022
- * @brief This file contains the headers of the interrupt handlers.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_IT_H
-#define __STM32F4xx_IT_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_IT_H */
-
diff --git a/底盘/底盘-old/底盘/keilkill.bat b/底盘/底盘-old/底盘/keilkill.bat
deleted file mode 100644
index accc110..0000000
--- a/底盘/底盘-old/底盘/keilkill.bat
+++ /dev/null
@@ -1,27 +0,0 @@
-del *.bak /s
-del *.ddk /s
-del *.edk /s
-del *.lst /s
-del *.lnp /s
-del *.mpf /s
-del *.mpj /s
-del *.obj /s
-del *.omf /s
-::del *.opt /s ::ɾJLINK
-del *.plg /s
-del *.rpt /s
-del *.tmp /s
-del *.__i /s
-del *.crf /s
-del *.o /s
-del *.d /s
-del *.axf /s
-del *.tra /s
-del *.dep /s
-del JLinkLog.txt /s
-
-del *.iex /s
-del *.htm /s
-del *.sct /s
-del *.map /s
-exit