LSMushui
a4da5ad17c
- 云台(ROBOT_TYPE_GIMBAL)与底盘(ROBOT_TYPE_CHASSIS)完整固件源码 - 新增根级 .gitignore,排除 Keil MDK-ARM 构建产物(.o/.d/.crf/.axf/.lnp/.map/.htm/.sct/.dep/.iex/.lst 等) 与 *.uvguix.* / DebugConfig/(与机器绑定的 UI 布局) - core.autocrlf=false,避免固件源码在检出时被改动换行符
78 lines
2.6 KiB
C
78 lines
2.6 KiB
C
/* USER CODE BEGIN Header */
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/**
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******************************************************************************
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* @file dma.c
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* @brief This file provides code for the configuration
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* of all the requested memory to memory DMA transfers.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2026 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* USER CODE END Header */
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/* Includes ------------------------------------------------------------------*/
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#include "dma.h"
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/* USER CODE BEGIN 0 */
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/* USER CODE END 0 */
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/*----------------------------------------------------------------------------*/
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/* Configure DMA */
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/*----------------------------------------------------------------------------*/
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/* USER CODE BEGIN 1 */
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/* USER CODE END 1 */
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/**
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* Enable DMA controller clock
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*/
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void MX_DMA_Init(void)
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{
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/* DMA controller clock enable */
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__HAL_RCC_DMA1_CLK_ENABLE();
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__HAL_RCC_DMA2_CLK_ENABLE();
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/* DMA interrupt init */
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/* DMA1_Stream1_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn);
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/* DMA1_Stream7_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn);
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/* DMA2_Stream1_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA2_Stream1_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA2_Stream1_IRQn);
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/* DMA2_Stream2_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn);
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/* DMA2_Stream3_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn);
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/* DMA2_Stream5_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA2_Stream5_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA2_Stream5_IRQn);
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/* DMA2_Stream6_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn);
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/* DMA2_Stream7_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn);
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}
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/* USER CODE BEGIN 2 */
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/* USER CODE END 2 */
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