Horldsence
4f893ce140
两块 ESP32-S3-WROOM-1-N16R8 图传板（DVP 接口接 OV2640/OV3660/OV5640）， 向队伍客户端与裁判终端推 UDP 图传。固件是跑在 ESP-IDF 上的 Rust，用官方 esp32-camera 组件采集；客户端是 Rust + Slint 桌面程序。 三个 crate 各自独立构建： . firmware，交叉编译到 Xtensa protocol/ 线路格式与帧重组，两端共用，无 ESP-IDF 依赖，有单元测试 client/ Slint 桌面客户端 视频走 UDP 而非 TCP：实测传感器产出 22 fps，TCP MJPEG 只送出 1.9 fps， 且只占用链路能力的 1%——链路是空的，帧堵在队头阻塞后面等一个实时画面 等不起的重传计时器。改为独立数据报、不重传、缺片丢整帧后达到 20.8 fps。 发现是双向的：板子每 2 秒广播 Hello，客户端广播 Subscribe，板子据此定向 推流。板子身份由 MAC 派生，重启不变，所以客户端可以把绑定存进配置。 裁判端同时收两块板子（每个发送方一个重组器），队伍端绑定其中一块并只显示 自己那一边的血量。装甲板接口已预留（ArmorSource trait + ARMOR_PORT）， 当前无数据源，界面显示占位符。 vendor 了 esp32-camera 2.1.7：组件注册表的版本求解器找不到它，且需要打一处 补丁（见 components/esp32-camera/target/esp32s3/ll_cam.c）。 .gitignore 三条 target/ 都锚定在根目录，因为 protocol/ 与 client/ 各自也是 独立 crate；而 components/esp32-camera/target/ 是上游的按芯片分目录，里面是 源码，必须保留。
217 lines
6.9 KiB
C
217 lines
6.9 KiB
C
/*
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* This file is part of the OpenMV project.
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* Copyright (c) 2013/2014 Ibrahim Abdelkader <i.abdalkader@gmail.com>
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* This work is licensed under the MIT license, see the file LICENSE for details.
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*
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* OV2640 register definitions.
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*/
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#ifndef __REG_REGS_H__
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#define __REG_REGS_H__
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/* DSP register bank FF=0x00*/
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#define R_BYPASS 0x05
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#define QS 0x44
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#define CTRLI 0x50
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#define HSIZE 0x51
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#define VSIZE 0x52
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#define XOFFL 0x53
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#define YOFFL 0x54
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#define VHYX 0x55
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#define DPRP 0x56
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#define TEST 0x57
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#define ZMOW 0x5A
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#define ZMOH 0x5B
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#define ZMHH 0x5C
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#define BPADDR 0x7C
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#define BPDATA 0x7D
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#define CTRL2 0x86
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#define CTRL3 0x87
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#define SIZEL 0x8C
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#define HSIZE8 0xC0
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#define VSIZE8 0xC1
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#define CTRL0 0xC2
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#define CTRL1 0xC3
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#define R_DVP_SP 0xD3
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#define IMAGE_MODE 0xDA
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#define RESET 0xE0
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#define MS_SP 0xF0
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#define SS_ID 0xF7
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#define SS_CTRL 0xF7
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#define MC_BIST 0xF9
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#define MC_AL 0xFA
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#define MC_AH 0xFB
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#define MC_D 0xFC
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#define P_CMD 0xFD
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#define P_STATUS 0xFE
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#define BANK_SEL 0xFF
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#define CTRLI_LP_DP 0x80
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#define CTRLI_ROUND 0x40
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#define CTRL0_AEC_EN 0x80
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#define CTRL0_AEC_SEL 0x40
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#define CTRL0_STAT_SEL 0x20
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#define CTRL0_VFIRST 0x10
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#define CTRL0_YUV422 0x08
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#define CTRL0_YUV_EN 0x04
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#define CTRL0_RGB_EN 0x02
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#define CTRL0_RAW_EN 0x01
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#define CTRL2_DCW_EN 0x20
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#define CTRL2_SDE_EN 0x10
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#define CTRL2_UV_ADJ_EN 0x08
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#define CTRL2_UV_AVG_EN 0x04
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#define CTRL2_CMX_EN 0x01
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#define CTRL3_BPC_EN 0x80
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#define CTRL3_WPC_EN 0x40
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#define R_DVP_SP_AUTO_MODE 0x80
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#define R_BYPASS_DSP_EN 0x00
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#define R_BYPASS_DSP_BYPAS 0x01
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#define IMAGE_MODE_Y8_DVP_EN 0x40
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#define IMAGE_MODE_JPEG_EN 0x10
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#define IMAGE_MODE_YUV422 0x00
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#define IMAGE_MODE_RAW10 0x04
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#define IMAGE_MODE_RGB565 0x08
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#define IMAGE_MODE_HREF_VSYNC 0x02
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#define IMAGE_MODE_LBYTE_FIRST 0x01
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#define RESET_MICROC 0x40
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#define RESET_SCCB 0x20
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#define RESET_JPEG 0x10
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#define RESET_DVP 0x04
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#define RESET_IPU 0x02
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#define RESET_CIF 0x01
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#define MC_BIST_RESET 0x80
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#define MC_BIST_BOOT_ROM_SEL 0x40
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#define MC_BIST_12KB_SEL 0x20
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#define MC_BIST_12KB_MASK 0x30
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#define MC_BIST_512KB_SEL 0x08
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#define MC_BIST_512KB_MASK 0x0C
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#define MC_BIST_BUSY_BIT_R 0x02
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#define MC_BIST_MC_RES_ONE_SH_W 0x02
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#define MC_BIST_LAUNCH 0x01
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typedef enum {
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BANK_DSP, BANK_SENSOR, BANK_MAX
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} ov2640_bank_t;
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/* Sensor register bank FF=0x01*/
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#define GAIN 0x00
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#define COM1 0x03
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#define REG04 0x04
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#define REG08 0x08
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#define COM2 0x09
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#define REG_PID 0x0A
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#define REG_VER 0x0B
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#define COM3 0x0C
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#define COM4 0x0D
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#define AEC 0x10
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#define CLKRC 0x11
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#define COM7 0x12
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#define COM8 0x13
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#define COM9 0x14 /* AGC gain ceiling */
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#define COM10 0x15
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#define HSTART 0x17
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#define HSTOP 0x18
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#define VSTART 0x19
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#define VSTOP 0x1A
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#define REG_MIDH 0x1C
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#define REG_MIDL 0x1D
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#define AEW 0x24
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#define AEB 0x25
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#define VV 0x26
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#define REG2A 0x2A
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#define FRARL 0x2B
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#define ADDVSL 0x2D
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#define ADDVSH 0x2E
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#define YAVG 0x2F
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#define HSDY 0x30
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#define HEDY 0x31
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#define REG32 0x32
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#define ARCOM2 0x34
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#define REG45 0x45
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#define FLL 0x46
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#define FLH 0x47
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#define COM19 0x48
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#define ZOOMS 0x49
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#define COM22 0x4B
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#define COM25 0x4E
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#define BD50 0x4F
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#define BD60 0x50
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#define REG5D 0x5D
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#define REG5E 0x5E
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#define REG5F 0x5F
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#define REG60 0x60
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#define HISTO_LOW 0x61
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#define HISTO_HIGH 0x62
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#define REG04_DEFAULT 0x28
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#define REG04_HFLIP_IMG 0x80
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#define REG04_VFLIP_IMG 0x40
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#define REG04_VREF_EN 0x10
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#define REG04_HREF_EN 0x08
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#define REG04_SET(x) (REG04_DEFAULT|x)
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#define COM2_STDBY 0x10
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#define COM2_OUT_DRIVE_1x 0x00
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#define COM2_OUT_DRIVE_2x 0x01
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#define COM2_OUT_DRIVE_3x 0x02
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#define COM2_OUT_DRIVE_4x 0x03
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#define COM3_DEFAULT 0x38
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#define COM3_BAND_50Hz 0x04
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#define COM3_BAND_60Hz 0x00
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#define COM3_BAND_AUTO 0x02
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#define COM3_BAND_SET(x) (COM3_DEFAULT|x)
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#define COM7_SRST 0x80
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#define COM7_RES_UXGA 0x00 /* UXGA */
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#define COM7_RES_SVGA 0x40 /* SVGA */
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#define COM7_RES_CIF 0x20 /* CIF */
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#define COM7_ZOOM_EN 0x04 /* Enable Zoom */
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#define COM7_COLOR_BAR 0x02 /* Enable Color Bar Test */
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#define COM8_DEFAULT 0xC0
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#define COM8_BNDF_EN 0x20 /* Enable Banding filter */
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#define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */
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#define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */
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#define COM8_SET(x) (COM8_DEFAULT|x)
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#define COM9_DEFAULT 0x08
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#define COM9_AGC_GAIN_2x 0x00 /* AGC: 2x */
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#define COM9_AGC_GAIN_4x 0x01 /* AGC: 4x */
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#define COM9_AGC_GAIN_8x 0x02 /* AGC: 8x */
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#define COM9_AGC_GAIN_16x 0x03 /* AGC: 16x */
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#define COM9_AGC_GAIN_32x 0x04 /* AGC: 32x */
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#define COM9_AGC_GAIN_64x 0x05 /* AGC: 64x */
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#define COM9_AGC_GAIN_128x 0x06 /* AGC: 128x */
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#define COM9_AGC_SET(x) (COM9_DEFAULT|(x<<5))
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#define COM10_HREF_EN 0x80 /* HSYNC changes to HREF */
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#define COM10_HSYNC_EN 0x40 /* HREF changes to HSYNC */
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#define COM10_PCLK_FREE 0x20 /* PCLK output option: free running PCLK */
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#define COM10_PCLK_EDGE 0x10 /* Data is updated at the rising edge of PCLK */
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#define COM10_HREF_NEG 0x08 /* HREF negative */
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#define COM10_VSYNC_NEG 0x02 /* VSYNC negative */
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#define COM10_HSYNC_NEG 0x01 /* HSYNC negative */
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#define CTRL1_AWB 0x08 /* Enable AWB */
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#define VV_AGC_TH_SET(h,l) ((h<<4)|(l&0x0F))
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#define REG32_UXGA 0x36
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#define REG32_SVGA 0x09
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#define REG32_CIF 0x89
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#define CLKRC_2X 0x80
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#define CLKRC_2X_UXGA (0x01 | CLKRC_2X)
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#define CLKRC_2X_SVGA CLKRC_2X
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#define CLKRC_2X_CIF CLKRC_2X
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#endif //__REG_REGS_H__
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